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d223677f54e4cf501204d00e1bc091f7e1561264
[openwrt/staging/chunkeey.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the offset,
148 + * user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,83 @@
392 +#ifndef __AR531X_PLATFORM_H
393 +#define __AR531X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + u32 reset_base;
467 + u32 reset_mac;
468 + u32 reset_phy;
469 + u32 phy_base;
470 + struct ar231x_board_config *config;
471 + char *macaddr;
472 +};
473 +
474 +#endif /* __AR531X_PLATFORM_H */
475 --- /dev/null
476 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
477 @@ -0,0 +1,84 @@
478 +/*
479 + * Atheros SoC specific CPU feature overrides
480 + *
481 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
482 + *
483 + * This file was derived from: include/asm-mips/cpu-features.h
484 + * Copyright (C) 2003, 2004 Ralf Baechle
485 + * Copyright (C) 2004 Maciej W. Rozycki
486 + *
487 + * This program is free software; you can redistribute it and/or modify it
488 + * under the terms of the GNU General Public License version 2 as published
489 + * by the Free Software Foundation.
490 + *
491 + */
492 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
493 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
494 +
495 +/*
496 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
497 + */
498 +#define cpu_has_tlb 1
499 +#define cpu_has_4kex 1
500 +#define cpu_has_3k_cache 0
501 +#define cpu_has_4k_cache 1
502 +#define cpu_has_tx39_cache 0
503 +#define cpu_has_sb1_cache 0
504 +#define cpu_has_fpu 0
505 +#define cpu_has_32fpr 0
506 +#define cpu_has_counter 1
507 +/* #define cpu_has_watch ? */
508 +/* #define cpu_has_divec ? */
509 +/* #define cpu_has_vce ? */
510 +/* #define cpu_has_cache_cdex_p ? */
511 +/* #define cpu_has_cache_cdex_s ? */
512 +/* #define cpu_has_prefetch ? */
513 +/* #define cpu_has_mcheck ? */
514 +#define cpu_has_ejtag 1
515 +
516 +#if !defined(CONFIG_ATHEROS_AR5312)
517 +# define cpu_has_llsc 1
518 +#else
519 +/*
520 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
521 + * ll/sc instructions.
522 + */
523 +# define cpu_has_llsc 0
524 +#endif
525 +
526 +#define cpu_has_mips16 0
527 +#define cpu_has_mdmx 0
528 +#define cpu_has_mips3d 0
529 +#define cpu_has_smartmips 0
530 +
531 +/* #define cpu_has_vtag_icache ? */
532 +/* #define cpu_has_dc_aliases ? */
533 +/* #define cpu_has_ic_fills_f_dc ? */
534 +/* #define cpu_has_pindexed_dcache ? */
535 +
536 +/* #define cpu_icache_snoops_remote_store ? */
537 +
538 +#define cpu_has_mips32r1 1
539 +
540 +#if !defined(CONFIG_ATHEROS_AR5312)
541 +# define cpu_has_mips32r2 1
542 +#endif
543 +
544 +#define cpu_has_mips64r1 0
545 +#define cpu_has_mips64r2 0
546 +
547 +#define cpu_has_dsp 0
548 +#define cpu_has_mipsmt 0
549 +
550 +/* #define cpu_has_nofpuex ? */
551 +#define cpu_has_64bits 0
552 +#define cpu_has_64bit_zero_reg 0
553 +#define cpu_has_64bit_gp_regs 0
554 +#define cpu_has_64bit_addresses 0
555 +
556 +/* #define cpu_has_inclusive_pcaches ? */
557 +
558 +/* #define cpu_dcache_line_size() ? */
559 +/* #define cpu_icache_line_size() ? */
560 +
561 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
562 --- /dev/null
563 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
564 @@ -0,0 +1,76 @@
565 +/*
566 + * This file is subject to the terms and conditions of the GNU General Public
567 + * License. See the file "COPYING" in the main directory of this archive
568 + * for more details.
569 + *
570 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
571 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
572 + *
573 + */
574 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
575 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
576 +
577 +#define PCI_DMA_OFFSET 0x20000000
578 +
579 +#include <linux/device.h>
580 +
581 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
582 +{
583 +#ifdef CONFIG_PCI
584 + extern struct bus_type pci_bus_type;
585 +
586 + if (dev && dev->bus == &pci_bus_type)
587 + return PCI_DMA_OFFSET;
588 + else
589 +#endif
590 + return 0;
591 +}
592 +
593 +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
594 +{
595 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
596 +}
597 +
598 +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
599 +{
600 + return page_to_phys(page) + ar231x_dev_offset(dev);
601 +}
602 +
603 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
604 + dma_addr_t dma_addr)
605 +{
606 + return dma_addr - ar231x_dev_offset(dev);
607 +}
608 +
609 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
610 + size_t size, enum dma_data_direction direction)
611 +{
612 +}
613 +
614 +static inline int plat_dma_supported(struct device *dev, u64 mask)
615 +{
616 + return 1;
617 +}
618 +
619 +static inline void plat_extra_sync_for_device(struct device *dev)
620 +{
621 + return;
622 +}
623 +
624 +static inline int plat_dma_mapping_error(struct device *dev,
625 + dma_addr_t dma_addr)
626 +{
627 + return 0;
628 +}
629 +
630 +static inline int plat_device_is_coherent(struct device *dev)
631 +{
632 +#ifdef CONFIG_DMA_COHERENT
633 + return 1;
634 +#endif
635 +#ifdef CONFIG_DMA_NONCOHERENT
636 + return 0;
637 +#endif
638 +}
639 +
640 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
641 --- /dev/null
642 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
643 @@ -0,0 +1,30 @@
644 +#ifndef _ATHEROS_GPIO_H_
645 +#define _ATHEROS_GPIO_H_
646 +
647 +#include <ar231x.h>
648 +
649 +#define gpio_get_value __gpio_get_value
650 +#define gpio_set_value __gpio_set_value
651 +#define gpio_cansleep __gpio_cansleep
652 +
653 +/*
654 + * Wrappers for the generic GPIO layer
655 + */
656 +
657 +/* not sure if these are used? */
658 +
659 +/* Returns IRQ to attach for gpio. Unchecked function */
660 +static inline int gpio_to_irq(unsigned gpio)
661 +{
662 + return AR531X_GPIO_IRQ(gpio);
663 +}
664 +
665 +/* Returns gpio for IRQ attached. Unchecked function */
666 +static inline int irq_to_gpio(unsigned irq)
667 +{
668 + return irq - AR531X_GPIO_IRQ(0);
669 +}
670 +
671 +#include <asm-generic/gpio.h> /* cansleep wrappers */
672 +
673 +#endif
674 --- /dev/null
675 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
676 @@ -0,0 +1,6 @@
677 +#ifndef __AR531X_RESET_H
678 +#define __AR531X_RESET_H
679 +
680 +void ar531x_disable_reset_button(void);
681 +
682 +#endif /* __AR531X_RESET_H */
683 --- /dev/null
684 +++ b/arch/mips/include/asm/mach-ar231x/war.h
685 @@ -0,0 +1,25 @@
686 +/*
687 + * This file is subject to the terms and conditions of the GNU General Public
688 + * License. See the file "COPYING" in the main directory of this archive
689 + * for more details.
690 + *
691 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
692 + */
693 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
694 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
695 +
696 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
697 +#define R4600_V1_HIT_CACHEOP_WAR 0
698 +#define R4600_V2_HIT_CACHEOP_WAR 0
699 +#define R5432_CP0_INTERRUPT_WAR 0
700 +#define BCM1250_M3_WAR 0
701 +#define SIBYTE_1956_WAR 0
702 +#define MIPS4K_ICACHE_REFILL_WAR 0
703 +#define MIPS_CACHE_SYNC_WAR 0
704 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
705 +#define RM9000_CDEX_SMP_WAR 0
706 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
707 +#define R10000_LLSC_WAR 0
708 +#define MIPS34K_MISSED_ITLB_WAR 0
709 +
710 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
711 --- /dev/null
712 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
713 @@ -0,0 +1,580 @@
714 +/*
715 + * Register definitions for AR2315+
716 + *
717 + * This file is subject to the terms and conditions of the GNU General Public
718 + * License. See the file "COPYING" in the main directory of this archive
719 + * for more details.
720 + *
721 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
722 + * Copyright (C) 2006 FON Technology, SL.
723 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
724 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
725 + */
726 +
727 +#ifndef __AR2315_REG_H
728 +#define __AR2315_REG_H
729 +
730 +/*
731 + * IRQs
732 + */
733 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
734 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
735 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
736 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
737 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
738 +
739 +/*
740 + * Address map
741 + */
742 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
743 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
744 +#define AR2315_PCI 0x10100000 /* PCI MMR */
745 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
746 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
747 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
748 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
749 +#define AR2315_UART0 0x11100003 /* UART MMR */
750 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
751 +#define AR2315_PCIEXT 0x80000000 /* pci external */
752 +
753 +/*
754 + * Reset Register
755 + */
756 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
757 +
758 +#define AR2315_RESET_COLD_AHB 0x00000001
759 +#define AR2315_RESET_COLD_APB 0x00000002
760 +#define AR2315_RESET_COLD_CPU 0x00000004
761 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
762 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
763 +#define AR2317_RESET_SYSTEM 0x00000010
764 +
765 +
766 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
767 +
768 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
769 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
770 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
771 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
772 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
773 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
774 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
775 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
776 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
777 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
778 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
779 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
780 +
781 +/*
782 + * AHB master arbitration control
783 + */
784 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
785 +
786 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
787 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
788 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
789 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
790 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
791 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
792 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
793 +
794 +/*
795 + * Config Register
796 + */
797 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
798 +
799 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
800 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
801 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
802 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
803 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
804 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
805 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
806 +
807 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
808 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
809 +#define AR2315_CONFIG_PCIAHB 0x00000800
810 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
811 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
812 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
813 +#define AR2315_CONFIG_CPU_PCI 0x00020000
814 +#define AR2315_CONFIG_CPU_MMR 0x00040000
815 +#define AR2315_CONFIG_BIG 0x00000400
816 +
817 +
818 +/*
819 + * NMI control
820 + */
821 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
822 +
823 +#define AR2315_NMI_EN 1
824 +
825 +/*
826 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
827 + */
828 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
829 +
830 +#define AR2315_REV_MAJ 0x00f0
831 +#define AR2315_REV_MAJ_S 4
832 +#define AR2315_REV_MIN 0x000f
833 +#define AR2315_REV_MIN_S 0
834 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
835 +
836 +/*
837 + * Interface Enable
838 + */
839 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
840 +
841 +#define AR2315_IF_MASK 0x00000007
842 +#define AR2315_IF_DISABLED 0
843 +#define AR2315_IF_PCI 1
844 +#define AR2315_IF_TS_LOCAL 2
845 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
846 +#define AR2315_IF_LOCAL_HOST 0x00000008
847 +#define AR2315_IF_PCI_HOST 0x00000010
848 +#define AR2315_IF_PCI_INTR 0x00000020
849 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
850 +#define AR2315_IF_PCI_CLK_INPUT 0
851 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
852 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
853 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
854 +#define AR2315_IF_PCI_CLK_SHIFT 16
855 +
856 +/*
857 + * APB Interrupt control
858 + */
859 +
860 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
861 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
862 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
863 +
864 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
865 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
866 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
867 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
868 +#define AR2315_ISR_APB 0x0010 /* APB error */
869 +#define AR2315_ISR_TIMER 0x0020 /* timer */
870 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
871 +#define AR2315_ISR_WD 0x0080 /* watchdog */
872 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
873 +
874 +#define AR2315_GISR_MISC 0x0001
875 +#define AR2315_GISR_WLAN0 0x0002
876 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
877 +#define AR2315_GISR_LOCALPCI 0x0008
878 +#define AR2315_GISR_WMACPOLL 0x0010
879 +#define AR2315_GISR_TIMER 0x0020
880 +#define AR2315_GISR_ETHERNET 0x0040
881 +
882 +/*
883 + * Interrupt routing from IO to the processor IP bits
884 + * Define our inter mask and level
885 + */
886 +#define AR2315_INTR_MISCIO SR_IBIT3
887 +#define AR2315_INTR_WLAN0 SR_IBIT4
888 +#define AR2315_INTR_ENET0 SR_IBIT5
889 +#define AR2315_INTR_LOCALPCI SR_IBIT6
890 +#define AR2315_INTR_WMACPOLL SR_IBIT7
891 +#define AR2315_INTR_COMPARE SR_IBIT8
892 +
893 +/*
894 + * Timers
895 + */
896 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
897 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
898 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
899 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
900 +
901 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
902 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
903 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
904 +
905 +/*
906 + * CPU Performance Counters
907 + */
908 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
909 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
910 +
911 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
912 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
913 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
914 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
915 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
916 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
917 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
918 +
919 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
920 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
921 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
922 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
923 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
924 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
925 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
926 +
927 +/*
928 + * AHB Error Reporting.
929 + */
930 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
931 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
932 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
933 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
934 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
935 +
936 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
937 + /* write 1 to clear all bits in ERR0 */
938 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
939 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
940 +
941 +#define AR2315_PROCERR_HMAST 0x0000000f
942 +#define AR2315_PROCERR_HMAST_DFLT 0
943 +#define AR2315_PROCERR_HMAST_WMAC 1
944 +#define AR2315_PROCERR_HMAST_ENET 2
945 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
946 +#define AR2315_PROCERR_HMAST_LOCAL 4
947 +#define AR2315_PROCERR_HMAST_CPU 5
948 +#define AR2315_PROCERR_HMAST_PCITGT 6
949 +
950 +#define AR2315_PROCERR_HMAST_S 0
951 +#define AR2315_PROCERR_HWRITE 0x00000010
952 +#define AR2315_PROCERR_HSIZE 0x00000060
953 +#define AR2315_PROCERR_HSIZE_S 5
954 +#define AR2315_PROCERR_HTRANS 0x00000180
955 +#define AR2315_PROCERR_HTRANS_S 7
956 +#define AR2315_PROCERR_HBURST 0x00000e00
957 +#define AR2315_PROCERR_HBURST_S 9
958 +
959 +/*
960 + * Clock Control
961 + */
962 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
963 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
964 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
965 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
966 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
967 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
968 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
969 +
970 +/* PLLc Control fields */
971 +#define PLLC_REF_DIV_M 0x00000003
972 +#define PLLC_REF_DIV_S 0
973 +#define PLLC_FDBACK_DIV_M 0x0000007C
974 +#define PLLC_FDBACK_DIV_S 2
975 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
976 +#define PLLC_ADD_FDBACK_DIV_S 7
977 +#define PLLC_CLKC_DIV_M 0x0001c000
978 +#define PLLC_CLKC_DIV_S 14
979 +#define PLLC_CLKM_DIV_M 0x00700000
980 +#define PLLC_CLKM_DIV_S 20
981 +
982 +/* CPU CLK Control fields */
983 +#define CPUCLK_CLK_SEL_M 0x00000003
984 +#define CPUCLK_CLK_SEL_S 0
985 +#define CPUCLK_CLK_DIV_M 0x0000000c
986 +#define CPUCLK_CLK_DIV_S 2
987 +
988 +/* AMBA CLK Control fields */
989 +#define AMBACLK_CLK_SEL_M 0x00000003
990 +#define AMBACLK_CLK_SEL_S 0
991 +#define AMBACLK_CLK_DIV_M 0x0000000c
992 +#define AMBACLK_CLK_DIV_S 2
993 +
994 +/*
995 + * GPIO
996 + */
997 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
998 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
999 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1000 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1001 +
1002 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1003 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1004 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1005 +
1006 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1007 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1008 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1009 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1010 +
1011 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1012 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1013 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1014 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1015 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1016 +
1017 +#define AR2315_RESET_GPIO 5
1018 +#define AR2315_NUM_GPIO 22
1019 +
1020 +/*
1021 + * PCI Clock Control
1022 + */
1023 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1024 +
1025 +#define AR2315_PCICLK_INPUT_M 0x3
1026 +#define AR2315_PCICLK_INPUT_S 0
1027 +
1028 +#define AR2315_PCICLK_PLLC_CLKM 0
1029 +#define AR2315_PCICLK_PLLC_CLKM1 1
1030 +#define AR2315_PCICLK_PLLC_CLKC 2
1031 +#define AR2315_PCICLK_REF_CLK 3
1032 +
1033 +#define AR2315_PCICLK_DIV_M 0xc
1034 +#define AR2315_PCICLK_DIV_S 2
1035 +
1036 +#define AR2315_PCICLK_IN_FREQ 0
1037 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1038 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1039 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1040 +
1041 +/*
1042 + * Observation Control Register
1043 + */
1044 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1045 +#define OCR_GPIO0_IRIN 0x0040
1046 +#define OCR_GPIO1_IROUT 0x0080
1047 +#define OCR_GPIO3_RXCLR 0x0200
1048 +
1049 +/*
1050 + * General Clock Control
1051 + */
1052 +
1053 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1054 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1055 +#define MISCCLK_PROCREFCLK 0x00000002
1056 +
1057 +/*
1058 + * SDRAM Controller
1059 + * - No read or write buffers are included.
1060 + */
1061 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1062 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1063 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1064 +
1065 +#define SDRAM_DATA_WIDTH_M 0x00006000
1066 +#define SDRAM_DATA_WIDTH_S 13
1067 +
1068 +#define SDRAM_COL_WIDTH_M 0x00001E00
1069 +#define SDRAM_COL_WIDTH_S 9
1070 +
1071 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1072 +#define SDRAM_ROW_WIDTH_S 5
1073 +
1074 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1075 +#define SDRAM_BANKADDR_BITS_S 3
1076 +
1077 +/*
1078 + * SPI Flash Interface Registers
1079 + */
1080 +
1081 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1082 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1083 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1084 +
1085 +#define SPI_CTL_START 0x00000100
1086 +#define SPI_CTL_BUSY 0x00010000
1087 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1088 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1089 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1090 +#define SPI_CTL_SIZE_MASK 0x00060000
1091 +
1092 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1093 +#define SPI_OPCODE_MASK 0x000000ff
1094 +
1095 +/*
1096 + * PCI Bus Interface Registers
1097 + */
1098 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1099 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1100 +
1101 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1102 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1103 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1104 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1105 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1106 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1107 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1108 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1109 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1110 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1111 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1112 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1113 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1114 +
1115 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1116 +
1117 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1118 +
1119 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1120 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1121 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1122 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1123 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1124 +
1125 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1126 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1127 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1128 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1129 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1130 +
1131 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1132 +
1133 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1134 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1135 +
1136 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1137 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1138 +
1139 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1140 +
1141 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1142 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1143 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1144 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1145 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1146 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1147 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1148 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1149 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1150 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1151 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1152 +#define AR2315_PCI_EXT_INT 0x02000000
1153 +#define AR2315_PCI_ABORT_INT 0x04000000
1154 +
1155 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1156 +
1157 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1158 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1159 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1160 +
1161 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1162 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1163 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1164 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1165 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1166 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1167 +
1168 +
1169 +/*
1170 + * Local Bus Interface Registers
1171 + */
1172 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1173 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1174 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1175 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1176 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1177 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1178 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1179 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1180 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1181 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1182 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1183 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1184 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1185 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1186 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1187 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1188 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1189 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1190 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1191 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1192 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1193 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1194 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1195 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1196 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1197 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1198 +
1199 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1200 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1201 +
1202 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1203 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1204 +
1205 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1206 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1207 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1208 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1209 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1210 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1211 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1212 +#define AR2315_LBM_TIMEOUT_SHFT 7
1213 +#define AR2315_LBM_PORTMUX 0x07000000
1214 +
1215 +
1216 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1217 +
1218 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1219 +#define AR2315_LB_TXEN_0 0x01
1220 +#define AR2315_LB_TXEN_1 0x02
1221 +#define AR2315_LB_TXEN_2 0x04
1222 +#define AR2315_LB_TXEN_3 0x08
1223 +
1224 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1225 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1226 +
1227 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1228 +#define AR2315_LB_RXEN 0x01
1229 +
1230 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1231 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1232 +
1233 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1234 +#define AR2315_INT_TX_DESC 0x0001
1235 +#define AR2315_INT_TX_OK 0x0002
1236 +#define AR2315_INT_TX_ERR 0x0004
1237 +#define AR2315_INT_TX_EOF 0x0008
1238 +#define AR2315_INT_RX_DESC 0x0010
1239 +#define AR2315_INT_RX_OK 0x0020
1240 +#define AR2315_INT_RX_ERR 0x0040
1241 +#define AR2315_INT_RX_EOF 0x0080
1242 +#define AR2315_INT_TX_TRUNC 0x0100
1243 +#define AR2315_INT_TX_STARVE 0x0200
1244 +#define AR2315_INT_LB_TIMEOUT 0x0400
1245 +#define AR2315_INT_LB_ERR 0x0800
1246 +#define AR2315_INT_MBOX_WR 0x1000
1247 +#define AR2315_INT_MBOX_RD 0x2000
1248 +
1249 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1250 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1251 +
1252 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1253 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1254 +
1255 +/*
1256 + * IR Interface Registers
1257 + */
1258 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1259 +
1260 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1261 +
1262 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1263 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1264 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1265 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1266 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1267 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1268 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1269 +
1270 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1271 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1272 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1273 +
1274 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1275 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1276 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1277 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1278 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1279 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1280 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1281 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1282 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1283 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1284 +
1285 +#define HOST_PCI_DEV_ID 3
1286 +#define HOST_PCI_MBAR0 0x10000000
1287 +#define HOST_PCI_MBAR1 0x20000000
1288 +#define HOST_PCI_MBAR2 0x30000000
1289 +
1290 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1291 +#define PCI_DEVICE_MEM_SPACE 0x800000
1292 +
1293 +#endif /* __AR2315_REG_H */
1294 --- /dev/null
1295 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1296 @@ -0,0 +1,233 @@
1297 +/*
1298 + * This file is subject to the terms and conditions of the GNU General Public
1299 + * License. See the file "COPYING" in the main directory of this archive
1300 + * for more details.
1301 + *
1302 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1303 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1304 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1305 + */
1306 +
1307 +#ifndef AR5312_H
1308 +#define AR5312_H
1309 +
1310 +#include <asm/addrspace.h>
1311 +
1312 +/*
1313 + * IRQs
1314 + */
1315 +
1316 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1317 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1318 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1319 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1320 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1321 +
1322 +
1323 +/* Address Map */
1324 +#define AR531X_WLAN0 0x18000000
1325 +#define AR531X_WLAN1 0x18500000
1326 +#define AR531X_ENET0 0x18100000
1327 +#define AR531X_ENET1 0x18200000
1328 +#define AR531X_SDRAMCTL 0x18300000
1329 +#define AR531X_FLASHCTL 0x18400000
1330 +#define AR531X_APBBASE 0x1c000000
1331 +#define AR531X_FLASH 0x1e000000
1332 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1333 +
1334 +/*
1335 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1336 + * should be considered available. The AR5312 supports 2 enet MACS,
1337 + * even though many reference boards only actually use 1 of them
1338 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1339 + * The AR2312 supports 1 enet MAC.
1340 + */
1341 +#define AR531X_NUM_ENET_MAC 2
1342 +
1343 +/*
1344 + * Need these defines to determine true number of ethernet MACs
1345 + */
1346 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1347 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1348 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1349 +
1350 +/*
1351 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1352 + * should be considered available.
1353 + */
1354 +#define AR531X_NUM_WMAC 2
1355 +
1356 +/* Reset/Timer Block Address Map */
1357 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1358 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1359 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1360 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1361 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1362 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1363 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1364 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1365 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1366 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1367 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1368 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1369 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1370 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1371 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1372 +
1373 +/* AR531X_WD_CTRL register bit field definitions */
1374 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1375 +#define AR531X_WD_CTRL_NMI 0x0001
1376 +#define AR531X_WD_CTRL_RESET 0x0002
1377 +
1378 +/* AR531X_ISR register bit field definitions */
1379 +#define AR531X_ISR_NONE 0x0000
1380 +#define AR531X_ISR_TIMER 0x0001
1381 +#define AR531X_ISR_AHBPROC 0x0002
1382 +#define AR531X_ISR_AHBDMA 0x0004
1383 +#define AR531X_ISR_GPIO 0x0008
1384 +#define AR531X_ISR_UART0 0x0010
1385 +#define AR531X_ISR_UART0DMA 0x0020
1386 +#define AR531X_ISR_WD 0x0040
1387 +#define AR531X_ISR_LOCAL 0x0080
1388 +
1389 +/* AR531X_RESET register bit field definitions */
1390 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1391 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1392 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1393 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1394 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1395 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1396 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1397 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1398 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1399 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1400 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1401 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1402 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1403 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1404 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1405 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1406 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1407 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1408 +
1409 +#define AR531X_RESET_WMAC0_BITS \
1410 + (AR531X_RESET_WLAN0 |\
1411 + AR531X_RESET_WARM_WLAN0_MAC |\
1412 + AR531X_RESET_WARM_WLAN0_BB)
1413 +
1414 +#define AR531X_RESERT_WMAC1_BITS \
1415 + (AR531X_RESET_WLAN1 |\
1416 + AR531X_RESET_WARM_WLAN1_MAC |\
1417 + AR531X_RESET_WARM_WLAN1_BB)
1418 +
1419 +/* AR5312_CLOCKCTL1 register bit field definitions */
1420 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1421 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1422 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1423 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1424 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1425 +
1426 +/* Valid for AR5312 and AR2312 */
1427 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1428 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1429 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1430 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1431 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1432 +
1433 +/* Valid for AR2313 */
1434 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1435 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1436 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1437 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1438 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1439 +
1440 +
1441 +/* AR531X_ENABLE register bit field definitions */
1442 +#define AR531X_ENABLE_WLAN0 0x0001
1443 +#define AR531X_ENABLE_ENET0 0x0002
1444 +#define AR531X_ENABLE_ENET1 0x0004
1445 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1446 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1447 +#define AR531X_ENABLE_WLAN1 \
1448 + (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
1449 + AR531X_ENABLE_WLAN1_DMA)
1450 +
1451 +/* AR531X_REV register bit field definitions */
1452 +#define AR531X_REV_WMAC_MAJ 0xf000
1453 +#define AR531X_REV_WMAC_MAJ_S 12
1454 +#define AR531X_REV_WMAC_MIN 0x0f00
1455 +#define AR531X_REV_WMAC_MIN_S 8
1456 +#define AR531X_REV_MAJ 0x00f0
1457 +#define AR531X_REV_MAJ_S 4
1458 +#define AR531X_REV_MIN 0x000f
1459 +#define AR531X_REV_MIN_S 0
1460 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1461 +
1462 +/* Major revision numbers, bits 7..4 of Revision ID register */
1463 +#define AR531X_REV_MAJ_AR5312 0x4
1464 +#define AR531X_REV_MAJ_AR2313 0x5
1465 +
1466 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1467 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1468 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1469 +
1470 +/* AR531X_FLASHCTL register bit field definitions */
1471 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1472 +#define FLASHCTL_IDCY_S 0
1473 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1474 +#define FLASHCTL_WST1_S 5
1475 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1476 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1477 +#define FLASHCTL_WST2_S 11
1478 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1479 +#define FLASHCTL_AC_S 16
1480 +#define FLASHCTL_AC_128K 0x00000000
1481 +#define FLASHCTL_AC_256K 0x00010000
1482 +#define FLASHCTL_AC_512K 0x00020000
1483 +#define FLASHCTL_AC_1M 0x00030000
1484 +#define FLASHCTL_AC_2M 0x00040000
1485 +#define FLASHCTL_AC_4M 0x00050000
1486 +#define FLASHCTL_AC_8M 0x00060000
1487 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1488 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1489 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1490 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1491 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1492 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1493 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1494 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1495 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1496 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1497 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1498 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1499 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1500 +
1501 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1502 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1503 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1504 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1505 +
1506 +/* ARM SDRAM Controller -- just enough to determine memory size */
1507 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1508 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1509 +#define MEM_CFG1_AC0_S 8
1510 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1511 +#define MEM_CFG1_AC1_S 12
1512 +
1513 +/* GPIO Address Map */
1514 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1515 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1516 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1517 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1518 +
1519 +/* GPIO Control Register bit field definitions */
1520 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1521 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1522 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1523 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1524 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1525 +#define AR531X_NUM_GPIO 8
1526 +
1527 +
1528 +#endif
1529 +
1530 --- /dev/null
1531 +++ b/arch/mips/ar231x/ar5312.c
1532 @@ -0,0 +1,579 @@
1533 +/*
1534 + * This file is subject to the terms and conditions of the GNU General Public
1535 + * License. See the file "COPYING" in the main directory of this archive
1536 + * for more details.
1537 + *
1538 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1539 + * Copyright (C) 2006 FON Technology, SL.
1540 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1541 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1542 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1543 + */
1544 +
1545 +/*
1546 + * Platform devices for Atheros SoCs
1547 + */
1548 +
1549 +#include <generated/autoconf.h>
1550 +#include <linux/init.h>
1551 +#include <linux/module.h>
1552 +#include <linux/types.h>
1553 +#include <linux/string.h>
1554 +#include <linux/mtd/physmap.h>
1555 +#include <linux/platform_device.h>
1556 +#include <linux/kernel.h>
1557 +#include <linux/reboot.h>
1558 +#include <linux/leds.h>
1559 +#include <linux/gpio.h>
1560 +#include <asm/bootinfo.h>
1561 +#include <asm/reboot.h>
1562 +#include <asm/time.h>
1563 +#include <linux/irq.h>
1564 +#include <linux/io.h>
1565 +
1566 +#include <ar231x_platform.h>
1567 +#include <ar5312_regs.h>
1568 +#include <ar231x.h>
1569 +#include "devices.h"
1570 +#include "ar5312.h"
1571 +
1572 +static void
1573 +ar5312_misc_irq_dispatch(void)
1574 +{
1575 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1576 +
1577 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1578 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1579 + (void)ar231x_read_reg(AR531X_TIMER);
1580 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1581 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1582 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1583 + do_IRQ(AR531X_MISC_IRQ_UART0);
1584 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1585 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1586 + else
1587 + do_IRQ(AR531X_MISC_IRQ_NONE);
1588 +}
1589 +
1590 +static asmlinkage void
1591 +ar5312_irq_dispatch(void)
1592 +{
1593 + int pending = read_c0_status() & read_c0_cause();
1594 +
1595 + if (pending & CAUSEF_IP2)
1596 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1597 + else if (pending & CAUSEF_IP3)
1598 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1599 + else if (pending & CAUSEF_IP4)
1600 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1601 + else if (pending & CAUSEF_IP5)
1602 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1603 + else if (pending & CAUSEF_IP6)
1604 + ar5312_misc_irq_dispatch();
1605 + else if (pending & CAUSEF_IP7)
1606 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1607 +}
1608 +
1609 +
1610 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1611 +static void
1612 +ar5312_misc_intr_enable(struct irq_data *d)
1613 +{
1614 + unsigned int imr;
1615 +
1616 + imr = ar231x_read_reg(AR531X_IMR);
1617 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1618 + ar231x_write_reg(AR531X_IMR, imr);
1619 +}
1620 +
1621 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1622 +static void
1623 +ar5312_misc_intr_disable(struct irq_data *d)
1624 +{
1625 + unsigned int imr;
1626 +
1627 + imr = ar231x_read_reg(AR531X_IMR);
1628 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1629 + ar231x_write_reg(AR531X_IMR, imr);
1630 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1631 +}
1632 +
1633 +static struct irq_chip ar5312_misc_intr_controller = {
1634 + .irq_mask = ar5312_misc_intr_disable,
1635 + .irq_unmask = ar5312_misc_intr_enable,
1636 +};
1637 +
1638 +
1639 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1640 +{
1641 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1642 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1643 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1644 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1645 +
1646 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1647 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1648 + dma1);
1649 +
1650 + machine_restart("AHB error"); /* Catastrophic failure */
1651 + return IRQ_HANDLED;
1652 +}
1653 +
1654 +
1655 +static struct irqaction ar5312_ahb_proc_interrupt = {
1656 + .handler = ar5312_ahb_proc_handler,
1657 + .name = "ar5312_ahb_proc_interrupt",
1658 +};
1659 +
1660 +
1661 +static struct irqaction cascade = {
1662 + .handler = no_action,
1663 + .name = "cascade",
1664 +};
1665 +
1666 +void __init ar5312_irq_init(void)
1667 +{
1668 + int i;
1669 +
1670 + if (!is_5312())
1671 + return;
1672 +
1673 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1674 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1675 + int irq = AR531X_MISC_IRQ_BASE + i;
1676 + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
1677 + handle_level_irq);
1678 + }
1679 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1680 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1681 +}
1682 +
1683 +static u32
1684 +ar5312_gpio_set_output(u32 mask, u32 val)
1685 +{
1686 + u32 reg;
1687 +
1688 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1689 + reg |= mask;
1690 + reg &= ~val;
1691 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1692 + return reg;
1693 +}
1694 +
1695 +static u32
1696 +ar5312_gpio_get(u32 valid_mask)
1697 +{
1698 + u32 reg;
1699 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1700 + reg &= valid_mask;
1701 + return reg;
1702 +}
1703 +
1704 +static u32
1705 +ar5312_gpio_set(u32 mask, u32 value)
1706 +{
1707 + u32 reg;
1708 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1709 + reg &= ~mask;
1710 + reg |= value;
1711 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1712 + return reg;
1713 +}
1714 +
1715 +/*
1716 + * gpiolib implementations. Original mask based methods preserved
1717 + */
1718 +static int
1719 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1720 +{
1721 + struct ar231x_gpio_chip *gpch =
1722 + container_of(chip, struct ar231x_gpio_chip, chip);
1723 + u32 mask = 1 << gpio;
1724 + u32 rett;
1725 + if (!(gpch->valid_mask & mask))
1726 + return 0;
1727 + rett = ar5312_gpio_get(gpch->valid_mask);
1728 + return !!(rett & mask);
1729 +}
1730 +
1731 +static void
1732 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1733 +{
1734 + struct ar231x_gpio_chip *gpch =
1735 + container_of(chip, struct ar231x_gpio_chip, chip);
1736 + u32 mask = 1 << gpio;
1737 + if (!(gpch->valid_mask & mask))
1738 + return;
1739 + ar5312_gpio_set(mask, (!!value) * mask);
1740 +}
1741 +
1742 +static int
1743 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1744 +{
1745 + struct ar231x_gpio_chip *gpch =
1746 + container_of(chip, struct ar231x_gpio_chip, chip);
1747 + u32 mask = 1 << gpio;
1748 + if (!(gpch->valid_mask & mask))
1749 + return -ENXIO;
1750 + ar5312_gpio_set_output(mask, 0);
1751 + return 0;
1752 +}
1753 +static int
1754 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1755 +{
1756 + struct ar231x_gpio_chip *gpch =
1757 + container_of(chip, struct ar231x_gpio_chip, chip);
1758 + u32 mask = 1 << gpio;
1759 + if (!(gpch->valid_mask & mask))
1760 + return -ENXIO;
1761 + ar5312_gpio_set_output(mask, mask);
1762 + ar5312_gpio_set(mask, (!!value) * mask);
1763 + return 0;
1764 +}
1765 +
1766 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1767 + .valid_mask = (1 << 22) - 1,
1768 + .chip = {
1769 + .label = "ar5312-gpio",
1770 + .direction_input = ar5312_gpio_direction_input,
1771 + .direction_output = ar5312_gpio_direction_output,
1772 + .set = ar5312_gpio_set_value,
1773 + .get = ar5312_gpio_get_value,
1774 + .base = 0,
1775 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1776 + }
1777 +};
1778 +
1779 +/* end of gpiolib */
1780 +
1781 +static struct physmap_flash_data ar5312_flash_data = {
1782 + .width = 2,
1783 +};
1784 +
1785 +static struct resource ar5312_flash_resource = {
1786 + .start = AR531X_FLASH,
1787 + .end = AR531X_FLASH + 0x800000 - 1,
1788 + .flags = IORESOURCE_MEM,
1789 +};
1790 +
1791 +static struct ar231x_eth ar5312_eth0_data = {
1792 + .reset_base = AR531X_RESET,
1793 + .reset_mac = AR531X_RESET_ENET0,
1794 + .reset_phy = AR531X_RESET_EPHY0,
1795 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1796 + .config = &ar231x_board,
1797 +};
1798 +
1799 +static struct ar231x_eth ar5312_eth1_data = {
1800 + .reset_base = AR531X_RESET,
1801 + .reset_mac = AR531X_RESET_ENET1,
1802 + .reset_phy = AR531X_RESET_EPHY1,
1803 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1804 + .config = &ar231x_board,
1805 +};
1806 +
1807 +static struct platform_device ar5312_physmap_flash = {
1808 + .name = "physmap-flash",
1809 + .id = 0,
1810 + .dev.platform_data = &ar5312_flash_data,
1811 + .resource = &ar5312_flash_resource,
1812 + .num_resources = 1,
1813 +};
1814 +
1815 +#ifdef CONFIG_LEDS_GPIO
1816 +static struct gpio_led ar5312_leds[] = {
1817 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1818 +};
1819 +
1820 +static const struct gpio_led_platform_data ar5312_led_data = {
1821 + .num_leds = ARRAY_SIZE(ar5312_leds),
1822 + .leds = (void *)ar5312_leds,
1823 +};
1824 +
1825 +static struct platform_device ar5312_gpio_leds = {
1826 + .name = "leds-gpio",
1827 + .id = -1,
1828 + .dev.platform_data = (void *)&ar5312_led_data,
1829 +};
1830 +#endif
1831 +
1832 +/*
1833 + * NB: This mapping size is larger than the actual flash size,
1834 + * but this shouldn't be a problem here, because the flash
1835 + * will simply be mapped multiple times.
1836 + */
1837 +static char __init *ar5312_flash_limit(void)
1838 +{
1839 + u32 ctl;
1840 + /*
1841 + * Configure flash bank 0.
1842 + * Assume 8M window size. Flash will be aliased if it's smaller
1843 + */
1844 + ctl = FLASHCTL_E |
1845 + FLASHCTL_AC_8M |
1846 + FLASHCTL_RBLE |
1847 + (0x01 << FLASHCTL_IDCY_S) |
1848 + (0x07 << FLASHCTL_WST1_S) |
1849 + (0x07 << FLASHCTL_WST2_S) |
1850 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1851 +
1852 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1853 +
1854 + /* Disable other flash banks */
1855 + ar231x_write_reg(AR531X_FLASHCTL1,
1856 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1857 +
1858 + ar231x_write_reg(AR531X_FLASHCTL2,
1859 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1860 +
1861 + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
1862 +}
1863 +
1864 +int __init ar5312_init_devices(void)
1865 +{
1866 + struct ar231x_boarddata *config;
1867 + u32 fctl = 0;
1868 + u8 *c;
1869 +
1870 + if (!is_5312())
1871 + return 0;
1872 +
1873 + /* Locate board/radio config data */
1874 + ar231x_find_config(ar5312_flash_limit());
1875 + config = ar231x_board.config;
1876 +
1877 + /* AR2313 has CPU minor rev. 10 */
1878 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1879 + ar231x_devtype = DEV_TYPE_AR2313;
1880 +
1881 + /* AR2312 shares the same Silicon ID as AR5312 */
1882 + else if (config->flags & BD_ISCASPER)
1883 + ar231x_devtype = DEV_TYPE_AR2312;
1884 +
1885 + /* Everything else is probably AR5312 or compatible */
1886 + else
1887 + ar231x_devtype = DEV_TYPE_AR5312;
1888 +
1889 + /* fixup flash width */
1890 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1891 + switch (fctl) {
1892 + case FLASHCTL_MWx16:
1893 + ar5312_flash_data.width = 2;
1894 + break;
1895 + case FLASHCTL_MWx8:
1896 + default:
1897 + ar5312_flash_data.width = 1;
1898 + break;
1899 + }
1900 +
1901 + platform_device_register(&ar5312_physmap_flash);
1902 +
1903 +#ifdef CONFIG_LEDS_GPIO
1904 + ar5312_leds[0].gpio = config->sys_led_gpio;
1905 + platform_device_register(&ar5312_gpio_leds);
1906 +#endif
1907 +
1908 + /* Fix up MAC addresses if necessary */
1909 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1910 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1911 +
1912 + /* If ENET0 and ENET1 have the same mac address,
1913 + * increment the one from ENET1 */
1914 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1915 + c = config->enet1_mac + 5;
1916 + while ((c >= config->enet1_mac) && !(++(*c)))
1917 + c--;
1918 + }
1919 +
1920 + switch (ar231x_devtype) {
1921 + case DEV_TYPE_AR5312:
1922 + ar5312_eth0_data.macaddr = config->enet0_mac;
1923 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1924 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1925 +
1926 + ar5312_eth1_data.macaddr = config->enet1_mac;
1927 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1928 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1929 +
1930 + if (!ar231x_board.radio)
1931 + return 0;
1932 +
1933 + if (!(config->flags & BD_WLAN0))
1934 + break;
1935 +
1936 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1937 + break;
1938 + /*
1939 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1940 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1941 + */
1942 + case DEV_TYPE_AR2312:
1943 + case DEV_TYPE_AR2313:
1944 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1945 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1946 + ar5312_eth1_data.macaddr = config->enet0_mac;
1947 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1948 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1949 +
1950 + if (!ar231x_board.radio)
1951 + return 0;
1952 + break;
1953 + default:
1954 + break;
1955 + }
1956 +
1957 + if (config->flags & BD_WLAN1)
1958 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1959 +
1960 + return 0;
1961 +}
1962 +
1963 +
1964 +static void ar5312_restart(char *command)
1965 +{
1966 + /* reset the system */
1967 + local_irq_disable();
1968 + while (1)
1969 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1970 +}
1971 +
1972 +
1973 +/*
1974 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1975 + * to determine the predevisor value.
1976 + */
1977 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1978 +
1979 +
1980 +static int __init
1981 +ar5312_cpu_frequency(void)
1982 +{
1983 + unsigned int scratch;
1984 + unsigned int predivide_mask, predivide_shift;
1985 + unsigned int multiplier_mask, multiplier_shift;
1986 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1987 + unsigned int doubler_mask;
1988 + u16 devid;
1989 +
1990 + /* Trust the bootrom's idea of cpu frequency. */
1991 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1992 + if (scratch)
1993 + return scratch;
1994 +
1995 + devid = ar231x_read_reg(AR531X_REV);
1996 + devid &= AR531X_REV_MAJ;
1997 + devid >>= AR531X_REV_MAJ_S;
1998 + if (devid == AR531X_REV_MAJ_AR2313) {
1999 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2000 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2001 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2002 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2003 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2004 + } else { /* AR5312 and AR2312 */
2005 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2006 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2007 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2008 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2009 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2010 + }
2011 +
2012 + /*
2013 + * Clocking is derived from a fixed 40MHz input clock.
2014 + *
2015 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2016 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2017 + * flash, Timer, Watchdog Timer)
2018 + *
2019 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2020 + *
2021 + * So, for example, with a PLL multiplier of 5, we have
2022 + *
2023 + * cpu_freq = 200MHz
2024 + * sys_freq = 50MHz
2025 + * cnt_freq = 100MHz
2026 + *
2027 + * We compute the CPU frequency, based on PLL settings.
2028 + */
2029 +
2030 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2031 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2032 + predivisor = clockctl1_predivide_table[predivide_select];
2033 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2034 +
2035 + if (clock_ctl1 & doubler_mask)
2036 + multiplier = multiplier << 1;
2037 +
2038 + return (40000000 / predivisor) * multiplier;
2039 +}
2040 +
2041 +static inline int
2042 +ar5312_sys_frequency(void)
2043 +{
2044 + return ar5312_cpu_frequency() / 4;
2045 +}
2046 +
2047 +void __init
2048 +ar5312_time_init(void)
2049 +{
2050 + if (!is_5312())
2051 + return;
2052 +
2053 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2054 +}
2055 +
2056 +int __init
2057 +ar5312_gpio_init(void)
2058 +{
2059 + int ret;
2060 + struct ar231x_gpio_chip *gpch;
2061 + gpch = &ar5312_gpio_chip;
2062 + ret = gpiochip_add(&gpch->chip);
2063 + if (ret) {
2064 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2065 + return ret;
2066 + }
2067 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2068 + gpch->chip.ngpio);
2069 + return ret;
2070 +}
2071 +
2072 +void __init
2073 +ar5312_prom_init(void)
2074 +{
2075 + u32 memsize, memcfg, bank0AC, bank1AC;
2076 + u32 devid;
2077 +
2078 + if (!is_5312())
2079 + return;
2080 +
2081 + /* Detect memory size */
2082 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2083 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2084 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2085 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2086 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2087 + memsize <<= 20;
2088 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2089 +
2090 + devid = ar231x_read_reg(AR531X_REV);
2091 + devid >>= AR531X_REV_WMAC_MIN_S;
2092 + devid &= AR531X_REV_CHIP;
2093 + ar231x_board.devid = (u16) devid;
2094 + ar5312_gpio_init();
2095 +}
2096 +
2097 +void __init
2098 +ar5312_plat_setup(void)
2099 +{
2100 + if (!is_5312())
2101 + return;
2102 +
2103 + /* Clear any lingering AHB errors */
2104 + ar231x_read_reg(AR531X_PROCADDR);
2105 + ar231x_read_reg(AR531X_DMAADDR);
2106 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2107 +
2108 + _machine_restart = ar5312_restart;
2109 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2110 +}
2111 +
2112 --- /dev/null
2113 +++ b/arch/mips/ar231x/ar2315.c
2114 @@ -0,0 +1,693 @@
2115 +/*
2116 + * This file is subject to the terms and conditions of the GNU General Public
2117 + * License. See the file "COPYING" in the main directory of this archive
2118 + * for more details.
2119 + *
2120 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2121 + * Copyright (C) 2006 FON Technology, SL.
2122 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2123 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2124 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2125 + */
2126 +
2127 +/*
2128 + * Platform devices for Atheros SoCs
2129 + */
2130 +
2131 +#include <generated/autoconf.h>
2132 +#include <linux/init.h>
2133 +#include <linux/module.h>
2134 +#include <linux/types.h>
2135 +#include <linux/string.h>
2136 +#include <linux/platform_device.h>
2137 +#include <linux/kernel.h>
2138 +#include <linux/reboot.h>
2139 +#include <linux/delay.h>
2140 +#include <linux/leds.h>
2141 +#include <linux/gpio.h>
2142 +#include <asm/bootinfo.h>
2143 +#include <asm/reboot.h>
2144 +#include <asm/time.h>
2145 +#include <linux/irq.h>
2146 +#include <linux/io.h>
2147 +
2148 +#include <ar231x_platform.h>
2149 +#include <ar2315_regs.h>
2150 +#include <ar231x.h>
2151 +#include "devices.h"
2152 +#include "ar2315.h"
2153 +
2154 +static u32 gpiointmask, gpiointval;
2155 +
2156 +static inline void ar2315_gpio_irq(void)
2157 +{
2158 + u32 pend;
2159 + int bit = -1;
2160 +
2161 + /* only do one gpio interrupt at a time */
2162 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2163 +
2164 + if (pend) {
2165 + bit = fls(pend) - 1;
2166 + pend &= ~(1 << bit);
2167 + gpiointval ^= (1 << bit);
2168 + }
2169 +
2170 + if (!pend)
2171 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2172 +
2173 + /* Enable interrupt with edge detection */
2174 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2175 + return;
2176 +
2177 + if (bit >= 0)
2178 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2179 +}
2180 +
2181 +
2182 +/*
2183 + * Called when an interrupt is received, this function
2184 + * determines exactly which interrupt it was, and it
2185 + * invokes the appropriate handler.
2186 + *
2187 + * Implicitly, we also define interrupt priority by
2188 + * choosing which to dispatch first.
2189 + */
2190 +static asmlinkage void
2191 +ar2315_irq_dispatch(void)
2192 +{
2193 + int pending = read_c0_status() & read_c0_cause();
2194 +
2195 + if (pending & CAUSEF_IP3)
2196 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2197 + else if (pending & CAUSEF_IP4)
2198 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2199 + else if (pending & CAUSEF_IP2) {
2200 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2201 +
2202 + if (misc_intr & AR2315_ISR_SPI)
2203 + do_IRQ(AR531X_MISC_IRQ_SPI);
2204 + else if (misc_intr & AR2315_ISR_TIMER)
2205 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2206 + else if (misc_intr & AR2315_ISR_AHB)
2207 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2208 + else if (misc_intr & AR2315_ISR_GPIO)
2209 + ar2315_gpio_irq();
2210 + else if (misc_intr & AR2315_ISR_UART0)
2211 + do_IRQ(AR531X_MISC_IRQ_UART0);
2212 + else if (misc_intr & AR2315_ISR_WD)
2213 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2214 + else
2215 + do_IRQ(AR531X_MISC_IRQ_NONE);
2216 + } else if (pending & CAUSEF_IP7)
2217 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2218 +}
2219 +
2220 +static void ar2315_set_gpiointmask(int gpio, int level)
2221 +{
2222 + u32 reg;
2223 +
2224 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2225 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2226 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2227 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2228 +}
2229 +
2230 +static void ar2315_gpio_intr_enable(struct irq_data *d)
2231 +{
2232 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2233 +
2234 + /* Enable interrupt with edge detection */
2235 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2236 + return;
2237 +
2238 + gpiointmask |= (1 << gpio);
2239 + ar2315_set_gpiointmask(gpio, 3);
2240 +}
2241 +
2242 +static void ar2315_gpio_intr_disable(struct irq_data *d)
2243 +{
2244 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2245 +
2246 + /* Disable interrupt */
2247 + gpiointmask &= ~(1 << gpio);
2248 + ar2315_set_gpiointmask(gpio, 0);
2249 +}
2250 +
2251 +static struct irq_chip ar2315_gpio_intr_controller = {
2252 + .irq_mask = ar2315_gpio_intr_disable,
2253 + .irq_unmask = ar2315_gpio_intr_enable,
2254 +};
2255 +
2256 +static void
2257 +ar2315_misc_intr_enable(struct irq_data *d)
2258 +{
2259 + unsigned int imr;
2260 +
2261 + imr = ar231x_read_reg(AR2315_IMR);
2262 + switch (d->irq) {
2263 + case AR531X_MISC_IRQ_SPI:
2264 + imr |= AR2315_ISR_SPI;
2265 + break;
2266 + case AR531X_MISC_IRQ_TIMER:
2267 + imr |= AR2315_ISR_TIMER;
2268 + break;
2269 + case AR531X_MISC_IRQ_AHB_PROC:
2270 + imr |= AR2315_ISR_AHB;
2271 + break;
2272 + case AR531X_MISC_IRQ_GPIO:
2273 + imr |= AR2315_ISR_GPIO;
2274 + break;
2275 + case AR531X_MISC_IRQ_UART0:
2276 + imr |= AR2315_ISR_UART0;
2277 + break;
2278 + case AR531X_MISC_IRQ_WATCHDOG:
2279 + imr |= AR2315_ISR_WD;
2280 + break;
2281 + default:
2282 + break;
2283 + }
2284 + ar231x_write_reg(AR2315_IMR, imr);
2285 +}
2286 +
2287 +static void
2288 +ar2315_misc_intr_disable(struct irq_data *d)
2289 +{
2290 + unsigned int imr;
2291 +
2292 + imr = ar231x_read_reg(AR2315_IMR);
2293 + switch (d->irq) {
2294 + case AR531X_MISC_IRQ_SPI:
2295 + imr &= ~AR2315_ISR_SPI;
2296 + break;
2297 + case AR531X_MISC_IRQ_TIMER:
2298 + imr &= ~AR2315_ISR_TIMER;
2299 + break;
2300 + case AR531X_MISC_IRQ_AHB_PROC:
2301 + imr &= ~AR2315_ISR_AHB;
2302 + break;
2303 + case AR531X_MISC_IRQ_GPIO:
2304 + imr &= ~AR2315_ISR_GPIO;
2305 + break;
2306 + case AR531X_MISC_IRQ_UART0:
2307 + imr &= ~AR2315_ISR_UART0;
2308 + break;
2309 + case AR531X_MISC_IRQ_WATCHDOG:
2310 + imr &= ~AR2315_ISR_WD;
2311 + break;
2312 + default:
2313 + break;
2314 + }
2315 + ar231x_write_reg(AR2315_IMR, imr);
2316 +}
2317 +
2318 +static struct irq_chip ar2315_misc_intr_controller = {
2319 + .irq_mask = ar2315_misc_intr_disable,
2320 + .irq_unmask = ar2315_misc_intr_enable,
2321 +};
2322 +
2323 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2324 +{
2325 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2326 + ar231x_read_reg(AR2315_AHB_ERR1);
2327 +
2328 + pr_emerg("AHB fatal error\n");
2329 + machine_restart("AHB error"); /* Catastrophic failure */
2330 +
2331 + return IRQ_HANDLED;
2332 +}
2333 +
2334 +static struct irqaction ar2315_ahb_proc_interrupt = {
2335 + .handler = ar2315_ahb_proc_handler,
2336 + .name = "ar2315_ahb_proc_interrupt",
2337 +};
2338 +
2339 +static struct irqaction cascade = {
2340 + .handler = no_action,
2341 + .name = "cascade",
2342 +};
2343 +
2344 +void
2345 +ar2315_irq_init(void)
2346 +{
2347 + int i;
2348 +
2349 + if (!is_2315())
2350 + return;
2351 +
2352 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2353 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2354 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2355 + int irq = AR531X_MISC_IRQ_BASE + i;
2356 + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
2357 + handle_level_irq);
2358 + }
2359 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2360 + int irq = AR531X_GPIO_IRQ_BASE + i;
2361 + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2362 + handle_level_irq);
2363 + }
2364 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2365 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2366 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2367 +}
2368 +
2369 +static u32
2370 +ar2315_gpio_set_output(u32 mask, u32 val)
2371 +{
2372 + u32 reg;
2373 +
2374 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2375 + reg &= ~mask;
2376 + reg |= val;
2377 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2378 + return reg;
2379 +}
2380 +
2381 +static u32
2382 +ar2315_gpio_get(u32 valid_mask)
2383 +{
2384 + u32 reg;
2385 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2386 + reg &= valid_mask;
2387 + return reg;
2388 +}
2389 +
2390 +static u32
2391 +ar2315_gpio_set(u32 mask, u32 value)
2392 +{
2393 + u32 reg;
2394 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2395 + reg &= ~mask;
2396 + reg |= value;
2397 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2398 + return reg;
2399 +}
2400 +
2401 +/*
2402 + * gpiolib implementation. Original legacy mask based methods
2403 + * preserved for now.
2404 + */
2405 +static int
2406 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2407 +{
2408 + struct ar231x_gpio_chip *gpch =
2409 + container_of(chip, struct ar231x_gpio_chip, chip);
2410 + u32 mask = 1 << gpio;
2411 + u32 rett;
2412 + if (!(gpch->valid_mask & mask))
2413 + return 0;
2414 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2415 + return !!(rett & mask);
2416 +}
2417 +
2418 +static void
2419 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2420 +{
2421 + struct ar231x_gpio_chip *gpch =
2422 + container_of(chip, struct ar231x_gpio_chip, chip);
2423 + u32 mask = 1 << gpio;
2424 + if (!(gpch->valid_mask & mask))
2425 + return;
2426 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2427 +}
2428 +
2429 +static int
2430 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2431 +{
2432 + struct ar231x_gpio_chip *gpch =
2433 + container_of(chip, struct ar231x_gpio_chip, chip);
2434 + u32 mask = 1 << gpio;
2435 + if (!(gpch->valid_mask & mask))
2436 + return -ENXIO;
2437 + ar2315_gpio_set_output(mask, 0); /* legacy */
2438 + return 0;
2439 +}
2440 +
2441 +static int
2442 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2443 +{
2444 + struct ar231x_gpio_chip *gpch =
2445 + container_of(chip, struct ar231x_gpio_chip, chip);
2446 + u32 mask = 1 << gpio;
2447 + if (!(gpch->valid_mask & mask))
2448 + return -ENXIO;
2449 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2450 + ar2315_gpio_set(mask, (!!value) * mask);
2451 + return 0;
2452 +}
2453 +
2454 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2455 + .valid_mask = (1 << 22) - 1,
2456 + .chip = {
2457 + .label = "ar2315-gpio",
2458 + .direction_input = ar2315_gpio_direction_input,
2459 + .direction_output = ar2315_gpio_direction_output,
2460 + .set = ar2315_gpio_set_value,
2461 + .get = ar2315_gpio_get_value,
2462 + .base = 0,
2463 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2464 + }
2465 +};
2466 +
2467 +/* end of gpiolib */
2468 +
2469 +
2470 +static struct ar231x_eth ar2315_eth_data = {
2471 + .reset_base = AR2315_RESET,
2472 + .reset_mac = AR2315_RESET_ENET0,
2473 + .reset_phy = AR2315_RESET_EPHY0,
2474 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2475 + .config = &ar231x_board,
2476 +};
2477 +
2478 +static struct resource ar2315_spiflash_res[] = {
2479 + {
2480 + .name = "flash_base",
2481 + .flags = IORESOURCE_MEM,
2482 + .start = KSEG1ADDR(AR2315_SPI_READ),
2483 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2484 + },
2485 + {
2486 + .name = "flash_regs",
2487 + .flags = IORESOURCE_MEM,
2488 + .start = 0x11300000,
2489 + .end = 0x11300012,
2490 + },
2491 +};
2492 +
2493 +static struct platform_device ar2315_spiflash = {
2494 + .id = 0,
2495 + .name = "spiflash",
2496 + .resource = ar2315_spiflash_res,
2497 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2498 +};
2499 +
2500 +static struct platform_device ar2315_wdt = {
2501 + .id = 0,
2502 + .name = "ar2315_wdt",
2503 +};
2504 +
2505 +#define SPI_FLASH_CTL 0x00
2506 +#define SPI_FLASH_OPCODE 0x04
2507 +#define SPI_FLASH_DATA 0x08
2508 +
2509 +static inline u32
2510 +spiflash_read_reg(int reg)
2511 +{
2512 + return ar231x_read_reg(AR2315_SPI + reg);
2513 +}
2514 +
2515 +static inline void
2516 +spiflash_write_reg(int reg, u32 data)
2517 +{
2518 + ar231x_write_reg(AR2315_SPI + reg, data);
2519 +}
2520 +
2521 +static u32
2522 +spiflash_wait_status(void)
2523 +{
2524 + u32 reg;
2525 +
2526 + do {
2527 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2528 + } while (reg & SPI_CTL_BUSY);
2529 +
2530 + return reg;
2531 +}
2532 +
2533 +static u8
2534 +spiflash_probe(void)
2535 +{
2536 + u32 reg;
2537 +
2538 + reg = spiflash_wait_status();
2539 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2540 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2541 +
2542 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2543 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2544 +
2545 + reg = spiflash_wait_status();
2546 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2547 + reg &= 0xff;
2548 +
2549 + return (u8) reg;
2550 +}
2551 +
2552 +
2553 +#define STM_8MBIT_SIGNATURE 0x13
2554 +#define STM_16MBIT_SIGNATURE 0x14
2555 +#define STM_32MBIT_SIGNATURE 0x15
2556 +#define STM_64MBIT_SIGNATURE 0x16
2557 +#define STM_128MBIT_SIGNATURE 0x17
2558 +
2559 +static u8 __init *
2560 +ar2315_flash_limit(void)
2561 +{
2562 + u32 flash_size = 0;
2563 +
2564 + /* probe the flash chip size */
2565 + switch (spiflash_probe()) {
2566 + case STM_8MBIT_SIGNATURE:
2567 + flash_size = 0x00100000;
2568 + break;
2569 + case STM_16MBIT_SIGNATURE:
2570 + flash_size = 0x00200000;
2571 + break;
2572 + case STM_32MBIT_SIGNATURE:
2573 + flash_size = 0x00400000;
2574 + break;
2575 + case STM_64MBIT_SIGNATURE:
2576 + flash_size = 0x00800000;
2577 + break;
2578 + case STM_128MBIT_SIGNATURE:
2579 + flash_size = 0x01000000;
2580 + break;
2581 + }
2582 +
2583 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2584 + flash_size - 1;
2585 + return (u8 *)ar2315_spiflash_res[0].end + 1;
2586 +}
2587 +
2588 +#ifdef CONFIG_LEDS_GPIO
2589 +static struct gpio_led ar2315_leds[6];
2590 +static struct gpio_led_platform_data ar2315_led_data = {
2591 + .leds = (void *)ar2315_leds,
2592 +};
2593 +
2594 +static struct platform_device ar2315_gpio_leds = {
2595 + .name = "leds-gpio",
2596 + .id = -1,
2597 + .dev = {
2598 + .platform_data = (void *)&ar2315_led_data,
2599 + }
2600 +};
2601 +
2602 +static void __init
2603 +ar2315_init_gpio_leds(void)
2604 +{
2605 + static char led_names[6][6];
2606 + int i, led = 0;
2607 +
2608 + ar2315_led_data.num_leds = 0;
2609 + for (i = 1; i < 8; i++) {
2610 + if ((i == AR2315_RESET_GPIO) ||
2611 + (i == ar231x_board.config->reset_config_gpio))
2612 + continue;
2613 +
2614 + if (i == ar231x_board.config->sys_led_gpio)
2615 + strcpy(led_names[led], "wlan");
2616 + else
2617 + sprintf(led_names[led], "gpio%d", i);
2618 +
2619 + ar2315_leds[led].name = led_names[led];
2620 + ar2315_leds[led].gpio = i;
2621 + ar2315_leds[led].active_low = 0;
2622 + led++;
2623 + }
2624 + ar2315_led_data.num_leds = led;
2625 + platform_device_register(&ar2315_gpio_leds);
2626 +}
2627 +#else
2628 +static inline void ar2315_init_gpio_leds(void)
2629 +{
2630 +}
2631 +#endif
2632 +
2633 +int __init
2634 +ar2315_init_devices(void)
2635 +{
2636 + if (!is_2315())
2637 + return 0;
2638 +
2639 + /* Find board configuration */
2640 + ar231x_find_config(ar2315_flash_limit());
2641 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2642 +
2643 + ar2315_init_gpio_leds();
2644 + platform_device_register(&ar2315_wdt);
2645 + platform_device_register(&ar2315_spiflash);
2646 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2647 + &ar2315_eth_data);
2648 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2649 +
2650 + return 0;
2651 +}
2652 +
2653 +static void
2654 +ar2315_restart(char *command)
2655 +{
2656 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2657 +
2658 + local_irq_disable();
2659 +
2660 + /* try reset the system via reset control */
2661 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2662 +
2663 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2664 + * give it some time to attempt a gpio based hardware reset
2665 + * (atheros reference design workaround) */
2666 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2667 + mdelay(100);
2668 +
2669 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2670 + * workaround. Attempt to jump to the mips reset location -
2671 + * the boot loader itself might be able to recover the system */
2672 + mips_reset_vec();
2673 +}
2674 +
2675 +
2676 +/*
2677 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2678 + * to determine the predevisor value.
2679 + */
2680 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2681 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2682 +
2683 +static unsigned int __init
2684 +ar2315_sys_clk(unsigned int clock_ctl)
2685 +{
2686 + unsigned int pllc_ctrl, cpu_div;
2687 + unsigned int pllc_out, refdiv, fdiv, divby2;
2688 + unsigned int clk_div;
2689 +
2690 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2691 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2692 + refdiv = clockctl1_predivide_table[refdiv];
2693 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2694 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2695 + divby2 += 1;
2696 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2697 +
2698 + /* clkm input selected */
2699 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2700 + case 0:
2701 + case 1:
2702 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2703 + PLLC_CLKM_DIV_S];
2704 + break;
2705 + case 2:
2706 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2707 + PLLC_CLKC_DIV_S];
2708 + break;
2709 + default:
2710 + pllc_out = 40000000;
2711 + clk_div = 1;
2712 + break;
2713 + }
2714 +
2715 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2716 + cpu_div = cpu_div * 2 ?: 1;
2717 +
2718 + return pllc_out / (clk_div * cpu_div);
2719 +}
2720 +
2721 +static inline unsigned int
2722 +ar2315_cpu_frequency(void)
2723 +{
2724 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2725 +}
2726 +
2727 +static inline unsigned int
2728 +ar2315_apb_frequency(void)
2729 +{
2730 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2731 +}
2732 +
2733 +void __init
2734 +ar2315_time_init(void)
2735 +{
2736 + if (!is_2315())
2737 + return;
2738 +
2739 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2740 +}
2741 +
2742 +int __init
2743 +ar2315_gpio_init(void)
2744 +{
2745 + int ret;
2746 + struct ar231x_gpio_chip *gpch;
2747 + gpch = &ar2315_gpio_chip;
2748 + ret = gpiochip_add(&gpch->chip);
2749 + if (ret) {
2750 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2751 + return ret;
2752 + }
2753 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2754 + gpch->chip.ngpio);
2755 + return ret;
2756 +}
2757 +
2758 +
2759 +
2760 +void __init
2761 +ar2315_prom_init(void)
2762 +{
2763 + u32 memsize, memcfg, devid;
2764 +
2765 + if (!is_2315())
2766 + return;
2767 +
2768 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2769 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2770 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2771 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2772 + memsize <<= 3;
2773 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2774 +
2775 + /* Detect the hardware based on the device ID */
2776 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2777 + switch (devid) {
2778 + case 0x90:
2779 + case 0x91:
2780 + ar231x_devtype = DEV_TYPE_AR2317;
2781 + break;
2782 + default:
2783 + ar231x_devtype = DEV_TYPE_AR2315;
2784 + break;
2785 + }
2786 + ar2315_gpio_init();
2787 + ar231x_board.devid = devid;
2788 +}
2789 +
2790 +void __init
2791 +ar2315_plat_setup(void)
2792 +{
2793 + u32 config;
2794 +
2795 + if (!is_2315())
2796 + return;
2797 +
2798 + /* Clear any lingering AHB errors */
2799 + config = read_c0_config();
2800 + write_c0_config(config & ~0x3);
2801 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2802 + ar231x_read_reg(AR2315_AHB_ERR1);
2803 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2804 +
2805 + _machine_restart = ar2315_restart;
2806 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2807 +}
2808 --- /dev/null
2809 +++ b/arch/mips/ar231x/ar2315.h
2810 @@ -0,0 +1,37 @@
2811 +#ifndef __AR2315_H
2812 +#define __AR2315_H
2813 +
2814 +#ifdef CONFIG_ATHEROS_AR2315
2815 +
2816 +extern void ar2315_irq_init(void);
2817 +extern int ar2315_init_devices(void);
2818 +extern void ar2315_prom_init(void);
2819 +extern void ar2315_plat_setup(void);
2820 +extern void ar2315_time_init(void);
2821 +
2822 +#else
2823 +
2824 +static inline void ar2315_irq_init(void)
2825 +{
2826 +}
2827 +
2828 +static inline int ar2315_init_devices(void)
2829 +{
2830 + return 0;
2831 +}
2832 +
2833 +static inline void ar2315_prom_init(void)
2834 +{
2835 +}
2836 +
2837 +static inline void ar2315_plat_setup(void)
2838 +{
2839 +}
2840 +
2841 +static inline void ar2315_time_init(void)
2842 +{
2843 +}
2844 +
2845 +#endif
2846 +
2847 +#endif
2848 --- /dev/null
2849 +++ b/arch/mips/ar231x/ar5312.h
2850 @@ -0,0 +1,38 @@
2851 +#ifndef __AR5312_H
2852 +#define __AR5312_H
2853 +
2854 +#ifdef CONFIG_ATHEROS_AR5312
2855 +
2856 +extern void ar5312_irq_init(void);
2857 +extern int ar5312_init_devices(void);
2858 +extern void ar5312_prom_init(void);
2859 +extern void ar5312_plat_setup(void);
2860 +extern void ar5312_time_init(void);
2861 +extern void ar5312_time_init(void);
2862 +
2863 +#else
2864 +
2865 +static inline void ar5312_irq_init(void)
2866 +{
2867 +}
2868 +
2869 +static inline int ar5312_init_devices(void)
2870 +{
2871 + return 0;
2872 +}
2873 +
2874 +static inline void ar5312_prom_init(void)
2875 +{
2876 +}
2877 +
2878 +static inline void ar5312_plat_setup(void)
2879 +{
2880 +}
2881 +
2882 +static inline void ar5312_time_init(void)
2883 +{
2884 +}
2885 +
2886 +#endif
2887 +
2888 +#endif
2889 --- /dev/null
2890 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2891 @@ -0,0 +1,57 @@
2892 +#ifndef __AR531X_H
2893 +#define __AR531X_H
2894 +
2895 +#include <linux/types.h>
2896 +#include <linux/io.h>
2897 +
2898 +#define AR531X_MISC_IRQ_BASE 0x20
2899 +#define AR531X_GPIO_IRQ_BASE 0x30
2900 +
2901 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2902 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2903 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2904 +
2905 +/* Miscellaneous interrupts, which share IP6 */
2906 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
2907 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
2908 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
2909 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
2910 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
2911 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
2912 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
2913 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
2914 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
2915 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
2916 +#define AR531X_MISC_IRQ_COUNT 10
2917 +
2918 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2919 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2920 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2921 +#define AR531X_GPIO_IRQ_COUNT 22
2922 +
2923 +static inline u32
2924 +ar231x_read_reg(u32 reg)
2925 +{
2926 + return __raw_readl((u32 *)KSEG1ADDR(reg));
2927 +}
2928 +
2929 +static inline void
2930 +ar231x_write_reg(u32 reg, u32 val)
2931 +{
2932 + __raw_writel(val, (u32 *)KSEG1ADDR(reg));
2933 +}
2934 +
2935 +static inline u32
2936 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2937 +{
2938 + u32 ret;
2939 +
2940 + ret = ar231x_read_reg(reg);
2941 + ret &= ~mask;
2942 + ret |= val;
2943 + ar231x_write_reg(reg, ret);
2944 +
2945 + return ret;
2946 +}
2947 +
2948 +#endif
2949 --- /dev/null
2950 +++ b/arch/mips/ar231x/devices.h
2951 @@ -0,0 +1,42 @@
2952 +#ifndef __AR231X_DEVICES_H
2953 +#define __AR231X_DEVICES_H
2954 +#include <linux/gpio.h>
2955 +
2956 +enum {
2957 + /* handled by ar5312.c */
2958 + DEV_TYPE_AR2312,
2959 + DEV_TYPE_AR2313,
2960 + DEV_TYPE_AR5312,
2961 +
2962 + /* handled by ar2315.c */
2963 + DEV_TYPE_AR2315,
2964 + DEV_TYPE_AR2316,
2965 + DEV_TYPE_AR2317,
2966 +
2967 + DEV_TYPE_UNKNOWN
2968 +};
2969 +
2970 +extern int ar231x_devtype;
2971 +extern struct ar231x_board_config ar231x_board;
2972 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2973 +
2974 +extern int ar231x_find_config(u8 *flash_limit);
2975 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2976 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2977 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2978 +
2979 +static inline bool is_2315(void)
2980 +{
2981 + return (current_cpu_data.cputype == CPU_4KEC);
2982 +}
2983 +
2984 +static inline bool is_5312(void)
2985 +{
2986 + return !is_2315();
2987 +}
2988 +
2989 +struct ar231x_gpio_chip {
2990 + u32 valid_mask;
2991 + struct gpio_chip chip;
2992 +};
2993 +#endif
2994 --- /dev/null
2995 +++ b/arch/mips/ar231x/devices.c
2996 @@ -0,0 +1,168 @@
2997 +#include <linux/kernel.h>
2998 +#include <linux/init.h>
2999 +#include <linux/serial.h>
3000 +#include <linux/serial_core.h>
3001 +#include <linux/serial_8250.h>
3002 +#include <linux/platform_device.h>
3003 +#include <ar231x_platform.h>
3004 +#include <ar231x.h>
3005 +#include "devices.h"
3006 +#include "ar5312.h"
3007 +#include "ar2315.h"
3008 +
3009 +struct ar231x_board_config ar231x_board;
3010 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3011 +
3012 +static struct resource ar231x_eth0_res[] = {
3013 + {
3014 + .name = "eth0_membase",
3015 + .flags = IORESOURCE_MEM,
3016 + },
3017 + {
3018 + .name = "eth0_irq",
3019 + .flags = IORESOURCE_IRQ,
3020 + }
3021 +};
3022 +
3023 +static struct resource ar231x_eth1_res[] = {
3024 + {
3025 + .name = "eth1_membase",
3026 + .flags = IORESOURCE_MEM,
3027 + },
3028 + {
3029 + .name = "eth1_irq",
3030 + .flags = IORESOURCE_IRQ,
3031 + }
3032 +};
3033 +
3034 +static struct platform_device ar231x_eth[] = {
3035 + {
3036 + .id = 0,
3037 + .name = "ar231x-eth",
3038 + .resource = ar231x_eth0_res,
3039 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3040 + },
3041 + {
3042 + .id = 1,
3043 + .name = "ar231x-eth",
3044 + .resource = ar231x_eth1_res,
3045 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3046 + }
3047 +};
3048 +
3049 +static struct resource ar231x_wmac0_res[] = {
3050 + {
3051 + .name = "wmac0_membase",
3052 + .flags = IORESOURCE_MEM,
3053 + },
3054 + {
3055 + .name = "wmac0_irq",
3056 + .flags = IORESOURCE_IRQ,
3057 + }
3058 +};
3059 +
3060 +static struct resource ar231x_wmac1_res[] = {
3061 + {
3062 + .name = "wmac1_membase",
3063 + .flags = IORESOURCE_MEM,
3064 + },
3065 + {
3066 + .name = "wmac1_irq",
3067 + .flags = IORESOURCE_IRQ,
3068 + }
3069 +};
3070 +
3071 +
3072 +static struct platform_device ar231x_wmac[] = {
3073 + {
3074 + .id = 0,
3075 + .name = "ar231x-wmac",
3076 + .resource = ar231x_wmac0_res,
3077 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3078 + .dev.platform_data = &ar231x_board,
3079 + },
3080 + {
3081 + .id = 1,
3082 + .name = "ar231x-wmac",
3083 + .resource = ar231x_wmac1_res,
3084 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3085 + .dev.platform_data = &ar231x_board,
3086 + },
3087 +};
3088 +
3089 +static const char * const devtype_strings[] = {
3090 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3091 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3092 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3093 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3094 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3095 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3096 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3097 +};
3098 +
3099 +const char *get_system_type(void)
3100 +{
3101 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3102 + !devtype_strings[ar231x_devtype])
3103 + return devtype_strings[DEV_TYPE_UNKNOWN];
3104 + return devtype_strings[ar231x_devtype];
3105 +}
3106 +
3107 +
3108 +int __init
3109 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3110 +{
3111 + struct resource *res;
3112 +
3113 + ar231x_eth[nr].dev.platform_data = pdata;
3114 + res = &ar231x_eth[nr].resource[0];
3115 + res->start = base;
3116 + res->end = base + 0x2000 - 1;
3117 + res++;
3118 + res->start = irq;
3119 + res->end = irq;
3120 + return platform_device_register(&ar231x_eth[nr]);
3121 +}
3122 +
3123 +void __init
3124 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3125 +{
3126 + struct uart_port s;
3127 +
3128 + memset(&s, 0, sizeof(s));
3129 +
3130 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3131 + s.iotype = UPIO_MEM;
3132 + s.irq = AR531X_MISC_IRQ_UART0;
3133 + s.regshift = 2;
3134 + s.mapbase = mapbase;
3135 + s.uartclk = uartclk;
3136 + s.membase = (void __iomem *)s.mapbase;
3137 +
3138 + early_serial_setup(&s);
3139 +}
3140 +
3141 +int __init
3142 +ar231x_add_wmac(int nr, u32 base, int irq)
3143 +{
3144 + struct resource *res;
3145 +
3146 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3147 + res = &ar231x_wmac[nr].resource[0];
3148 + res->start = base;
3149 + res->end = base + 0x10000 - 1;
3150 + res++;
3151 + res->start = irq;
3152 + res->end = irq;
3153 + return platform_device_register(&ar231x_wmac[nr]);
3154 +}
3155 +
3156 +static int __init ar231x_register_devices(void)
3157 +{
3158 + ar5312_init_devices();
3159 + ar2315_init_devices();
3160 +
3161 + return 0;
3162 +}
3163 +
3164 +device_initcall(ar231x_register_devices);
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