target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch

   1 From 671b5b9af51bd5296d4fe76155b3ba75c99000b9 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Mon, 13 Sep 2021 17:30:18 +0100
   4 Subject: [PATCH] drm/vc4: Reset HDMI MISC_CONTROL register.
   5
   6 The HDMI block can repeat pixels for double clocked modes,
   7 and the firmware is now configuring the block to do this as
   8 the PV is doing it incorrectly when at 2pixels/clock.
   9 If the kernel doesn't reset it then we end up with strange
  10 modes.
  11
  12 Reset MISC_CONTROL.
  13
  14 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  15 ---
  16  drivers/gpu/drm/vc4/vc4_hdmi.c      | 8 ++++++++
  17  drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 +++
  18  2 files changed, 11 insertions(+)
  19
  20 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  21 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  22 @@ -78,6 +78,9 @@
  23  #define VC5_HDMI_VERTB_VSPO_SHIFT              16
  24  #define VC5_HDMI_VERTB_VSPO_MASK               VC4_MASK(29, 16)
  25
  26 +#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT  0
  27 +#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK   VC4_MASK(3, 0)
  28 +
  29  #define VC5_HDMI_SCRAMBLER_CTL_ENABLE          BIT(0)
  30
  31  #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT     8
  32 @@ -962,6 +965,11 @@ static void vc5_hdmi_set_timings(struct
  33         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
  34         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
  35
  36 +       reg = HDMI_READ(HDMI_MISC_CONTROL);
  37 +       reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
  38 +       reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
  39 +       HDMI_WRITE(HDMI_MISC_CONTROL, reg);
  40 +
  41         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
  42
  43         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
  44 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
  45 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
  46 @@ -125,6 +125,7 @@ enum vc4_hdmi_field {
  47         HDMI_VERTB0,
  48         HDMI_VERTB1,
  49         HDMI_VID_CTL,
  50 +       HDMI_MISC_CONTROL,
  51  };
  52
  53  struct vc4_hdmi_register {
  54 @@ -235,6 +236,7 @@ static const struct vc4_hdmi_register __
  55         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
  56         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
  57         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
  58 +       VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
  59         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
  60         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
  61         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
  62 @@ -315,6 +317,7 @@ static const struct vc4_hdmi_register __
  63         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
  64         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
  65         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
  66 +       VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
  67         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
  68         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
  69         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),