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bcm63xx: kernel: add BCM63167 cpuid variant
[openwrt/staging/chunkeey.git] / target / linux / bcm63xx / patches-5.4 / 339-MIPS-BCM63XX-add-support-for-BCM63268.patch
1 From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sat, 7 Dec 2013 17:14:17 +0100
4 Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
5
6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
7 ---
8 arch/mips/bcm63xx/Kconfig | 5 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
10 arch/mips/bcm63xx/clk.c | 25 ++++-
11 arch/mips/bcm63xx/cpu.c | 59 +++++++++-
12 arch/mips/bcm63xx/dev-flash.c | 6 +
13 arch/mips/bcm63xx/dev-spi.c | 4 +-
14 arch/mips/bcm63xx/irq.c | 20 +++-
15 arch/mips/bcm63xx/reset.c | 21 ++++
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 12 files changed, 342 insertions(+), 12 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -61,6 +61,11 @@ config BCM63XX_CPU_6368
25 select HAVE_PCI
26 select BCM63XX_OHCI
27 select BCM63XX_EHCI
28 +
29 +config BCM63XX_CPU_63268
30 + bool "support 63268 CPU"
31 + select SYS_HAS_CPU_BMIPS4350
32 + select HAVE_PCI
33 endmenu
34
35 source "arch/mips/bcm63xx/boards/Kconfig"
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -697,7 +697,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
43 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -169,6 +169,8 @@ static void enetsw_set(struct clk *clk,
50 clk_disable_unlocked(&clk_swpkt_sar);
51 }
52 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
53 + } else if (BCMCPU_IS_63268()) {
54 + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
55 } else {
56 return;
57 }
58 @@ -214,6 +216,8 @@ static void usbh_set(struct clk *clk, in
59 bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
60 else if (BCMCPU_IS_6368())
61 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
62 + else if (BCMCPU_IS_63268())
63 + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
64 else
65 return;
66
67 @@ -236,6 +240,8 @@ static void usbd_set(struct clk *clk, in
68 bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
69 else if (BCMCPU_IS_6368())
70 bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
71 + else if (BCMCPU_IS_63268())
72 + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
73 else
74 return;
75
76 @@ -262,9 +268,13 @@ static void spi_set(struct clk *clk, int
77 mask = CKCTL_6358_SPI_EN;
78 else if (BCMCPU_IS_6362())
79 mask = CKCTL_6362_SPI_EN;
80 - else
81 - /* BCMCPU_IS_6368 */
82 + else if (BCMCPU_IS_6368())
83 mask = CKCTL_6368_SPI_EN;
84 + else if (BCMCPU_IS_63268())
85 + mask = CKCTL_63268_SPI_EN;
86 + else
87 + return;
88 +
89 bcm_hwclock_set(mask, enable);
90 }
91
92 @@ -283,6 +293,8 @@ static void hsspi_set(struct clk *clk, i
93 mask = CKCTL_6328_HSSPI_EN;
94 else if (BCMCPU_IS_6362())
95 mask = CKCTL_6362_HSSPI_EN;
96 + else if (BCMCPU_IS_63268())
97 + mask = CKCTL_63268_HSSPI_EN;
98 else
99 return;
100
101 @@ -352,6 +364,8 @@ static void pcie_set(struct clk *clk, in
102 bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
103 else if (BCMCPU_IS_6362())
104 bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
105 + else if (BCMCPU_IS_63268())
106 + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
107 }
108
109 static struct clk clk_pcie = {
110 @@ -536,6 +550,21 @@ static struct clk_lookup bcm6368_clks[]
111 CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
112 };
113
114 +static struct clk_lookup bcm63268_clks[] = {
115 + /* fixed rate clocks */
116 + CLKDEV_INIT(NULL, "periph", &clk_periph),
117 + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
118 + CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
119 + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
120 + /* gated clocks */
121 + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
122 + CLKDEV_INIT(NULL, "usbh", &clk_usbh),
123 + CLKDEV_INIT(NULL, "usbd", &clk_usbd),
124 + CLKDEV_INIT(NULL, "spi", &clk_spi),
125 + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
126 + CLKDEV_INIT(NULL, "pcie", &clk_pcie),
127 +};
128 +
129 #define HSSPI_PLL_HZ_6328 133333333
130 #define HSSPI_PLL_HZ_6362 400000000
131
132 @@ -568,6 +597,10 @@ static int __init bcm63xx_clk_init(void)
133 case BCM6368_CPU_ID:
134 clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
135 break;
136 + case BCM63268_CPU_ID:
137 + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
138 + clkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks));
139 + break;
140 }
141
142 return 0;
143 --- a/arch/mips/bcm63xx/cpu.c
144 +++ b/arch/mips/bcm63xx/cpu.c
145 @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
146
147 };
148
149 +static const unsigned long bcm63268_regs_base[] = {
150 + __GEN_CPU_REGS_TABLE(63268)
151 +};
152 +
153 +static const int bcm63268_irqs[] = {
154 + __GEN_CPU_IRQ_TABLE(63268)
155 +
156 +};
157 +
158 u32 bcm63xx_get_cpu_variant(void)
159 {
160 return bcm63xx_cpu_variant;
161 @@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi
162
163 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
164 }
165 + case BCM63268_CPU_ID:
166 + {
167 + unsigned int tmp, mips_pll_fcvo;
168 +
169 + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
170 + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
171 + STRAPBUS_63268_FCVO_SHIFT;
172 + switch (mips_pll_fcvo) {
173 + case 0x3:
174 + case 0xe:
175 + return 320000000;
176 + case 0xa:
177 + return 333000000;
178 + case 0x2:
179 + case 0xb:
180 + case 0xf:
181 + return 400000000;
182 + default:
183 + return 0;
184 + }
185 + }
186
187 default:
188 panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
189 @@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v
190 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
191 u32 val;
192
193 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
194 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
195 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
196
197 if (BCMCPU_IS_6345()) {
198 @@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void)
199 unsigned int tmp;
200 unsigned int cpu = smp_processor_id();
201 u32 chipid_reg;
202 + bool long_chipid = false;
203 u8 __maybe_unused varid = 0;
204
205 /* soc registers location depends on cpu type */
206 @@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void)
207 case 0x10:
208 chipid_reg = BCM_6345_PERF_BASE;
209 break;
210 + case 0x80:
211 + long_chipid = true;
212 + /* fall-through */
213 default:
214 chipid_reg = BCM_6368_PERF_BASE;
215 break;
216 @@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void)
217 break;
218 }
219
220 +
221 /*
222 * really early to panic, but delaying panic would not help since we
223 * will never get any working console
224 @@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void)
225
226 /* read out CPU type */
227 tmp = bcm_readl(chipid_reg);
228 - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
229 - bcm63xx_cpu_variant = bcm63xx_cpu_id;
230 +
231 + if (long_chipid) {
232 + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
233 + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
234 + } else {
235 + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
236 + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
237 + }
238 +
239 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
240 - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
241 + bcm63xx_cpu_variant = bcm63xx_cpu_id;
242
243 switch (bcm63xx_cpu_id) {
244 case BCM3368_CPU_ID:
245 @@ -400,6 +442,16 @@ void __init bcm63xx_cpu_init(void)
246 /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
247 bcm63xx_cpu_id = BCM6368_CPU_ID;
248 break;
249 + case BCM63167_CPU_ID:
250 + case BCM63168_CPU_ID:
251 + case BCM63169_CPU_ID:
252 + case BCM63268_CPU_ID:
253 + case BCM63269_CPU_ID:
254 + bcm63xx_regs_base = bcm63268_regs_base;
255 + bcm63xx_irqs = bcm63268_irqs;
256 +
257 + bcm63xx_cpu_id = BCM63268_CPU_ID;
258 + break;
259 default:
260 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
261 break;
262 --- a/arch/mips/bcm63xx/dev-flash.c
263 +++ b/arch/mips/bcm63xx/dev-flash.c
264 @@ -84,6 +84,12 @@ static int __init bcm63xx_detect_flash_t
265 return BCM63XX_FLASH_TYPE_SERIAL;
266 else
267 return BCM63XX_FLASH_TYPE_NAND;
268 + case BCM63268_CPU_ID:
269 + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
270 + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
271 + return BCM63XX_FLASH_TYPE_SERIAL;
272 + else
273 + return BCM63XX_FLASH_TYPE_NAND;
274 case BCM6368_CPU_ID:
275 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
276 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
277 --- a/arch/mips/bcm63xx/dev-spi.c
278 +++ b/arch/mips/bcm63xx/dev-spi.c
279 @@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void)
280 }
281
282 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
283 - BCMCPU_IS_6368()) {
284 + BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
285 bcm63xx_spi_device.name = "bcm6358-spi",
286 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
287 }
288 --- a/arch/mips/bcm63xx/irq.c
289 +++ b/arch/mips/bcm63xx/irq.c
290 @@ -149,6 +149,20 @@ void __init arch_init_irq(void)
291 ext_irqs[5] = BCM_6368_EXT_IRQ5;
292 ext_shift = 4;
293 break;
294 + case BCM63268_CPU_ID:
295 + periph_bases[0] += PERF_IRQMASK_63268_REG(0);
296 + periph_bases[1] += PERF_IRQMASK_63268_REG(1);
297 + periph_irq_count = 2;
298 + periph_width = 4;
299 +
300 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
301 + ext_irq_count = 4;
302 + ext_irqs[0] = BCM_63268_EXT_IRQ0;
303 + ext_irqs[1] = BCM_63268_EXT_IRQ1;
304 + ext_irqs[2] = BCM_63268_EXT_IRQ2;
305 + ext_irqs[3] = BCM_63268_EXT_IRQ3;
306 + ext_shift = 4;
307 + break;
308 default:
309 BUG();
310 }
311 --- a/arch/mips/bcm63xx/reset.c
312 +++ b/arch/mips/bcm63xx/reset.c
313 @@ -126,6 +126,20 @@
314 #define BCM6368_RESET_PCIE 0
315 #define BCM6368_RESET_PCIE_EXT 0
316
317 +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
318 +#define BCM63268_RESET_ENET 0
319 +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK
320 +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK
321 +#define BCM63268_RESET_DSL 0
322 +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK
323 +#define BCM63268_RESET_EPHY 0
324 +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
325 +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
326 +#define BCM63268_RESET_MPI 0
327 +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
328 + SOFTRESET_63268_PCIE_CORE_MASK)
329 +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
330 +
331 /*
332 * core reset bits
333 */
334 @@ -157,6 +171,10 @@ static const u32 bcm6368_reset_bits[] =
335 __GEN_RESET_BITS_TABLE(6368)
336 };
337
338 +static const u32 bcm63268_reset_bits[] = {
339 + __GEN_RESET_BITS_TABLE(63268)
340 +};
341 +
342 const u32 *bcm63xx_reset_bits;
343 static int reset_reg;
344
345 @@ -183,6 +201,9 @@ static int __init bcm63xx_reset_bits_ini
346 } else if (BCMCPU_IS_6368()) {
347 reset_reg = PERF_SOFTRESET_6368_REG;
348 bcm63xx_reset_bits = bcm6368_reset_bits;
349 + } else if (BCMCPU_IS_63268()) {
350 + reset_reg = PERF_SOFTRESET_63268_REG;
351 + bcm63xx_reset_bits = bcm63268_reset_bits;
352 }
353
354 return 0;
355 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
356 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
357 @@ -22,6 +22,11 @@
358 #define BCM6362_CPU_ID 0x6362
359 #define BCM6368_CPU_ID 0x6368
360 #define BCM6369_CPU_ID 0x6369
361 +#define BCM63167_CPU_ID 0x63167
362 +#define BCM63168_CPU_ID 0x63168
363 +#define BCM63169_CPU_ID 0x63169
364 +#define BCM63268_CPU_ID 0x63268
365 +#define BCM63269_CPU_ID 0x63269
366
367 void __init bcm63xx_cpu_init(void);
368 u32 bcm63xx_get_cpu_variant(void);
369 @@ -62,6 +67,10 @@ static inline u32 __pure __bcm63xx_get_c
370 #ifdef CONFIG_BCM63XX_CPU_6368
371 case BCM6368_CPU_ID:
372 #endif
373 +
374 +#ifdef CONFIG_BCM63XX_CPU_63268
375 + case BCM63268_CPU_ID:
376 +#endif
377 break;
378 default:
379 unreachable();
380 @@ -87,6 +96,7 @@ static inline u32 __pure bcm63xx_get_cpu
381 #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
382 #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
383 #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
384 +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
385
386 #define BCMCPU_VARIANT_IS_3368() \
387 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
388 @@ -110,6 +120,16 @@ static inline u32 __pure bcm63xx_get_cpu
389 (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
390 #define BCMCPU_VARIANT_IS_6369() \
391 (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
392 +#define BCMCPU_VARIANT_IS_63167() \
393 + (bcm63xx_get_cpu_variant() == BCM63167_CPU_ID)
394 +#define BCMCPU_VARIANT_IS_63168() \
395 + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
396 +#define BCMCPU_VARIANT_IS_63169() \
397 + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
398 +#define BCMCPU_VARIANT_IS_63268() \
399 + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
400 +#define BCMCPU_VARIANT_IS_63269() \
401 + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
402
403 /*
404 * While registers sets are (mostly) the same across 63xx CPU, base
405 @@ -574,6 +594,52 @@ enum bcm63xx_regs_set {
406 #define BCM_6368_RNG_BASE (0xb0004180)
407 #define BCM_6368_MISC_BASE (0xdeadbeef)
408
409 +/*
410 + * 63268 register sets base address
411 + */
412 +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef)
413 +#define BCM_63268_PERF_BASE (0xb0000000)
414 +#define BCM_63268_TIMER_BASE (0xb0000080)
415 +#define BCM_63268_WDT_BASE (0xb000009c)
416 +#define BCM_63268_UART0_BASE (0xb0000180)
417 +#define BCM_63268_UART1_BASE (0xb00001a0)
418 +#define BCM_63268_GPIO_BASE (0xb00000c0)
419 +#define BCM_63268_SPI_BASE (0xb0000800)
420 +#define BCM_63268_HSSPI_BASE (0xb0001000)
421 +#define BCM_63268_UDC0_BASE (0xdeadbeef)
422 +#define BCM_63268_USBDMA_BASE (0xb000c800)
423 +#define BCM_63268_OHCI0_BASE (0xb0002600)
424 +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef)
425 +#define BCM_63268_USBH_PRIV_BASE (0xb0002700)
426 +#define BCM_63268_USBD_BASE (0xb0002400)
427 +#define BCM_63268_MPI_BASE (0xdeadbeef)
428 +#define BCM_63268_PCMCIA_BASE (0xdeadbeef)
429 +#define BCM_63268_PCIE_BASE (0xb06e0000)
430 +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef)
431 +#define BCM_63268_DSL_BASE (0xdeadbeef)
432 +#define BCM_63268_UBUS_BASE (0xdeadbeef)
433 +#define BCM_63268_ENET0_BASE (0xdeadbeef)
434 +#define BCM_63268_ENET1_BASE (0xdeadbeef)
435 +#define BCM_63268_ENETDMA_BASE (0xb000d800)
436 +#define BCM_63268_ENETDMAC_BASE (0xb000da00)
437 +#define BCM_63268_ENETDMAS_BASE (0xb000dc00)
438 +#define BCM_63268_ENETSW_BASE (0xb0700000)
439 +#define BCM_63268_EHCI0_BASE (0xb0002500)
440 +#define BCM_63268_SDRAM_BASE (0xdeadbeef)
441 +#define BCM_63268_MEMC_BASE (0xdeadbeef)
442 +#define BCM_63268_DDR_BASE (0xb0003000)
443 +#define BCM_63268_M2M_BASE (0xdeadbeef)
444 +#define BCM_63268_ATM_BASE (0xdeadbeef)
445 +#define BCM_63268_XTM_BASE (0xb0007000)
446 +#define BCM_63268_XTMDMA_BASE (0xb000b800)
447 +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef)
448 +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef)
449 +#define BCM_63268_PCM_BASE (0xb000b000)
450 +#define BCM_63268_PCMDMA_BASE (0xb000b800)
451 +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef)
452 +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
453 +#define BCM_63268_RNG_BASE (0xdeadbeef)
454 +#define BCM_63268_MISC_BASE (0xb0001800)
455
456 extern const unsigned long *bcm63xx_regs_base;
457
458 @@ -1042,6 +1108,73 @@ enum bcm63xx_irq {
459 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
460 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
461
462 +/*
463 + * 63268 irqs
464 + */
465 +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
466 +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32)
467 +
468 +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
469 +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16)
470 +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5)
471 +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2)
472 +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23)
473 +#define BCM_63268_UDC0_IRQ 0
474 +#define BCM_63268_ENET0_IRQ 0
475 +#define BCM_63268_ENET1_IRQ 0
476 +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13)
477 +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6)
478 +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
479 +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
480 +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
481 +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19)
482 +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4)
483 +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20)
484 +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5)
485 +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21)
486 +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6)
487 +#define BCM_63268_PCMCIA_IRQ 0
488 +#define BCM_63268_ENET0_RXDMA_IRQ 0
489 +#define BCM_63268_ENET0_TXDMA_IRQ 0
490 +#define BCM_63268_ENET1_RXDMA_IRQ 0
491 +#define BCM_63268_ENET1_TXDMA_IRQ 0
492 +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8)
493 +#define BCM_63268_ATM_IRQ 0
494 +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1)
495 +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2)
496 +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3)
497 +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4)
498 +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0)
499 +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1)
500 +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2)
501 +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3)
502 +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17)
503 +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
504 +
505 +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20)
506 +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3)
507 +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
508 +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
509 +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18)
510 +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
511 +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15)
512 +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
513 +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
514 +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
515 +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
516 +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22)
517 +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7)
518 +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24)
519 +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25)
520 +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10)
521 +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11)
522 +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0)
523 +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1)
524 +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12)
525 +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13)
526 +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14)
527 +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15)
528 +
529 extern const int *bcm63xx_irqs;
530
531 #define __GEN_CPU_IRQ_TABLE(__cpu) \
532 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
533 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
534 @@ -23,6 +23,8 @@ static inline unsigned long bcm63xx_gpio
535 return 48;
536 case BCM6368_CPU_ID:
537 return 38;
538 + case BCM63268_CPU_ID:
539 + return 52;
540 case BCM6348_CPU_ID:
541 default:
542 return 37;
543 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
544 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
545 @@ -10,6 +10,8 @@
546 #define PERF_REV_REG 0x0
547 #define REV_CHIPID_SHIFT 16
548 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
549 +#define REV_LONG_CHIPID_SHIFT 12
550 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
551 #define REV_VARID_SHIFT 12
552 #define REV_VARID_MASK (0xf << REV_VARID_SHIFT)
553 #define REV_REVID_SHIFT 0
554 @@ -212,6 +214,52 @@
555 CKCTL_6368_NAND_EN | \
556 CKCTL_6368_IPSEC_EN)
557
558 +#define CKCTL_63268_DISABLE_GLESS (1 << 0)
559 +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1)
560 +#define CKCTL_63268_VDSL_AFE_EN (1 << 2)
561 +#define CKCTL_63268_VDSL_EN (1 << 3)
562 +#define CKCTL_63268_MIPS_EN (1 << 4)
563 +#define CKCTL_63268_WLAN_OCP_EN (1 << 5)
564 +#define CKCTL_63268_DECT_EN (1 << 6)
565 +#define CKCTL_63268_FAP0_EN (1 << 7)
566 +#define CKCTL_63268_FAP1_EN (1 << 8)
567 +#define CKCTL_63268_SAR_EN (1 << 9)
568 +#define CKCTL_63268_ROBOSW_EN (1 << 10)
569 +#define CKCTL_63268_PCM_EN (1 << 11)
570 +#define CKCTL_63268_USBD_EN (1 << 12)
571 +#define CKCTL_63268_USBH_EN (1 << 13)
572 +#define CKCTL_63268_IPSEC_EN (1 << 14)
573 +#define CKCTL_63268_SPI_EN (1 << 15)
574 +#define CKCTL_63268_HSSPI_EN (1 << 16)
575 +#define CKCTL_63268_PCIE_EN (1 << 17)
576 +#define CKCTL_63268_PHYMIPS_EN (1 << 18)
577 +#define CKCTL_63268_GMAC_EN (1 << 19)
578 +#define CKCTL_63268_NAND_EN (1 << 20)
579 +#define CKCTL_63268_TBUS_EN (1 << 27)
580 +#define CKCTL_63268_ROBOSW250_EN (1 << 31)
581 +
582 +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \
583 + CKCTL_63268_VDSL_AFE_EN | \
584 + CKCTL_63268_VDSL_EN | \
585 + CKCTL_63268_WLAN_OCP_EN | \
586 + CKCTL_63268_DECT_EN | \
587 + CKCTL_63268_FAP0_EN | \
588 + CKCTL_63268_FAP1_EN | \
589 + CKCTL_63268_SAR_EN | \
590 + CKCTL_63268_ROBOSW_EN | \
591 + CKCTL_63268_PCM_EN | \
592 + CKCTL_63268_USBD_EN | \
593 + CKCTL_63268_USBH_EN | \
594 + CKCTL_63268_IPSEC_EN | \
595 + CKCTL_63268_SPI_EN | \
596 + CKCTL_63268_HSSPI_EN | \
597 + CKCTL_63268_PCIE_EN | \
598 + CKCTL_63268_PHYMIPS_EN | \
599 + CKCTL_63268_GMAC_EN | \
600 + CKCTL_63268_NAND_EN | \
601 + CKCTL_63268_TBUS_EN | \
602 + CKCTL_63268_ROBOSW250_EN)
603 +
604 /* System PLL Control register */
605 #define PERF_SYS_PLL_CTL_REG 0x8
606 #define SYS_PLL_SOFT_RESET 0x1
607 @@ -225,6 +273,7 @@
608 #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
609 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
610 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
611 +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20)
612
613 /* Interrupt Status register */
614 #define PERF_IRQSTAT_3368_REG 0x10
615 @@ -235,6 +284,7 @@
616 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
617 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
618 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
619 +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20)
620
621 /* External Interrupt Configuration register */
622 #define PERF_EXTIRQ_CFG_REG_3368 0x14
623 @@ -245,6 +295,7 @@
624 #define PERF_EXTIRQ_CFG_REG_6358 0x14
625 #define PERF_EXTIRQ_CFG_REG_6362 0x18
626 #define PERF_EXTIRQ_CFG_REG_6368 0x18
627 +#define PERF_EXTIRQ_CFG_REG_63268 0x18
628
629 #define PERF_EXTIRQ_CFG_REG2_6358 0x1c
630 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
631 @@ -275,6 +326,7 @@
632 #define PERF_SOFTRESET_6358_REG 0x34
633 #define PERF_SOFTRESET_6362_REG 0x10
634 #define PERF_SOFTRESET_6368_REG 0x10
635 +#define PERF_SOFTRESET_63268_REG 0x10
636
637 #define SOFTRESET_3368_SPI_MASK (1 << 0)
638 #define SOFTRESET_3368_ENET_MASK (1 << 2)
639 @@ -368,6 +420,26 @@
640 #define SOFTRESET_6368_USBH_MASK (1 << 12)
641 #define SOFTRESET_6368_PCM_MASK (1 << 13)
642
643 +#define SOFTRESET_63268_SPI_MASK (1 << 0)
644 +#define SOFTRESET_63268_IPSEC_MASK (1 << 1)
645 +#define SOFTRESET_63268_EPHY_MASK (1 << 2)
646 +#define SOFTRESET_63268_SAR_MASK (1 << 3)
647 +#define SOFTRESET_63268_ENETSW_MASK (1 << 4)
648 +#define SOFTRESET_63268_USBS_MASK (1 << 5)
649 +#define SOFTRESET_63268_USBH_MASK (1 << 6)
650 +#define SOFTRESET_63268_PCM_MASK (1 << 7)
651 +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8)
652 +#define SOFTRESET_63268_PCIE_MASK (1 << 9)
653 +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10)
654 +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11)
655 +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12)
656 +#define SOFTRESET_63268_FAP0_MASK (1 << 13)
657 +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14)
658 +#define SOFTRESET_63268_DECT_MASK (1 << 15)
659 +#define SOFTRESET_63268_FAP1_MASK (1 << 16)
660 +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17)
661 +#define SOFTRESET_63268_GPHY_MASK (1 << 18)
662 +
663 /* MIPS PLL control register */
664 #define PERF_MIPSPLLCTL_REG 0x34
665 #define MIPSPLLCTL_N1_SHIFT 20
666 @@ -1367,6 +1439,13 @@
667 #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
668 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
669
670 +#define MISC_STRAPBUS_63268_REG 0x14
671 +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9)
672 +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11)
673 +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11)
674 +#define STRAPBUS_63268_FCVO_SHIFT 21
675 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
676 +
677 #define MISC_STRAPBUS_6328_REG 0x240
678 #define STRAPBUS_6328_FCVO_SHIFT 7
679 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
680 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
681 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
682 @@ -26,6 +26,7 @@ static inline int is_bcm63xx_internal_re
683 case BCM6328_CPU_ID:
684 case BCM6362_CPU_ID:
685 case BCM6368_CPU_ID:
686 + case BCM63268_CPU_ID:
687 if (offset >= 0xb0000000 && offset < 0xb1000000)
688 return 1;
689 break;
690 --- a/arch/mips/bcm63xx/dev-hsspi.c
691 +++ b/arch/mips/bcm63xx/dev-hsspi.c
692 @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
693
694 int __init bcm63xx_hsspi_register(void)
695 {
696 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
697 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
698 return -ENODEV;
699
700 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
701 --- a/arch/mips/bcm63xx/dev-enet.c
702 +++ b/arch/mips/bcm63xx/dev-enet.c
703 @@ -184,7 +184,8 @@ static int __init register_shared(void)
704 else
705 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
706
707 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
708 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
709 + BCMCPU_IS_63268())
710 chan_count = 32;
711 else if (BCMCPU_IS_6345())
712 chan_count = 8;
713 @@ -292,7 +293,8 @@ bcm63xx_enetsw_register(const struct bcm
714 {
715 int ret;
716
717 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
718 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
719 + !BCMCPU_IS_63268())
720 return -ENODEV;
721
722 ret = register_shared();
723 @@ -313,6 +315,8 @@ bcm63xx_enetsw_register(const struct bcm
724 enetsw_pd.num_ports = ENETSW_PORTS_6328;
725 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
726 enetsw_pd.num_ports = ENETSW_PORTS_6368;
727 + else if (BCMCPU_IS_63268())
728 + enetsw_pd.num_ports = ENETSW_PORTS_63268;
729
730 enetsw_pd.dma_has_sram = true;
731 enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
732 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
733 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
734 @@ -67,6 +67,7 @@ struct bcm63xx_enet_platform_data {
735 #define ENETSW_MAX_PORT 8
736 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
737 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
738 +#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */
739
740 #define ENETSW_RGMII_PORT0 4
741
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