04df06c0db7bebb2eb4e215ad866e0ca9dc1ff6a
[openwrt/staging/chunkeey.git] / target / linux / bmips / dts / bcm6362.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /dts-v1/;
4
5 #include <dt-bindings/clock/bcm6362-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm6362-reset.h>
10 #include <dt-bindings/soc/bcm6362-pm.h>
11
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "brcm,bcm6362";
16
17 aliases {
18 nflash = &nflash;
19 pinctrl = &pinctrl;
20 serial0 = &uart0;
21 serial1 = &uart1;
22 spi0 = &lsspi;
23 spi1 = &hsspi;
24 };
25
26 chosen {
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
29 };
30
31 clocks {
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
34
35 #clock-cells = <0>;
36
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
39 };
40
41 hsspi_osc: hsspi-osc {
42 compatible = "fixed-clock";
43
44 #clock-cells = <0>;
45
46 clock-frequency = <400000000>;
47 clock-output-names = "hsspi_osc";
48 };
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 mips-hpt-frequency = <200000000>;
55
56 cpu@0 {
57 compatible = "brcm,bmips4350", "mips,mips4Kc";
58 device_type = "cpu";
59 reg = <0>;
60 };
61
62 cpu@1 {
63 compatible = "brcm,bmips4350", "mips,mips4Kc";
64 device_type = "cpu";
65 reg = <1>;
66 };
67 };
68
69 cpu_intc: interrupt-controller {
70 #address-cells = <0>;
71 compatible = "mti,cpu-interrupt-controller";
72
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 };
76
77 memory@0 {
78 device_type = "memory";
79 reg = <0 0>;
80 };
81
82 ubus {
83 #address-cells = <1>;
84 #size-cells = <1>;
85
86 compatible = "simple-bus";
87 ranges;
88
89 periph_clk: clock-controller@10000004 {
90 compatible = "brcm,bcm6362-clocks";
91 reg = <0x10000004 0x4>;
92 #clock-cells = <1>;
93 };
94
95 pll_cntl: syscon@10000008 {
96 compatible = "syscon", "simple-mfd";
97 reg = <0x10000008 0x4>;
98 native-endian;
99
100 syscon-reboot {
101 compatible = "syscon-reboot";
102 offset = <0x0>;
103 mask = <0x1>;
104 };
105 };
106
107 periph_rst: reset-controller@10000010 {
108 compatible = "brcm,bcm6345-reset";
109 reg = <0x10000010 0x4>;
110 #reset-cells = <1>;
111 };
112
113 ext_intc: interrupt-controller@10000018 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-ext-intc";
116 reg = <0x10000018 0x4>;
117
118 interrupt-controller;
119 #interrupt-cells = <2>;
120
121 interrupts = <BCM6362_IRQ_EXT0>,
122 <BCM6362_IRQ_EXT1>,
123 <BCM6362_IRQ_EXT2>,
124 <BCM6362_IRQ_EXT3>;
125 };
126
127 periph_intc: interrupt-controller@10000020 {
128 #address-cells = <1>;
129 compatible = "brcm,bcm6345-l1-intc";
130 reg = <0x10000020 0x10>,
131 <0x10000030 0x10>;
132
133 interrupt-controller;
134 #interrupt-cells = <1>;
135
136 interrupt-parent = <&cpu_intc>;
137 interrupts = <2>, <3>;
138 };
139
140 wdt: watchdog@1000005c {
141 compatible = "brcm,bcm7038-wdt";
142 reg = <0x1000005c 0xc>;
143
144 clocks = <&periph_osc>;
145
146 timeout-sec = <30>;
147 };
148
149 gpio: syscon@10000080 {
150 compatible = "syscon", "simple-mfd";
151 reg = <0x10000080 0x80>;
152 native-endian;
153
154 pinctrl: pin-controller {
155 compatible = "brcm,bcm6362-pinctrl";
156
157 gpio-controller;
158 #gpio-cells = <2>;
159
160 interrupts-extended = <&ext_intc 0 0>,
161 <&ext_intc 1 0>,
162 <&ext_intc 2 0>,
163 <&ext_intc 3 0>;
164 interrupt-names = "gpio24",
165 "gpio25",
166 "gpio26",
167 "gpio27";
168
169 pinctrl_usb_device_led: usb_device_led {
170 function = "usb_device_led";
171 pins = "gpio0";
172 };
173
174 pinctrl_sys_irq: sys_irq {
175 function = "sys_irq";
176 pins = "gpio1";
177 };
178
179 pinctrl_serial_led: serial_led {
180 pinctrl_serial_led_clk: serial_led_clk {
181 function = "serial_led_clk";
182 pins = "gpio2";
183 };
184
185 pinctrl_serial_led_data: serial_led_data {
186 function = "serial_led_data";
187 pins = "gpio3";
188 };
189 };
190
191 pinctrl_robosw_led_data: robosw_led_data {
192 function = "robosw_led_data";
193 pins = "gpio4";
194 };
195
196 pinctrl_robosw_led_clk: robosw_led_clk {
197 function = "robosw_led_clk";
198 pins = "gpio5";
199 };
200
201 pinctrl_robosw_led0: robosw_led0 {
202 function = "robosw_led0";
203 pins = "gpio6";
204 };
205
206 pinctrl_robosw_led1: robosw_led1 {
207 function = "robosw_led1";
208 pins = "gpio7";
209 };
210
211 pinctrl_inet_led: inet_led {
212 function = "inet_led";
213 pins = "gpio8";
214 };
215
216 pinctrl_spi_cs2: spi_cs2 {
217 function = "spi_cs2";
218 pins = "gpio9";
219 };
220
221 pinctrl_spi_cs3: spi_cs3 {
222 function = "spi_cs3";
223 pins = "gpio10";
224 };
225
226 pinctrl_ntr_pulse: ntr_pulse {
227 function = "ntr_pulse";
228 pins = "gpio11";
229 };
230
231 pinctrl_uart1_scts: uart1_scts {
232 function = "uart1_scts";
233 pins = "gpio12";
234 };
235
236 pinctrl_uart1_srts: uart1_srts {
237 function = "uart1_srts";
238 pins = "gpio13";
239 };
240
241 pinctrl_uart1: uart1 {
242 pinctrl_uart1_sdin: uart1_sdin {
243 function = "uart1_sdin";
244 pins = "gpio14";
245 };
246
247 pinctrl_uart1_sdout: uart1_sdout {
248 function = "uart1_sdout";
249 pins = "gpio15";
250 };
251 };
252
253 pinctrl_adsl_spi: adsl_spi {
254 pinctrl_adsl_spi_miso: adsl_spi_miso {
255 function = "adsl_spi_miso";
256 pins = "gpio16";
257 };
258
259 pinctrl_adsl_spi_mosi: adsl_spi_mosi {
260 function = "adsl_spi_mosi";
261 pins = "gpio17";
262 };
263
264 pinctrl_adsl_spi_clk: adsl_spi_clk {
265 function = "adsl_spi_clk";
266 pins = "gpio18";
267 };
268
269 pinctrl_adsl_spi_cs: adsl_spi_cs {
270 function = "adsl_spi_cs";
271 pins = "gpio19";
272 };
273 };
274
275 pinctrl_ephy0_led: ephy0_led {
276 function = "ephy0_led";
277 pins = "gpio20";
278 };
279
280 pinctrl_ephy1_led: ephy1_led {
281 function = "ephy1_led";
282 pins = "gpio21";
283 };
284
285 pinctrl_ephy2_led: ephy2_led {
286 function = "ephy2_led";
287 pins = "gpio22";
288 };
289
290 pinctrl_ephy3_led: ephy3_led {
291 function = "ephy3_led";
292 pins = "gpio23";
293 };
294
295 pinctrl_ext_irq0: ext_irq0 {
296 function = "ext_irq0";
297 pins = "gpio24";
298 };
299
300 pinctrl_ext_irq1: ext_irq1 {
301 function = "ext_irq1";
302 pins = "gpio25";
303 };
304
305 pinctrl_ext_irq2: ext_irq2 {
306 function = "ext_irq2";
307 pins = "gpio26";
308 };
309
310 pinctrl_ext_irq3: ext_irq3 {
311 function = "ext_irq3";
312 pins = "gpio27";
313 };
314
315 pinctrl_nand: nand {
316 function = "nand";
317 group = "nand_grp";
318 };
319 };
320 };
321
322 uart0: serial@10000100 {
323 compatible = "brcm,bcm6345-uart";
324 reg = <0x10000100 0x18>;
325
326 interrupt-parent = <&periph_intc>;
327 interrupts = <BCM6362_IRQ_UART0>;
328
329 clocks = <&periph_osc>;
330 clock-names = "periph";
331
332 status = "disabled";
333 };
334
335 uart1: serial@10000120 {
336 compatible = "brcm,bcm6345-uart";
337 reg = <0x10000120 0x18>;
338
339 interrupt-parent = <&periph_intc>;
340 interrupts = <BCM6362_IRQ_UART1>;
341
342 clocks = <&periph_osc>;
343 clock-names = "periph";
344
345 status = "disabled";
346 };
347
348 nflash: nand@10000200 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 compatible = "brcm,nand-bcm6368",
352 "brcm,brcmnand-v2.2",
353 "brcm,brcmnand";
354 reg = <0x10000200 0x180>,
355 <0x10000600 0x200>,
356 <0x10000070 0x10>;
357 reg-names = "nand",
358 "nand-cache",
359 "nand-int-base";
360
361 interrupt-parent = <&periph_intc>;
362 interrupts = <BCM6362_IRQ_NAND>;
363
364 clocks = <&periph_clk BCM6362_CLK_NAND>;
365 clock-names = "nand";
366
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_nand>;
369
370 status = "disabled";
371 };
372
373 lsspi: spi@10000800 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 compatible = "brcm,bcm6358-spi";
377 reg = <0x10000800 0x70c>;
378
379 interrupt-parent = <&periph_intc>;
380 interrupts = <BCM6362_IRQ_LSSPI>;
381
382 clocks = <&periph_clk BCM6362_CLK_SPI>;
383 clock-names = "spi";
384
385 resets = <&periph_rst BCM6362_RST_SPI>;
386
387 status = "disabled";
388 };
389
390 hsspi: spi@10001000 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "brcm,bcm6328-hsspi";
394 reg = <0x10001000 0x600>;
395
396 interrupt-parent = <&periph_intc>;
397 interrupts = <BCM6362_IRQ_HSSPI>;
398
399 clocks = <&periph_clk BCM6362_CLK_HSSPI>,
400 <&hsspi_osc>;
401 clock-names = "hsspi",
402 "pll";
403
404 resets = <&periph_rst BCM6362_RST_SPI>;
405
406 status = "disabled";
407 };
408
409 serdes_cntl: syscon@10001804 {
410 compatible = "syscon";
411 reg = <0x10001804 0x4>;
412 native-endian;
413 };
414
415 periph_pwr: power-controller@10001848 {
416 compatible = "brcm,bcm6362-power-controller";
417 reg = <0x10001848 0x4>;
418 #power-domain-cells = <1>;
419 };
420
421 leds: led-controller@10001900 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 compatible = "brcm,bcm6328-leds";
425 reg = <0x10001900 0x24>;
426
427 status = "disabled";
428 };
429
430 ehci: usb@10002500 {
431 compatible = "brcm,bcm6362-ehci", "generic-ehci";
432 reg = <0x10002500 0x100>;
433 big-endian;
434 spurious-oc;
435
436 interrupt-parent = <&periph_intc>;
437 interrupts = <BCM6362_IRQ_EHCI>;
438
439 phys = <&usbh 0>;
440 phy-names = "usb";
441
442 status = "disabled";
443 };
444
445 ohci: usb@10002600 {
446 compatible = "brcm,bcm6362-ohci", "generic-ohci";
447 reg = <0x10002600 0x100>;
448 big-endian;
449 no-big-frame-no;
450
451 interrupt-parent = <&periph_intc>;
452 interrupts = <BCM6362_IRQ_OHCI>;
453
454 phys = <&usbh 0>;
455 phy-names = "usb";
456
457 status = "disabled";
458 };
459
460 usbh: usb-phy@10002700 {
461 compatible = "brcm,bcm6362-usbh-phy";
462 reg = <0x10002700 0x38>;
463
464 #phy-cells = <1>;
465
466 clocks = <&periph_clk BCM6362_CLK_USBH>;
467 clock-names = "usbh";
468
469 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
470 resets = <&periph_rst BCM6362_RST_USBH>;
471
472 status = "disabled";
473 };
474
475 ethernet: ethernet@1000d800 {
476 compatible = "brcm,bcm6362-enetsw";
477 reg = <0x1000d800 0x80>,
478 <0x1000da00 0x80>,
479 <0x1000dc00 0x80>;
480 reg-names = "dma",
481 "dma-channels",
482 "dma-sram";
483
484 interrupt-parent = <&periph_intc>;
485 interrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;
486 interrupt-names = "rx";
487
488 clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
489 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
490 <&periph_clk BCM6362_CLK_ROBOSW>;
491
492 resets = <&periph_rst BCM6362_RST_ENETSW>,
493 <&periph_rst BCM6362_RST_EPHY>;
494
495 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,
496 <&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;
497
498 dma-rx = <0>;
499 dma-tx = <1>;
500
501 status = "disabled";
502 };
503
504 switch0: switch@10e00000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "brcm,bcm6328-switch";
508 reg = <0x10e00000 0x8000>;
509 big-endian;
510
511 ports {
512 #address-cells = <1>;
513 #size-cells = <0>;
514
515 port@8 {
516 reg = <8>;
517 label = "cpu";
518
519 phy-mode = "internal";
520 ethernet = <&ethernet>;
521
522 fixed-link {
523 speed = <1000>;
524 full-duplex;
525 };
526 };
527 };
528 };
529
530 mdio: mdio@10e000b0 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "brcm,bcm6368-mdio-mux";
534 reg = <0x10e000b0 0x8>;
535
536 mdio_int: mdio@0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 reg = <0>;
540
541 phy1: ethernet-phy@1 {
542 compatible = "ethernet-phy-ieee802.3-c22";
543 reg = <1>;
544 };
545
546 phy2: ethernet-phy@2 {
547 compatible = "ethernet-phy-ieee802.3-c22";
548 reg = <2>;
549 };
550
551 phy3: ethernet-phy@3 {
552 compatible = "ethernet-phy-ieee802.3-c22";
553 reg = <3>;
554 };
555
556 phy4: ethernet-phy@4 {
557 compatible = "ethernet-phy-ieee802.3-c22";
558 reg = <4>;
559 };
560 };
561
562 mdio_ext: mdio@1 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 reg = <1>;
566 };
567 };
568
569 pcie: pcie@10e40000 {
570 compatible = "brcm,bcm6328-pcie";
571 reg = <0x10e40000 0x10000>;
572 #address-cells = <3>;
573 #size-cells = <2>;
574
575 device_type = "pci";
576 bus-range = <0x00 0x01>;
577 ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
578 linux,pci-probe-only = <1>;
579
580 interrupt-parent = <&periph_intc>;
581 interrupts = <BCM6362_IRQ_PCIE_RC>;
582
583 clocks = <&periph_clk BCM6362_CLK_PCIE>;
584 clock-names = "pcie";
585
586 resets = <&periph_rst BCM6362_RST_PCIE>,
587 <&periph_rst BCM6362_RST_PCIE_EXT>,
588 <&periph_rst BCM6362_RST_PCIE_CORE>;
589 reset-names = "pcie",
590 "pcie-ext",
591 "pcie-core";
592
593 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
594
595 brcm,serdes = <&serdes_cntl>;
596
597 status = "disabled";
598 };
599 };
600 };