target/linux/bmips/patches-5.10/408-Documentation-add-BCM63268-pincontroller-binding-doc.patch

   1 From 826266914f8397c996d2d4d821b315d614bfc325 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Wed, 27 Jul 2016 11:37:08 +0200
   4 Subject: [PATCH 09/12] Documentation: add BCM63268 pincontroller binding
   5  documentation
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Add binding documentation for the pincontrol core found in the BCM63268
  11 family SoCs.
  12
  13 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  14 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  15 ---
  16  .../pinctrl/brcm,bcm63268-pinctrl.yaml        | 198 ++++++++++++++++++
  17  1 file changed, 198 insertions(+)
  18  create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
  19
  20 --- /dev/null
  21 +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
  22 @@ -0,0 +1,198 @@
  23 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  24 +%YAML 1.2
  25 +---
  26 +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
  27 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  28 +
  29 +title: Broadcom BCM63268 pin controller
  30 +
  31 +maintainers:
  32 +  - Álvaro Fernández Rojas <noltari@gmail.com>
  33 +  - Jonas Gorski <jonas.gorski@gmail.com>
  34 +
  35 +description: |+
  36 +  The pin controller node should be the child of a syscon node.
  37 +
  38 +  Refer to the the bindings described in
  39 +  Documentation/devicetree/bindings/mfd/syscon.yaml
  40 +
  41 +properties:
  42 +  compatible:
  43 +    const: brcm,bcm63268-pinctrl
  44 +
  45 +  gpio-controller: true
  46 +
  47 +  '#gpio-cells':
  48 +    description:
  49 +      Specifies the pin number and flags, as defined in
  50 +      include/dt-bindings/gpio/gpio.h
  51 +    const: 2
  52 +
  53 +  interrupts-extended:
  54 +    description:
  55 +      One interrupt per each of the 4 GPIO ports supported by the controller,
  56 +      sorted by port number ascending order.
  57 +    minItems: 4
  58 +    maxItems: 4
  59 +
  60 +patternProperties:
  61 +  '^.*$':
  62 +    if:
  63 +      type: object
  64 +    then:
  65 +      properties:
  66 +        function:
  67 +          $ref: "/schemas/types.yaml#/definitions/string"
  68 +          enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
  69 +                  hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
  70 +                  vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
  71 +                  nand, gpio35_alt, dectpd, vdsl_phy_override_0,
  72 +                  vdsl_phy_override_1, vdsl_phy_override_2,
  73 +                  vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
  74 +
  75 +        pins:
  76 +          $ref: "/schemas/types.yaml#/definitions/string"
  77 +          enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
  78 +                  gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
  79 +                  dectpd_grp, vdsl_phy_override_0_grp,
  80 +                  vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
  81 +                  vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
  82 +
  83 +required:
  84 +  - compatible
  85 +  - gpio-controller
  86 +  - '#gpio-cells'
  87 +
  88 +additionalProperties: false
  89 +
  90 +examples:
  91 +  - |
  92 +    gpio@100000c0 {
  93 +      compatible = "syscon", "simple-mfd";
  94 +      reg = <0x100000c0 0x80>;
  95 +
  96 +      pinctrl: pinctrl {
  97 +        compatible = "brcm,bcm63268-pinctrl";
  98 +
  99 +        gpio-controller;
 100 +        #gpio-cells = <2>;
 101 +
 102 +        interrupts-extended = <&ext_intc 0 0>,
 103 +                              <&ext_intc 1 0>,
 104 +                              <&ext_intc 2 0>,
 105 +                              <&ext_intc 3 0>;
 106 +        interrupt-names = "gpio32",
 107 +                          "gpio33",
 108 +                          "gpio34",
 109 +                          "gpio35";
 110 +
 111 +        pinctrl_serial_led: serial_led {
 112 +          pinctrl_serial_led_clk: serial_led_clk {
 113 +            function = "serial_led_clk";
 114 +            pins = "gpio0";
 115 +          };
 116 +
 117 +          pinctrl_serial_led_data: serial_led_data {
 118 +            function = "serial_led_data";
 119 +            pins = "gpio1";
 120 +          };
 121 +        };
 122 +
 123 +        pinctrl_hsspi_cs4: hsspi_cs4 {
 124 +          function = "hsspi_cs4";
 125 +          pins = "gpio16";
 126 +        };
 127 +
 128 +        pinctrl_hsspi_cs5: hsspi_cs5 {
 129 +          function = "hsspi_cs5";
 130 +          pins = "gpio17";
 131 +        };
 132 +
 133 +        pinctrl_hsspi_cs6: hsspi_cs6 {
 134 +          function = "hsspi_cs6";
 135 +          pins = "gpio8";
 136 +        };
 137 +
 138 +        pinctrl_hsspi_cs7: hsspi_cs7 {
 139 +          function = "hsspi_cs7";
 140 +          pins = "gpio9";
 141 +        };
 142 +
 143 +        pinctrl_adsl_spi: adsl_spi {
 144 +          pinctrl_adsl_spi_miso: adsl_spi_miso {
 145 +            function = "adsl_spi_miso";
 146 +            pins = "gpio18";
 147 +          };
 148 +
 149 +          pinctrl_adsl_spi_mosi: adsl_spi_mosi {
 150 +            function = "adsl_spi_mosi";
 151 +            pins = "gpio19";
 152 +          };
 153 +        };
 154 +
 155 +        pinctrl_vreq_clk: vreq_clk {
 156 +          function = "vreq_clk";
 157 +          pins = "gpio22";
 158 +        };
 159 +
 160 +        pinctrl_pcie_clkreq_b: pcie_clkreq_b {
 161 +          function = "pcie_clkreq_b";
 162 +          pins = "gpio23";
 163 +        };
 164 +
 165 +        pinctrl_robosw_led_clk: robosw_led_clk {
 166 +          function = "robosw_led_clk";
 167 +          pins = "gpio30";
 168 +        };
 169 +
 170 +        pinctrl_robosw_led_data: robosw_led_data {
 171 +          function = "robosw_led_data";
 172 +          pins = "gpio31";
 173 +        };
 174 +
 175 +        pinctrl_nand: nand {
 176 +          function = "nand";
 177 +          group = "nand_grp";
 178 +        };
 179 +
 180 +        pinctrl_gpio35_alt: gpio35_alt {
 181 +          function = "gpio35_alt";
 182 +          pin = "gpio35";
 183 +        };
 184 +
 185 +        pinctrl_dectpd: dectpd {
 186 +          function = "dectpd";
 187 +          group = "dectpd_grp";
 188 +        };
 189 +
 190 +        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {
 191 +          function = "vdsl_phy_override_0";
 192 +          group = "vdsl_phy_override_0_grp";
 193 +        };
 194 +
 195 +        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {
 196 +          function = "vdsl_phy_override_1";
 197 +          group = "vdsl_phy_override_1_grp";
 198 +        };
 199 +
 200 +        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {
 201 +          function = "vdsl_phy_override_2";
 202 +          group = "vdsl_phy_override_2_grp";
 203 +        };
 204 +
 205 +        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {
 206 +          function = "vdsl_phy_override_3";
 207 +          group = "vdsl_phy_override_3_grp";
 208 +        };
 209 +
 210 +        pinctrl_dsl_gpio8: dsl_gpio8 {
 211 +          function = "dsl_gpio8";
 212 +          group = "dsl_gpio8";
 213 +        };
 214 +
 215 +        pinctrl_dsl_gpio9: dsl_gpio9 {
 216 +          function = "dsl_gpio9";
 217 +          group = "dsl_gpio9";
 218 +        };
 219 +      };
 220 +    };