target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch

   1 From 67071edadb9965b7c9a36443c5d6e6808dfae8d9 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 12:51:41 +0000
   4 Subject: [PATCH] clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver
   5
   6 As the use of BCM2835_CLOCK_COUNT in
   7 include/dt-bindings/clock/bcm2835.h is frowned upon as
   8 it needs to get modified every time a new clock gets introduced
   9 this patch changes the clk-bcm2835 driver to use a different
  10 scheme for registration of clocks and pll, so that there
  11 is no more need for BCM2835_CLOCK_COUNT to be defined.
  12
  13 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  14 Signed-off-by: Eric Anholt <eric@anholt.net>
  15 Reviewed-by: Eric Anholt <eric@anholt.net>
  16 (cherry picked from commit 56eb3a2ed9726961e1bcfa69d4a3f86d68f0eb52)
  17 ---
  18  drivers/clk/bcm/clk-bcm2835.c       | 167 ++++++++++++++++++++----------------
  19  include/dt-bindings/clock/bcm2835.h |   2 -
  20  2 files changed, 94 insertions(+), 75 deletions(-)
  21
  22 --- a/drivers/clk/bcm/clk-bcm2835.c
  23 +++ b/drivers/clk/bcm/clk-bcm2835.c
  24 @@ -301,7 +301,7 @@ struct bcm2835_cprman {
  25         const char *osc_name;
  26
  27         struct clk_onecell_data onecell;
  28 -       struct clk *clks[BCM2835_CLOCK_COUNT];
  29 +       struct clk *clks[];
  30  };
  31
  32  static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
  33 @@ -853,6 +853,25 @@ static const struct bcm2835_clock_data b
  34         .is_mash_clock = true,
  35  };
  36
  37 +struct bcm2835_gate_data {
  38 +       const char *name;
  39 +       const char *parent;
  40 +
  41 +       u32 ctl_reg;
  42 +};
  43 +
  44 +/*
  45 + * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
  46 + * you have the debug bit set in the power manager, which we
  47 + * don't bother exposing) are individual gates off of the
  48 + * non-stop vpu clock.
  49 + */
  50 +static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
  51 +       .name = "peri_image",
  52 +       .parent = "vpu",
  53 +       .ctl_reg = CM_PERIICTL,
  54 +};
  55 +
  56  struct bcm2835_pll {
  57         struct clk_hw hw;
  58         struct bcm2835_cprman *cprman;
  59 @@ -1666,14 +1685,81 @@ static struct clk *bcm2835_register_cloc
  60         return devm_clk_register(cprman->dev, &clock->hw);
  61  }
  62
  63 +static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
  64 +                                        const struct bcm2835_gate_data *data)
  65 +{
  66 +       return clk_register_gate(cprman->dev, data->name, data->parent,
  67 +                                CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
  68 +                                cprman->regs + data->ctl_reg,
  69 +                                CM_GATE_BIT, 0, &cprman->regs_lock);
  70 +}
  71 +
  72 +typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
  73 +                                           const void *data);
  74 +struct bcm2835_clk_desc {
  75 +       bcm2835_clk_register clk_register;
  76 +       const void *data;
  77 +};
  78 +
  79 +#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
  80 +                         .data = d }
  81 +#define REGISTER_PLL(d)                _REGISTER(&bcm2835_register_pll, d)
  82 +#define REGISTER_PLL_DIV(d)    _REGISTER(&bcm2835_register_pll_divider, d)
  83 +#define REGISTER_CLK(d)                _REGISTER(&bcm2835_register_clock, d)
  84 +#define REGISTER_GATE(d)       _REGISTER(&bcm2835_register_gate, d)
  85 +
  86 +static const struct bcm2835_clk_desc clk_desc_array[] = {
  87 +       /* register PLL */
  88 +       [BCM2835_PLLA]          = REGISTER_PLL(&bcm2835_plla_data),
  89 +       [BCM2835_PLLB]          = REGISTER_PLL(&bcm2835_pllb_data),
  90 +       [BCM2835_PLLC]          = REGISTER_PLL(&bcm2835_pllc_data),
  91 +       [BCM2835_PLLD]          = REGISTER_PLL(&bcm2835_plld_data),
  92 +       [BCM2835_PLLH]          = REGISTER_PLL(&bcm2835_pllh_data),
  93 +       /* the PLL dividers */
  94 +       [BCM2835_PLLA_CORE]     = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
  95 +       [BCM2835_PLLA_PER]      = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
  96 +       [BCM2835_PLLC_CORE0]    = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
  97 +       [BCM2835_PLLC_CORE1]    = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
  98 +       [BCM2835_PLLC_CORE2]    = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
  99 +       [BCM2835_PLLC_PER]      = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
 100 +       [BCM2835_PLLD_CORE]     = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
 101 +       [BCM2835_PLLD_PER]      = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
 102 +       [BCM2835_PLLH_RCAL]     = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
 103 +       [BCM2835_PLLH_AUX]      = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
 104 +       [BCM2835_PLLH_PIX]      = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
 105 +       /* the clocks */
 106 +       [BCM2835_CLOCK_TIMER]   = REGISTER_CLK(&bcm2835_clock_timer_data),
 107 +       [BCM2835_CLOCK_OTP]     = REGISTER_CLK(&bcm2835_clock_otp_data),
 108 +       [BCM2835_CLOCK_TSENS]   = REGISTER_CLK(&bcm2835_clock_tsens_data),
 109 +       [BCM2835_CLOCK_VPU]     = REGISTER_CLK(&bcm2835_clock_vpu_data),
 110 +       [BCM2835_CLOCK_V3D]     = REGISTER_CLK(&bcm2835_clock_v3d_data),
 111 +       [BCM2835_CLOCK_ISP]     = REGISTER_CLK(&bcm2835_clock_isp_data),
 112 +       [BCM2835_CLOCK_H264]    = REGISTER_CLK(&bcm2835_clock_h264_data),
 113 +       [BCM2835_CLOCK_V3D]     = REGISTER_CLK(&bcm2835_clock_v3d_data),
 114 +       [BCM2835_CLOCK_SDRAM]   = REGISTER_CLK(&bcm2835_clock_sdram_data),
 115 +       [BCM2835_CLOCK_UART]    = REGISTER_CLK(&bcm2835_clock_uart_data),
 116 +       [BCM2835_CLOCK_VEC]     = REGISTER_CLK(&bcm2835_clock_vec_data),
 117 +       [BCM2835_CLOCK_HSM]     = REGISTER_CLK(&bcm2835_clock_hsm_data),
 118 +       [BCM2835_CLOCK_EMMC]    = REGISTER_CLK(&bcm2835_clock_emmc_data),
 119 +       [BCM2835_CLOCK_PWM]     = REGISTER_CLK(&bcm2835_clock_pwm_data),
 120 +       /* the gates */
 121 +       [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
 122 +               &bcm2835_clock_peri_image_data),
 123 +};
 124 +
 125  static int bcm2835_clk_probe(struct platform_device *pdev)
 126  {
 127         struct device *dev = &pdev->dev;
 128         struct clk **clks;
 129         struct bcm2835_cprman *cprman;
 130         struct resource *res;
 131 +       const struct bcm2835_clk_desc *desc;
 132 +       const size_t asize = ARRAY_SIZE(clk_desc_array);
 133 +       size_t i;
 134
 135 -       cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
 136 +       cprman = devm_kzalloc(dev,
 137 +                             sizeof(*cprman) + asize * sizeof(*clks),
 138 +                             GFP_KERNEL);
 139         if (!cprman)
 140                 return -ENOMEM;
 141
 142 @@ -1690,80 +1776,15 @@ static int bcm2835_clk_probe(struct plat
 143
 144         platform_set_drvdata(pdev, cprman);
 145
 146 -       cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
 147 +       cprman->onecell.clk_num = asize;
 148         cprman->onecell.clks = cprman->clks;
 149         clks = cprman->clks;
 150
 151 -       clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
 152 -       clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
 153 -       clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
 154 -       clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
 155 -       clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
 156 -
 157 -       clks[BCM2835_PLLA_CORE] =
 158 -               bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
 159 -       clks[BCM2835_PLLA_PER] =
 160 -               bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
 161 -       clks[BCM2835_PLLC_CORE0] =
 162 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
 163 -       clks[BCM2835_PLLC_CORE1] =
 164 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
 165 -       clks[BCM2835_PLLC_CORE2] =
 166 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
 167 -       clks[BCM2835_PLLC_PER] =
 168 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
 169 -       clks[BCM2835_PLLD_CORE] =
 170 -               bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
 171 -       clks[BCM2835_PLLD_PER] =
 172 -               bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
 173 -       clks[BCM2835_PLLH_RCAL] =
 174 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
 175 -       clks[BCM2835_PLLH_AUX] =
 176 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
 177 -       clks[BCM2835_PLLH_PIX] =
 178 -               bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
 179 -
 180 -       clks[BCM2835_CLOCK_TIMER] =
 181 -               bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
 182 -       clks[BCM2835_CLOCK_OTP] =
 183 -               bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
 184 -       clks[BCM2835_CLOCK_TSENS] =
 185 -               bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
 186 -       clks[BCM2835_CLOCK_VPU] =
 187 -               bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
 188 -       clks[BCM2835_CLOCK_V3D] =
 189 -               bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
 190 -       clks[BCM2835_CLOCK_ISP] =
 191 -               bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
 192 -       clks[BCM2835_CLOCK_H264] =
 193 -               bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
 194 -       clks[BCM2835_CLOCK_V3D] =
 195 -               bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
 196 -       clks[BCM2835_CLOCK_SDRAM] =
 197 -               bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
 198 -       clks[BCM2835_CLOCK_UART] =
 199 -               bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
 200 -       clks[BCM2835_CLOCK_VEC] =
 201 -               bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
 202 -       clks[BCM2835_CLOCK_HSM] =
 203 -               bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
 204 -       clks[BCM2835_CLOCK_EMMC] =
 205 -               bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
 206 -
 207 -       /*
 208 -        * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
 209 -        * you have the debug bit set in the power manager, which we
 210 -        * don't bother exposing) are individual gates off of the
 211 -        * non-stop vpu clock.
 212 -        */
 213 -       clks[BCM2835_CLOCK_PERI_IMAGE] =
 214 -               clk_register_gate(dev, "peri_image", "vpu",
 215 -                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
 216 -                                 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
 217 -                                 0, &cprman->regs_lock);
 218 -
 219 -       clks[BCM2835_CLOCK_PWM] =
 220 -               bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
 221 +       for (i = 0; i < asize; i++) {
 222 +               desc = &clk_desc_array[i];
 223 +               if (desc->clk_register && desc->data)
 224 +                       clks[i] = desc->clk_register(cprman, desc->data);
 225 +       }
 226
 227         return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
 228                                    &cprman->onecell);
 229 --- a/include/dt-bindings/clock/bcm2835.h
 230 +++ b/include/dt-bindings/clock/bcm2835.h
 231 @@ -44,5 +44,3 @@
 232  #define BCM2835_CLOCK_EMMC             28
 233  #define BCM2835_CLOCK_PERI_IMAGE       29
 234  #define BCM2835_CLOCK_PWM              30
 235 -
 236 -#define BCM2835_CLOCK_COUNT            31