target/linux/brcm47xx/patches-4.14/330-Revert-MIPS-BCM47XX-Enable-74K-Core-ExternalSync-for.patch

   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Date: Fri, 27 Jul 2018 12:39:01 +0200
   3 Subject: [PATCH] Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe
   4  erratum"
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This reverts commit 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175.
  10
  11 Enabling ExternalSync caused a regression for BCM4718A1 (used e.g. in
  12 Netgear E3000 and ASUS RT-N16): it simply hangs during PCIe
  13 initialization. It's likely that BCM4717A1 is also affected.
  14
  15 I didn't notice that earlier as the only BCM47XX devices with PCIe I
  16 own are:
  17 1) BCM4706 with 2 x 14e4:4331
  18 2) BCM4706 with 14e4:4360 and 14e4:4331
  19 it appears that BCM4706 is unaffected.
  20
  21 While BCM5300X-ES300-RDS.pdf seems to document that erratum and its
  22 workarounds (according to quotes provided by Tokunori) it seems not even
  23 Broadcom follows them.
  24
  25 According to the provided info Broadcom should define CONF7_ES in their
  26 SDK's mipsinc.h and implement workaround in the si_mips_init(). Checking
  27 both didn't reveal such code. It *could* mean Broadcom also had some
  28 problems with the given workaround.
  29
  30 Reported-by: Michael Marley <michael@michaelmarley.com>
  31 Cc: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
  32 Cc: Paul Burton <paul.burton@mips.com>
  33 Cc: Hauke Mehrtens <hauke@hauke-m.de>
  34 Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
  35 Cc: stable@vger.kernel.org
  36 Cc: James Hogan <jhogan@kernel.org>
  37 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  38 ---
  39  arch/mips/bcm47xx/setup.c        | 6 ------
  40  arch/mips/include/asm/mipsregs.h | 3 ---
  41  2 files changed, 9 deletions(-)
  42
  43 --- a/arch/mips/bcm47xx/setup.c
  44 +++ b/arch/mips/bcm47xx/setup.c
  45 @@ -212,12 +212,6 @@ static int __init bcm47xx_cpu_fixes(void
  46                  */
  47                 if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
  48                         cpu_wait = NULL;
  49 -
  50 -               /*
  51 -                * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
  52 -                * Enable ExternalSync for sync instruction to take effect
  53 -                */
  54 -               set_c0_config7(MIPS_CONF7_ES);
  55                 break;
  56  #endif
  57         }
  58 --- a/arch/mips/include/asm/mipsregs.h
  59 +++ b/arch/mips/include/asm/mipsregs.h
  60 @@ -680,8 +680,6 @@
  61  #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
  62
  63  #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
  64 -/* ExternalSync */
  65 -#define MIPS_CONF7_ES          (_ULCAST_(1) << 8)
  66
  67  #define MIPS_CONF7_IAR         (_ULCAST_(1) << 10)
  68  #define MIPS_CONF7_AR          (_ULCAST_(1) << 16)
  69 @@ -2747,7 +2745,6 @@ __BUILD_SET_C0(status)
  70  __BUILD_SET_C0(cause)
  71  __BUILD_SET_C0(config)
  72  __BUILD_SET_C0(config5)
  73 -__BUILD_SET_C0(config7)
  74  __BUILD_SET_C0(intcontrol)
  75  __BUILD_SET_C0(intctl)
  76  __BUILD_SET_C0(srsmap)