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[openwrt/staging/chunkeey.git] / target / linux / brcm63xx / patches-3.9 / 315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch
1 From 6ec70ebfccd31ae3668d99b5703e5c9ce38384b4 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Thu, 25 Apr 2013 00:24:06 +0200
4 Subject: [PATCH 06/13] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
5
6 For SMP affinity support we need to discrimnate between the registers
7 for both CPUs.
8
9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
10 ---
11 arch/mips/bcm63xx/irq.c | 78 ++++++++++-----------
12 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++---
13 2 files changed, 47 insertions(+), 47 deletions(-)
14
15 --- a/arch/mips/bcm63xx/irq.c
16 +++ b/arch/mips/bcm63xx/irq.c
17 @@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
18
19 #ifndef BCMCPU_RUNTIME_DETECT
20 #ifdef CONFIG_BCM63XX_CPU_6328
21 -#define irq_stat_reg PERF_IRQSTAT_6328_REG
22 -#define irq_mask_reg PERF_IRQMASK_6328_REG
23 +#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
24 +#define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
25 #define irq_bits 64
26 #define is_ext_irq_cascaded 1
27 #define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
28 @@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
29 #define ext_irq_cfg_reg2 0
30 #endif
31 #ifdef CONFIG_BCM63XX_CPU_6338
32 -#define irq_stat_reg PERF_IRQSTAT_6338_REG
33 -#define irq_mask_reg PERF_IRQMASK_6338_REG
34 +#define irq_stat_reg0 PERF_IRQSTAT_6338_REG
35 +#define irq_mask_reg0 PERF_IRQMASK_6338_REG
36 #define irq_bits 32
37 #define is_ext_irq_cascaded 0
38 #define ext_irq_start 0
39 @@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
40 #define ext_irq_cfg_reg2 0
41 #endif
42 #ifdef CONFIG_BCM63XX_CPU_6345
43 -#define irq_stat_reg PERF_IRQSTAT_6345_REG
44 -#define irq_mask_reg PERF_IRQMASK_6345_REG
45 +#define irq_stat_reg0 PERF_IRQSTAT_6345_REG
46 +#define irq_mask_reg0 PERF_IRQMASK_6345_REG
47 #define irq_bits 32
48 #define is_ext_irq_cascaded 0
49 #define ext_irq_start 0
50 @@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
51 #define ext_irq_cfg_reg2 0
52 #endif
53 #ifdef CONFIG_BCM63XX_CPU_6348
54 -#define irq_stat_reg PERF_IRQSTAT_6348_REG
55 -#define irq_mask_reg PERF_IRQMASK_6348_REG
56 +#define irq_stat_reg0 PERF_IRQSTAT_6348_REG
57 +#define irq_mask_reg0 PERF_IRQMASK_6348_REG
58 #define irq_bits 32
59 #define is_ext_irq_cascaded 0
60 #define ext_irq_start 0
61 @@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
62 #define ext_irq_cfg_reg2 0
63 #endif
64 #ifdef CONFIG_BCM63XX_CPU_6358
65 -#define irq_stat_reg PERF_IRQSTAT_6358_REG
66 -#define irq_mask_reg PERF_IRQMASK_6358_REG
67 +#define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
68 +#define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
69 #define irq_bits 32
70 #define is_ext_irq_cascaded 1
71 #define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
72 @@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
73 #define ext_irq_cfg_reg2 0
74 #endif
75 #ifdef CONFIG_BCM63XX_CPU_6362
76 -#define irq_stat_reg PERF_IRQSTAT_6362_REG
77 -#define irq_mask_reg PERF_IRQMASK_6362_REG
78 +#define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
79 +#define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
80 #define irq_bits 64
81 #define is_ext_irq_cascaded 1
82 #define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
83 @@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
84 #define ext_irq_cfg_reg2 0
85 #endif
86 #ifdef CONFIG_BCM63XX_CPU_6368
87 -#define irq_stat_reg PERF_IRQSTAT_6368_REG
88 -#define irq_mask_reg PERF_IRQMASK_6368_REG
89 +#define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
90 +#define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
91 #define irq_bits 64
92 #define is_ext_irq_cascaded 1
93 #define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
94 @@ -115,15 +115,15 @@ static void __internal_irq_unmask_64(uns
95 #define internal_irq_unmask __internal_irq_unmask_64
96 #endif
97
98 -#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
99 -#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
100 +#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
101 +#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
102
103 static inline void bcm63xx_init_irq(void)
104 {
105 }
106 #else /* ! BCMCPU_RUNTIME_DETECT */
107
108 -static u32 irq_stat_addr, irq_mask_addr;
109 +static u32 irq_stat_addr0, irq_mask_addr0;
110 static void (*dispatch_internal)(void);
111 static int is_ext_irq_cascaded;
112 static unsigned int ext_irq_count;
113 @@ -136,13 +136,13 @@ static void bcm63xx_init_irq(void)
114 {
115 int irq_bits;
116
117 - irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
118 - irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
119 + irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
120 + irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
121
122 switch (bcm63xx_get_cpu_id()) {
123 case BCM6328_CPU_ID:
124 - irq_stat_addr += PERF_IRQSTAT_6328_REG;
125 - irq_mask_addr += PERF_IRQMASK_6328_REG;
126 + irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
127 + irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
128 irq_bits = 64;
129 ext_irq_count = 4;
130 is_ext_irq_cascaded = 1;
131 @@ -151,29 +151,29 @@ static void bcm63xx_init_irq(void)
132 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
133 break;
134 case BCM6338_CPU_ID:
135 - irq_stat_addr += PERF_IRQSTAT_6338_REG;
136 - irq_mask_addr += PERF_IRQMASK_6338_REG;
137 + irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
138 + irq_mask_addr0 += PERF_IRQMASK_6338_REG;
139 irq_bits = 32;
140 ext_irq_count = 4;
141 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
142 break;
143 case BCM6345_CPU_ID:
144 - irq_stat_addr += PERF_IRQSTAT_6345_REG;
145 - irq_mask_addr += PERF_IRQMASK_6345_REG;
146 + irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
147 + irq_mask_addr0 += PERF_IRQMASK_6345_REG;
148 irq_bits = 32;
149 ext_irq_count = 4;
150 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
151 break;
152 case BCM6348_CPU_ID:
153 - irq_stat_addr += PERF_IRQSTAT_6348_REG;
154 - irq_mask_addr += PERF_IRQMASK_6348_REG;
155 + irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
156 + irq_mask_addr0 += PERF_IRQMASK_6348_REG;
157 irq_bits = 32;
158 ext_irq_count = 4;
159 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
160 break;
161 case BCM6358_CPU_ID:
162 - irq_stat_addr += PERF_IRQSTAT_6358_REG;
163 - irq_mask_addr += PERF_IRQMASK_6358_REG;
164 + irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
165 + irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
166 irq_bits = 32;
167 ext_irq_count = 4;
168 is_ext_irq_cascaded = 1;
169 @@ -182,8 +182,8 @@ static void bcm63xx_init_irq(void)
170 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
171 break;
172 case BCM6362_CPU_ID:
173 - irq_stat_addr += PERF_IRQSTAT_6362_REG;
174 - irq_mask_addr += PERF_IRQMASK_6362_REG;
175 + irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
176 + irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
177 irq_bits = 64;
178 ext_irq_count = 4;
179 is_ext_irq_cascaded = 1;
180 @@ -192,8 +192,8 @@ static void bcm63xx_init_irq(void)
181 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
182 break;
183 case BCM6368_CPU_ID:
184 - irq_stat_addr += PERF_IRQSTAT_6368_REG;
185 - irq_mask_addr += PERF_IRQMASK_6368_REG;
186 + irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
187 + irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
188 irq_bits = 64;
189 ext_irq_count = 6;
190 is_ext_irq_cascaded = 1;
191 @@ -253,8 +253,8 @@ void __dispatch_internal_##width(void)
192 for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
193 u32 val; \
194 \
195 - val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
196 - val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
197 + val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \
198 + val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \
199 pending[--tgt] = val; \
200 \
201 if (val) \
202 @@ -281,9 +281,9 @@ static void __internal_irq_mask_##width(
203 unsigned reg = (irq / 32) ^ (width/32 - 1); \
204 unsigned bit = irq & 0x1f; \
205 \
206 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
207 + val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
208 val &= ~(1 << bit); \
209 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
210 + bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
211 } \
212 \
213 static void __internal_irq_unmask_##width(unsigned int irq) \
214 @@ -292,9 +292,9 @@ static void __internal_irq_unmask_##widt
215 unsigned reg = (irq / 32) ^ (width/32 - 1); \
216 unsigned bit = irq & 0x1f; \
217 \
218 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
219 + val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
220 val |= (1 << bit); \
221 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
222 + bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
223 }
224
225 BUILD_IPIC_INTERNAL(32);
226 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
227 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
228 @@ -181,22 +181,22 @@
229 #define SYS_PLL_SOFT_RESET 0x1
230
231 /* Interrupt Mask register */
232 -#define PERF_IRQMASK_6328_REG 0x20
233 +#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
234 #define PERF_IRQMASK_6338_REG 0xc
235 #define PERF_IRQMASK_6345_REG 0xc
236 #define PERF_IRQMASK_6348_REG 0xc
237 -#define PERF_IRQMASK_6358_REG 0xc
238 -#define PERF_IRQMASK_6362_REG 0x20
239 -#define PERF_IRQMASK_6368_REG 0x20
240 +#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
241 +#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
242 +#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
243
244 /* Interrupt Status register */
245 -#define PERF_IRQSTAT_6328_REG 0x28
246 +#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
247 #define PERF_IRQSTAT_6338_REG 0x10
248 #define PERF_IRQSTAT_6345_REG 0x10
249 #define PERF_IRQSTAT_6348_REG 0x10
250 -#define PERF_IRQSTAT_6358_REG 0x10
251 -#define PERF_IRQSTAT_6362_REG 0x28
252 -#define PERF_IRQSTAT_6368_REG 0x28
253 +#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
254 +#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
255 +#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
256
257 /* External Interrupt Configuration register */
258 #define PERF_EXTIRQ_CFG_REG_6328 0x18
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