target/linux/brcm63xx/patches-3.9/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch

   1 From 46442450ffb95a869894b0dfd1e5b4f973d4b4ee Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Thu, 25 Apr 2013 00:24:06 +0200
   4 Subject: [PATCH 07/14] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
   5
   6 The SMP capable irq controllers have two interupt output pins which are
   7 controlled through separate registers.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/bcm63xx/irq.c                           |   86 ++++++++++-----------
  12  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   16 ++--
  13  2 files changed, 51 insertions(+), 51 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/irq.c
  16 +++ b/arch/mips/bcm63xx/irq.c
  17 @@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
  18
  19  #ifndef BCMCPU_RUNTIME_DETECT
  20  #ifdef CONFIG_BCM63XX_CPU_3368
  21 -#define irq_stat_reg           PERF_IRQSTAT_3368_REG
  22 -#define irq_mask_reg           PERF_IRQMASK_3368_REG
  23 +#define irq_stat_reg0          PERF_IRQSTAT_3368_REG
  24 +#define irq_mask_reg0          PERF_IRQMASK_3368_REG
  25  #define irq_bits               32
  26  #define is_ext_irq_cascaded    0
  27  #define ext_irq_start          0
  28 @@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
  29  #define ext_irq_cfg_reg2       0
  30  #endif
  31  #ifdef CONFIG_BCM63XX_CPU_6328
  32 -#define irq_stat_reg           PERF_IRQSTAT_6328_REG
  33 -#define irq_mask_reg           PERF_IRQMASK_6328_REG
  34 +#define irq_stat_reg0          PERF_IRQSTAT_6328_REG(0)
  35 +#define irq_mask_reg0          PERF_IRQMASK_6328_REG(0)
  36  #define irq_bits               64
  37  #define is_ext_irq_cascaded    1
  38  #define ext_irq_start          (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
  39 @@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
  40  #define ext_irq_cfg_reg2       0
  41  #endif
  42  #ifdef CONFIG_BCM63XX_CPU_6338
  43 -#define irq_stat_reg           PERF_IRQSTAT_6338_REG
  44 -#define irq_mask_reg           PERF_IRQMASK_6338_REG
  45 +#define irq_stat_reg0          PERF_IRQSTAT_6338_REG
  46 +#define irq_mask_reg0          PERF_IRQMASK_6338_REG
  47  #define irq_bits               32
  48  #define is_ext_irq_cascaded    0
  49  #define ext_irq_start          0
  50 @@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
  51  #define ext_irq_cfg_reg2       0
  52  #endif
  53  #ifdef CONFIG_BCM63XX_CPU_6345
  54 -#define irq_stat_reg           PERF_IRQSTAT_6345_REG
  55 -#define irq_mask_reg           PERF_IRQMASK_6345_REG
  56 +#define irq_stat_reg0          PERF_IRQSTAT_6345_REG
  57 +#define irq_mask_reg0          PERF_IRQMASK_6345_REG
  58  #define irq_bits               32
  59  #define is_ext_irq_cascaded    0
  60  #define ext_irq_start          0
  61 @@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
  62  #define ext_irq_cfg_reg2       0
  63  #endif
  64  #ifdef CONFIG_BCM63XX_CPU_6348
  65 -#define irq_stat_reg           PERF_IRQSTAT_6348_REG
  66 -#define irq_mask_reg           PERF_IRQMASK_6348_REG
  67 +#define irq_stat_reg0          PERF_IRQSTAT_6348_REG
  68 +#define irq_mask_reg0          PERF_IRQMASK_6348_REG
  69  #define irq_bits               32
  70  #define is_ext_irq_cascaded    0
  71  #define ext_irq_start          0
  72 @@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
  73  #define ext_irq_cfg_reg2       0
  74  #endif
  75  #ifdef CONFIG_BCM63XX_CPU_6358
  76 -#define irq_stat_reg           PERF_IRQSTAT_6358_REG
  77 -#define irq_mask_reg           PERF_IRQMASK_6358_REG
  78 +#define irq_stat_reg0          PERF_IRQSTAT_6358_REG(0)
  79 +#define irq_mask_reg0          PERF_IRQMASK_6358_REG(0)
  80  #define irq_bits               32
  81  #define is_ext_irq_cascaded    1
  82  #define ext_irq_start          (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
  83 @@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
  84  #define ext_irq_cfg_reg2       0
  85  #endif
  86  #ifdef CONFIG_BCM63XX_CPU_6362
  87 -#define irq_stat_reg           PERF_IRQSTAT_6362_REG
  88 -#define irq_mask_reg           PERF_IRQMASK_6362_REG
  89 +#define irq_stat_reg0          PERF_IRQSTAT_6362_REG(0)
  90 +#define irq_mask_reg0          PERF_IRQMASK_6362_REG(0)
  91  #define irq_bits               64
  92  #define is_ext_irq_cascaded    1
  93  #define ext_irq_start          (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
  94 @@ -105,8 +105,8 @@ static void __internal_irq_unmask_64(uns
  95  #define ext_irq_cfg_reg2       0
  96  #endif
  97  #ifdef CONFIG_BCM63XX_CPU_6368
  98 -#define irq_stat_reg           PERF_IRQSTAT_6368_REG
  99 -#define irq_mask_reg           PERF_IRQMASK_6368_REG
 100 +#define irq_stat_reg0          PERF_IRQSTAT_6368_REG(0)
 101 +#define irq_mask_reg0          PERF_IRQMASK_6368_REG(0)
 102  #define irq_bits               64
 103  #define is_ext_irq_cascaded    1
 104  #define ext_irq_start          (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
 105 @@ -126,15 +126,15 @@ static void __internal_irq_unmask_64(uns
 106  #define internal_irq_unmask                    __internal_irq_unmask_64
 107  #endif
 108
 109 -#define irq_stat_addr  (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
 110 -#define irq_mask_addr  (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
 111 +#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
 112 +#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
 113
 114  static inline void bcm63xx_init_irq(void)
 115  {
 116  }
 117  #else /* ! BCMCPU_RUNTIME_DETECT */
 118
 119 -static u32 irq_stat_addr, irq_mask_addr;
 120 +static u32 irq_stat_addr0, irq_mask_addr0;
 121  static void (*dispatch_internal)(void);
 122  static int is_ext_irq_cascaded;
 123  static unsigned int ext_irq_count;
 124 @@ -147,20 +147,20 @@ static void bcm63xx_init_irq(void)
 125  {
 126         int irq_bits;
 127
 128 -       irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
 129 -       irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
 130 +       irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
 131 +       irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
 132
 133         switch (bcm63xx_get_cpu_id()) {
 134         case BCM3368_CPU_ID:
 135 -               irq_stat_addr += PERF_IRQSTAT_3368_REG;
 136 -               irq_mask_addr += PERF_IRQMASK_3368_REG;
 137 +               irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
 138 +               irq_mask_addr0 += PERF_IRQMASK_3368_REG;
 139                 irq_bits = 32;
 140                 ext_irq_count = 4;
 141                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
 142                 break;
 143         case BCM6328_CPU_ID:
 144 -               irq_stat_addr += PERF_IRQSTAT_6328_REG;
 145 -               irq_mask_addr += PERF_IRQMASK_6328_REG;
 146 +               irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
 147 +               irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
 148                 irq_bits = 64;
 149                 ext_irq_count = 4;
 150                 is_ext_irq_cascaded = 1;
 151 @@ -169,29 +169,29 @@ static void bcm63xx_init_irq(void)
 152                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
 153                 break;
 154         case BCM6338_CPU_ID:
 155 -               irq_stat_addr += PERF_IRQSTAT_6338_REG;
 156 -               irq_mask_addr += PERF_IRQMASK_6338_REG;
 157 +               irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
 158 +               irq_mask_addr0 += PERF_IRQMASK_6338_REG;
 159                 irq_bits = 32;
 160                 ext_irq_count = 4;
 161                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
 162                 break;
 163         case BCM6345_CPU_ID:
 164 -               irq_stat_addr += PERF_IRQSTAT_6345_REG;
 165 -               irq_mask_addr += PERF_IRQMASK_6345_REG;
 166 +               irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
 167 +               irq_mask_addr0 += PERF_IRQMASK_6345_REG;
 168                 irq_bits = 32;
 169                 ext_irq_count = 4;
 170                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
 171                 break;
 172         case BCM6348_CPU_ID:
 173 -               irq_stat_addr += PERF_IRQSTAT_6348_REG;
 174 -               irq_mask_addr += PERF_IRQMASK_6348_REG;
 175 +               irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
 176 +               irq_mask_addr0 += PERF_IRQMASK_6348_REG;
 177                 irq_bits = 32;
 178                 ext_irq_count = 4;
 179                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
 180                 break;
 181         case BCM6358_CPU_ID:
 182 -               irq_stat_addr += PERF_IRQSTAT_6358_REG;
 183 -               irq_mask_addr += PERF_IRQMASK_6358_REG;
 184 +               irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
 185 +               irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
 186                 irq_bits = 32;
 187                 ext_irq_count = 4;
 188                 is_ext_irq_cascaded = 1;
 189 @@ -200,8 +200,8 @@ static void bcm63xx_init_irq(void)
 190                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 191                 break;
 192         case BCM6362_CPU_ID:
 193 -               irq_stat_addr += PERF_IRQSTAT_6362_REG;
 194 -               irq_mask_addr += PERF_IRQMASK_6362_REG;
 195 +               irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
 196 +               irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
 197                 irq_bits = 64;
 198                 ext_irq_count = 4;
 199                 is_ext_irq_cascaded = 1;
 200 @@ -210,8 +210,8 @@ static void bcm63xx_init_irq(void)
 201                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 202                 break;
 203         case BCM6368_CPU_ID:
 204 -               irq_stat_addr += PERF_IRQSTAT_6368_REG;
 205 -               irq_mask_addr += PERF_IRQMASK_6368_REG;
 206 +               irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
 207 +               irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
 208                 irq_bits = 64;
 209                 ext_irq_count = 6;
 210                 is_ext_irq_cascaded = 1;
 211 @@ -271,8 +271,8 @@ void __dispatch_internal_##width(void)
 212         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
 213                 u32 val;                                                \
 214                                                                         \
 215 -               val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
 216 -               val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
 217 +               val = bcm_readl(irq_stat_addr0 + src * sizeof(u32));    \
 218 +               val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32));   \
 219                 pending[--tgt] = val;                                   \
 220                                                                         \
 221                 if (val)                                                \
 222 @@ -299,9 +299,9 @@ static void __internal_irq_mask_##width(
 223         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
 224         unsigned bit = irq & 0x1f;                                      \
 225                                                                         \
 226 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
 227 +       val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
 228         val &= ~(1 << bit);                                             \
 229 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
 230 +       bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
 231  }                                                                      \
 232                                                                         \
 233  static void __internal_irq_unmask_##width(unsigned int irq)            \
 234 @@ -310,9 +310,9 @@ static void __internal_irq_unmask_##widt
 235         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
 236         unsigned bit = irq & 0x1f;                                      \
 237                                                                         \
 238 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
 239 +       val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
 240         val |= (1 << bit);                                              \
 241 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
 242 +       bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
 243  }
 244
 245  BUILD_IPIC_INTERNAL(32);
 246 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 247 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 248 @@ -215,23 +215,23 @@
 249
 250  /* Interrupt Mask register */
 251  #define PERF_IRQMASK_3368_REG          0xc
 252 -#define PERF_IRQMASK_6328_REG          0x20
 253 +#define PERF_IRQMASK_6328_REG(x)       (0x20 + (x) * 0x10)
 254  #define PERF_IRQMASK_6338_REG          0xc
 255  #define PERF_IRQMASK_6345_REG          0xc
 256  #define PERF_IRQMASK_6348_REG          0xc
 257 -#define PERF_IRQMASK_6358_REG          0xc
 258 -#define PERF_IRQMASK_6362_REG          0x20
 259 -#define PERF_IRQMASK_6368_REG          0x20
 260 +#define PERF_IRQMASK_6358_REG(x)       (0xc + (x) * 0x2c)
 261 +#define PERF_IRQMASK_6362_REG(x)       (0x20 + (x) * 0x10)
 262 +#define PERF_IRQMASK_6368_REG(x)       (0x20 + (x) * 0x10)
 263
 264  /* Interrupt Status register */
 265  #define PERF_IRQSTAT_3368_REG          0x10
 266 -#define PERF_IRQSTAT_6328_REG          0x28
 267 +#define PERF_IRQSTAT_6328_REG(x)       (0x28 + (x) * 0x10)
 268  #define PERF_IRQSTAT_6338_REG          0x10
 269  #define PERF_IRQSTAT_6345_REG          0x10
 270  #define PERF_IRQSTAT_6348_REG          0x10
 271 -#define PERF_IRQSTAT_6358_REG          0x10
 272 -#define PERF_IRQSTAT_6362_REG          0x28
 273 -#define PERF_IRQSTAT_6368_REG          0x28
 274 +#define PERF_IRQSTAT_6358_REG(x)       (0x10 + (x) * 0x2c)
 275 +#define PERF_IRQSTAT_6362_REG(x)       (0x28 + (x) * 0x10)
 276 +#define PERF_IRQSTAT_6368_REG(x)       (0x28 + (x) * 0x10)
 277
 278  /* External Interrupt Configuration register */
 279  #define PERF_EXTIRQ_CFG_REG_3368       0x14