094eaa88ccdadb952c053922a51e649294da31ac
[openwrt/staging/chunkeey.git] / target / linux / brcm63xx / patches-3.9 / 316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch
1 From b14de5c78d32f8f98535a99ea56bb924beb66810 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Thu, 25 Apr 2013 00:31:29 +0200
4 Subject: [PATCH 07/13] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
5 second CPU
6
7 Populate it for all platforms with a BMIPS4350.
8
9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
10 ---
11 arch/mips/bcm63xx/irq.c | 28 +++++++++++++++++++++++++++-
12 1 file changed, 27 insertions(+), 1 deletion(-)
13
14 --- a/arch/mips/bcm63xx/irq.c
15 +++ b/arch/mips/bcm63xx/irq.c
16 @@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns
17 #ifdef CONFIG_BCM63XX_CPU_6328
18 #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
19 #define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
20 +#define irq_stat_reg1 PERF_IRQSTAT_6328_REG(1)
21 +#define irq_mask_reg1 PERF_IRQMASK_6328_REG(1)
22 #define irq_bits 64
23 #define is_ext_irq_cascaded 1
24 #define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
25 @@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
26 #ifdef CONFIG_BCM63XX_CPU_6338
27 #define irq_stat_reg0 PERF_IRQSTAT_6338_REG
28 #define irq_mask_reg0 PERF_IRQMASK_6338_REG
29 +#define irq_stat_reg1 0
30 +#define irq_mask_reg1 0
31 #define irq_bits 32
32 #define is_ext_irq_cascaded 0
33 #define ext_irq_start 0
34 @@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
35 #ifdef CONFIG_BCM63XX_CPU_6345
36 #define irq_stat_reg0 PERF_IRQSTAT_6345_REG
37 #define irq_mask_reg0 PERF_IRQMASK_6345_REG
38 +#define irq_stat_reg1 0
39 +#define irq_mask_reg1 0
40 #define irq_bits 32
41 #define is_ext_irq_cascaded 0
42 #define ext_irq_start 0
43 @@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
44 #ifdef CONFIG_BCM63XX_CPU_6348
45 #define irq_stat_reg0 PERF_IRQSTAT_6348_REG
46 #define irq_mask_reg0 PERF_IRQMASK_6348_REG
47 +#define irq_stat_reg1 0
48 +#define irq_mask_reg1 0
49 #define irq_bits 32
50 #define is_ext_irq_cascaded 0
51 #define ext_irq_start 0
52 @@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
53 #ifdef CONFIG_BCM63XX_CPU_6358
54 #define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
55 #define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
56 +#define irq_stat_reg1 PERF_IRQSTAT_6358_REG(1)
57 +#define irq_mask_reg1 PERF_IRQMASK_6358_REG(1)
58 #define irq_bits 32
59 #define is_ext_irq_cascaded 1
60 #define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
61 @@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
62 #ifdef CONFIG_BCM63XX_CPU_6362
63 #define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
64 #define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
65 +#define irq_stat_reg1 PERF_IRQSTAT_6362_REG(1)
66 +#define irq_mask_reg1 PERF_IRQMASK_6362_REG(1)
67 #define irq_bits 64
68 #define is_ext_irq_cascaded 1
69 #define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
70 @@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
71 #ifdef CONFIG_BCM63XX_CPU_6368
72 #define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
73 #define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
74 +#define irq_stat_reg1 PERF_IRQSTAT_6368_REG(1)
75 +#define irq_mask_reg1 PERF_IRQMASK_6368_REG(1)
76 #define irq_bits 64
77 #define is_ext_irq_cascaded 1
78 #define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
79 @@ -117,13 +131,15 @@ static void __internal_irq_unmask_64(uns
80
81 #define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
82 #define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
83 +#define irq_stat_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1)
84 +#define irq_mask_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1)
85
86 static inline void bcm63xx_init_irq(void)
87 {
88 }
89 #else /* ! BCMCPU_RUNTIME_DETECT */
90
91 -static u32 irq_stat_addr0, irq_mask_addr0;
92 +static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
93 static void (*dispatch_internal)(void);
94 static int is_ext_irq_cascaded;
95 static unsigned int ext_irq_count;
96 @@ -138,11 +154,15 @@ static void bcm63xx_init_irq(void)
97
98 irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
99 irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
100 + irq_stat_addr1 = bcm63xx_regset_address(RSET_PERF);
101 + irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
102
103 switch (bcm63xx_get_cpu_id()) {
104 case BCM6328_CPU_ID:
105 irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
106 irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
107 + irq_stat_addr1 += PERF_IRQSTAT_6328_REG(1);
108 + irq_stat_addr1 += PERF_IRQMASK_6328_REG(1);
109 irq_bits = 64;
110 ext_irq_count = 4;
111 is_ext_irq_cascaded = 1;
112 @@ -174,6 +194,8 @@ static void bcm63xx_init_irq(void)
113 case BCM6358_CPU_ID:
114 irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
115 irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
116 + irq_stat_addr1 += PERF_IRQSTAT_6358_REG(1);
117 + irq_mask_addr1 += PERF_IRQMASK_6358_REG(1);
118 irq_bits = 32;
119 ext_irq_count = 4;
120 is_ext_irq_cascaded = 1;
121 @@ -184,6 +206,8 @@ static void bcm63xx_init_irq(void)
122 case BCM6362_CPU_ID:
123 irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
124 irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
125 + irq_stat_addr1 += PERF_IRQSTAT_6362_REG(1);
126 + irq_mask_addr1 += PERF_IRQMASK_6362_REG(1);
127 irq_bits = 64;
128 ext_irq_count = 4;
129 is_ext_irq_cascaded = 1;
130 @@ -194,6 +218,8 @@ static void bcm63xx_init_irq(void)
131 case BCM6368_CPU_ID:
132 irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
133 irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
134 + irq_stat_addr1 += PERF_IRQSTAT_6368_REG(1);
135 + irq_mask_addr1 += PERF_IRQMASK_6368_REG(1);
136 irq_bits = 64;
137 ext_irq_count = 6;
138 is_ext_irq_cascaded = 1;