target/linux/brcm63xx/patches-3.9/319-MIPS-BCM63XX-protect-irq-register-accesses-with-a-sp.patch

   1 From 7b8e7bc9806b61be2f07bf2bbb5e3ee6e0f333e9 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 21 Apr 2013 15:38:56 +0200
   4 Subject: [PATCH 10/13] MIPS: BCM63XX: protect irq register accesses with a
   5  spinlock
   6
   7 Since IRQs can be handled on both CPUs, we need to ensure that we
   8 don't try to modify the IRQ registers at the same time.
   9
  10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  11 ---
  12  arch/mips/bcm63xx/irq.c |   47 ++++++++++++++++++++++++++++++++++++++++++-----
  13  1 file changed, 42 insertions(+), 5 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/irq.c
  16 +++ b/arch/mips/bcm63xx/irq.c
  17 @@ -12,6 +12,7 @@
  18  #include <linux/interrupt.h>
  19  #include <linux/module.h>
  20  #include <linux/irq.h>
  21 +#include <linux/spinlock.h>
  22  #include <asm/irq_cpu.h>
  23  #include <asm/mipsregs.h>
  24  #include <bcm63xx_cpu.h>
  25 @@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
  26  static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
  27  static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
  28
  29 +static DEFINE_SPINLOCK(ipic_lock);
  30 +static DEFINE_SPINLOCK(epic_lock);
  31 +
  32  #ifndef BCMCPU_RUNTIME_DETECT
  33  #ifdef CONFIG_BCM63XX_CPU_6328
  34  #define irq_stat_reg0          PERF_IRQSTAT_6328_REG(0)
  35 @@ -290,7 +294,9 @@ void __dispatch_internal_##width(int cpu
  36         static int i;                                                   \
  37         u32 irq_stat_addr = get_irq_stat_addr(cpu);                     \
  38         u32 irq_mask_addr = get_irq_mask_addr(cpu);                     \
  39 +       unsigned long flags;                                            \
  40                                                                         \
  41 +       spin_lock_irqsave(&ipic_lock, flags);                           \
  42         /* read registers in reverse order */                           \
  43         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
  44                 u32 val;                                                \
  45 @@ -302,6 +308,7 @@ void __dispatch_internal_##width(int cpu
  46                 if (val)                                                \
  47                         irqs_pending = true;                            \
  48         }                                                               \
  49 +       spin_unlock_irqrestore(&ipic_lock, flags);                      \
  50                                                                         \
  51         if (!irqs_pending)                                              \
  52                 return;                                                 \
  53 @@ -381,12 +388,20 @@ asmlinkage void plat_irq_dispatch(void)
  54   */
  55  static void bcm63xx_internal_irq_mask(struct irq_data *d)
  56  {
  57 +       unsigned long flags;
  58 +
  59 +       spin_lock_irqsave(&ipic_lock, flags);
  60         internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
  61 +       spin_unlock_irqrestore(&ipic_lock, flags);
  62  }
  63
  64  static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  65  {
  66 +       unsigned long flags;
  67 +
  68 +       spin_lock_irqsave(&ipic_lock, flags);
  69         internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
  70 +       spin_unlock_irqrestore(&ipic_lock, flags);
  71  }
  72
  73  /*
  74 @@ -397,8 +412,11 @@ static void bcm63xx_external_irq_mask(st
  75  {
  76         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
  77         u32 reg, regaddr;
  78 +       unsigned long flags;
  79
  80         regaddr = get_ext_irq_perf_reg(irq);
  81 +
  82 +       spin_lock_irqsave(&epic_lock, flags);
  83         reg = bcm_perf_readl(regaddr);
  84
  85         if (BCMCPU_IS_6348())
  86 @@ -407,16 +425,24 @@ static void bcm63xx_external_irq_mask(st
  87                 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
  88
  89         bcm_perf_writel(reg, regaddr);
  90 -       if (is_ext_irq_cascaded)
  91 -               internal_irq_mask(irq + ext_irq_start);
  92 +       spin_unlock_irqrestore(&epic_lock, flags);
  93 +
  94 +       if (is_ext_irq_cascaded) {
  95 +               struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
  96 +
  97 +               bcm63xx_internal_irq_mask(cd);
  98 +       }
  99  }
 100
 101  static void bcm63xx_external_irq_unmask(struct irq_data *d)
 102  {
 103         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 104         u32 reg, regaddr;
 105 +       unsigned long flags;
 106
 107         regaddr = get_ext_irq_perf_reg(irq);
 108 +
 109 +       spin_lock_irqsave(&epic_lock, flags);
 110         reg = bcm_perf_readl(regaddr);
 111
 112         if (BCMCPU_IS_6348())
 113 @@ -425,16 +451,22 @@ static void bcm63xx_external_irq_unmask(
 114                 reg |= EXTIRQ_CFG_MASK(irq % 4);
 115
 116         bcm_perf_writel(reg, regaddr);
 117 +       spin_unlock_irqrestore(&epic_lock, flags);
 118 +
 119 +       if (is_ext_irq_cascaded) {
 120 +               struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
 121
 122 -       if (is_ext_irq_cascaded)
 123 -               internal_irq_unmask(irq + ext_irq_start);
 124 +               bcm63xx_internal_irq_unmask(cd);
 125 +       }
 126  }
 127
 128  static void bcm63xx_external_irq_clear(struct irq_data *d)
 129  {
 130         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 131         u32 reg, regaddr;
 132 +       unsigned long flags;
 133
 134 +       spin_lock_irqsave(&epic_lock, flags);
 135         regaddr = get_ext_irq_perf_reg(irq);
 136         reg = bcm_perf_readl(regaddr);
 137
 138 @@ -444,6 +476,7 @@ static void bcm63xx_external_irq_clear(s
 139                 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 140
 141         bcm_perf_writel(reg, regaddr);
 142 +       spin_unlock_irqrestore(&epic_lock, flags);
 143  }
 144
 145  static int bcm63xx_external_irq_set_type(struct irq_data *d,
 146 @@ -452,6 +485,7 @@ static int bcm63xx_external_irq_set_type
 147         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 148         u32 reg, regaddr;
 149         int levelsense, sense, bothedge;
 150 +       unsigned long flags;
 151
 152         flow_type &= IRQ_TYPE_SENSE_MASK;
 153
 154 @@ -486,9 +520,11 @@ static int bcm63xx_external_irq_set_type
 155         }
 156
 157         regaddr = get_ext_irq_perf_reg(irq);
 158 -       reg = bcm_perf_readl(regaddr);
 159         irq %= 4;
 160
 161 +       spin_lock_irqsave(&epic_lock, flags);
 162 +       reg = bcm_perf_readl(regaddr);
 163 +
 164         switch (bcm63xx_get_cpu_id()) {
 165         case BCM6348_CPU_ID:
 166                 if (levelsense)
 167 @@ -529,6 +565,7 @@ static int bcm63xx_external_irq_set_type
 168         }
 169
 170         bcm_perf_writel(reg, regaddr);
 171 +       spin_unlock_irqrestore(&epic_lock, flags);
 172
 173         irqd_set_trigger_type(d, flow_type);
 174         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))