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mac80211: update to wireless-testing 2013-06-27, fix ATH_USER_REGD handling
[openwrt/staging/chunkeey.git] / target / linux / brcm63xx / patches-3.9 / 419-MIPS-BCM63XX-enable-enet-for-BCM6345.patch
1 From 1b0b5d325d0cc50cade62afd6a9416fb3cd1e658 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Mon, 7 Jan 2013 17:42:45 +0100
4 Subject: [PATCH 69/72] 443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch
5
6 ---
7 arch/mips/bcm63xx/dev-enet.c | 63 ++++++-
8 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +-
9 .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 88 +++++++++
10 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 43 ++++-
11 drivers/net/ethernet/broadcom/bcm63xx_enet.c | 199 ++++++++++++--------
12 drivers/net/ethernet/broadcom/bcm63xx_enet.h | 15 ++
13 6 files changed, 320 insertions(+), 91 deletions(-)
14
15 --- a/arch/mips/bcm63xx/dev-enet.c
16 +++ b/arch/mips/bcm63xx/dev-enet.c
17 @@ -9,10 +9,44 @@
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/platform_device.h>
21 +#include <linux/export.h>
22 #include <bcm63xx_dev_enet.h>
23 #include <bcm63xx_io.h>
24 #include <bcm63xx_regs.h>
25
26 +#ifdef BCMCPU_RUNTIME_DETECT
27 +static const unsigned long bcm6xxx_regs_enetdmac[] = {
28 + [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
29 + [ENETDMAC_IR] = ENETDMAC_IR_REG,
30 + [ENETDMAC_IRMASK] = ENETDMAC_IRMASK_REG,
31 + [ENETDMAC_MAXBURST] = ENETDMAC_MAXBURST_REG,
32 +};
33 +
34 +static const unsigned long bcm6345_regs_enetdmac[] = {
35 + [ENETDMAC_CHANCFG] = ENETDMA_6345_CHANCFG_REG,
36 + [ENETDMAC_IR] = ENETDMA_6345_IR_REG,
37 + [ENETDMAC_IRMASK] = ENETDMA_6345_IRMASK_REG,
38 + [ENETDMAC_MAXBURST] = ENETDMA_6345_MAXBURST_REG,
39 + [ENETDMAC_BUFALLOC] = ENETDMA_6345_BUFALLOC_REG,
40 + [ENETDMAC_RSTART] = ENETDMA_6345_RSTART_REG,
41 + [ENETDMAC_FC] = ENETDMA_6345_FC_REG,
42 + [ENETDMAC_LEN] = ENETDMA_6345_LEN_REG,
43 +};
44 +
45 +const unsigned long *bcm63xx_regs_enetdmac;
46 +EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
47 +
48 +static __init void bcm63xx_enetdmac_regs_init(void)
49 +{
50 + if (BCMCPU_IS_6345())
51 + bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
52 + else
53 + bcm63xx_regs_enetdmac = bcm6xxx_regs_enetdmac;
54 +}
55 +#else
56 +static __init void bcm63xx_enetdmac_regs_init(void) { }
57 +#endif
58 +
59 static struct resource shared_res[] = {
60 {
61 .start = -1, /* filled at runtime */
62 @@ -137,9 +171,14 @@ static int __init register_shared(void)
63 if (shared_device_registered)
64 return 0;
65
66 + bcm63xx_enetdmac_regs_init();
67 +
68 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
69 shared_res[0].end = shared_res[0].start;
70 - shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
71 + if (BCMCPU_IS_6345())
72 + shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
73 + else
74 + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
75
76 if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
77 chan_count = 32;
78 @@ -172,7 +211,7 @@ int __init bcm63xx_enet_register(int uni
79 if (unit > 1)
80 return -ENODEV;
81
82 - if (unit == 1 && BCMCPU_IS_6338())
83 + if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
84 return -ENODEV;
85
86 ret = register_shared();
87 @@ -213,6 +252,20 @@ int __init bcm63xx_enet_register(int uni
88 dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
89 }
90
91 + dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
92 + dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
93 + if (BCMCPU_IS_6345()) {
94 + dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
95 + dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
96 + dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
97 + dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
98 + dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
99 + dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
100 + dpd->dma_no_sram = 1;
101 + dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
102 + } else
103 + dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
104 +
105 ret = platform_device_register(pdev);
106 if (ret)
107 return ret;
108 @@ -246,6 +299,10 @@ bcm63xx_enetsw_register(const struct bcm
109 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
110 enetsw_pd.num_ports = ENETSW_PORTS_6368;
111
112 + enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
113 + enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
114 + enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
115 +
116 ret = platform_device_register(&bcm63xx_enetsw_device);
117 if (ret)
118 return ret;
119 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
120 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
121 @@ -175,6 +175,7 @@ enum bcm63xx_regs_set {
122 #define BCM_6368_RSET_SPI_SIZE 1804
123 #define RSET_ENET_SIZE 2048
124 #define RSET_ENETDMA_SIZE 256
125 +#define RSET_6345_ENETDMA_SIZE 64
126 #define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
127 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
128 #define RSET_ENETSW_SIZE 65536
129 @@ -305,7 +306,7 @@ enum bcm63xx_regs_set {
130 #define BCM_6345_USBDMA_BASE (0xfffe2800)
131 #define BCM_6345_ENET0_BASE (0xfffe1800)
132 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
133 -#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
134 +#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
135 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
136 #define BCM_6345_ENETSW_BASE (0xdeadbeef)
137 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
138 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
139 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
140 @@ -4,6 +4,8 @@
141 #include <linux/if_ether.h>
142 #include <linux/init.h>
143
144 +#include <bcm63xx_regs.h>
145 +
146 /*
147 * on board ethernet platform data
148 */
149 @@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
150 int phy_id, int reg),
151 void (*mii_write)(struct net_device *dev,
152 int phy_id, int reg, int val));
153 +
154 + /* DMA channel enable mask */
155 + u32 dma_chan_en_mask;
156 +
157 + /* DMA channel interrupt mask */
158 + u32 dma_chan_int_mask;
159 +
160 + /* Set to one if DMA engine has *no* SRAM */
161 + unsigned int dma_no_sram;
162 +
163 + /* DMA channel register width */
164 + unsigned int dma_chan_width;
165 +
166 + /* DMA descriptor shift */
167 + unsigned int dma_desc_shift;
168 };
169
170 /*
171 @@ -63,6 +80,15 @@ struct bcm63xx_enetsw_platform_data {
172 char mac_addr[ETH_ALEN];
173 int num_ports;
174 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
175 +
176 + /* DMA channel enable mask */
177 + u32 dma_chan_en_mask;
178 +
179 + /* DMA channel interrupt mask */
180 + u32 dma_chan_int_mask;
181 +
182 + /* DMA channel register width */
183 + unsigned int dma_chan_width;
184 };
185
186 int __init bcm63xx_enet_register(int unit,
187 @@ -70,4 +96,69 @@ int __init bcm63xx_enet_register(int uni
188
189 int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
190
191 +enum bcm63xx_regs_enetdmac {
192 + ENETDMAC_CHANCFG,
193 + ENETDMAC_IR,
194 + ENETDMAC_IRMASK,
195 + ENETDMAC_MAXBURST,
196 + ENETDMAC_BUFALLOC,
197 + ENETDMAC_RSTART,
198 + ENETDMAC_FC,
199 + ENETDMAC_LEN,
200 +};
201 +
202 +static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
203 +{
204 +#ifdef BCMCPU_RUNTIME_DETECT
205 + extern const unsigned long *bcm63xx_regs_enetdmac;
206 +
207 + return bcm63xx_regs_enetdmac[reg];
208 +#else
209 +#ifdef CONFIG_BCM63XX_CPU_6345
210 + switch (reg) {
211 + case ENETDMAC_CHANCFG:
212 + return ENETDMA_6345_CHANCFG_REG;
213 + case ENETDMAC_IR:
214 + return ENETDMA_6345_IR_REG;
215 + case ENETDMAC_IRMASK:
216 + return ENETDMA_6345_IRMASK_REG;
217 + case ENETDMAC_MAXBURST:
218 + return ENETDMA_6345_MAXBURST_REG;
219 + case ENETDMAC_BUFALLOC:
220 + return ENETDMA_6345_BUFALLOC_REG;
221 + case ENETDMAC_RSTART:
222 + return ENETDMA_6345_RSTART_REG;
223 + case ENETDMAC_FC:
224 + return ENETDMA_6345_FC_REG;
225 + case ENETDMAC_LEN:
226 + return ENETDMA_6345_LEN_REG;
227 + }
228 +#endif
229 +#if defined(CONFIG_BCM63XX_CPU_6328) || \
230 + defined(CONFIG_BCM63XX_CPU_6338) || \
231 + defined(CONFIG_BCM63XX_CPU_6348) || \
232 + defined(CONFIG_BCM63XX_CPU_6358) || \
233 + defined(CONFIG_BCM63XX_CPU_6362) || \
234 + defined(CONFIG_BCM63XX_CPU_6368)
235 + switch (reg) {
236 + case ENETDMAC_CHANCFG:
237 + return ENETDMAC_CHANCFG_REG;
238 + case ENETDMAC_IR:
239 + return ENETDMAC_IR_REG;
240 + case ENETDMAC_IRMASK:
241 + return ENETDMAC_IRMASK_REG;
242 + case ENETDMAC_MAXBURST:
243 + return ENETDMAC_MAXBURST_REG;
244 + case ENETDMAC_BUFALLOC:
245 + case ENETDMAC_RSTART:
246 + case ENETDMAC_FC:
247 + case ENETDMAC_LEN:
248 + return 0;
249 + }
250 +#endif
251 +#endif
252 + return 0;
253 +}
254 +
255 +
256 #endif /* ! BCM63XX_DEV_ENET_H_ */
257 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
258 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
259 @@ -730,6 +730,8 @@
260 /*************************************************************************
261 * _REG relative to RSET_ENETDMA
262 *************************************************************************/
263 +#define ENETDMA_CHAN_WIDTH 0x10
264 +#define ENETDMA_6345_CHAN_WIDTH 0x40
265
266 /* Controller Configuration Register */
267 #define ENETDMA_CFG_REG (0x0)
268 @@ -785,31 +787,56 @@
269 /* State Ram Word 4 */
270 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
271
272 +/* Broadcom 6345 ENET DMA definitions */
273 +#define ENETDMA_6345_CHANCFG_REG (0x00)
274 +
275 +#define ENETDMA_6345_MAXBURST_REG (0x40)
276 +
277 +#define ENETDMA_6345_RSTART_REG (0x08)
278 +
279 +#define ENETDMA_6345_LEN_REG (0x0C)
280 +
281 +#define ENETDMA_6345_IR_REG (0x14)
282 +
283 +#define ENETDMA_6345_IRMASK_REG (0x18)
284 +
285 +#define ENETDMA_6345_FC_REG (0x1C)
286 +
287 +#define ENETDMA_6345_BUFALLOC_REG (0x20)
288 +
289 +/* Shift down for EOP, SOP and WRAP bits */
290 +#define ENETDMA_6345_DESC_SHIFT (3)
291
292 /*************************************************************************
293 * _REG relative to RSET_ENETDMAC
294 *************************************************************************/
295
296 /* Channel Configuration register */
297 -#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
298 +#define ENETDMAC_CHANCFG_REG (0x0)
299 #define ENETDMAC_CHANCFG_EN_SHIFT 0
300 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
301 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
302 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
303 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
304 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
305 +#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
306 +#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
307 +#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
308 +#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
309 +#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
310 +#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
311
312 /* Interrupt Control/Status register */
313 -#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
314 +#define ENETDMAC_IR_REG (0x4)
315 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
316 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
317 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
318
319 /* Interrupt Mask register */
320 -#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
321 +#define ENETDMAC_IRMASK_REG (0x8)
322
323 /* Maximum Burst Length */
324 -#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
325 +#define ENETDMAC_MAXBURST_REG (0xc)
326
327
328 /*************************************************************************
329 @@ -817,16 +844,16 @@
330 *************************************************************************/
331
332 /* Ring Start Address register */
333 -#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
334 +#define ENETDMAS_RSTART_REG (0x0)
335
336 /* State Ram Word 2 */
337 -#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
338 +#define ENETDMAS_SRAM2_REG (0x4)
339
340 /* State Ram Word 3 */
341 -#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
342 +#define ENETDMAS_SRAM3_REG (0x8)
343
344 /* State Ram Word 4 */
345 -#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
346 +#define ENETDMAS_SRAM4_REG (0xc)
347
348
349 /*************************************************************************
350 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
351 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
352 @@ -115,26 +115,28 @@ static inline void enet_dma_writel(struc
353 bcm_writel(val, bcm_enet_shared_base[0] + off);
354 }
355
356 -static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
357 +static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
358 {
359 - return bcm_readl(bcm_enet_shared_base[1] + off);
360 + return bcm_readl(bcm_enet_shared_base[1] +
361 + (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
362 }
363
364 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
365 - u32 val, u32 off)
366 + u32 val, u32 off, int chan)
367 {
368 - bcm_writel(val, bcm_enet_shared_base[1] + off);
369 + bcm_writel(val, bcm_enet_shared_base[1] +
370 + (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
371 }
372
373 -static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
374 +static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
375 {
376 - return bcm_readl(bcm_enet_shared_base[2] + off);
377 + return bcm_readl(bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
378 }
379
380 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
381 - u32 val, u32 off)
382 + u32 val, u32 off, int chan)
383 {
384 - bcm_writel(val, bcm_enet_shared_base[2] + off);
385 + bcm_writel(val, bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
386 }
387
388 /*
389 @@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
390 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
391 len_stat |= DMADESC_OWNER_MASK;
392 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
393 - len_stat |= DMADESC_WRAP_MASK;
394 + len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
395 priv->rx_dirty_desc = 0;
396 } else {
397 priv->rx_dirty_desc++;
398 @@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
399 priv->rx_desc_count++;
400
401 /* tell dma engine we allocated one buffer */
402 - enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
403 + if (!priv->dma_no_sram)
404 + enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
405 + else
406 + enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
407 }
408
409 /* If rx ring is still empty, set a timer to try allocating
410 @@ -357,7 +362,8 @@ static int bcm_enet_receive_queue(struct
411
412 /* if the packet does not have start of packet _and_
413 * end of packet flag set, then just recycle it */
414 - if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
415 + if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
416 + (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
417 dev->stats.rx_dropped++;
418 continue;
419 }
420 @@ -418,8 +424,8 @@ static int bcm_enet_receive_queue(struct
421 bcm_enet_refill_rx(dev);
422
423 /* kick rx dma */
424 - enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
425 - ENETDMAC_CHANCFG_REG(priv->rx_chan));
426 + enet_dmac_writel(priv, priv->dma_chan_en_mask,
427 + ENETDMAC_CHANCFG, priv->rx_chan);
428 }
429
430 return processed;
431 @@ -494,10 +500,10 @@ static int bcm_enet_poll(struct napi_str
432 dev = priv->net_dev;
433
434 /* ack interrupts */
435 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
436 - ENETDMAC_IR_REG(priv->rx_chan));
437 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
438 - ENETDMAC_IR_REG(priv->tx_chan));
439 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
440 + ENETDMAC_IR, priv->rx_chan);
441 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
442 + ENETDMAC_IR, priv->tx_chan);
443
444 /* reclaim sent skb */
445 tx_work_done = bcm_enet_tx_reclaim(dev, 0);
446 @@ -516,10 +522,10 @@ static int bcm_enet_poll(struct napi_str
447 napi_complete(napi);
448
449 /* restore rx/tx interrupt */
450 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
451 - ENETDMAC_IRMASK_REG(priv->rx_chan));
452 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
453 - ENETDMAC_IRMASK_REG(priv->tx_chan));
454 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
455 + ENETDMAC_IRMASK, priv->rx_chan);
456 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
457 + ENETDMAC_IRMASK, priv->tx_chan);
458
459 return rx_work_done;
460 }
461 @@ -562,8 +568,8 @@ static irqreturn_t bcm_enet_isr_dma(int
462 priv = netdev_priv(dev);
463
464 /* mask rx/tx interrupts */
465 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
466 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
467 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
468 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
469
470 napi_schedule(&priv->napi);
471
472 @@ -624,14 +630,14 @@ static int bcm_enet_start_xmit(struct sk
473 DMA_TO_DEVICE);
474
475 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
476 - len_stat |= DMADESC_ESOP_MASK |
477 + len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
478 DMADESC_APPEND_CRC |
479 DMADESC_OWNER_MASK;
480
481 priv->tx_curr_desc++;
482 if (priv->tx_curr_desc == priv->tx_ring_size) {
483 priv->tx_curr_desc = 0;
484 - len_stat |= DMADESC_WRAP_MASK;
485 + len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
486 }
487 priv->tx_desc_count--;
488
489 @@ -642,8 +648,8 @@ static int bcm_enet_start_xmit(struct sk
490 wmb();
491
492 /* kick tx dma */
493 - enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
494 - ENETDMAC_CHANCFG_REG(priv->tx_chan));
495 + enet_dmac_writel(priv, priv->dma_chan_en_mask,
496 + ENETDMAC_CHANCFG, priv->tx_chan);
497
498 /* stop queue if no more desc available */
499 if (!priv->tx_desc_count)
500 @@ -771,6 +777,9 @@ static void bcm_enet_set_flow(struct bcm
501 val &= ~ENET_RXCFG_ENFLOW_MASK;
502 enet_writel(priv, val, ENET_RXCFG_REG);
503
504 + if (priv->dma_no_sram)
505 + return;
506 +
507 /* tx flow control (pause frame generation) */
508 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
509 if (tx_en)
510 @@ -886,8 +895,8 @@ static int bcm_enet_open(struct net_devi
511
512 /* mask all interrupts and request them */
513 enet_writel(priv, 0, ENET_IRMASK_REG);
514 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
515 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
516 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
517 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
518
519 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
520 if (ret)
521 @@ -964,8 +973,12 @@ static int bcm_enet_open(struct net_devi
522 priv->rx_curr_desc = 0;
523
524 /* initialize flow control buffer allocation */
525 - enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
526 - ENETDMA_BUFALLOC_REG(priv->rx_chan));
527 + if (!priv->dma_no_sram)
528 + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
529 + ENETDMA_BUFALLOC_REG(priv->rx_chan));
530 + else
531 + enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
532 + ENETDMAC_BUFALLOC, priv->rx_chan);
533
534 if (bcm_enet_refill_rx(dev)) {
535 dev_err(kdev, "cannot allocate rx skb queue\n");
536 @@ -974,18 +987,30 @@ static int bcm_enet_open(struct net_devi
537 }
538
539 /* write rx & tx ring addresses */
540 - enet_dmas_writel(priv, priv->rx_desc_dma,
541 - ENETDMAS_RSTART_REG(priv->rx_chan));
542 - enet_dmas_writel(priv, priv->tx_desc_dma,
543 - ENETDMAS_RSTART_REG(priv->tx_chan));
544 + if (!priv->dma_no_sram) {
545 + enet_dmas_writel(priv, priv->rx_desc_dma,
546 + ENETDMAS_RSTART_REG, priv->rx_chan);
547 + enet_dmas_writel(priv, priv->tx_desc_dma,
548 + ENETDMAS_RSTART_REG, priv->tx_chan);
549 + } else {
550 + enet_dmac_writel(priv, priv->rx_desc_dma,
551 + ENETDMAC_RSTART, priv->rx_chan);
552 + enet_dmac_writel(priv, priv->tx_desc_dma,
553 + ENETDMAC_RSTART, priv->tx_chan);
554 + }
555
556 /* clear remaining state ram for rx & tx channel */
557 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
558 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
559 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
560 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
561 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
562 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
563 + if (!priv->dma_no_sram) {
564 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
565 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
566 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
567 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
568 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
569 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
570 + } else {
571 + enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
572 + enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
573 + }
574
575 /* set max rx/tx length */
576 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
577 @@ -993,18 +1018,24 @@ static int bcm_enet_open(struct net_devi
578
579 /* set dma maximum burst len */
580 enet_dmac_writel(priv, priv->dma_maxburst,
581 - ENETDMAC_MAXBURST_REG(priv->rx_chan));
582 + ENETDMAC_MAXBURST, priv->rx_chan);
583 enet_dmac_writel(priv, priv->dma_maxburst,
584 - ENETDMAC_MAXBURST_REG(priv->tx_chan));
585 + ENETDMAC_MAXBURST, priv->tx_chan);
586
587 /* set correct transmit fifo watermark */
588 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
589
590 /* set flow control low/high threshold to 1/3 / 2/3 */
591 - val = priv->rx_ring_size / 3;
592 - enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
593 - val = (priv->rx_ring_size * 2) / 3;
594 - enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
595 + if (!priv->dma_no_sram) {
596 + val = priv->rx_ring_size / 3;
597 + enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
598 + val = (priv->rx_ring_size * 2) / 3;
599 + enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
600 + } else {
601 + enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
602 + enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
603 + enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
604 + }
605
606 /* all set, enable mac and interrupts, start dma engine and
607 * kick rx dma channel */
608 @@ -1013,26 +1044,26 @@ static int bcm_enet_open(struct net_devi
609 val |= ENET_CTL_ENABLE_MASK;
610 enet_writel(priv, val, ENET_CTL_REG);
611 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
612 - enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
613 - ENETDMAC_CHANCFG_REG(priv->rx_chan));
614 + enet_dmac_writel(priv, priv->dma_chan_en_mask,
615 + ENETDMAC_CHANCFG, priv->rx_chan);
616
617 /* watch "mib counters about to overflow" interrupt */
618 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
619 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
620
621 /* watch "packet transferred" interrupt in rx and tx */
622 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
623 - ENETDMAC_IR_REG(priv->rx_chan));
624 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
625 - ENETDMAC_IR_REG(priv->tx_chan));
626 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
627 + ENETDMAC_IR, priv->rx_chan);
628 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
629 + ENETDMAC_IR, priv->tx_chan);
630
631 /* make sure we enable napi before rx interrupt */
632 napi_enable(&priv->napi);
633
634 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
635 - ENETDMAC_IRMASK_REG(priv->rx_chan));
636 - enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
637 - ENETDMAC_IRMASK_REG(priv->tx_chan));
638 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
639 + ENETDMAC_IRMASK, priv->rx_chan);
640 + enet_dmac_writel(priv, priv->dma_chan_int_mask,
641 + ENETDMAC_IRMASK, priv->tx_chan);
642
643 if (priv->has_phy)
644 phy_start(priv->phydev);
645 @@ -1109,13 +1140,13 @@ static void bcm_enet_disable_dma(struct
646 {
647 int limit;
648
649 - enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
650 + enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
651
652 limit = 1000;
653 do {
654 u32 val;
655
656 - val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
657 + val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
658 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
659 break;
660 udelay(1);
661 @@ -1142,8 +1173,8 @@ static int bcm_enet_stop(struct net_devi
662
663 /* mask all interrupts */
664 enet_writel(priv, 0, ENET_IRMASK_REG);
665 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
666 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
667 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
668 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
669
670 /* make sure no mib update is scheduled */
671 cancel_work_sync(&priv->mib_update_task);
672 @@ -1751,6 +1782,11 @@ static int bcm_enet_probe(struct platfor
673 priv->pause_tx = pd->pause_tx;
674 priv->force_duplex_full = pd->force_duplex_full;
675 priv->force_speed_100 = pd->force_speed_100;
676 + priv->dma_chan_en_mask = pd->dma_chan_en_mask;
677 + priv->dma_chan_int_mask = pd->dma_chan_int_mask;
678 + priv->dma_chan_width = pd->dma_chan_width;
679 + priv->dma_no_sram = pd->dma_no_sram;
680 + priv->dma_desc_shift = pd->dma_desc_shift;
681 }
682
683 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
684 @@ -2122,8 +2158,8 @@ static int bcm_enetsw_open(struct net_de
685 kdev = &priv->pdev->dev;
686
687 /* mask all interrupts and request them */
688 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
689 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
690 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
691 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
692
693 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
694 IRQF_DISABLED, dev->name, dev);
695 @@ -2247,23 +2283,23 @@ static int bcm_enetsw_open(struct net_de
696
697 /* write rx & tx ring addresses */
698 enet_dmas_writel(priv, priv->rx_desc_dma,
699 - ENETDMAS_RSTART_REG(priv->rx_chan));
700 + ENETDMAS_RSTART_REG, priv->rx_chan);
701 enet_dmas_writel(priv, priv->tx_desc_dma,
702 - ENETDMAS_RSTART_REG(priv->tx_chan));
703 + ENETDMAS_RSTART_REG, priv->tx_chan);
704
705 /* clear remaining state ram for rx & tx channel */
706 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
707 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
708 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
709 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
710 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
711 - enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
712 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
713 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
714 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
715 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
716 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
717 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
718
719 /* set dma maximum burst len */
720 enet_dmac_writel(priv, priv->dma_maxburst,
721 - ENETDMAC_MAXBURST_REG(priv->rx_chan));
722 + ENETDMAC_MAXBURST, priv->rx_chan);
723 enet_dmac_writel(priv, priv->dma_maxburst,
724 - ENETDMAC_MAXBURST_REG(priv->tx_chan));
725 + ENETDMAC_MAXBURST, priv->tx_chan);
726
727 /* set flow control low/high threshold to 1/3 / 2/3 */
728 val = priv->rx_ring_size / 3;
729 @@ -2276,21 +2312,21 @@ static int bcm_enetsw_open(struct net_de
730 wmb();
731 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
732 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
733 - ENETDMAC_CHANCFG_REG(priv->rx_chan));
734 + ENETDMAC_CHANCFG, priv->rx_chan);
735
736 /* watch "packet transferred" interrupt in rx and tx */
737 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
738 - ENETDMAC_IR_REG(priv->rx_chan));
739 + ENETDMAC_IR, priv->rx_chan);
740 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
741 - ENETDMAC_IR_REG(priv->tx_chan));
742 + ENETDMAC_IR, priv->tx_chan);
743
744 /* make sure we enable napi before rx interrupt */
745 napi_enable(&priv->napi);
746
747 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
748 - ENETDMAC_IRMASK_REG(priv->rx_chan));
749 + ENETDMAC_IRMASK, priv->rx_chan);
750 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
751 - ENETDMAC_IRMASK_REG(priv->tx_chan));
752 + ENETDMAC_IRMASK, priv->tx_chan);
753
754 netif_carrier_on(dev);
755 netif_start_queue(dev);
756 @@ -2396,8 +2432,8 @@ static int bcm_enetsw_stop(struct net_de
757 del_timer_sync(&priv->rx_timeout);
758
759 /* mask all interrupts */
760 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
761 - enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
762 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
763 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
764
765 /* disable dma & mac */
766 bcm_enet_disable_dma(priv, priv->tx_chan);
767 @@ -2735,6 +2771,9 @@ static int bcm_enetsw_probe(struct platf
768 memcpy(priv->used_ports, pd->used_ports,
769 sizeof (pd->used_ports));
770 priv->num_ports = pd->num_ports;
771 + priv->dma_chan_en_mask = pd->dma_chan_en_mask;
772 + priv->dma_chan_int_mask = pd->dma_chan_int_mask;
773 + priv->dma_chan_width = pd->dma_chan_width;
774 }
775
776 ret = compute_hw_mtu(priv, dev->mtu);
777 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
778 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
779 @@ -339,6 +339,21 @@ struct bcm_enet_priv {
780 /* used to poll switch port state */
781 struct timer_list swphy_poll;
782 spinlock_t enetsw_mdio_lock;
783 +
784 + /* dma channel enable mask */
785 + u32 dma_chan_en_mask;
786 +
787 + /* dma channel interrupt mask */
788 + u32 dma_chan_int_mask;
789 +
790 + /* dma engine has *no* internal SRAM */
791 + unsigned int dma_no_sram;
792 +
793 + /* dma channel width */
794 + unsigned int dma_chan_width;
795 +
796 + /* dma descriptor shift value */
797 + unsigned int dma_desc_shift;
798 };
799
800 static inline int bcm_enet_port_is_rgmii(int portid)
Staging tree of Christian Lamparter