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[openwrt/staging/chunkeey.git] / target / linux / danube / files / drivers / char / danube_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 // ### TO DO: general issues:
22 // - power management
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fs.h>
37 #include <linux/proc_fs.h>
38 #include <linux/fcntl.h>
39 #include <linux/ptrace.h>
40 #include <linux/mm.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/delay.h>
44 #include <linux/spinlock.h>
45 #include <linux/slab.h>
46
47 #include <asm/system.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/uaccess.h>
51 #include <asm/bitops.h>
52
53 #include <linux/types.h>
54 #include <linux/kernel.h>
55 #include <linux/version.h>
56
57 #include <asm/danube/danube.h>
58 #include <asm/danube/danube_irq.h>
59 #include <asm/danube/ifx_ssc_defines.h>
60 #include <asm/danube/ifx_ssc.h>
61
62 #ifdef SSC_FRAME_INT_ENABLE
63 #undef SSC_FRAME_INT_ENABLE
64 #endif
65
66 #define not_yet
67
68 #define SPI_VINETIC
69
70
71
72 /* allow the user to set the major device number */
73 static int maj = 0;
74
75 /*
76 * This is the per-channel data structure containing pointers, flags
77 * and variables for the port. This driver supports a maximum of PORT_CNT.
78 * isp is allocated in ifx_ssc_init() based on the chip version.
79 */
80 static struct ifx_ssc_port *isp;
81
82 /* prototypes for fops */
83 static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
84 static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
85 //static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
86 int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
87 unsigned long);
88 int ifx_ssc_open (struct inode *, struct file *);
89 int ifx_ssc_close (struct inode *, struct file *);
90
91 /* other forward declarations */
92 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
93 static void ifx_ssc_rx_int (int, void *, struct pt_regs *);
94 static void ifx_ssc_tx_int (int, void *, struct pt_regs *);
95 static void ifx_ssc_err_int (int, void *, struct pt_regs *);
96 #ifdef SSC_FRAME_INT_ENABLE
97 static void ifx_ssc_frm_int (int, void *, struct pt_regs *);
98 #endif
99 static void tx_int (struct ifx_ssc_port *);
100 static int ifx_ssc1_read_proc (char *, char **, off_t, int, int *, void *);
101 static void ifx_gpio_init (void);
102 /************************************************************************
103 * Function declaration
104 ************************************************************************/
105 //interrupt.c
106 extern unsigned int danube_get_fpi_hz (void);
107 extern void disable_danube_irq (unsigned int irq_nr);
108 extern void enable_danube_irq (unsigned int irq_nr);
109 extern void mask_and_ack_danube_irq (unsigned int irq_nr);
110
111 /*****************************************************************/
112 typedef struct {
113 int (*request) (unsigned int, irq_handler_t handler,
114 unsigned long, const char *, void *);
115 void (*free) (unsigned int irq, void *dev_id);
116 void (*enable) (unsigned int irq);
117 void (*disable) (unsigned int irq);
118 void (*clear) (unsigned int irq);
119 } ifx_int_wrapper_t;
120
121 static ifx_int_wrapper_t ifx_int_wrapper = {
122 request:request_irq, // IM action: enable int
123 free:free_irq, // IM action: disable int
124 enable:enable_danube_irq,
125 disable:disable_danube_irq,
126 clear:mask_and_ack_danube_irq,
127 //end:
128 };
129
130 /* Fops-struct */
131 static struct file_operations ifx_ssc_fops = {
132 owner:THIS_MODULE,
133 read:ifx_ssc_read, /* read */
134 write:ifx_ssc_write, /* write */
135 // poll: ifx_ssc_poll, /* poll */
136 ioctl:ifx_ssc_ioctl, /* ioctl */
137 open:ifx_ssc_open, /* open */
138 release:ifx_ssc_close, /* release */
139 };
140
141 static inline unsigned int
142 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
143 { // ATTENTION: This function assumes that the CLC register is set with the
144 // appropriate value for RMC.
145 unsigned int rmc;
146
147 rmc = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CLC) &
148 IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
149 if (rmc == 0) {
150 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
151 return (0);
152 }
153 return (danube_get_fpi_hz () / rmc);
154 }
155
156 #ifndef not_yet
157 #ifdef IFX_SSC_INT_USE_BH
158 /*
159 * This routine is used by the interrupt handler to schedule
160 * processing in the software interrupt portion of the driver
161 * (also known as the "bottom half"). This can be called any
162 * number of times for any channel without harm.
163 */
164 static inline void
165 ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
166 {
167 info->event |= 1 << event; /* remember what kind of event and who */
168 queue_task (&info->tqueue, &tq_cyclades); /* it belongs to */
169 mark_bh (CYCLADES_BH); /* then trigger event */
170 } /* ifx_ssc_sched_event */
171
172 /*
173 * This routine is used to handle the "bottom half" processing for the
174 * serial driver, known also the "software interrupt" processing.
175 * This processing is done at the kernel interrupt level, after the
176 * cy#/_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
177 * is where time-consuming activities which can not be done in the
178 * interrupt driver proper are done; the interrupt driver schedules
179 * them using ifx_ssc_sched_event(), and they get done here.
180 *
181 * This is done through one level of indirection--the task queue.
182 * When a hardware interrupt service routine wants service by the
183 * driver's bottom half, it enqueues the appropriate tq_struct (one
184 * per port) to the tq_cyclades work queue and sets a request flag
185 * via mark_bh for processing that queue. When the time is right,
186 * do_ifx_ssc_bh is called (because of the mark_bh) and it requests
187 * that the work queue be processed.
188 *
189 * Although this may seem unwieldy, it gives the system a way to
190 * pass an argument (in this case the pointer to the ifx_ssc_port
191 * structure) to the bottom half of the driver. Previous kernels
192 * had to poll every port to see if that port needed servicing.
193 */
194 static void
195 do_ifx_ssc_bh (void)
196 {
197 run_task_queue (&tq_cyclades);
198 } /* do_ifx_ssc_bh */
199
200 static void
201 do_softint (void *private_)
202 {
203 struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
204
205 if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event)) {
206 wake_up_interruptible (&info->open_wait);
207 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
208 }
209 if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event)) {
210 wake_up_interruptible (&info->open_wait);
211 }
212 if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event)) {
213 wake_up_interruptible (&info->delta_msr_wait);
214 }
215 if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event)) {
216 wake_up_interruptible (&tty->write_wait);
217 }
218 #ifdef Z_WAKE
219 if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event)) {
220 wake_up_interruptible (&info->shutdown_wait);
221 }
222 #endif
223 } /* do_softint */
224 #endif /* IFX_SSC_INT_USE_BH */
225 #endif // not_yet
226
227 inline static void
228 rx_int (struct ifx_ssc_port *info)
229 {
230 int fifo_fill_lev, bytes_in_buf, i;
231 unsigned long tmp_val;
232 unsigned long *tmp_ptr;
233 unsigned int rx_valid_cnt;
234 /* number of words waiting in the RX FIFO */
235 fifo_fill_lev = (READ_PERIPHERAL_REGISTER (info->mapbase +
236 IFX_SSC_FSTAT) &
237 IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >>
238 IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
239 // Note: There are always 32 bits in a fifo-entry except for the last
240 // word of a contigous transfer block and except for not in rx-only
241 // mode and CON.ENBV set. But for this case it should be a convention
242 // in software which helps:
243 // In tx or rx/tx mode all transfers from the buffer to the FIFO are
244 // 32-bit wide, except for the last three bytes, which could be a
245 // combination of 16- and 8-bit access.
246 // => The whole block is received as 32-bit words as a contigous stream,
247 // even if there was a gap in tx which has the fifo run out of data!
248 // Just the last fifo entry *may* be partially filled (0, 1, 2 or 3 bytes)!
249
250 /* free space in the RX buffer */
251 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
252 // transfer with 32 bits per entry
253 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
254 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
255 *tmp_ptr =
256 READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
257 info->rxbuf_ptr += 4;
258 info->stats.rxBytes += 4;
259 fifo_fill_lev--;
260 bytes_in_buf -= 4;
261 } // while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0))
262 // now do the rest as mentioned in STATE.RXBV
263 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
264 rx_valid_cnt =
265 (READ_PERIPHERAL_REGISTER
266 (info->mapbase +
267 IFX_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK)
268 >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
269 if (rx_valid_cnt == 0)
270 break;
271 if (rx_valid_cnt > bytes_in_buf) {
272 // ### TO DO: warning message: not block aligned data, other data
273 // in this entry will be lost
274 rx_valid_cnt = bytes_in_buf;
275 }
276 tmp_val =
277 READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RB);
278
279 for (i = 0; i < rx_valid_cnt; i++) {
280 *info->rxbuf_ptr =
281 (tmp_val >> (8 * (rx_valid_cnt - i - 1))) &
282 0xff;
283 /*
284 *info->rxbuf_ptr = tmp_val & 0xff;
285 tmp_val >>= 8;
286 */
287 bytes_in_buf--;
288
289 info->rxbuf_ptr++;
290 }
291 info->stats.rxBytes += rx_valid_cnt;
292 } // while ((bytes_in_buf > 0) && (fifo_fill_lev > 0))
293
294 // check if transfer is complete
295 if (info->rxbuf_ptr >= info->rxbuf_end) {
296 ifx_int_wrapper.disable (info->rxirq);
297 /* wakeup any processes waiting in read() */
298 wake_up_interruptible (&info->rwait);
299 /* and in poll() */
300 //wake_up_interruptible(&info->pwait);
301 }
302 else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) &&
303 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) ==
304 0)) {
305 // if buffer not filled completely and rx request done initiate new transfer
306 /*
307 if (info->rxbuf_end - info->rxbuf_ptr < 65536)
308 */
309 if (info->rxbuf_end - info->rxbuf_ptr <
310 IFX_SSC_RXREQ_BLOCK_SIZE)
311 WRITE_PERIPHERAL_REGISTER ((info->rxbuf_end -
312 info->
313 rxbuf_ptr) <<
314 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
315 info->mapbase +
316 IFX_SSC_RXREQ);
317 else
318 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE <<
319 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
320 info->mapbase +
321 IFX_SSC_RXREQ);
322 }
323 } // rx_int
324
325 inline static void
326 tx_int (struct ifx_ssc_port *info)
327 {
328
329 int fifo_space, fill, i;
330 fifo_space = ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_ID) &
331 IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
332 -
333 ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_FSTAT) &
334 IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >>
335 IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
336
337 if (fifo_space == 0)
338 return;
339
340 fill = info->txbuf_end - info->txbuf_ptr;
341
342 if (fill > fifo_space * 4)
343 fill = fifo_space * 4;
344
345 for (i = 0; i < fill / 4; i++) {
346 // at first 32 bit access
347 WRITE_PERIPHERAL_REGISTER (*(UINT32 *) info->txbuf_ptr,
348 info->mapbase + IFX_SSC_TB);
349 info->txbuf_ptr += 4;
350 }
351
352 fifo_space -= fill / 4;
353 info->stats.txBytes += fill & ~0x3;
354 fill &= 0x3;
355 if ((fifo_space > 0) & (fill > 1)) {
356 // trailing 16 bit access
357 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr,
358 info->mapbase + IFX_SSC_TB);
359 info->txbuf_ptr += 2;
360 info->stats.txBytes += 2;
361 fifo_space--;
362 /* added by bingtao */
363 fill -= 2;
364 }
365 if ((fifo_space > 0) & (fill > 0)) {
366 // trailing 8 bit access
367 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr,
368 info->mapbase + IFX_SSC_TB);
369 info->txbuf_ptr++;
370 info->stats.txBytes++;
371 /*
372 fifo_space --;
373 */
374 }
375
376 // check if transmission complete
377 if (info->txbuf_ptr >= info->txbuf_end) {
378 ifx_int_wrapper.disable (info->txirq);
379 kfree (info->txbuf);
380 info->txbuf = NULL;
381 /* wake up any process waiting in poll() */
382 //wake_up_interruptible(&info->pwait);
383 }
384
385 } // tx_int
386
387 static void
388 ifx_ssc_rx_int (int irq, void *dev_id, struct pt_regs *regs)
389 {
390 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
391 //WRITE_PERIPHERAL_REGISTER(IFX_SSC_R_BIT, info->mapbase + IFX_SSC_IRN_CR);
392 rx_int (info);
393 }
394
395 static void
396 ifx_ssc_tx_int (int irq, void *dev_id, struct pt_regs *regs)
397 {
398 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
399 //WRITE_PERIPHERAL_REGISTER(IFX_SSC_T_BIT, info->mapbase + IFX_SSC_IRN_CR);
400 tx_int (info);
401 }
402
403 static void
404 ifx_ssc_err_int (int irq, void *dev_id, struct pt_regs *regs)
405 {
406 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
407 unsigned int state;
408 unsigned int write_back = 0;
409 unsigned long flags;
410
411 local_irq_save (flags);
412 state = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE);
413
414 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
415 info->stats.rxUnErr++;
416 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
417 }
418 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
419 info->stats.rxOvErr++;
420 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
421 }
422 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
423 info->stats.txOvErr++;
424 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
425 }
426 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
427 info->stats.txUnErr++;
428 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
429 }
430 // if ((state & IFX_SSC_STATE_ABORT_ERR) != 0) {
431 // info->stats.abortErr++;
432 // write_back |= IFX_SSC_WHBSTATE_CLR_ABORT_ERROR;
433 // }
434 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
435 info->stats.modeErr++;
436 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
437 }
438
439 if (write_back)
440 WRITE_PERIPHERAL_REGISTER (write_back,
441 info->mapbase + IFX_SSC_WHBSTATE);
442
443 local_irq_restore (flags);
444 }
445
446 #ifdef SSC_FRAME_INT_ENABLE
447 static void
448 ifx_ssc_frm_int (int irq, void *dev_id, struct pt_regs *regs)
449 {
450 // ### TO DO: wake up framing wait-queue in conjunction with batch execution
451 }
452 #endif
453
454 static void
455 ifx_ssc_abort (struct ifx_ssc_port *info)
456 {
457 unsigned long flags;
458 bool enabled;
459
460 local_irq_save (flags);
461
462 // disable all int's
463 ifx_int_wrapper.disable (info->rxirq);
464 ifx_int_wrapper.disable (info->txirq);
465 ifx_int_wrapper.disable (info->errirq);
466 /*
467 ifx_int_wrapper.disable(info->frmirq);
468 */
469 local_irq_restore (flags);
470
471 // disable SSC (also aborts a receive request!)
472 // ### TO DO: Perhaps it's better to abort after the receiption of a
473 // complete word. The disable cuts the transmission immediatly and
474 // releases the chip selects. This could result in unpredictable
475 // behavior of connected external devices!
476 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
477 & IFX_SSC_STATE_IS_ENABLED) != 0;
478 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE,
479 info->mapbase + IFX_SSC_WHBSTATE);
480
481 // flush fifos
482 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH,
483 info->mapbase + IFX_SSC_TXFCON);
484 WRITE_PERIPHERAL_REGISTER (IFX_SSC_XFCON_FIFO_FLUSH,
485 info->mapbase + IFX_SSC_RXFCON);
486
487 // free txbuf
488 if (info->txbuf != NULL) {
489 kfree (info->txbuf);
490 info->txbuf = NULL;
491 }
492
493 // wakeup read process
494 if (info->rxbuf != NULL)
495 wake_up_interruptible (&info->rwait);
496
497 // clear pending int's
498 ifx_int_wrapper.clear (info->rxirq);
499 ifx_int_wrapper.clear (info->txirq);
500 ifx_int_wrapper.clear (info->errirq);
501 /*
502 ifx_int_wrapper.clear(info->frmirq);
503 */
504
505 // clear error flags
506 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR,
507 info->mapbase + IFX_SSC_WHBSTATE);
508
509 //printk("IFX SSC%d: Transmission aborted\n", info->port_nr);
510 // enable SSC
511 if (enabled)
512 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE,
513 info->mapbase + IFX_SSC_WHBSTATE);
514
515 } // ifx_ssc_abort
516
517 /*
518 * This routine is called whenever a port is opened. It enforces
519 * exclusive opening of a port and enables interrupts, etc.
520 */
521 int
522 ifx_ssc_open (struct inode *inode, struct file *filp)
523 {
524 struct ifx_ssc_port *info;
525 int line;
526 int from_kernel = 0;
527
528 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
529 from_kernel = 1;
530 line = (int) inode;
531 }
532 else {
533 line = MINOR (filp->f_dentry->d_inode->i_rdev);
534 filp->f_op = &ifx_ssc_fops;
535 }
536
537 /* don't open more minor devices than we can support */
538 if (line < 0 || line >= PORT_CNT)
539 return -ENXIO;
540
541 info = &isp[line];
542
543 /* exclusive open */
544 if (info->port_is_open != 0)
545 return -EBUSY;
546 info->port_is_open++;
547
548 ifx_int_wrapper.disable (info->rxirq);
549 ifx_int_wrapper.disable (info->txirq);
550 ifx_int_wrapper.disable (info->errirq);
551 /*
552 ifx_int_wrapper.disable(info->frmirq);
553 */
554
555 /* Flush and enable TX/RX FIFO */
556 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL <<
557 IFX_SSC_XFCON_ITL_OFFSET) |
558 IFX_SSC_XFCON_FIFO_FLUSH |
559 IFX_SSC_XFCON_FIFO_ENABLE,
560 info->mapbase + IFX_SSC_TXFCON);
561 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL <<
562 IFX_SSC_XFCON_ITL_OFFSET) |
563 IFX_SSC_XFCON_FIFO_FLUSH |
564 IFX_SSC_XFCON_FIFO_ENABLE,
565 info->mapbase + IFX_SSC_RXFCON);
566
567 /* logically flush the software FIFOs */
568 info->rxbuf_ptr = 0;
569 info->txbuf_ptr = 0;
570
571 /* clear all error bits */
572 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ALL_ERROR,
573 info->mapbase + IFX_SSC_WHBSTATE);
574
575 // clear pending interrupts
576 ifx_int_wrapper.clear (info->rxirq);
577 ifx_int_wrapper.clear (info->txirq);
578 ifx_int_wrapper.clear (info->errirq);
579 /*
580 ifx_int_wrapper.clear(info->frmirq);
581 */
582
583 // enable SSC
584 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE,
585 info->mapbase + IFX_SSC_WHBSTATE);
586
587 return 0;
588 } /* ifx_ssc_open */
589
590 EXPORT_SYMBOL (ifx_ssc_open);
591
592 /*
593 * This routine is called when a particular device is closed.
594 */
595 int
596 ifx_ssc_close (struct inode *inode, struct file *filp)
597 {
598 struct ifx_ssc_port *info;
599 int idx;
600
601 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
602 idx = (int) inode;
603 else
604 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
605
606 if (idx < 0 || idx >= PORT_CNT)
607 return -ENXIO;
608
609 info = &isp[idx];
610 if (!info)
611 return -ENXIO;
612
613 // disable SSC
614 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE,
615 info->mapbase + IFX_SSC_WHBSTATE);
616
617 // call abort function to disable int's, flush fifos...
618 ifx_ssc_abort (info);
619
620 info->port_is_open--;
621
622 return 0;
623 } /* ifx_ssc_close */
624
625 EXPORT_SYMBOL (ifx_ssc_close);
626
627 /* added by bingtao */
628 /* helper routine to handle reads from the kernel or user-space */
629 /* info->rxbuf : never kfree and contains valid data */
630 /* should be points to NULL after copying data !!! */
631 static ssize_t
632 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len,
633 int from_kernel)
634 {
635 ssize_t ret_val;
636 unsigned long flags;
637
638 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
639 return -EFAULT;
640 local_irq_save (flags);
641 info->rxbuf_ptr = info->rxbuf;
642 info->rxbuf_end = info->rxbuf + len;
643 local_irq_restore (flags);
644 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
645 /* TXRX in poll mode */
646 while (info->rxbuf_ptr < info->rxbuf_end) {
647 /* This is the key point, if you don't check this condition
648 kfree (NULL) will happen
649 because tx only need write into FIFO, it's much fast than rx
650 So when rx still waiting , tx already finish and release buf
651 */
652 if (info->txbuf_ptr < info->txbuf_end) {
653 tx_int (info);
654 }
655
656 rx_int (info);
657 };
658
659 ret_val = info->rxbuf_ptr - info->rxbuf;
660 return (ret_val);
661 } // ifx_ssc_read_helper_poll
662
663 /* helper routine to handle reads from the kernel or user-space */
664 /* info->rx_buf : never kfree and contains valid data */
665 /* should be points to NULL after copying data !!! */
666 static ssize_t
667 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len,
668 int from_kernel)
669 {
670 ssize_t ret_val;
671 unsigned long flags;
672 DECLARE_WAITQUEUE (wait, current);
673
674 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
675 return -EFAULT;
676 local_irq_save (flags);
677 info->rxbuf_ptr = info->rxbuf;
678 info->rxbuf_end = info->rxbuf + len;
679 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
680 if ((info->txbuf == NULL) ||
681 (info->txbuf != info->txbuf_ptr) ||
682 (info->txbuf_end != len + info->txbuf)) {
683 local_irq_restore (flags);
684 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __FUNCTION__);
685 return -EFAULT;
686 }
687 local_irq_restore (flags);
688 /* should enable tx, right? */
689 tx_int (info);
690 if (info->txbuf_ptr < info->txbuf_end) {
691 ifx_int_wrapper.enable (info->txirq);
692 }
693
694 ifx_int_wrapper.enable (info->rxirq);
695 }
696 else { // rx mode
697 local_irq_restore (flags);
698 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) &
699 IFX_SSC_RXCNT_TODO_MASK)
700 return -EBUSY;
701 ifx_int_wrapper.enable (info->rxirq);
702 // rx request limited to ' bytes
703 /*
704 if (len < 65536)
705 */
706 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
707 WRITE_PERIPHERAL_REGISTER (len <<
708 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
709 info->mapbase +
710 IFX_SSC_RXREQ);
711 else
712 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE <<
713 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
714 info->mapbase +
715 IFX_SSC_RXREQ);
716 }
717
718 __add_wait_queue (&info->rwait, &wait);
719 set_current_state (TASK_INTERRUPTIBLE);
720 // wakeup done in rx_int
721
722 do {
723 local_irq_save (flags);
724 if (info->rxbuf_ptr >= info->rxbuf_end)
725 break;
726 local_irq_restore (flags);
727
728 // if (filp->f_flags & O_NONBLOCK)
729 // {
730 // N = -EAGAIN;
731 // goto out;
732 // }
733 if (signal_pending (current)) {
734 ret_val = -ERESTARTSYS;
735 goto out;
736 }
737 schedule ();
738 } while (1);
739
740 ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len
741 local_irq_restore (flags);
742
743 out:
744 current->state = TASK_RUNNING;
745 __remove_wait_queue (&info->rwait, &wait);
746 return (ret_val);
747 } // ifx_ssc_read_helper
748
749 #if 0
750 /* helper routine to handle reads from the kernel or user-space */
751 /* appropriate in interrupt context */
752 static ssize_t
753 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len,
754 int from_kernel)
755 {
756 ssize_t ret_val;
757 unsigned long flags;
758 DECLARE_WAITQUEUE (wait, current);
759
760 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
761 return -EFAULT;
762 local_irq_save (flags);
763 info->rxbuf_ptr = info->rxbuf;
764 info->rxbuf_end = info->rxbuf + len;
765 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
766 if ((info->txbuf == NULL) ||
767 (info->txbuf != info->txbuf_ptr) ||
768 (info->txbuf_end != len + info->txbuf)) {
769 local_irq_restore (flags);
770 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __FUNCTION__);
771 return -EFAULT;
772 }
773 local_irq_restore (flags);
774 /* should enable tx, right? */
775 tx_int (info);
776 if (!in_irq ()) {
777 if (info->txbuf_ptr < info->txbuf_end) {
778 ifx_int_wrapper.enable (info->txirq);
779 }
780 ifx_int_wrapper.enable (info->rxirq);
781 }
782 }
783 else { // rx mode
784 local_irq_restore (flags);
785 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_RXCNT) &
786 IFX_SSC_RXCNT_TODO_MASK)
787 return -EBUSY;
788 if (!in_irq ()) {
789 ifx_int_wrapper.enable (info->rxirq);
790 }
791
792 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
793 WRITE_PERIPHERAL_REGISTER (len <<
794 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
795 info->mapbase +
796 IFX_SSC_RXREQ);
797 else
798 WRITE_PERIPHERAL_REGISTER (IFX_SSC_RXREQ_BLOCK_SIZE <<
799 IFX_SSC_RXREQ_RXCOUNT_OFFSET,
800 info->mapbase +
801 IFX_SSC_RXREQ);
802 }
803 if (in_irq ()) {
804 do {
805 rx_int (info);
806 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
807 tx_int (info);
808 }
809
810 if (info->rxbuf_ptr >= info->rxbuf_end)
811 break;
812 } while (1);
813 ret_val = info->rxbuf_ptr - info->rxbuf;
814 }
815 else {
816 __add_wait_queue (&info->rwait, &wait);
817 set_current_state (TASK_INTERRUPTIBLE);
818 // wakeup done in rx_int
819
820 do {
821 local_irq_save (flags);
822 if (info->rxbuf_ptr >= info->rxbuf_end)
823 break;
824 local_irq_restore (flags);
825
826 if (signal_pending (current)) {
827 ret_val = -ERESTARTSYS;
828 goto out;
829 }
830 schedule ();
831 } while (1);
832
833 ret_val = info->rxbuf_ptr - info->rxbuf; // should be equal to len
834 local_irq_restore (flags);
835
836 out:
837 current->state = TASK_RUNNING;
838 __remove_wait_queue (&info->rwait, &wait);
839 }
840 return (ret_val);
841 } // ifx_ssc_read_helper
842 #endif
843
844 /* helper routine to handle writes to the kernel or user-space */
845 /* info->txbuf has two cases:
846 * 1) return value < 0 (-EFAULT), not touched at all
847 * 2) kfree and points to NULL in interrupt routine (but maybe later )
848 */
849 static ssize_t
850 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
851 size_t len, int from_kernel)
852 {
853 // check if in tx or tx/rx mode
854 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
855 return -EFAULT;
856
857 info->txbuf_ptr = info->txbuf;
858 info->txbuf_end = len + info->txbuf;
859 /* start the transmission (not in rx/tx, see read helper) */
860 if (info->opts.modeRxTx == IFX_SSC_MODE_TX) {
861 tx_int (info);
862 if (info->txbuf_ptr < info->txbuf_end) {
863 ifx_int_wrapper.enable (info->txirq);
864 }
865 }
866 //local_irq_restore(flags);
867 return len;
868 }
869
870 /*
871 * kernel interfaces for read and write.
872 * The caller must set port to: n for SSC<m> with n=m-1 (e.g. n=0 for SSC1)
873 */
874 ssize_t
875 ifx_ssc_kread (int port, char *kbuf, size_t len)
876 {
877 struct ifx_ssc_port *info;
878 ssize_t ret_val;
879
880 if (port < 0 || port >= PORT_CNT)
881 return -ENXIO;
882
883 if (len == 0)
884 return 0;
885
886 info = &isp[port];
887
888 // check if reception in progress
889 if (info->rxbuf != NULL) {
890 printk ("SSC device busy\n");
891 return -EBUSY;
892 }
893
894 info->rxbuf = kbuf;
895 if (info->rxbuf == NULL) {
896 printk ("SSC device error\n");
897 return -EINVAL;
898 }
899
900 /* changed by bingtao */
901 /* change by TaiCheng */
902 //if (!in_irq()){
903 if (0) {
904 ret_val = ifx_ssc_read_helper (info, kbuf, len, 1);
905 }
906 else {
907 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
908 };
909 info->rxbuf = NULL;
910
911 // ### TO DO: perhaps warn if ret_val != len
912 ifx_int_wrapper.disable (info->rxirq);
913
914 return (ret_val);
915 } // ifx_ssc_kread
916
917 EXPORT_SYMBOL (ifx_ssc_kread);
918
919 ssize_t
920 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
921 {
922 struct ifx_ssc_port *info;
923 ssize_t ret_val;
924
925 if (port < 0 || port >= PORT_CNT)
926 return -ENXIO;
927
928 if (len == 0)
929 return 0;
930
931 info = &isp[port];
932
933 // check if transmission in progress
934 if (info->txbuf != NULL)
935 return -EBUSY;
936 info->txbuf = (char *) kbuf;
937
938 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
939 if (ret_val < 0) {
940 info->txbuf = NULL;
941 }
942 return ret_val;
943 }
944
945 EXPORT_SYMBOL (ifx_ssc_kwrite);
946
947 /*
948 * user interfaces to read and write
949 */
950 static ssize_t
951 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
952 {
953 ssize_t ret_val;
954 int idx;
955 struct ifx_ssc_port *info;
956
957 /*
958 if (len == 0)
959 return (0);
960 */
961 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
962 info = &isp[idx];
963
964 // check if reception in progress
965 if (info->rxbuf != NULL)
966 return -EBUSY;
967
968 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
969 if (info->rxbuf == NULL)
970 return -ENOMEM;
971
972 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
973 // ### TO DO: perhaps warn if ret_val != len
974 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
975 ret_val = -EFAULT;
976
977 ifx_int_wrapper.disable (info->rxirq);
978
979 kfree (info->rxbuf);
980 info->rxbuf = NULL;
981 return (ret_val);
982 } // ifx_ssc_read
983
984 /*
985 * As many bytes as we have free space for are copied from the user
986 * into txbuf and the actual byte count is returned. The transmission is
987 * always kicked off by calling the appropriate TX routine.
988 */
989 static ssize_t
990 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
991 {
992 int idx;
993 struct ifx_ssc_port *info;
994 int ret_val;
995
996 if (len == 0)
997 return (0);
998
999 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
1000 info = &isp[idx];
1001
1002 // check if transmission in progress
1003 if (info->txbuf != NULL)
1004 return -EBUSY;
1005
1006 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
1007 if (info->txbuf == NULL)
1008 return -ENOMEM;
1009
1010 ret_val = copy_from_user (info->txbuf, ubuf, len);
1011 if (ret_val == 0)
1012 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
1013 else
1014 ret_val = -EFAULT;
1015 if (ret_val < 0) {
1016 kfree (info->txbuf); // otherwise will be done in ISR
1017 info->txbuf = NULL;
1018 }
1019 return (ret_val);
1020 } /* ifx_ssc_write */
1021
1022 /*
1023 * ------------------------------------------------------------
1024 * ifx_ssc_ioctl() and friends
1025 * ------------------------------------------------------------
1026 */
1027
1028 /*-----------------------------------------------------------------------------
1029 FUNC-NAME : ifx_ssc_frm_status_get
1030 LONG-NAME : framing status get
1031 PURPOSE : Get the actual status of the framing.
1032
1033 PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
1034
1035 RESULT : pointer to a structure ifx_ssc_frm_status which holds busy and
1036 count values.
1037
1038 REMARKS : Returns a register value independent of framing is enabled or
1039 not! Changes structure inside of info, so the return value isn't
1040 needed at all, but could be used for simple access.
1041 -----------------------------------------------------------------------------*/
1042 static struct ifx_ssc_frm_status *
1043 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
1044 {
1045 unsigned long tmp;
1046
1047 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFSTAT);
1048 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
1049 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
1050 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK)
1051 >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
1052 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK)
1053 >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
1054 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
1055 info->frm_status.EnIntAfterData =
1056 (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
1057 info->frm_status.EnIntAfterPause =
1058 (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
1059 return (&info->frm_status);
1060 } // ifx_ssc_frm_status_get
1061
1062 /*-----------------------------------------------------------------------------
1063 FUNC-NAME : ifx_ssc_frm_control_get
1064 LONG-NAME : framing control get
1065 PURPOSE : Get the actual control values of the framing.
1066
1067 PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
1068
1069 RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits
1070 and count reload values.
1071
1072 REMARKS : Changes structure inside of info, so the return value isn't
1073 needed at all, but could be used for simple access.
1074 -----------------------------------------------------------------------------*/
1075 static struct ifx_ssc_frm_opts *
1076 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
1077 {
1078 unsigned long tmp;
1079
1080 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON);
1081 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
1082 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK)
1083 >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
1084 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
1085 >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
1086 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK)
1087 >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
1088 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK)
1089 >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
1090 info->frm_opts.StopAfterPause =
1091 (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
1092 return (&info->frm_opts);
1093 } // ifx_ssc_frm_control_get
1094
1095 /*-----------------------------------------------------------------------------
1096 FUNC-NAME : ifx_ssc_frm_control_set
1097 LONG-NAME : framing control set
1098 PURPOSE : Set the actual control values of the framing.
1099
1100 PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
1101
1102 RESULT : pointer to a structure ifx_ssc_frm_opts which holds control bits
1103 and count reload values.
1104
1105 REMARKS :
1106 -----------------------------------------------------------------------------*/
1107 static int
1108 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
1109 {
1110 unsigned long tmp;
1111
1112 // check parameters
1113 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX) ||
1114 (info->frm_opts.DataLength < 1) ||
1115 (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX) ||
1116 (info->frm_opts.PauseLength < 1) ||
1117 ((info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >>
1118 IFX_SSC_SFCON_PAUSE_DATA_OFFSET)) !=
1119 0)
1120 ||
1121 ((info->frm_opts.
1122 IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >>
1123 IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)) != 0))
1124 return -EINVAL;
1125
1126 // read interrupt bits (they're not changed here)
1127 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_SFCON) &
1128 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE |
1129 IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
1130
1131 // set all values with respect to it's bit position (for data and pause
1132 // length set N-1)
1133 tmp = (info->frm_opts.DataLength -
1134 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
1135 tmp |= (info->frm_opts.PauseLength -
1136 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
1137 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
1138 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
1139 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
1140 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
1141
1142 WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_SFCON);
1143
1144 return 0;
1145 } // ifx_ssc_frm_control_set
1146
1147 /*-----------------------------------------------------------------------------
1148 FUNC-NAME : ifx_ssc_rxtx_mode_set
1149 LONG-NAME : rxtx mode set
1150 PURPOSE : Set the transmission mode.
1151
1152 PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
1153
1154 RESULT : Returns error code
1155
1156 REMARKS : Assumes that SSC not used (SSC disabled, device not opened yet
1157 or just closed)
1158 -----------------------------------------------------------------------------*/
1159 static int
1160 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
1161 {
1162 unsigned long tmp;
1163
1164 // check parameters
1165 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
1166 return -EINVAL;
1167 /*check BUSY and RXCNT */
1168 if (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) &
1169 IFX_SSC_STATE_BUSY
1170 || READ_PERIPHERAL_REGISTER (info->mapbase +
1171 IFX_SSC_RXCNT) &
1172 IFX_SSC_RXCNT_TODO_MASK)
1173 return -EBUSY;
1174 // modify
1175 tmp = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
1176 ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
1177 WRITE_PERIPHERAL_REGISTER (tmp, info->mapbase + IFX_SSC_CON);
1178 info->opts.modeRxTx = val;
1179 /*
1180 printk(KERN_DEBUG "IFX SSC%d: Setting mode to %s%s\n",
1181 info->port_nr,
1182 ((val & IFX_SSC_CON_RX_OFF) == 0) ? "rx ":"",
1183 ((val & IFX_SSC_CON_TX_OFF) == 0) ? "tx":"");
1184 */
1185 return 0;
1186 } // ifx_ssc_rxtx_mode_set
1187
1188 void
1189 ifx_gpio_init (void)
1190 {
1191 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
1192 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
1193 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
1194 *(DANUBE_GPIO_P0_DIR) = (*DANUBE_GPIO_P0_DIR) | (0xA000);
1195 *(DANUBE_GPIO_P0_ALTSEL0) =
1196 (((*DANUBE_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
1197 *(DANUBE_GPIO_P0_ALTSEL1) =
1198 (((*DANUBE_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
1199 *(DANUBE_GPIO_P0_OD) = (*DANUBE_GPIO_P0_OD) | 0xA000;
1200
1201 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
1202 *(DANUBE_GPIO_P1_DIR) = ((*DANUBE_GPIO_P1_DIR) | (0x46)) & (~1);
1203 *(DANUBE_GPIO_P1_ALTSEL0) = ((*DANUBE_GPIO_P1_ALTSEL0) | (0x47));
1204 *(DANUBE_GPIO_P1_ALTSEL1) = (*DANUBE_GPIO_P1_ALTSEL1) & (~0x47);
1205 *(DANUBE_GPIO_P1_OD) = (*DANUBE_GPIO_P1_OD) | 0x0046;
1206
1207 /*CS3 */
1208 /*TODO: CS4 CS5 CS6 */
1209 *DANUBE_GPIO_P0_OUT = ((*DANUBE_GPIO_P0_OUT) | 0x2000);
1210
1211 }
1212
1213 /*
1214 * This routine intializes the SSC appropriately depending
1215 * on slave/master and full-/half-duplex mode.
1216 * It assumes that the SSC is disabled and the fifo's and buffers
1217 * are flushes later on.
1218 */
1219 static int
1220 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
1221 {
1222 unsigned long flags, bits;
1223 struct ifx_ssc_hwopts *opts = &info->opts;
1224
1225 /* sanity checks */
1226 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH) ||
1227 (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH)) {
1228 printk ("%s: sanity check failed\n", __FUNCTION__);
1229 return -EINVAL;
1230 }
1231 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
1232 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
1233 // if (opts->abortErrDetect)
1234 // bits |= IFX_SSC_CON_ABORT_ERR_CHECK;
1235 if (opts->rxOvErrDetect)
1236 bits |= IFX_SSC_CON_RX_OFL_CHECK;
1237 if (opts->rxUndErrDetect)
1238 bits |= IFX_SSC_CON_RX_UFL_CHECK;
1239 if (opts->txOvErrDetect)
1240 bits |= IFX_SSC_CON_TX_OFL_CHECK;
1241 if (opts->txUndErrDetect)
1242 bits |= IFX_SSC_CON_TX_UFL_CHECK;
1243 if (opts->loopBack)
1244 bits |= IFX_SSC_CON_LOOPBACK_MODE;
1245 if (opts->echoMode)
1246 bits |= IFX_SSC_CON_ECHO_MODE_ON;
1247 if (opts->headingControl)
1248 bits |= IFX_SSC_CON_MSB_FIRST;
1249 if (opts->clockPhase)
1250 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
1251 if (opts->clockPolarity)
1252 bits |= IFX_SSC_CON_CLOCK_FALL;
1253 switch (opts->modeRxTx) {
1254 case IFX_SSC_MODE_TX:
1255 bits |= IFX_SSC_CON_RX_OFF;
1256 break;
1257 case IFX_SSC_MODE_RX:
1258 bits |= IFX_SSC_CON_TX_OFF;
1259 break;
1260 } // switch (opts->modeRxT)
1261 local_irq_save (flags);
1262 WRITE_PERIPHERAL_REGISTER (bits, info->mapbase + IFX_SSC_CON);
1263 WRITE_PERIPHERAL_REGISTER ((info->opts.
1264 gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
1265 (info->opts.
1266 gpoInv << IFX_SSC_GPOCON_INVOUT0_POS),
1267 info->mapbase + IFX_SSC_GPOCON);
1268 /*TODO: disable cs */
1269 WRITE_PERIPHERAL_REGISTER (info->opts.
1270 gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS,
1271 info->mapbase + IFX_SSC_WHBGPOSTAT);
1272
1273 //master mode
1274 if (opts->masterSelect) {
1275 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_MASTER_SELECT,
1276 info->mapbase + IFX_SSC_WHBSTATE);
1277 }
1278 else {
1279 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_MASTER_SELECT,
1280 info->mapbase + IFX_SSC_WHBSTATE);
1281 }
1282 // init serial framing
1283 WRITE_PERIPHERAL_REGISTER (0, info->mapbase + IFX_SSC_SFCON);
1284 /* set up the port pins */
1285 //check for general requirements to switch (external) pad/pin characteristics
1286 ifx_gpio_init ();
1287 local_irq_restore (flags);
1288
1289 return 0;
1290 } // ifx_ssc_sethwopts
1291
1292 static int
1293 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
1294 {
1295 unsigned int ifx_ssc_clock;
1296 unsigned int br;
1297 unsigned long flags;
1298 bool enabled;
1299
1300 ifx_ssc_clock = ifx_ssc_get_kernel_clk (info);
1301 if (ifx_ssc_clock == 0)
1302 return -EINVAL;
1303 local_irq_save (flags);
1304 /* have to disable the SSC to set the baudrate */
1305 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1306 & IFX_SSC_STATE_IS_ENABLED) != 0;
1307 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE,
1308 info->mapbase + IFX_SSC_WHBSTATE);
1309
1310 // compute divider
1311 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
1312 asm ("SYNC");
1313 if (br > 0xffff ||
1314 ((br == 0) &&
1315 ((READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE) &
1316 IFX_SSC_STATE_IS_MASTER) == 0))) {
1317 local_irq_restore (flags);
1318 printk ("%s: illegal baudrate %u\n", __FUNCTION__, baud);
1319 return -EINVAL;
1320 }
1321 WRITE_PERIPHERAL_REGISTER (br, info->mapbase + IFX_SSC_BR);
1322 if (enabled)
1323 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE,
1324 info->mapbase + IFX_SSC_WHBSTATE);
1325
1326 local_irq_restore (flags);
1327 return 0;
1328 } // ifx_ssc_set_baud
1329
1330 static int
1331 ifx_ssc_hwinit (struct ifx_ssc_port *info)
1332 {
1333 unsigned long flags;
1334 bool enabled;
1335
1336 /* have to disable the SSC */
1337 enabled = (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1338 & IFX_SSC_STATE_IS_ENABLED) != 0;
1339 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE,
1340 info->mapbase + IFX_SSC_WHBSTATE);
1341
1342 if (ifx_ssc_sethwopts (info) < 0) {
1343 printk ("%s: setting the hardware options failed\n",
1344 __FUNCTION__);
1345 return -EINVAL;
1346 }
1347
1348 if (ifx_ssc_set_baud (info, info->baud) < 0) {
1349 printk ("%s: setting the baud rate failed\n", __FUNCTION__);
1350 return -EINVAL;
1351 }
1352 local_irq_save (flags);
1353 /* TX FIFO */
1354 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_TXFIFO_FL <<
1355 IFX_SSC_XFCON_ITL_OFFSET) |
1356 IFX_SSC_XFCON_FIFO_ENABLE,
1357 info->mapbase + IFX_SSC_TXFCON);
1358 /* RX FIFO */
1359 WRITE_PERIPHERAL_REGISTER ((IFX_SSC_DEF_RXFIFO_FL <<
1360 IFX_SSC_XFCON_ITL_OFFSET) |
1361 IFX_SSC_XFCON_FIFO_ENABLE,
1362 info->mapbase + IFX_SSC_RXFCON);
1363 local_irq_restore (flags);
1364 if (enabled)
1365 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_SET_ENABLE,
1366 info->mapbase + IFX_SSC_WHBSTATE);
1367 return 0;
1368 } // ifx_ssc_hwinit
1369
1370 /*-----------------------------------------------------------------------------
1371 FUNC-NAME : ifx_ssc_batch_exec
1372 LONG-NAME :
1373 PURPOSE :
1374
1375 PARAMETER : *info pointer to the port-specific structure ifx_ssc_port.
1376
1377 RESULT : Returns error code
1378
1379 REMARKS :
1380 -----------------------------------------------------------------------------*/
1381 static int
1382 ifx_ssc_batch_exec (struct ifx_ssc_port *info,
1383 struct ifx_ssc_batch_list *batch_anchor)
1384 {
1385 // ### TO DO: implement user space batch execution
1386 // first, copy the whole linked list from user to kernel space
1387 // save some hardware options
1388 // execute list
1389 // restore hardware options if selected
1390 return -EFAULT;
1391 } // ifx_ssc_batch_exec
1392
1393 /*
1394 * This routine allows the driver to implement device-
1395 * specific ioctl's. If the ioctl number passed in cmd is
1396 * not recognized by the driver, it should return ENOIOCTLCMD.
1397 */
1398 int
1399 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd,
1400 unsigned long data)
1401 {
1402 struct ifx_ssc_port *info;
1403 int line, ret_val = 0;
1404 unsigned long flags;
1405 unsigned long tmp;
1406 int from_kernel = 0;
1407
1408 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
1409 from_kernel = 1;
1410 line = (int) inode;
1411 }
1412 else
1413 line = MINOR (filp->f_dentry->d_inode->i_rdev);
1414
1415 /* don't use more minor devices than we can support */
1416 if (line < 0 || line >= PORT_CNT)
1417 return -ENXIO;
1418
1419 info = &isp[line];
1420
1421 switch (cmd) {
1422 case IFX_SSC_STATS_READ:
1423 /* data must be a pointer to a struct ifx_ssc_statistics */
1424 if (from_kernel)
1425 memcpy ((void *) data, (void *) &info->stats,
1426 sizeof (struct ifx_ssc_statistics));
1427 else if (copy_to_user ((void *) data,
1428 (void *) &info->stats,
1429 sizeof (struct ifx_ssc_statistics)))
1430 ret_val = -EFAULT;
1431 break;
1432 case IFX_SSC_STATS_RESET:
1433 /* just resets the statistics counters */
1434 memset ((void *) &info->stats, 0,
1435 sizeof (struct ifx_ssc_statistics));
1436 break;
1437 case IFX_SSC_BAUD_SET:
1438 /* if the buffers are not empty then the port is */
1439 /* busy and we shouldn't change things on-the-fly! */
1440 if (!info->txbuf || !info->rxbuf ||
1441 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1442 & IFX_SSC_STATE_BUSY)) {
1443 ret_val = -EBUSY;
1444 break;
1445 }
1446 /* misuse flags */
1447 if (from_kernel)
1448 flags = *((unsigned long *) data);
1449 else if (copy_from_user ((void *) &flags,
1450 (void *) data, sizeof (flags))) {
1451 ret_val = -EFAULT;
1452 break;
1453 }
1454 if (flags == 0) {
1455 ret_val = -EINVAL;
1456 break;
1457 }
1458 if (ifx_ssc_set_baud (info, flags) < 0) {
1459 ret_val = -EINVAL;
1460 break;
1461 }
1462 info->baud = flags;
1463 break;
1464 case IFX_SSC_BAUD_GET:
1465 if (from_kernel)
1466 *((unsigned int *) data) = info->baud;
1467 else if (copy_to_user ((void *) data,
1468 (void *) &info->baud,
1469 sizeof (unsigned long)))
1470 ret_val = -EFAULT;
1471 break;
1472 case IFX_SSC_RXTX_MODE_SET:
1473 if (from_kernel)
1474 tmp = *((unsigned long *) data);
1475 else if (copy_from_user ((void *) &tmp,
1476 (void *) data, sizeof (tmp))) {
1477 ret_val = -EFAULT;
1478 break;
1479 }
1480 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
1481 break;
1482 case IFX_SSC_RXTX_MODE_GET:
1483 tmp = READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_CON) &
1484 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
1485 if (from_kernel)
1486 *((unsigned int *) data) = tmp;
1487 else if (copy_to_user ((void *) data,
1488 (void *) &tmp, sizeof (tmp)))
1489 ret_val = -EFAULT;
1490 break;
1491
1492 case IFX_SSC_ABORT:
1493 ifx_ssc_abort (info);
1494 break;
1495
1496 case IFX_SSC_GPO_OUT_SET:
1497 if (from_kernel)
1498 tmp = *((unsigned long *) data);
1499 else if (copy_from_user ((void *) &tmp,
1500 (void *) data, sizeof (tmp))) {
1501 ret_val = -EFAULT;
1502 break;
1503 }
1504 if (tmp > IFX_SSC_MAX_GPO_OUT)
1505 ret_val = -EINVAL;
1506 else
1507 WRITE_PERIPHERAL_REGISTER
1508 (1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
1509 info->mapbase + IFX_SSC_WHBGPOSTAT);
1510 break;
1511 case IFX_SSC_GPO_OUT_CLR:
1512 if (from_kernel)
1513 tmp = *((unsigned long *) data);
1514 else if (copy_from_user ((void *) &tmp,
1515 (void *) data, sizeof (tmp))) {
1516 ret_val = -EFAULT;
1517 break;
1518 }
1519 if (tmp > IFX_SSC_MAX_GPO_OUT)
1520 ret_val = -EINVAL;
1521 else {
1522 WRITE_PERIPHERAL_REGISTER
1523 (1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1524 info->mapbase + IFX_SSC_WHBGPOSTAT);
1525 }
1526 break;
1527 case IFX_SSC_GPO_OUT_GET:
1528 tmp = READ_PERIPHERAL_REGISTER
1529 (info->mapbase + IFX_SSC_GPOSTAT);
1530 if (from_kernel)
1531 *((unsigned int *) data) = tmp;
1532 else if (copy_to_user ((void *) data,
1533 (void *) &tmp, sizeof (tmp)))
1534 ret_val = -EFAULT;
1535 break;
1536 case IFX_SSC_FRM_STATUS_GET:
1537 ifx_ssc_frm_status_get (info);
1538 if (from_kernel)
1539 memcpy ((void *) data, (void *) &info->frm_status,
1540 sizeof (struct ifx_ssc_frm_status));
1541 else if (copy_to_user ((void *) data,
1542 (void *) &info->frm_status,
1543 sizeof (struct ifx_ssc_frm_status)))
1544 ret_val = -EFAULT;
1545 break;
1546 case IFX_SSC_FRM_CONTROL_GET:
1547 ifx_ssc_frm_control_get (info);
1548 if (from_kernel)
1549 memcpy ((void *) data, (void *) &info->frm_opts,
1550 sizeof (struct ifx_ssc_frm_opts));
1551 else if (copy_to_user ((void *) data,
1552 (void *) &info->frm_opts,
1553 sizeof (struct ifx_ssc_frm_opts)))
1554 ret_val = -EFAULT;
1555 break;
1556 case IFX_SSC_FRM_CONTROL_SET:
1557 if (from_kernel)
1558 memcpy ((void *) &info->frm_opts, (void *) data,
1559 sizeof (struct ifx_ssc_frm_opts));
1560 else if (copy_to_user ((void *) &info->frm_opts,
1561 (void *) data,
1562 sizeof (struct ifx_ssc_frm_opts))) {
1563 ret_val = -EFAULT;
1564 break;
1565 }
1566 ret_val = ifx_ssc_frm_control_set (info);
1567 break;
1568 case IFX_SSC_HWOPTS_SET:
1569 /* data must be a pointer to a struct ifx_ssc_hwopts */
1570 /* if the buffers are not empty then the port is */
1571 /* busy and we shouldn't change things on-the-fly! */
1572 if (!info->txbuf || !info->rxbuf ||
1573 (READ_PERIPHERAL_REGISTER (info->mapbase + IFX_SSC_STATE)
1574 & IFX_SSC_STATE_BUSY)) {
1575 ret_val = -EBUSY;
1576 break;
1577 }
1578 if (from_kernel)
1579 memcpy ((void *) &info->opts, (void *) data,
1580 sizeof (struct ifx_ssc_hwopts));
1581 else if (copy_from_user ((void *) &info->opts,
1582 (void *) data,
1583 sizeof (struct ifx_ssc_hwopts))) {
1584 ret_val = -EFAULT;
1585 break;
1586 }
1587 if (ifx_ssc_hwinit (info) < 0) {
1588 ret_val = -EIO;
1589 }
1590 break;
1591 case IFX_SSC_HWOPTS_GET:
1592 /* data must be a pointer to a struct ifx_ssc_hwopts */
1593 if (from_kernel)
1594 memcpy ((void *) data, (void *) &info->opts,
1595 sizeof (struct ifx_ssc_hwopts));
1596 else if (copy_to_user ((void *) data,
1597 (void *) &info->opts,
1598 sizeof (struct ifx_ssc_hwopts)))
1599 ret_val = -EFAULT;
1600 break;
1601 default:
1602 ret_val = -ENOIOCTLCMD;
1603 }
1604
1605 return ret_val;
1606 } /* ifx_ssc_ioctl */
1607
1608 EXPORT_SYMBOL (ifx_ssc_ioctl);
1609
1610 ///* the poll routine */
1611 //static unsigned int
1612 //ifx_ssc_poll(struct file *filp, struct poll_table_struct *pts)
1613 //{
1614 // int unit = MINOR(filp->f_dentry->d_inode->i_rdev);
1615 // struct ifx_ssc_port *info;
1616 // unsigned int mask = 0;
1617 // int spc;
1618 //
1619 // info = &isp[unit];
1620 //
1621 // /* add event to the wait queues */
1622 // /* DO NOT FORGET TO DO A WAKEUP ON THESE !!!! */
1623 // poll_wait(filp, &info->pwait, pts);
1624 //
1625 // /* are there bytes in the RX SW-FIFO? */
1626 // if (info->rxrp != info->rxwp)
1627 // mask |= POLLIN | POLLRDNORM;
1628 //
1629 // /* free space in the TX SW-FIFO */
1630 // spc = info->txrp - info->txwp - 1;
1631 // if (spc < 0)
1632 // spc += TX_BUFSIZE;
1633 //#ifdef IFX_SSC_USEDMA
1634 // /* writing always works, except in the DMA case when all descriptors */
1635 // /* are used up */
1636 // if (unit == 1 && info->dma_freecnt == 0)
1637 // spc = 0;
1638 //#endif
1639 // if (spc > 0)
1640 // mask |= POLLOUT | POLLWRNORM;
1641 //
1642 // return (mask);
1643 //}
1644
1645 static int
1646 ifx_ssc1_read_proc (char *page, char **start, off_t offset, int count,
1647 int *eof, void *data)
1648 {
1649 int off = 0;
1650 unsigned long flags;
1651
1652 /* don't want any interrupts here */
1653 local_save_flags(flags);
1654 local_irq_disable();
1655
1656 /* print statistics */
1657 off += sprintf (page + off,
1658 "Statistics for Infineon Synchronous Serial Controller SSC1\n");
1659 off += sprintf (page + off, "RX overflow errors %d\n",
1660 isp[0].stats.rxOvErr);
1661 off += sprintf (page + off, "RX underflow errors %d\n",
1662 isp[0].stats.rxUnErr);
1663 off += sprintf (page + off, "TX overflow errors %d\n",
1664 isp[0].stats.txOvErr);
1665 off += sprintf (page + off, "TX underflow errors %d\n",
1666 isp[0].stats.txUnErr);
1667 off += sprintf (page + off, "Abort errors %d\n",
1668 isp[0].stats.abortErr);
1669 off += sprintf (page + off, "Mode errors %d\n", isp[0].stats.modeErr);
1670 off += sprintf (page + off, "RX Bytes %d\n", isp[0].stats.rxBytes);
1671 off += sprintf (page + off, "TX Bytes %d\n", isp[0].stats.txBytes);
1672
1673 local_irq_restore(flags); /* XXXXX */
1674 *eof = 1;
1675 return (off);
1676 }
1677
1678 /*
1679 * This routine prints out the appropriate serial driver version number
1680 */
1681 static inline void
1682 show_version (void)
1683 {
1684 #if 0
1685 printk ("Infineon Technologies Synchronous Serial Controller (SSC) driver\n" " version %s - built %s %s\n", IFX_SSC_DRV_VERSION, __DATE__, __TIME__);
1686 #endif
1687 } /* show_version */
1688
1689 /*
1690 * Due to the fact that a port can be dynamically switched between slave
1691 * and master mode using an IOCTL the hardware is not initialized here,
1692 * but in ifx_ssc_hwinit() as a result of an IOCTL.
1693 */
1694 int __init
1695 ifx_ssc_init (void)
1696 {
1697 struct ifx_ssc_port *info;
1698 int i, nbytes;
1699 unsigned long flags;
1700 int ret_val;
1701
1702 // ### TO DO: dynamic port count evaluation due to pin multiplexing
1703
1704 ret_val = -ENOMEM;
1705 nbytes = PORT_CNT * sizeof (struct ifx_ssc_port);
1706 isp = (struct ifx_ssc_port *) kmalloc (nbytes, GFP_KERNEL);
1707 if (isp == NULL) {
1708 printk ("%s: no memory for isp\n", __FUNCTION__);
1709 return (ret_val);
1710 }
1711 memset (isp, 0, nbytes);
1712
1713 show_version ();
1714
1715 /* register the device */
1716 ret_val = -ENXIO;
1717 /*
1718 i = maj;
1719 */
1720 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0) {
1721 printk ("Unable to register major %d for the Infineon SSC\n",
1722 maj);
1723 if (maj == 0) {
1724 goto errout;
1725 }
1726 else {
1727 maj = 0;
1728 if ((i =
1729 register_chrdev (maj, "ssc",
1730 &ifx_ssc_fops)) < 0) {
1731 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1732 goto errout;
1733 }
1734 }
1735 }
1736 if (maj == 0)
1737 maj = i;
1738 //printk("registered major %d for Infineon SSC\n", maj);
1739
1740 /* set default values in ifx_ssc_port */
1741 for (i = 0; i < PORT_CNT; i++) {
1742 info = &isp[i];
1743 info->port_nr = i;
1744 /* default values for the HwOpts */
1745 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1746 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1747 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1748 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1749 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1750 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1751 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1752 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1753 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1754 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1755 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1756 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1757 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1758 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1759 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1760 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1761 info->baud = IFX_SSC_DEF_BAUDRATE;
1762 info->rxbuf = NULL;
1763 info->txbuf = NULL;
1764 /* values specific to SSC1 */
1765 if (i == 0) {
1766 info->mapbase = DANUBE_SSC1_BASE_ADDR;
1767 // ### TO DO: power management
1768
1769 // setting interrupt vectors
1770 info->txirq = DANUBE_SSC_TIR;
1771 info->rxirq = DANUBE_SSC_RIR;
1772 info->errirq = DANUBE_SSC_EIR;
1773 /*
1774 info->frmirq = IFX_SSC_FIR;
1775 */
1776 }
1777 /* activate SSC */
1778 /* CLC.DISS = 0 */
1779 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC <<
1780 IFX_CLC_RUN_DIVIDER_OFFSET,
1781 info->mapbase + IFX_SSC_CLC);
1782
1783 // ### TO DO: multiple instances
1784
1785 init_waitqueue_head (&info->rwait);
1786 //init_waitqueue_head(&info->pwait);
1787
1788 local_irq_save (flags);
1789
1790 // init serial framing register
1791 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_SFCON,
1792 info->mapbase + IFX_SSC_SFCON);
1793
1794 /* try to get the interrupts */
1795 // ### TO DO: interrupt handling with multiple instances
1796 ret_val =
1797 ifx_int_wrapper.request (info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
1798 if (ret_val) {
1799 printk ("%s: unable to get irq %d\n", __FUNCTION__,
1800 info->txirq);
1801 local_irq_restore (flags);
1802 goto errout;
1803 }
1804 ret_val =
1805 ifx_int_wrapper.request (info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
1806 if (ret_val) {
1807 printk ("%s: unable to get irq %d\n", __FUNCTION__,
1808 info->rxirq);
1809 local_irq_restore (flags);
1810 goto irqerr;
1811 }
1812 ret_val =
1813 ifx_int_wrapper.request (info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
1814 if (ret_val) {
1815 printk ("%s: unable to get irq %d\n", __FUNCTION__,
1816 info->errirq);
1817 local_irq_restore (flags);
1818 goto irqerr;
1819 }
1820 /*
1821 ret_val = ifx_int_wrapper.request(info->frmirq, ifx_ssc_frm_int,
1822 0, "ifx_ssc_frm", info);
1823 if (ret_val){
1824 printk("%s: unable to get irq %d\n", __FUNCTION__,
1825 info->frmirq);
1826 local_irq_restore(flags);
1827 goto irqerr;
1828 }
1829
1830 */
1831 WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_IRNEN,
1832 info->mapbase + IFX_SSC_IRN_EN);
1833 ifx_int_wrapper.enable (info->txirq);
1834 ifx_int_wrapper.enable (info->rxirq);
1835 ifx_int_wrapper.enable (info->errirq);
1836
1837 local_irq_restore (flags);
1838 } // for (i = 0; i < PORT_CNT; i++)
1839
1840 /* init the SSCs with default values */
1841 for (i = 0; i < PORT_CNT; i++) {
1842 info = &isp[i];
1843 if (ifx_ssc_hwinit (info) < 0) {
1844 printk ("%s: hardware init failed for port %d\n",
1845 __FUNCTION__, i);
1846 goto irqerr;
1847 }
1848 }
1849
1850 /* register /proc read handler */
1851 // ### TO DO: multiple instances
1852 /* for SSC1, which is always present */
1853 create_proc_read_entry ("driver/ssc1", 0, NULL, ifx_ssc1_read_proc,
1854 NULL);
1855 return 0;
1856
1857 irqerr:
1858 // ### TO DO: multiple instances
1859 ifx_int_wrapper.free (isp[0].txirq, &isp[0]);
1860 ifx_int_wrapper.free (isp[0].rxirq, &isp[0]);
1861 ifx_int_wrapper.free (isp[0].errirq, &isp[0]);
1862 /*
1863 ifx_int_wrapper.free(isp[0].frmirq, &isp[0]);
1864 */
1865 errout:
1866 /* free up any allocated memory in the error case */
1867 kfree (isp);
1868 return (ret_val);
1869 } /* ifx_ssc_init */
1870
1871 void
1872 ifx_ssc_cleanup_module (void)
1873 {
1874 int i;
1875
1876 /* free up any allocated memory */
1877 for (i = 0; i < PORT_CNT; i++) {
1878 /* disable the SSC */
1879 WRITE_PERIPHERAL_REGISTER (IFX_SSC_WHBSTATE_CLR_ENABLE,
1880 isp[i].mapbase + IFX_SSC_WHBSTATE);
1881 /* free the interrupts */
1882 ifx_int_wrapper.free (isp[i].txirq, &isp[i]);
1883 ifx_int_wrapper.free (isp[i].rxirq, &isp[i]);
1884 ifx_int_wrapper.free (isp[i].errirq, &isp[i]);
1885 /*
1886 ifx_int_wrapper.free(isp[i].frmirq, &isp[i]);
1887
1888 if (isp[i].rxbuf != NULL)
1889 kfree(isp[i].rxbuf);
1890 if (isp[i].txbuf != NULL)
1891 kfree(isp[i].txbuf);
1892 */
1893 }
1894 kfree (isp);
1895 /* unregister the device */
1896 // if (unregister_chrdev (maj, "ssc")) {
1897 // printk ("Unable to unregister major %d for the SSC\n", maj);
1898 // }
1899 /* delete /proc read handler */
1900 remove_proc_entry ("driver/ssc1", NULL);
1901 remove_proc_entry ("driver/ssc2", NULL);
1902 } /* ifx_ssc_cleanup_module */
1903
1904 module_exit (ifx_ssc_cleanup_module);
1905
1906 /* Module entry-points */
1907 module_init (ifx_ssc_init);
1908
1909 #ifndef MODULE
1910 static int __init
1911 ifx_ssc_set_maj (char *str)
1912 {
1913 maj = simple_strtol (str, NULL, 0);
1914 return 1;
1915 }
1916
1917 __setup ("ssc_maj=", ifx_ssc_set_maj);
1918 #endif /* !MODULE */
1919
1920 #define DANUBE_SSC_EMSG(fmt,arg...) printk("%s: "fmt,__FUNCTION__, ##arg)
1921 /* Brief: chip select enable
1922 */
1923 inline int
1924 ifx_ssc_cs_low (u32 pin)
1925 {
1926 int ret = 0;
1927 if ((ret =
1928 ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR,
1929 (unsigned long) &pin))) {
1930 DANUBE_SSC_EMSG ("clear CS %d fails\n", pin);
1931 }
1932 wmb ();
1933 return ret;
1934 }
1935
1936 EXPORT_SYMBOL (ifx_ssc_cs_low);
1937 /* Brief: chip select disable
1938 */
1939 inline int
1940 ifx_ssc_cs_high (u32 pin)
1941 {
1942 int ret = 0;
1943 if ((ret =
1944 ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET,
1945 (unsigned long) &pin))) {
1946 DANUBE_SSC_EMSG ("set CS %d fails\n", pin);
1947 }
1948 wmb ();
1949 return ret;
1950 }
1951
1952 EXPORT_SYMBOL (ifx_ssc_cs_high);
1953 /* Brief: one SSC session
1954 * Parameter:
1955 * tx_buf
1956 * tx_len
1957 * rx_buf
1958 * rx_len
1959 * session_mode: IFX_SSC_MODE_RXTX or IFX_SSC_MODE_TX
1960 * Return: >=0 number of bytes received (if rx_buf != 0) or transmitted
1961 * <0 error code
1962 * Description:
1963 * 0. copy data to internal buffer
1964 * 1. Write command
1965 * 2a. If SSC_SESSION_MODE_TXONLY, read tx_len data
1966 * 2b. If not Read back (tx_len + rx_len) data
1967 * 3. copy internal buffer to rx buf if necessary
1968 */
1969 static int
1970 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1971 {
1972 int ret = 0;
1973
1974 char *ssc_tx_buf = NULL;
1975 char *ssc_rx_buf = NULL;
1976
1977 // volatile char ssc_tx_buf[128]={0};
1978 // volatile char ssc_rx_buf[128]={0};
1979
1980 int eff_size = 0;
1981 u8 mode = 0;
1982
1983 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1984 DANUBE_SSC_EMSG ("invalid parameters\n");
1985 ret = -EINVAL;
1986 goto ssc_session_exit;
1987 }
1988 else if (tx_buf == NULL || tx_len == 0) {
1989 if (rx_buf != NULL && rx_len != 0) {
1990 mode = IFX_SSC_MODE_RX;
1991 }
1992 else {
1993 DANUBE_SSC_EMSG ("invalid parameters\n");
1994 ret = -EINVAL;
1995 goto ssc_session_exit;
1996 }
1997 }
1998 else if (rx_buf == NULL || rx_len == 0) {
1999 if (tx_buf != NULL && tx_len != 0) {
2000 mode = IFX_SSC_MODE_TX;
2001 }
2002 else {
2003 DANUBE_SSC_EMSG ("invalid parameters\n");
2004 ret = -EINVAL;
2005 goto ssc_session_exit;
2006 }
2007 }
2008 else {
2009 mode = IFX_SSC_MODE_RXTX;
2010 }
2011
2012 if (mode == IFX_SSC_MODE_RXTX) {
2013 eff_size = tx_len + rx_len;
2014 }
2015 else if (mode == IFX_SSC_MODE_RX) {
2016 eff_size = rx_len;
2017 }
2018 else {
2019 eff_size = tx_len;
2020 }
2021
2022 //4 bytes alignment, required by driver
2023 /* change by TaiCheng */
2024 //if (in_irq()){
2025 if (1) {
2026 ssc_tx_buf =
2027 (char *) kmalloc (sizeof (char) *
2028 ((eff_size + 3) & (~3)),
2029 GFP_ATOMIC);
2030 ssc_rx_buf =
2031 (char *) kmalloc (sizeof (char) *
2032 ((eff_size + 3) & (~3)),
2033 GFP_ATOMIC);
2034 }
2035 else {
2036 ssc_tx_buf =
2037 (char *) kmalloc (sizeof (char) *
2038 ((eff_size + 3) & (~3)),
2039 GFP_KERNEL);
2040 ssc_rx_buf =
2041 (char *) kmalloc (sizeof (char) *
2042 ((eff_size + 3) & (~3)),
2043 GFP_KERNEL);
2044 }
2045 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
2046 DANUBE_SSC_EMSG ("no memory for size of %d\n", eff_size);
2047 ret = -ENOMEM;
2048 goto ssc_session_exit;
2049 }
2050 memset ((void *) ssc_tx_buf, 0, eff_size);
2051 memset ((void *) ssc_rx_buf, 0, eff_size);
2052
2053 if (tx_len > 0) {
2054 memcpy (ssc_tx_buf, tx_buf, tx_len);
2055 }
2056
2057 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
2058
2059 if (ret > 0) {
2060 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
2061 }
2062
2063 if (ret != eff_size) {
2064 DANUBE_SSC_EMSG ("ifx_ssc_write return %d\n", ret);
2065 goto ssc_session_exit;
2066 }
2067 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
2068 if (ret != eff_size) {
2069 DANUBE_SSC_EMSG ("ifx_ssc_read return %d\n", ret);
2070 goto ssc_session_exit;
2071 }
2072
2073 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
2074
2075 if (mode == IFX_SSC_MODE_TX) {
2076 ret = tx_len;
2077 }
2078 else {
2079 ret = rx_len;
2080 }
2081 ssc_session_exit:
2082
2083 if (ssc_tx_buf != NULL)
2084 kfree (ssc_tx_buf);
2085 if (ssc_rx_buf != NULL)
2086 kfree (ssc_rx_buf);
2087
2088 if (ret < 0) {
2089 printk ("ssc session fails\n");
2090 }
2091 return ret;
2092 }
2093
2094 /* Brief: TX-RX session
2095 * Parameter:
2096 * tx_buf
2097 * tx_len
2098 * rx_buf
2099 * rx_len
2100 * Return: >=0 number of bytes received
2101 * <0 error code
2102 * Description:
2103 * 1. TX session
2104 * 2. RX session
2105 */
2106 int
2107 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
2108 {
2109 return ssc_session (tx_buf, tx_len, rx_buf, rx_len);
2110 }
2111
2112 EXPORT_SYMBOL (ifx_ssc_txrx);
2113 /* Brief: TX only session
2114 * Parameter:
2115 * tx_buf
2116 * tx_len
2117 * Return: >=0 number of bytes transmitted
2118 * <0 error code
2119 */
2120 int
2121 ifx_ssc_tx (char *tx_buf, u32 tx_len)
2122 {
2123 return ssc_session (tx_buf, tx_len, NULL, 0);
2124 }
2125
2126 EXPORT_SYMBOL (ifx_ssc_tx);
2127 /* Brief: RX only session
2128 * Parameter:
2129 * rx_buf
2130 * rx_len
2131 * Return: >=0 number of bytes received
2132 * <0 error code
2133 */
2134 int
2135 ifx_ssc_rx (char *rx_buf, u32 rx_len)
2136 {
2137 return ssc_session (NULL, 0, rx_buf, rx_len);
2138 }
2139
2140 EXPORT_SYMBOL (ifx_ssc_rx);
2141
2142 MODULE_LICENSE("GPL");
2143 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2144 MODULE_DESCRIPTION("danube ssc driver");
2145
Staging tree of Christian Lamparter