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generic: rtl8366: update vlan handling code for rtl8366s
[openwrt/staging/chunkeey.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 /* Switch Global Configuration register */
38 #define RTL8366_SGCR 0x0000
39 #define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
40 #define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
41 #define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
43 #define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
44 #define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
45 #define RTL8366_SGCR_MAX_LENGTH_16000 RTL8366_SGCR_MAX_LENGTH(0x3)
46
47 /* Port Enable Control register */
48 #define RTL8366_PECR 0x0001
49
50 /* Switch Security Control registers */
51 #define RTL8366_SSCR0 0x0002
52 #define RTL8366_SSCR1 0x0003
53 #define RTL8366_SSCR2 0x0004
54 #define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
55
56 #define RTL8366_RESET_CTRL_REG 0x0100
57 #define RTL8366_CHIP_CTRL_RESET_HW 1
58 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
59
60 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
61 #define RTL8366S_CHIP_VERSION_MASK 0xf
62 #define RTL8366S_CHIP_ID_REG 0x0105
63 #define RTL8366S_CHIP_ID_8366 0x8366
64
65 /* PHY registers control */
66 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
67 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
68
69 #define RTL8366S_PHY_CTRL_READ 1
70 #define RTL8366S_PHY_CTRL_WRITE 0
71
72 #define RTL8366S_PHY_REG_MASK 0x1f
73 #define RTL8366S_PHY_PAGE_OFFSET 5
74 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
75 #define RTL8366S_PHY_NO_OFFSET 9
76 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
77
78 /* LED control registers */
79 #define RTL8366_LED_BLINKRATE_REG 0x0420
80 #define RTL8366_LED_BLINKRATE_BIT 0
81 #define RTL8366_LED_BLINKRATE_MASK 0x0007
82
83 #define RTL8366_LED_CTRL_REG 0x0421
84 #define RTL8366_LED_0_1_CTRL_REG 0x0422
85 #define RTL8366_LED_2_3_CTRL_REG 0x0423
86
87 #define RTL8366S_MIB_COUNT 33
88 #define RTL8366S_GLOBAL_MIB_COUNT 1
89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
90 #define RTL8366S_MIB_COUNTER_BASE 0x1000
91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
92 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
93 #define RTL8366S_MIB_CTRL_REG 0x11F0
94 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
95 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
96 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
97
98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
101
102
103 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
105 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
106 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
108
109
110 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
111 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
112
113 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
114
115 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
116 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
118
119 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
120
121
122 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
123 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
125 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
128 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
129
130
131 #define RTL8366_PORT_NUM_CPU 5
132 #define RTL8366_NUM_PORTS 6
133 #define RTL8366_NUM_VLANS 16
134 #define RTL8366_NUM_LEDGROUPS 4
135 #define RTL8366_NUM_VIDS 4096
136 #define RTL8366S_PRIORITYMAX 7
137 #define RTL8366S_FIDMAX 7
138
139
140 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
141 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
142 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
143 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
144
145 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
146 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
147
148 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
149 RTL8366_PORT_2 | \
150 RTL8366_PORT_3 | \
151 RTL8366_PORT_4 | \
152 RTL8366_PORT_UNKNOWN | \
153 RTL8366_PORT_CPU)
154
155 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
156 RTL8366_PORT_2 | \
157 RTL8366_PORT_3 | \
158 RTL8366_PORT_4 | \
159 RTL8366_PORT_UNKNOWN)
160
161 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
162 RTL8366_PORT_2 | \
163 RTL8366_PORT_3 | \
164 RTL8366_PORT_4)
165
166 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
167 RTL8366_PORT_CPU)
168
169 struct rtl8366s {
170 struct device *parent;
171 struct rtl8366_smi smi;
172 struct switch_dev dev;
173 char buf[4096];
174 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
175 struct dentry *debugfs_root;
176 #endif
177 };
178
179 struct rtl8366s_vlan_mc {
180 u16 reserved2:1;
181 u16 priority:3;
182 u16 vid:12;
183
184 u16 reserved1:1;
185 u16 fid:3;
186 u16 untag:6;
187 u16 member:6;
188 };
189
190 struct rtl8366s_vlan_4k {
191 u16 reserved1:4;
192 u16 vid:12;
193
194 u16 reserved2:1;
195 u16 fid:3;
196 u16 untag:6;
197 u16 member:6;
198 };
199
200 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
201 u16 g_dbg_reg;
202 #endif
203
204 struct mib_counter {
205 unsigned base;
206 unsigned offset;
207 unsigned length;
208 const char *name;
209 };
210
211 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
212 { 0, 0, 4, "IfInOctets" },
213 { 0, 4, 4, "EtherStatsOctets" },
214 { 0, 8, 2, "EtherStatsUnderSizePkts" },
215 { 0, 10, 2, "EtherFragments" },
216 { 0, 12, 2, "EtherStatsPkts64Octets" },
217 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
218 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
219 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
220 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
221 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
222 { 0, 24, 2, "EtherOversizeStats" },
223 { 0, 26, 2, "EtherStatsJabbers" },
224 { 0, 28, 2, "IfInUcastPkts" },
225 { 0, 30, 2, "EtherStatsMulticastPkts" },
226 { 0, 32, 2, "EtherStatsBroadcastPkts" },
227 { 0, 34, 2, "EtherStatsDropEvents" },
228 { 0, 36, 2, "Dot3StatsFCSErrors" },
229 { 0, 38, 2, "Dot3StatsSymbolErrors" },
230 { 0, 40, 2, "Dot3InPauseFrames" },
231 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
232 { 0, 44, 4, "IfOutOctets" },
233 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
234 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
235 { 0, 52, 2, "Dot3sDeferredTransmissions" },
236 { 0, 54, 2, "Dot3StatsLateCollisions" },
237 { 0, 56, 2, "EtherStatsCollisions" },
238 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
239 { 0, 60, 2, "Dot3OutPauseFrames" },
240 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
241
242 /*
243 * The following counters are accessible at a different
244 * base address.
245 */
246 { 1, 0, 2, "Dot1dTpPortInDiscards" },
247 { 1, 2, 2, "IfOutUcastPkts" },
248 { 1, 4, 2, "IfOutMulticastPkts" },
249 { 1, 6, 2, "IfOutBroadcastPkts" },
250 };
251
252 #define REG_WR(_smi, _reg, _val) \
253 do { \
254 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
255 if (err) \
256 return err; \
257 } while (0)
258
259 #define REG_RMW(_smi, _reg, _mask, _val) \
260 do { \
261 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
262 if (err) \
263 return err; \
264 } while (0)
265
266 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
267 {
268 return container_of(smi, struct rtl8366s, smi);
269 }
270
271 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
272 {
273 return container_of(sw, struct rtl8366s, dev);
274 }
275
276 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
277 {
278 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
279 return &rtl->smi;
280 }
281
282 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
283 {
284 int timeout = 10;
285 u32 data;
286
287 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
288 RTL8366_CHIP_CTRL_RESET_HW);
289 do {
290 msleep(1);
291 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
292 return -EIO;
293
294 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
295 break;
296 } while (--timeout);
297
298 if (!timeout) {
299 printk("Timeout waiting for the switch to reset\n");
300 return -EIO;
301 }
302
303 return 0;
304 }
305
306 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
307 {
308 int err;
309
310 /* set maximum packet length to 1536 bytes */
311 REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK,
312 RTL8366_SGCR_MAX_LENGTH_1536);
313
314 /* enable all ports */
315 REG_WR(smi, RTL8366_PECR, 0);
316
317 /* disable learning for all ports */
318 REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL);
319
320 /* disable auto ageing for all ports */
321 REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL);
322
323 /* don't drop packets whose DA has not been learned */
324 REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0);
325
326 return 0;
327 }
328
329 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
330 u32 phy_no, u32 page, u32 addr, u32 *data)
331 {
332 u32 reg;
333 int ret;
334
335 if (phy_no > RTL8366S_PHY_NO_MAX)
336 return -EINVAL;
337
338 if (page > RTL8366S_PHY_PAGE_MAX)
339 return -EINVAL;
340
341 if (addr > RTL8366S_PHY_ADDR_MAX)
342 return -EINVAL;
343
344 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
345 RTL8366S_PHY_CTRL_READ);
346 if (ret)
347 return ret;
348
349 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
350 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
351 (addr & RTL8366S_PHY_REG_MASK);
352
353 ret = rtl8366_smi_write_reg(smi, reg, 0);
354 if (ret)
355 return ret;
356
357 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
358 if (ret)
359 return ret;
360
361 return 0;
362 }
363
364 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
365 u32 phy_no, u32 page, u32 addr, u32 data)
366 {
367 u32 reg;
368 int ret;
369
370 if (phy_no > RTL8366S_PHY_NO_MAX)
371 return -EINVAL;
372
373 if (page > RTL8366S_PHY_PAGE_MAX)
374 return -EINVAL;
375
376 if (addr > RTL8366S_PHY_ADDR_MAX)
377 return -EINVAL;
378
379 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
380 RTL8366S_PHY_CTRL_WRITE);
381 if (ret)
382 return ret;
383
384 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
385 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
386 (addr & RTL8366S_PHY_REG_MASK);
387
388 ret = rtl8366_smi_write_reg(smi, reg, data);
389 if (ret)
390 return ret;
391
392 return 0;
393 }
394
395 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
396 int port, unsigned long long *val)
397 {
398 int i;
399 int err;
400 u32 addr, data;
401 u64 mibvalue;
402
403 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
404 return -EINVAL;
405
406 switch (rtl8366s_mib_counters[counter].base) {
407 case 0:
408 addr = RTL8366S_MIB_COUNTER_BASE +
409 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
410 break;
411
412 case 1:
413 addr = RTL8366S_MIB_COUNTER_BASE2 +
414 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 addr += rtl8366s_mib_counters[counter].offset;
422
423 /*
424 * Writing access counter address first
425 * then ASIC will prepare 64bits counter wait for being retrived
426 */
427 data = 0; /* writing data will be discard by ASIC */
428 err = rtl8366_smi_write_reg(smi, addr, data);
429 if (err)
430 return err;
431
432 /* read MIB control register */
433 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
434 if (err)
435 return err;
436
437 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
438 return -EBUSY;
439
440 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
441 return -EIO;
442
443 mibvalue = 0;
444 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
445 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
446 if (err)
447 return err;
448
449 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
450 }
451
452 *val = mibvalue;
453 return 0;
454 }
455
456 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
457 struct rtl8366_vlan_4k *vlan4k)
458 {
459 struct rtl8366s_vlan_4k vlan4k_priv;
460 int err;
461 u32 data;
462 u16 *tableaddr;
463
464 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
465 vlan4k_priv.vid = vid;
466
467 if (vid >= RTL8366_NUM_VIDS)
468 return -EINVAL;
469
470 tableaddr = (u16 *)&vlan4k_priv;
471
472 /* write VID */
473 data = *tableaddr;
474 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
475 if (err)
476 return err;
477
478 /* write table access control word */
479 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
480 RTL8366S_TABLE_VLAN_READ_CTRL);
481 if (err)
482 return err;
483
484 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
485 if (err)
486 return err;
487
488 *tableaddr = data;
489 tableaddr++;
490
491 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
492 &data);
493 if (err)
494 return err;
495
496 *tableaddr = data;
497
498 vlan4k->vid = vid;
499 vlan4k->untag = vlan4k_priv.untag;
500 vlan4k->member = vlan4k_priv.member;
501 vlan4k->fid = vlan4k_priv.fid;
502
503 return 0;
504 }
505
506 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
507 const struct rtl8366_vlan_4k *vlan4k)
508 {
509 struct rtl8366s_vlan_4k vlan4k_priv;
510 int err;
511 u32 data;
512 u16 *tableaddr;
513
514 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
515 vlan4k->member > RTL8366_PORT_ALL ||
516 vlan4k->untag > RTL8366_PORT_ALL ||
517 vlan4k->fid > RTL8366S_FIDMAX)
518 return -EINVAL;
519
520 vlan4k_priv.vid = vlan4k->vid;
521 vlan4k_priv.untag = vlan4k->untag;
522 vlan4k_priv.member = vlan4k->member;
523 vlan4k_priv.fid = vlan4k->fid;
524
525 tableaddr = (u16 *)&vlan4k_priv;
526
527 data = *tableaddr;
528
529 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
530 if (err)
531 return err;
532
533 tableaddr++;
534
535 data = *tableaddr;
536
537 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
538 data);
539 if (err)
540 return err;
541
542 /* write table access control word */
543 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
544 RTL8366S_TABLE_VLAN_WRITE_CTRL);
545
546 return err;
547 }
548
549 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
550 struct rtl8366_vlan_mc *vlanmc)
551 {
552 struct rtl8366s_vlan_mc vlanmc_priv;
553 int err;
554 u32 addr;
555 u32 data;
556 u16 *tableaddr;
557
558 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
559
560 if (index >= RTL8366_NUM_VLANS)
561 return -EINVAL;
562
563 tableaddr = (u16 *)&vlanmc_priv;
564
565 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
566 err = rtl8366_smi_read_reg(smi, addr, &data);
567 if (err)
568 return err;
569
570 *tableaddr = data;
571 tableaddr++;
572
573 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
574 err = rtl8366_smi_read_reg(smi, addr, &data);
575 if (err)
576 return err;
577
578 *tableaddr = data;
579
580 vlanmc->vid = vlanmc_priv.vid;
581 vlanmc->priority = vlanmc_priv.priority;
582 vlanmc->untag = vlanmc_priv.untag;
583 vlanmc->member = vlanmc_priv.member;
584 vlanmc->fid = vlanmc_priv.fid;
585
586 return 0;
587 }
588
589 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
590 const struct rtl8366_vlan_mc *vlanmc)
591 {
592 struct rtl8366s_vlan_mc vlanmc_priv;
593 int err;
594 u32 addr;
595 u32 data;
596 u16 *tableaddr;
597
598 if (index >= RTL8366_NUM_VLANS ||
599 vlanmc->vid >= RTL8366_NUM_VIDS ||
600 vlanmc->priority > RTL8366S_PRIORITYMAX ||
601 vlanmc->member > RTL8366_PORT_ALL ||
602 vlanmc->untag > RTL8366_PORT_ALL ||
603 vlanmc->fid > RTL8366S_FIDMAX)
604 return -EINVAL;
605
606 vlanmc_priv.vid = vlanmc->vid;
607 vlanmc_priv.priority = vlanmc->priority;
608 vlanmc_priv.untag = vlanmc->untag;
609 vlanmc_priv.member = vlanmc->member;
610 vlanmc_priv.fid = vlanmc->fid;
611
612 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
613
614 tableaddr = (u16 *)&vlanmc_priv;
615 data = *tableaddr;
616
617 err = rtl8366_smi_write_reg(smi, addr, data);
618 if (err)
619 return err;
620
621 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
622
623 tableaddr++;
624 data = *tableaddr;
625
626 err = rtl8366_smi_write_reg(smi, addr, data);
627 if (err)
628 return err;
629
630 return 0;
631 }
632
633 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
634 {
635 u32 data;
636 int err;
637
638 if (port >= RTL8366_NUM_PORTS)
639 return -EINVAL;
640
641 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
642 &data);
643 if (err)
644 return err;
645
646 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
647 RTL8366S_PORT_VLAN_CTRL_MASK;
648
649 return 0;
650 }
651
652 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
653 {
654 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
655 return -EINVAL;
656
657 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
658 RTL8366S_PORT_VLAN_CTRL_MASK <<
659 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
660 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
661 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
662 }
663
664 static int rtl8366s_set_vlan(struct rtl8366_smi *smi, int vid, u32 member,
665 u32 untag, u32 fid)
666 {
667 struct rtl8366_vlan_4k vlan4k;
668 int err;
669 int i;
670
671 /* Update the 4K table */
672 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
673 if (err)
674 return err;
675
676 vlan4k.member = member;
677 vlan4k.untag = untag;
678 vlan4k.fid = fid;
679 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
680 if (err)
681 return err;
682
683 /* Try to find an existing MC entry for this VID */
684 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
685 struct rtl8366_vlan_mc vlanmc;
686
687 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
688 if (err)
689 return err;
690
691 if (vid == vlanmc.vid) {
692 /* update the MC entry */
693 vlanmc.member = member;
694 vlanmc.untag = untag;
695 vlanmc.fid = fid;
696
697 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
698 break;
699 }
700 }
701
702 return err;
703 }
704
705 static int rtl8366s_get_pvid(struct rtl8366_smi *smi, int port, int *val)
706 {
707 struct rtl8366_vlan_mc vlanmc;
708 int err;
709 int index;
710
711 err = rtl8366s_get_mc_index(smi, port, &index);
712 if (err)
713 return err;
714
715 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
716 if (err)
717 return err;
718
719 *val = vlanmc.vid;
720 return 0;
721 }
722
723 static int rtl8366s_mc_is_used(struct rtl8366_smi *smi, int mc_index,
724 int *used)
725 {
726 int err;
727 int i;
728
729 *used = 0;
730 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
731 int index = 0;
732
733 err = rtl8366s_get_mc_index(smi, i, &index);
734 if (err)
735 return err;
736
737 if (mc_index == index) {
738 *used = 1;
739 break;
740 }
741 }
742
743 return 0;
744 }
745
746 static int rtl8366s_set_pvid(struct rtl8366_smi *smi, unsigned port,
747 unsigned vid)
748 {
749 struct rtl8366_vlan_mc vlanmc;
750 struct rtl8366_vlan_4k vlan4k;
751 int err;
752 int i;
753
754 /* Try to find an existing MC entry for this VID */
755 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
756 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
757 if (err)
758 return err;
759
760 if (vid == vlanmc.vid) {
761 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
762 if (err)
763 return err;
764
765 err = rtl8366s_set_mc_index(smi, port, i);
766 return err;
767 }
768 }
769
770 /* We have no MC entry for this VID, try to find an empty one */
771 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
772 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
773 if (err)
774 return err;
775
776 if (vlanmc.vid == 0 && vlanmc.member == 0) {
777 /* Update the entry from the 4K table */
778 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
779 if (err)
780 return err;
781
782 vlanmc.vid = vid;
783 vlanmc.member = vlan4k.member;
784 vlanmc.untag = vlan4k.untag;
785 vlanmc.fid = vlan4k.fid;
786 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
787 if (err)
788 return err;
789
790 err = rtl8366s_set_mc_index(smi, port, i);
791 return err;
792 }
793 }
794
795 /* MC table is full, try to find an unused entry and replace it */
796 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
797 int used;
798
799 err = rtl8366s_mc_is_used(smi, i, &used);
800 if (err)
801 return err;
802
803 if (!used) {
804 /* Update the entry from the 4K table */
805 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
806 if (err)
807 return err;
808
809 vlanmc.vid = vid;
810 vlanmc.member = vlan4k.member;
811 vlanmc.untag = vlan4k.untag;
812 vlanmc.fid = vlan4k.fid;
813 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
814 if (err)
815 return err;
816
817 err = rtl8366s_set_mc_index(smi, port, i);
818 return err;
819 }
820 }
821
822 dev_err(smi->parent,
823 "all VLAN member configurations are in use\n");
824
825 return -ENOSPC;
826 }
827
828 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
829 {
830 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
831 RTL8366_CHIP_CTRL_VLAN,
832 (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
833 }
834
835 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
836 {
837 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
838 1, (enable) ? 1 : 0);
839 }
840
841 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
842 {
843 struct rtl8366_vlan_mc vlanmc;
844 int err;
845 int i;
846
847 /* clear VLAN member configurations */
848 vlanmc.vid = 0;
849 vlanmc.priority = 0;
850 vlanmc.member = 0;
851 vlanmc.untag = 0;
852 vlanmc.fid = 0;
853 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
854 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
855 if (err)
856 return err;
857 }
858
859 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
860 if (i == RTL8366_PORT_CPU)
861 continue;
862
863 err = rtl8366s_set_vlan(smi, (i + 1),
864 (1 << i) | RTL8366_PORT_CPU,
865 (1 << i) | RTL8366_PORT_CPU,
866 0);
867 if (err)
868 return err;
869
870 err = rtl8366s_set_pvid(smi, i, (i + 1));
871 if (err)
872 return err;
873 }
874
875 return 0;
876 }
877
878 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
879 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
880 {
881 file->private_data = inode->i_private;
882 return 0;
883 }
884
885 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
886 char __user *user_buf,
887 size_t count, loff_t *ppos)
888 {
889 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
890 struct rtl8366_smi *smi = &rtl->smi;
891 int i, j, len = 0;
892 char *buf = rtl->buf;
893
894 len += snprintf(buf + len, sizeof(rtl->buf) - len,
895 "%-36s %12s %12s %12s %12s %12s %12s\n",
896 "Counter",
897 "Port 0", "Port 1", "Port 2",
898 "Port 3", "Port 4", "Port 5");
899
900 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
901 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
902 rtl8366s_mib_counters[i].name);
903 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
904 unsigned long long counter = 0;
905
906 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
907 len += snprintf(buf + len,
908 sizeof(rtl->buf) - len,
909 "%12llu ", counter);
910 else
911 len += snprintf(buf + len,
912 sizeof(rtl->buf) - len,
913 "%12s ", "error");
914 }
915 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
916 }
917
918 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
919 }
920
921 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
922 char __user *user_buf,
923 size_t count, loff_t *ppos)
924 {
925 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
926 struct rtl8366_smi *smi = &rtl->smi;
927 int i, j, len = 0;
928 char *buf = rtl->buf;
929
930 len += snprintf(buf + len, sizeof(rtl->buf) - len,
931 "VLAN Member Config:\n");
932 len += snprintf(buf + len, sizeof(rtl->buf) - len,
933 "\t id \t vid \t prio \t member \t untag \t fid "
934 "\tports\n");
935
936 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
937 struct rtl8366_vlan_mc vlanmc;
938
939 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
940
941 len += snprintf(buf + len, sizeof(rtl->buf) - len,
942 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
943 "\t", i, vlanmc.vid, vlanmc.priority,
944 vlanmc.member, vlanmc.untag, vlanmc.fid);
945
946 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
947 int index = 0;
948 if (!rtl8366s_get_mc_index(smi, j, &index)) {
949 if (index == i)
950 len += snprintf(buf + len,
951 sizeof(rtl->buf) - len,
952 "%d", j);
953 }
954 }
955 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
956 }
957
958 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
959 }
960
961 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
962 char __user *user_buf,
963 size_t count, loff_t *ppos)
964 {
965 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
966 struct rtl8366_smi *smi = &rtl->smi;
967 u32 t, reg = g_dbg_reg;
968 int err, len = 0;
969 char *buf = rtl->buf;
970
971 memset(buf, '\0', sizeof(rtl->buf));
972
973 err = rtl8366_smi_read_reg(smi, reg, &t);
974 if (err) {
975 len += snprintf(buf, sizeof(rtl->buf),
976 "Read failed (reg: 0x%04x)\n", reg);
977 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
978 }
979
980 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
981 reg, t);
982
983 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
984 }
985
986 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
987 const char __user *user_buf,
988 size_t count, loff_t *ppos)
989 {
990 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
991 struct rtl8366_smi *smi = &rtl->smi;
992 unsigned long data;
993 u32 reg = g_dbg_reg;
994 int err;
995 size_t len;
996 char *buf = rtl->buf;
997
998 len = min(count, sizeof(rtl->buf) - 1);
999 if (copy_from_user(buf, user_buf, len)) {
1000 dev_err(rtl->parent, "copy from user failed\n");
1001 return -EFAULT;
1002 }
1003
1004 buf[len] = '\0';
1005 if (len > 0 && buf[len - 1] == '\n')
1006 buf[len - 1] = '\0';
1007
1008
1009 if (strict_strtoul(buf, 16, &data)) {
1010 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
1011 } else {
1012 err = rtl8366_smi_write_reg(smi, reg, data);
1013 if (err) {
1014 dev_err(rtl->parent,
1015 "writing reg 0x%04x val 0x%04lx failed\n",
1016 reg, data);
1017 }
1018 }
1019
1020 return count;
1021 }
1022
1023 static const struct file_operations fops_rtl8366s_regs = {
1024 .read = rtl8366s_read_debugfs_reg,
1025 .write = rtl8366s_write_debugfs_reg,
1026 .open = rtl8366s_debugfs_open,
1027 .owner = THIS_MODULE
1028 };
1029
1030 static const struct file_operations fops_rtl8366s_vlan = {
1031 .read = rtl8366s_read_debugfs_vlan,
1032 .open = rtl8366s_debugfs_open,
1033 .owner = THIS_MODULE
1034 };
1035
1036 static const struct file_operations fops_rtl8366s_mibs = {
1037 .read = rtl8366s_read_debugfs_mibs,
1038 .open = rtl8366s_debugfs_open,
1039 .owner = THIS_MODULE
1040 };
1041
1042 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
1043 {
1044 struct dentry *node;
1045 struct dentry *root;
1046
1047 if (!rtl->debugfs_root)
1048 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1049
1050 if (!rtl->debugfs_root) {
1051 dev_err(rtl->parent, "Unable to create debugfs dir\n");
1052 return;
1053 }
1054 root = rtl->debugfs_root;
1055
1056 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1057 if (!node) {
1058 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1059 "reg");
1060 return;
1061 }
1062
1063 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1064 &fops_rtl8366s_regs);
1065 if (!node) {
1066 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1067 "val");
1068 return;
1069 }
1070
1071 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
1072 &fops_rtl8366s_vlan);
1073 if (!node) {
1074 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1075 "vlan");
1076 return;
1077 }
1078
1079 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1080 &fops_rtl8366s_mibs);
1081 if (!node) {
1082 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1083 "mibs");
1084 return;
1085 }
1086 }
1087
1088 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
1089 {
1090 if (rtl->debugfs_root) {
1091 debugfs_remove_recursive(rtl->debugfs_root);
1092 rtl->debugfs_root = NULL;
1093 }
1094 }
1095
1096 #else
1097 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
1098 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
1099 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1100
1101 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
1102 const struct switch_attr *attr,
1103 struct switch_val *val)
1104 {
1105 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1106 int err = 0;
1107
1108 if (val->value.i == 1)
1109 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
1110
1111 return err;
1112 }
1113
1114 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1115 const struct switch_attr *attr,
1116 struct switch_val *val)
1117 {
1118 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1119 u32 data;
1120
1121 if (attr->ofs == 1) {
1122 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1123
1124 if (data & RTL8366_CHIP_CTRL_VLAN)
1125 val->value.i = 1;
1126 else
1127 val->value.i = 0;
1128 } else if (attr->ofs == 2) {
1129 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1130
1131 if (data & 0x0001)
1132 val->value.i = 1;
1133 else
1134 val->value.i = 0;
1135 }
1136
1137 return 0;
1138 }
1139
1140 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1141 const struct switch_attr *attr,
1142 struct switch_val *val)
1143 {
1144 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1145 u32 data;
1146
1147 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1148
1149 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1150
1151 return 0;
1152 }
1153
1154 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1155 const struct switch_attr *attr,
1156 struct switch_val *val)
1157 {
1158 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1159
1160 if (val->value.i >= 6)
1161 return -EINVAL;
1162
1163 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
1164 RTL8366_LED_BLINKRATE_MASK,
1165 val->value.i);
1166 }
1167
1168 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1169 const struct switch_attr *attr,
1170 struct switch_val *val)
1171 {
1172 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1173
1174 if (attr->ofs == 1)
1175 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1176 else
1177 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1178 }
1179
1180 static const char *rtl8366s_speed_str(unsigned speed)
1181 {
1182 switch (speed) {
1183 case 0:
1184 return "10baseT";
1185 case 1:
1186 return "100baseT";
1187 case 2:
1188 return "1000baseT";
1189 }
1190
1191 return "unknown";
1192 }
1193
1194 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1195 const struct switch_attr *attr,
1196 struct switch_val *val)
1197 {
1198 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1199 struct rtl8366_smi *smi = &rtl->smi;
1200 u32 len = 0, data = 0;
1201
1202 if (val->port_vlan >= RTL8366_NUM_PORTS)
1203 return -EINVAL;
1204
1205 memset(rtl->buf, '\0', sizeof(rtl->buf));
1206 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1207 (val->port_vlan / 2), &data);
1208
1209 if (val->port_vlan % 2)
1210 data = data >> 8;
1211
1212 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1213 len = snprintf(rtl->buf, sizeof(rtl->buf),
1214 "port:%d link:up speed:%s %s-duplex %s%s%s",
1215 val->port_vlan,
1216 rtl8366s_speed_str(data &
1217 RTL8366S_PORT_STATUS_SPEED_MASK),
1218 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1219 "full" : "half",
1220 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1221 "tx-pause ": "",
1222 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1223 "rx-pause " : "",
1224 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1225 "nway ": "");
1226 } else {
1227 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1228 val->port_vlan);
1229 }
1230
1231 val->value.s = rtl->buf;
1232 val->len = len;
1233
1234 return 0;
1235 }
1236
1237 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1240 {
1241 int i;
1242 u32 len = 0;
1243 struct rtl8366_vlan_4k vlan4k;
1244 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1245 struct rtl8366_smi *smi = &rtl->smi;
1246 char *buf = rtl->buf;
1247 int err;
1248
1249 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1250 return -EINVAL;
1251
1252 memset(buf, '\0', sizeof(rtl->buf));
1253
1254 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1255 if (err)
1256 return err;
1257
1258 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1259 "VLAN %d: Ports: '", vlan4k.vid);
1260
1261 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1262 if (!(vlan4k.member & (1 << i)))
1263 continue;
1264
1265 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
1266 (vlan4k.untag & (1 << i)) ? "" : "t");
1267 }
1268
1269 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1270 "', members=%04x, untag=%04x, fid=%u",
1271 vlan4k.member, vlan4k.untag, vlan4k.fid);
1272
1273 val->value.s = buf;
1274 val->len = len;
1275
1276 return 0;
1277 }
1278
1279 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1280 const struct switch_attr *attr,
1281 struct switch_val *val)
1282 {
1283 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1284 u32 data;
1285 u32 mask;
1286 u32 reg;
1287
1288 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1289 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1290 return -EINVAL;
1291
1292 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1293 reg = RTL8366_LED_BLINKRATE_REG;
1294 mask = 0xF << 4;
1295 data = val->value.i << 4;
1296 } else {
1297 reg = RTL8366_LED_CTRL_REG;
1298 mask = 0xF << (val->port_vlan * 4),
1299 data = val->value.i << (val->port_vlan * 4);
1300 }
1301
1302 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
1303 }
1304
1305 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1306 const struct switch_attr *attr,
1307 struct switch_val *val)
1308 {
1309 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1310 u32 data = 0;
1311
1312 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1313 return -EINVAL;
1314
1315 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1316 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1317
1318 return 0;
1319 }
1320
1321 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1322 const struct switch_attr *attr,
1323 struct switch_val *val)
1324 {
1325 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1326
1327 if (val->port_vlan >= RTL8366_NUM_PORTS)
1328 return -EINVAL;
1329
1330
1331 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1332 0, (1 << (val->port_vlan + 3)));
1333 }
1334
1335 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1336 const struct switch_attr *attr,
1337 struct switch_val *val)
1338 {
1339 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1340 struct rtl8366_smi *smi = &rtl->smi;
1341 int i, len = 0;
1342 unsigned long long counter = 0;
1343 char *buf = rtl->buf;
1344
1345 if (val->port_vlan >= RTL8366_NUM_PORTS)
1346 return -EINVAL;
1347
1348 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1349 "Port %d MIB counters\n",
1350 val->port_vlan);
1351
1352 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1353 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1354 "%-36s: ", rtl8366s_mib_counters[i].name);
1355 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1356 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1357 "%llu\n", counter);
1358 else
1359 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1360 "%s\n", "error");
1361 }
1362
1363 val->value.s = buf;
1364 val->len = len;
1365 return 0;
1366 }
1367
1368 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1369 struct switch_val *val)
1370 {
1371 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1372 struct switch_port *port;
1373 struct rtl8366_vlan_4k vlan4k;
1374 int i;
1375
1376 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1377 return -EINVAL;
1378
1379 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1380
1381 port = &val->value.ports[0];
1382 val->len = 0;
1383 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1384 if (!(vlan4k.member & BIT(i)))
1385 continue;
1386
1387 port->id = i;
1388 port->flags = (vlan4k.untag & BIT(i)) ?
1389 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1390 val->len++;
1391 port++;
1392 }
1393 return 0;
1394 }
1395
1396 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1397 struct switch_val *val)
1398 {
1399 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1400 struct switch_port *port;
1401 u32 member = 0;
1402 u32 untag = 0;
1403 int i;
1404
1405 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1406 return -EINVAL;
1407
1408 port = &val->value.ports[0];
1409 for (i = 0; i < val->len; i++, port++) {
1410 member |= BIT(port->id);
1411
1412 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1413 untag |= BIT(port->id);
1414 }
1415
1416 return rtl8366s_set_vlan(smi, val->port_vlan, member, untag, 0);
1417 }
1418
1419 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1420 {
1421 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1422 return rtl8366s_get_pvid(smi, port, val);
1423 }
1424
1425 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1426 {
1427 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1428 return rtl8366s_set_pvid(smi, port, val);
1429 }
1430
1431 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1432 {
1433 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1434 int err;
1435
1436 err = rtl8366s_reset_chip(smi);
1437 if (err)
1438 return err;
1439
1440 err = rtl8366s_hw_init(smi);
1441 if (err)
1442 return err;
1443
1444 return rtl8366s_reset_vlan(smi);
1445 }
1446
1447 static struct switch_attr rtl8366s_globals[] = {
1448 {
1449 .type = SWITCH_TYPE_INT,
1450 .name = "enable_vlan",
1451 .description = "Enable VLAN mode",
1452 .set = rtl8366s_sw_set_vlan_enable,
1453 .get = rtl8366s_sw_get_vlan_enable,
1454 .max = 1,
1455 .ofs = 1
1456 }, {
1457 .type = SWITCH_TYPE_INT,
1458 .name = "enable_vlan4k",
1459 .description = "Enable VLAN 4K mode",
1460 .set = rtl8366s_sw_set_vlan_enable,
1461 .get = rtl8366s_sw_get_vlan_enable,
1462 .max = 1,
1463 .ofs = 2
1464 }, {
1465 .type = SWITCH_TYPE_INT,
1466 .name = "reset_mibs",
1467 .description = "Reset all MIB counters",
1468 .set = rtl8366s_sw_reset_mibs,
1469 .get = NULL,
1470 .max = 1
1471 }, {
1472 .type = SWITCH_TYPE_INT,
1473 .name = "blinkrate",
1474 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1475 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1476 .set = rtl8366s_sw_set_blinkrate,
1477 .get = rtl8366s_sw_get_blinkrate,
1478 .max = 5
1479 },
1480 };
1481
1482 static struct switch_attr rtl8366s_port[] = {
1483 {
1484 .type = SWITCH_TYPE_STRING,
1485 .name = "link",
1486 .description = "Get port link information",
1487 .max = 1,
1488 .set = NULL,
1489 .get = rtl8366s_sw_get_port_link,
1490 }, {
1491 .type = SWITCH_TYPE_INT,
1492 .name = "reset_mib",
1493 .description = "Reset single port MIB counters",
1494 .max = 1,
1495 .set = rtl8366s_sw_reset_port_mibs,
1496 .get = NULL,
1497 }, {
1498 .type = SWITCH_TYPE_STRING,
1499 .name = "mib",
1500 .description = "Get MIB counters for port",
1501 .max = 33,
1502 .set = NULL,
1503 .get = rtl8366s_sw_get_port_mib,
1504 }, {
1505 .type = SWITCH_TYPE_INT,
1506 .name = "led",
1507 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1508 .max = 15,
1509 .set = rtl8366s_sw_set_port_led,
1510 .get = rtl8366s_sw_get_port_led,
1511 },
1512 };
1513
1514 static struct switch_attr rtl8366s_vlan[] = {
1515 {
1516 .type = SWITCH_TYPE_STRING,
1517 .name = "info",
1518 .description = "Get vlan information",
1519 .max = 1,
1520 .set = NULL,
1521 .get = rtl8366s_sw_get_vlan_info,
1522 },
1523 };
1524
1525 /* template */
1526 static struct switch_dev rtl8366_switch_dev = {
1527 .name = "RTL8366S",
1528 .cpu_port = RTL8366_PORT_NUM_CPU,
1529 .ports = RTL8366_NUM_PORTS,
1530 .vlans = RTL8366_NUM_VLANS,
1531 .attr_global = {
1532 .attr = rtl8366s_globals,
1533 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1534 },
1535 .attr_port = {
1536 .attr = rtl8366s_port,
1537 .n_attr = ARRAY_SIZE(rtl8366s_port),
1538 },
1539 .attr_vlan = {
1540 .attr = rtl8366s_vlan,
1541 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1542 },
1543
1544 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1545 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1546 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1547 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1548 .reset_switch = rtl8366s_sw_reset_switch,
1549 };
1550
1551 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1552 {
1553 struct switch_dev *dev = &rtl->dev;
1554 int err;
1555
1556 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1557 dev->priv = rtl;
1558 dev->devname = dev_name(rtl->parent);
1559
1560 err = register_switch(dev, NULL);
1561 if (err)
1562 dev_err(rtl->parent, "switch registration failed\n");
1563
1564 return err;
1565 }
1566
1567 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1568 {
1569 unregister_switch(&rtl->dev);
1570 }
1571
1572 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1573 {
1574 struct rtl8366_smi *smi = bus->priv;
1575 u32 val = 0;
1576 int err;
1577
1578 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1579 if (err)
1580 return 0xffff;
1581
1582 return val;
1583 }
1584
1585 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1586 {
1587 struct rtl8366_smi *smi = bus->priv;
1588 u32 t;
1589 int err;
1590
1591 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1592 /* flush write */
1593 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1594
1595 return err;
1596 }
1597
1598 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1599 {
1600 return (bus->read == rtl8366s_mii_read &&
1601 bus->write == rtl8366s_mii_write);
1602 }
1603
1604 static int rtl8366s_setup(struct rtl8366s *rtl)
1605 {
1606 struct rtl8366_smi *smi = &rtl->smi;
1607 int ret;
1608
1609 rtl8366s_debugfs_init(rtl);
1610
1611 ret = rtl8366s_reset_chip(smi);
1612 if (ret)
1613 return ret;
1614
1615 ret = rtl8366s_hw_init(smi);
1616 return ret;
1617 }
1618
1619 static int rtl8366s_detect(struct rtl8366_smi *smi)
1620 {
1621 u32 chip_id = 0;
1622 u32 chip_ver = 0;
1623 int ret;
1624
1625 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1626 if (ret) {
1627 dev_err(smi->parent, "unable to read chip id\n");
1628 return ret;
1629 }
1630
1631 switch (chip_id) {
1632 case RTL8366S_CHIP_ID_8366:
1633 break;
1634 default:
1635 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1636 return -ENODEV;
1637 }
1638
1639 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1640 &chip_ver);
1641 if (ret) {
1642 dev_err(smi->parent, "unable to read chip version\n");
1643 return ret;
1644 }
1645
1646 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1647 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1648
1649 return 0;
1650 }
1651
1652 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1653 .detect = rtl8366s_detect,
1654 .mii_read = rtl8366s_mii_read,
1655 .mii_write = rtl8366s_mii_write,
1656 };
1657
1658 static int __init rtl8366s_probe(struct platform_device *pdev)
1659 {
1660 static int rtl8366_smi_version_printed;
1661 struct rtl8366s_platform_data *pdata;
1662 struct rtl8366s *rtl;
1663 struct rtl8366_smi *smi;
1664 int err;
1665
1666 if (!rtl8366_smi_version_printed++)
1667 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1668 " version " RTL8366S_DRIVER_VER"\n");
1669
1670 pdata = pdev->dev.platform_data;
1671 if (!pdata) {
1672 dev_err(&pdev->dev, "no platform data specified\n");
1673 err = -EINVAL;
1674 goto err_out;
1675 }
1676
1677 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1678 if (!rtl) {
1679 dev_err(&pdev->dev, "no memory for private data\n");
1680 err = -ENOMEM;
1681 goto err_out;
1682 }
1683
1684 rtl->parent = &pdev->dev;
1685
1686 smi = &rtl->smi;
1687 smi->parent = &pdev->dev;
1688 smi->gpio_sda = pdata->gpio_sda;
1689 smi->gpio_sck = pdata->gpio_sck;
1690 smi->ops = &rtl8366s_smi_ops;
1691
1692 err = rtl8366_smi_init(smi);
1693 if (err)
1694 goto err_free_rtl;
1695
1696 platform_set_drvdata(pdev, rtl);
1697
1698 err = rtl8366s_setup(rtl);
1699 if (err)
1700 goto err_clear_drvdata;
1701
1702 err = rtl8366s_switch_init(rtl);
1703 if (err)
1704 goto err_clear_drvdata;
1705
1706 return 0;
1707
1708 err_clear_drvdata:
1709 platform_set_drvdata(pdev, NULL);
1710 rtl8366_smi_cleanup(smi);
1711 err_free_rtl:
1712 kfree(rtl);
1713 err_out:
1714 return err;
1715 }
1716
1717 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1718 {
1719 if (!rtl8366s_mii_bus_match(phydev->bus))
1720 return -EINVAL;
1721
1722 return 0;
1723 }
1724
1725 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1726 {
1727 return 0;
1728 }
1729
1730 static struct phy_driver rtl8366s_phy_driver = {
1731 .phy_id = 0x001cc960,
1732 .name = "Realtek RTL8366S",
1733 .phy_id_mask = 0x1ffffff0,
1734 .features = PHY_GBIT_FEATURES,
1735 .config_aneg = rtl8366s_phy_config_aneg,
1736 .config_init = rtl8366s_phy_config_init,
1737 .read_status = genphy_read_status,
1738 .driver = {
1739 .owner = THIS_MODULE,
1740 },
1741 };
1742
1743 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1744 {
1745 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1746
1747 if (rtl) {
1748 rtl8366s_switch_cleanup(rtl);
1749 rtl8366s_debugfs_remove(rtl);
1750 platform_set_drvdata(pdev, NULL);
1751 rtl8366_smi_cleanup(&rtl->smi);
1752 kfree(rtl);
1753 }
1754
1755 return 0;
1756 }
1757
1758 static struct platform_driver rtl8366s_driver = {
1759 .driver = {
1760 .name = RTL8366S_DRIVER_NAME,
1761 .owner = THIS_MODULE,
1762 },
1763 .probe = rtl8366s_probe,
1764 .remove = __devexit_p(rtl8366s_remove),
1765 };
1766
1767 static int __init rtl8366s_module_init(void)
1768 {
1769 int ret;
1770 ret = platform_driver_register(&rtl8366s_driver);
1771 if (ret)
1772 return ret;
1773
1774 ret = phy_driver_register(&rtl8366s_phy_driver);
1775 if (ret)
1776 goto err_platform_unregister;
1777
1778 return 0;
1779
1780 err_platform_unregister:
1781 platform_driver_unregister(&rtl8366s_driver);
1782 return ret;
1783 }
1784 module_init(rtl8366s_module_init);
1785
1786 static void __exit rtl8366s_module_exit(void)
1787 {
1788 phy_driver_unregister(&rtl8366s_phy_driver);
1789 platform_driver_unregister(&rtl8366s_driver);
1790 }
1791 module_exit(rtl8366s_module_exit);
1792
1793 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1794 MODULE_VERSION(RTL8366S_DRIVER_VER);
1795 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1796 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1797 MODULE_LICENSE("GPL v2");
1798 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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