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generic: ar8216: replace chip_type field with chip_{ver,rev} in ar8216_priv
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include "ar8216.h"
36
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
41
42 struct ar8216_priv;
43
44 #define AR8XXX_CAP_GIGE BIT(0)
45
46 enum {
47 AR8XXX_VER_AR8216 = 0x01,
48 AR8XXX_VER_AR8236 = 0x03,
49 AR8XXX_VER_AR8316 = 0x10,
50 AR8XXX_VER_AR8327 = 0x12,
51 };
52
53 struct ar8xxx_chip {
54 unsigned long caps;
55
56 int (*hw_init)(struct ar8216_priv *priv);
57 void (*init_globals)(struct ar8216_priv *priv);
58 void (*init_port)(struct ar8216_priv *priv, int port);
59 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
60 u32 ingress, u32 members, u32 pvid);
61 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
62 int (*atu_flush)(struct ar8216_priv *priv);
63 void (*vtu_flush)(struct ar8216_priv *priv);
64 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
65 };
66
67 struct ar8216_priv {
68 struct switch_dev dev;
69 struct phy_device *phy;
70 u32 (*read)(struct ar8216_priv *priv, int reg);
71 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
72 const struct net_device_ops *ndo_old;
73 struct net_device_ops ndo;
74 struct mutex reg_mutex;
75 u8 chip_ver;
76 u8 chip_rev;
77 const struct ar8xxx_chip *chip;
78 bool initialized;
79 bool port4_phy;
80 char buf[80];
81
82 bool init;
83 bool mii_lo_first;
84
85 /* all fields below are cleared on reset */
86 bool vlan;
87 u16 vlan_id[AR8X16_MAX_VLANS];
88 u8 vlan_table[AR8X16_MAX_VLANS];
89 u8 vlan_tagged;
90 u16 pvid[AR8X16_MAX_PORTS];
91 };
92
93 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
94
95 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
96 {
97 return priv->chip->caps & AR8XXX_CAP_GIGE;
98 }
99
100 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
101 {
102 return priv->chip_ver == AR8XXX_VER_AR8216;
103 }
104
105 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
106 {
107 return priv->chip_ver == AR8XXX_VER_AR8236;
108 }
109
110 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
111 {
112 return priv->chip_ver == AR8XXX_VER_AR8316;
113 }
114
115 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
116 {
117 return priv->chip_ver == AR8XXX_VER_AR8327;
118 }
119
120 static inline void
121 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
122 {
123 regaddr >>= 1;
124 *r1 = regaddr & 0x1e;
125
126 regaddr >>= 5;
127 *r2 = regaddr & 0x7;
128
129 regaddr >>= 3;
130 *page = regaddr & 0x1ff;
131 }
132
133 static u32
134 ar8216_mii_read(struct ar8216_priv *priv, int reg)
135 {
136 struct phy_device *phy = priv->phy;
137 struct mii_bus *bus = phy->bus;
138 u16 r1, r2, page;
139 u16 lo, hi;
140
141 split_addr((u32) reg, &r1, &r2, &page);
142
143 mutex_lock(&bus->mdio_lock);
144
145 bus->write(bus, 0x18, 0, page);
146 usleep_range(1000, 2000); /* wait for the page switch to propagate */
147 lo = bus->read(bus, 0x10 | r2, r1);
148 hi = bus->read(bus, 0x10 | r2, r1 + 1);
149
150 mutex_unlock(&bus->mdio_lock);
151
152 return (hi << 16) | lo;
153 }
154
155 static void
156 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
157 {
158 struct phy_device *phy = priv->phy;
159 struct mii_bus *bus = phy->bus;
160 u16 r1, r2, r3;
161 u16 lo, hi;
162
163 split_addr((u32) reg, &r1, &r2, &r3);
164 lo = val & 0xffff;
165 hi = (u16) (val >> 16);
166
167 mutex_lock(&bus->mdio_lock);
168
169 bus->write(bus, 0x18, 0, r3);
170 usleep_range(1000, 2000); /* wait for the page switch to propagate */
171 if (priv->mii_lo_first) {
172 bus->write(bus, 0x10 | r2, r1, lo);
173 bus->write(bus, 0x10 | r2, r1 + 1, hi);
174 } else {
175 bus->write(bus, 0x10 | r2, r1 + 1, hi);
176 bus->write(bus, 0x10 | r2, r1, lo);
177 }
178
179 mutex_unlock(&bus->mdio_lock);
180 }
181
182 static void
183 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
184 u16 dbg_addr, u16 dbg_data)
185 {
186 struct mii_bus *bus = priv->phy->bus;
187
188 mutex_lock(&bus->mdio_lock);
189 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
190 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
191 mutex_unlock(&bus->mdio_lock);
192 }
193
194 static u32
195 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
196 {
197 u32 v;
198
199 lockdep_assert_held(&priv->reg_mutex);
200
201 v = priv->read(priv, reg);
202 v &= ~mask;
203 v |= val;
204 priv->write(priv, reg, v);
205
206 return v;
207 }
208
209 static void
210 ar8216_read_port_link(struct ar8216_priv *priv, int port,
211 struct switch_port_link *link)
212 {
213 u32 status;
214 u32 speed;
215
216 memset(link, '\0', sizeof(*link));
217
218 status = priv->chip->read_port_status(priv, port);
219
220 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
221 if (link->aneg) {
222 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
223 if (!link->link)
224 return;
225 } else {
226 link->link = true;
227 }
228
229 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
230 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
231 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
232
233 speed = (status & AR8216_PORT_STATUS_SPEED) >>
234 AR8216_PORT_STATUS_SPEED_S;
235
236 switch (speed) {
237 case AR8216_PORT_SPEED_10M:
238 link->speed = SWITCH_PORT_SPEED_10;
239 break;
240 case AR8216_PORT_SPEED_100M:
241 link->speed = SWITCH_PORT_SPEED_100;
242 break;
243 case AR8216_PORT_SPEED_1000M:
244 link->speed = SWITCH_PORT_SPEED_1000;
245 break;
246 default:
247 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
248 break;
249 }
250 }
251
252 static struct sk_buff *
253 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
254 {
255 struct ar8216_priv *priv = dev->phy_ptr;
256 unsigned char *buf;
257
258 if (unlikely(!priv))
259 goto error;
260
261 if (!priv->vlan)
262 goto send;
263
264 if (unlikely(skb_headroom(skb) < 2)) {
265 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
266 goto error;
267 }
268
269 buf = skb_push(skb, 2);
270 buf[0] = 0x10;
271 buf[1] = 0x80;
272
273 send:
274 return skb;
275
276 error:
277 dev_kfree_skb_any(skb);
278 return NULL;
279 }
280
281 static void
282 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
283 {
284 struct ar8216_priv *priv;
285 unsigned char *buf;
286 int port, vlan;
287
288 priv = dev->phy_ptr;
289 if (!priv)
290 return;
291
292 /* don't strip the header if vlan mode is disabled */
293 if (!priv->vlan)
294 return;
295
296 /* strip header, get vlan id */
297 buf = skb->data;
298 skb_pull(skb, 2);
299
300 /* check for vlan header presence */
301 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
302 return;
303
304 port = buf[0] & 0xf;
305
306 /* no need to fix up packets coming from a tagged source */
307 if (priv->vlan_tagged & (1 << port))
308 return;
309
310 /* lookup port vid from local table, the switch passes an invalid vlan id */
311 vlan = priv->vlan_id[priv->pvid[port]];
312
313 buf[14 + 2] &= 0xf0;
314 buf[14 + 2] |= vlan >> 8;
315 buf[15 + 2] = vlan & 0xff;
316 }
317
318 static int
319 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
320 {
321 int timeout = 20;
322 u32 t = 0;
323
324 while (1) {
325 t = priv->read(priv, reg);
326 if ((t & mask) == val)
327 return 0;
328
329 if (timeout-- <= 0)
330 break;
331
332 udelay(10);
333 }
334
335 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
336 (unsigned int) reg, t, mask, val);
337 return -ETIMEDOUT;
338 }
339
340 static void
341 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
342 {
343 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
344 return;
345 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
346 val &= AR8216_VTUDATA_MEMBER;
347 val |= AR8216_VTUDATA_VALID;
348 priv->write(priv, AR8216_REG_VTU_DATA, val);
349 }
350 op |= AR8216_VTU_ACTIVE;
351 priv->write(priv, AR8216_REG_VTU, op);
352 }
353
354 static void
355 ar8216_vtu_flush(struct ar8216_priv *priv)
356 {
357 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
358 }
359
360 static void
361 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
362 {
363 u32 op;
364
365 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
366 ar8216_vtu_op(priv, op, port_mask);
367 }
368
369 static int
370 ar8216_atu_flush(struct ar8216_priv *priv)
371 {
372 int ret;
373
374 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
375 if (!ret)
376 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
377
378 return ret;
379 }
380
381 static u32
382 ar8216_read_port_status(struct ar8216_priv *priv, int port)
383 {
384 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
385 }
386
387 static void
388 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
389 u32 members, u32 pvid)
390 {
391 u32 header;
392
393 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
394 header = AR8216_PORT_CTRL_HEADER;
395 else
396 header = 0;
397
398 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
399 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
400 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
401 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
402 AR8216_PORT_CTRL_LEARN | header |
403 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
404 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
405
406 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
407 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
408 AR8216_PORT_VLAN_DEFAULT_ID,
409 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
410 (ingress << AR8216_PORT_VLAN_MODE_S) |
411 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
412 }
413
414 static int
415 ar8216_hw_init(struct ar8216_priv *priv)
416 {
417 return 0;
418 }
419
420 static void
421 ar8216_init_globals(struct ar8216_priv *priv)
422 {
423 /* standard atheros magic */
424 priv->write(priv, 0x38, 0xc000050e);
425
426 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
427 AR8216_GCTRL_MTU, 1518 + 8 + 2);
428 }
429
430 static void
431 ar8216_init_port(struct ar8216_priv *priv, int port)
432 {
433 /* Enable port learning and tx */
434 priv->write(priv, AR8216_REG_PORT_CTRL(port),
435 AR8216_PORT_CTRL_LEARN |
436 (4 << AR8216_PORT_CTRL_STATE_S));
437
438 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
439
440 if (port == AR8216_PORT_CPU) {
441 priv->write(priv, AR8216_REG_PORT_STATUS(port),
442 AR8216_PORT_STATUS_LINK_UP |
443 (ar8xxx_has_gige(priv) ?
444 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
445 AR8216_PORT_STATUS_TXMAC |
446 AR8216_PORT_STATUS_RXMAC |
447 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
448 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
449 AR8216_PORT_STATUS_DUPLEX);
450 } else {
451 priv->write(priv, AR8216_REG_PORT_STATUS(port),
452 AR8216_PORT_STATUS_LINK_AUTO);
453 }
454 }
455
456 static const struct ar8xxx_chip ar8216_chip = {
457 .hw_init = ar8216_hw_init,
458 .init_globals = ar8216_init_globals,
459 .init_port = ar8216_init_port,
460 .setup_port = ar8216_setup_port,
461 .read_port_status = ar8216_read_port_status,
462 .atu_flush = ar8216_atu_flush,
463 .vtu_flush = ar8216_vtu_flush,
464 .vtu_load_vlan = ar8216_vtu_load_vlan,
465 };
466
467 static void
468 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
469 u32 members, u32 pvid)
470 {
471 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
472 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
473 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
474 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
475 AR8216_PORT_CTRL_LEARN |
476 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
477 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
478
479 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
480 AR8236_PORT_VLAN_DEFAULT_ID,
481 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
482
483 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
484 AR8236_PORT_VLAN2_VLAN_MODE |
485 AR8236_PORT_VLAN2_MEMBER,
486 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
487 (members << AR8236_PORT_VLAN2_MEMBER_S));
488 }
489
490 static int
491 ar8236_hw_init(struct ar8216_priv *priv)
492 {
493 int i;
494 struct mii_bus *bus;
495
496 if (priv->initialized)
497 return 0;
498
499 /* Initialize the PHYs */
500 bus = priv->phy->bus;
501 for (i = 0; i < 5; i++) {
502 mdiobus_write(bus, i, MII_ADVERTISE,
503 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
504 ADVERTISE_PAUSE_ASYM);
505 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
506 }
507 msleep(1000);
508
509 priv->initialized = true;
510 return 0;
511 }
512
513 static void
514 ar8236_init_globals(struct ar8216_priv *priv)
515 {
516 /* enable jumbo frames */
517 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
518 AR8316_GCTRL_MTU, 9018 + 8 + 2);
519 }
520
521 static const struct ar8xxx_chip ar8236_chip = {
522 .hw_init = ar8236_hw_init,
523 .init_globals = ar8236_init_globals,
524 .init_port = ar8216_init_port,
525 .setup_port = ar8236_setup_port,
526 .read_port_status = ar8216_read_port_status,
527 .atu_flush = ar8216_atu_flush,
528 .vtu_flush = ar8216_vtu_flush,
529 .vtu_load_vlan = ar8216_vtu_load_vlan,
530 };
531
532 static int
533 ar8316_hw_init(struct ar8216_priv *priv)
534 {
535 int i;
536 u32 val, newval;
537 struct mii_bus *bus;
538
539 val = priv->read(priv, 0x8);
540
541 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
542 if (priv->port4_phy) {
543 /* value taken from Ubiquiti RouterStation Pro */
544 newval = 0x81461bea;
545 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
546 } else {
547 newval = 0x01261be2;
548 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
549 }
550 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
551 /* value taken from AVM Fritz!Box 7390 sources */
552 newval = 0x010e5b71;
553 } else {
554 /* no known value for phy interface */
555 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
556 priv->phy->interface);
557 return -EINVAL;
558 }
559
560 if (val == newval)
561 goto out;
562
563 priv->write(priv, 0x8, newval);
564
565 /* Initialize the ports */
566 bus = priv->phy->bus;
567 for (i = 0; i < 5; i++) {
568 if ((i == 4) && priv->port4_phy &&
569 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
570 /* work around for phy4 rgmii mode */
571 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
572 /* rx delay */
573 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
574 /* tx delay */
575 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
576 msleep(1000);
577 }
578
579 /* initialize the port itself */
580 mdiobus_write(bus, i, MII_ADVERTISE,
581 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
582 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
583 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
584 msleep(1000);
585 }
586
587 out:
588 priv->initialized = true;
589 return 0;
590 }
591
592 static void
593 ar8316_init_globals(struct ar8216_priv *priv)
594 {
595 /* standard atheros magic */
596 priv->write(priv, 0x38, 0xc000050e);
597
598 /* enable cpu port to receive multicast and broadcast frames */
599 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
600
601 /* enable jumbo frames */
602 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
603 AR8316_GCTRL_MTU, 9018 + 8 + 2);
604 }
605
606 static const struct ar8xxx_chip ar8316_chip = {
607 .caps = AR8XXX_CAP_GIGE,
608 .hw_init = ar8316_hw_init,
609 .init_globals = ar8316_init_globals,
610 .init_port = ar8216_init_port,
611 .setup_port = ar8216_setup_port,
612 .read_port_status = ar8216_read_port_status,
613 .atu_flush = ar8216_atu_flush,
614 .vtu_flush = ar8216_vtu_flush,
615 .vtu_load_vlan = ar8216_vtu_load_vlan,
616 };
617
618 static u32
619 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
620 {
621 u32 t;
622
623 if (!cfg)
624 return 0;
625
626 t = 0;
627 switch (cfg->mode) {
628 case AR8327_PAD_NC:
629 break;
630
631 case AR8327_PAD_MAC2MAC_MII:
632 t = AR8327_PAD_MAC_MII_EN;
633 if (cfg->rxclk_sel)
634 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
635 if (cfg->txclk_sel)
636 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
637 break;
638
639 case AR8327_PAD_MAC2MAC_GMII:
640 t = AR8327_PAD_MAC_GMII_EN;
641 if (cfg->rxclk_sel)
642 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
643 if (cfg->txclk_sel)
644 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
645 break;
646
647 case AR8327_PAD_MAC_SGMII:
648 t = AR8327_PAD_SGMII_EN;
649 break;
650
651 case AR8327_PAD_MAC2PHY_MII:
652 t = AR8327_PAD_PHY_MII_EN;
653 if (cfg->rxclk_sel)
654 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
655 if (cfg->txclk_sel)
656 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
657 break;
658
659 case AR8327_PAD_MAC2PHY_GMII:
660 t = AR8327_PAD_PHY_GMII_EN;
661 if (cfg->pipe_rxclk_sel)
662 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
663 if (cfg->rxclk_sel)
664 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
665 if (cfg->txclk_sel)
666 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
667 break;
668
669 case AR8327_PAD_MAC_RGMII:
670 t = AR8327_PAD_RGMII_EN;
671 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
672 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
673 if (cfg->rxclk_delay_en)
674 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
675 if (cfg->txclk_delay_en)
676 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
677 break;
678
679 case AR8327_PAD_PHY_GMII:
680 t = AR8327_PAD_PHYX_GMII_EN;
681 break;
682
683 case AR8327_PAD_PHY_RGMII:
684 t = AR8327_PAD_PHYX_RGMII_EN;
685 break;
686
687 case AR8327_PAD_PHY_MII:
688 t = AR8327_PAD_PHYX_MII_EN;
689 break;
690 }
691
692 return t;
693 }
694
695 static int
696 ar8327_hw_init(struct ar8216_priv *priv)
697 {
698 struct ar8327_platform_data *pdata;
699 u32 t;
700 int i;
701
702 pdata = priv->phy->dev.platform_data;
703 if (!pdata)
704 return -EINVAL;
705
706 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
707 priv->write(priv, AR8327_REG_PAD0_MODE, t);
708 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
709 priv->write(priv, AR8327_REG_PAD5_MODE, t);
710 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
711 priv->write(priv, AR8327_REG_PAD6_MODE, t);
712
713 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
714
715 /* fixup PHYs */
716 for (i = 0; i < AR8327_NUM_PHYS; i++) {
717 /* For 100M waveform */
718 ar8216_phy_dbg_write(priv, i, 0, 0x02ea);
719
720 /* Turn on Gigabit clock */
721 ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0);
722 }
723
724 return 0;
725 }
726
727 static void
728 ar8327_init_globals(struct ar8216_priv *priv)
729 {
730 u32 t;
731
732 /* enable CPU port and disable mirror port */
733 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
734 AR8327_FWD_CTRL0_MIRROR_PORT;
735 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
736
737 /* forward multicast and broadcast frames to CPU */
738 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
739 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
740 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
741 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
742
743 /* setup MTU */
744 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
745 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
746 }
747
748 static void
749 ar8327_init_cpuport(struct ar8216_priv *priv)
750 {
751 struct ar8327_platform_data *pdata;
752 struct ar8327_port_cfg *cfg;
753 u32 t;
754
755 pdata = priv->phy->dev.platform_data;
756 if (!pdata)
757 return;
758
759 cfg = &pdata->cpuport_cfg;
760 if (!cfg->force_link) {
761 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
762 AR8216_PORT_STATUS_LINK_AUTO);
763 return;
764 }
765
766 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
767 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
768 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
769 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
770 switch (cfg->speed) {
771 case AR8327_PORT_SPEED_10:
772 t |= AR8216_PORT_SPEED_10M;
773 break;
774 case AR8327_PORT_SPEED_100:
775 t |= AR8216_PORT_SPEED_100M;
776 break;
777 case AR8327_PORT_SPEED_1000:
778 t |= AR8216_PORT_SPEED_1000M;
779 break;
780 }
781
782 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
783 }
784
785 static void
786 ar8327_init_port(struct ar8216_priv *priv, int port)
787 {
788 u32 t;
789
790 if (port == AR8216_PORT_CPU) {
791 ar8327_init_cpuport(priv);
792 } else {
793 t = AR8216_PORT_STATUS_LINK_AUTO;
794 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
795 }
796
797 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
798
799 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
800
801 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
802 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
803
804 t = AR8327_PORT_LOOKUP_LEARN;
805 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
806 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
807 }
808
809 static u32
810 ar8327_read_port_status(struct ar8216_priv *priv, int port)
811 {
812 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
813 }
814
815 static int
816 ar8327_atu_flush(struct ar8216_priv *priv)
817 {
818 int ret;
819
820 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
821 AR8327_ATU_FUNC_BUSY, 0);
822 if (!ret)
823 priv->write(priv, AR8327_REG_ATU_FUNC,
824 AR8327_ATU_FUNC_OP_FLUSH);
825
826 return ret;
827 }
828
829 static void
830 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
831 {
832 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
833 AR8327_VTU_FUNC1_BUSY, 0))
834 return;
835
836 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
837 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
838
839 op |= AR8327_VTU_FUNC1_BUSY;
840 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
841 }
842
843 static void
844 ar8327_vtu_flush(struct ar8216_priv *priv)
845 {
846 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
847 }
848
849 static void
850 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
851 {
852 u32 op;
853 u32 val;
854 int i;
855
856 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
857 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
858 for (i = 0; i < AR8327_NUM_PORTS; i++) {
859 u32 mode;
860
861 if ((port_mask & BIT(i)) == 0)
862 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
863 else if (priv->vlan == 0)
864 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
865 else if (priv->vlan_tagged & BIT(i))
866 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
867 else
868 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
869
870 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
871 }
872 ar8327_vtu_op(priv, op, val);
873 }
874
875 static void
876 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
877 u32 members, u32 pvid)
878 {
879 u32 t;
880 u32 mode;
881
882 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
883 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
884 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
885
886 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
887 switch (egress) {
888 case AR8216_OUT_KEEP:
889 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
890 break;
891 case AR8216_OUT_STRIP_VLAN:
892 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
893 break;
894 case AR8216_OUT_ADD_VLAN:
895 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
896 break;
897 }
898
899 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
900 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
901 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
902
903 t = members;
904 t |= AR8327_PORT_LOOKUP_LEARN;
905 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
906 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
907 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
908 }
909
910 static const struct ar8xxx_chip ar8327_chip = {
911 .caps = AR8XXX_CAP_GIGE,
912 .hw_init = ar8327_hw_init,
913 .init_globals = ar8327_init_globals,
914 .init_port = ar8327_init_port,
915 .setup_port = ar8327_setup_port,
916 .read_port_status = ar8327_read_port_status,
917 .atu_flush = ar8327_atu_flush,
918 .vtu_flush = ar8327_vtu_flush,
919 .vtu_load_vlan = ar8327_vtu_load_vlan,
920 };
921
922 static int
923 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
924 struct switch_val *val)
925 {
926 struct ar8216_priv *priv = to_ar8216(dev);
927 priv->vlan = !!val->value.i;
928 return 0;
929 }
930
931 static int
932 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
933 struct switch_val *val)
934 {
935 struct ar8216_priv *priv = to_ar8216(dev);
936 val->value.i = priv->vlan;
937 return 0;
938 }
939
940
941 static int
942 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
943 {
944 struct ar8216_priv *priv = to_ar8216(dev);
945
946 /* make sure no invalid PVIDs get set */
947
948 if (vlan >= dev->vlans)
949 return -EINVAL;
950
951 priv->pvid[port] = vlan;
952 return 0;
953 }
954
955 static int
956 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
957 {
958 struct ar8216_priv *priv = to_ar8216(dev);
959 *vlan = priv->pvid[port];
960 return 0;
961 }
962
963 static int
964 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
965 struct switch_val *val)
966 {
967 struct ar8216_priv *priv = to_ar8216(dev);
968 priv->vlan_id[val->port_vlan] = val->value.i;
969 return 0;
970 }
971
972 static int
973 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
974 struct switch_val *val)
975 {
976 struct ar8216_priv *priv = to_ar8216(dev);
977 val->value.i = priv->vlan_id[val->port_vlan];
978 return 0;
979 }
980
981 static int
982 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
983 struct switch_port_link *link)
984 {
985 struct ar8216_priv *priv = to_ar8216(dev);
986
987 ar8216_read_port_link(priv, port, link);
988 return 0;
989 }
990
991 static int
992 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
993 {
994 struct ar8216_priv *priv = to_ar8216(dev);
995 u8 ports = priv->vlan_table[val->port_vlan];
996 int i;
997
998 val->len = 0;
999 for (i = 0; i < dev->ports; i++) {
1000 struct switch_port *p;
1001
1002 if (!(ports & (1 << i)))
1003 continue;
1004
1005 p = &val->value.ports[val->len++];
1006 p->id = i;
1007 if (priv->vlan_tagged & (1 << i))
1008 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1009 else
1010 p->flags = 0;
1011 }
1012 return 0;
1013 }
1014
1015 static int
1016 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1017 {
1018 struct ar8216_priv *priv = to_ar8216(dev);
1019 u8 *vt = &priv->vlan_table[val->port_vlan];
1020 int i, j;
1021
1022 *vt = 0;
1023 for (i = 0; i < val->len; i++) {
1024 struct switch_port *p = &val->value.ports[i];
1025
1026 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1027 priv->vlan_tagged |= (1 << p->id);
1028 } else {
1029 priv->vlan_tagged &= ~(1 << p->id);
1030 priv->pvid[p->id] = val->port_vlan;
1031
1032 /* make sure that an untagged port does not
1033 * appear in other vlans */
1034 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1035 if (j == val->port_vlan)
1036 continue;
1037 priv->vlan_table[j] &= ~(1 << p->id);
1038 }
1039 }
1040
1041 *vt |= 1 << p->id;
1042 }
1043 return 0;
1044 }
1045
1046 static int
1047 ar8216_sw_hw_apply(struct switch_dev *dev)
1048 {
1049 struct ar8216_priv *priv = to_ar8216(dev);
1050 u8 portmask[AR8X16_MAX_PORTS];
1051 int i, j;
1052
1053 mutex_lock(&priv->reg_mutex);
1054 /* flush all vlan translation unit entries */
1055 priv->chip->vtu_flush(priv);
1056
1057 memset(portmask, 0, sizeof(portmask));
1058 if (!priv->init) {
1059 /* calculate the port destination masks and load vlans
1060 * into the vlan translation unit */
1061 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1062 u8 vp = priv->vlan_table[j];
1063
1064 if (!vp)
1065 continue;
1066
1067 for (i = 0; i < dev->ports; i++) {
1068 u8 mask = (1 << i);
1069 if (vp & mask)
1070 portmask[i] |= vp & ~mask;
1071 }
1072
1073 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1074 priv->vlan_table[j]);
1075 }
1076 } else {
1077 /* vlan disabled:
1078 * isolate all ports, but connect them to the cpu port */
1079 for (i = 0; i < dev->ports; i++) {
1080 if (i == AR8216_PORT_CPU)
1081 continue;
1082
1083 portmask[i] = 1 << AR8216_PORT_CPU;
1084 portmask[AR8216_PORT_CPU] |= (1 << i);
1085 }
1086 }
1087
1088 /* update the port destination mask registers and tag settings */
1089 for (i = 0; i < dev->ports; i++) {
1090 int egress, ingress;
1091 int pvid;
1092
1093 if (priv->vlan) {
1094 pvid = priv->vlan_id[priv->pvid[i]];
1095 if (priv->vlan_tagged & (1 << i))
1096 egress = AR8216_OUT_ADD_VLAN;
1097 else
1098 egress = AR8216_OUT_STRIP_VLAN;
1099 ingress = AR8216_IN_SECURE;
1100 } else {
1101 pvid = i;
1102 egress = AR8216_OUT_KEEP;
1103 ingress = AR8216_IN_PORT_ONLY;
1104 }
1105
1106 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1107 pvid);
1108 }
1109 mutex_unlock(&priv->reg_mutex);
1110 return 0;
1111 }
1112
1113 static int
1114 ar8216_sw_reset_switch(struct switch_dev *dev)
1115 {
1116 struct ar8216_priv *priv = to_ar8216(dev);
1117 int i;
1118
1119 mutex_lock(&priv->reg_mutex);
1120 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1121 offsetof(struct ar8216_priv, vlan));
1122
1123 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1124 priv->vlan_id[i] = i;
1125
1126 /* Configure all ports */
1127 for (i = 0; i < dev->ports; i++)
1128 priv->chip->init_port(priv, i);
1129
1130 priv->chip->init_globals(priv);
1131 mutex_unlock(&priv->reg_mutex);
1132
1133 return ar8216_sw_hw_apply(dev);
1134 }
1135
1136 static struct switch_attr ar8216_globals[] = {
1137 {
1138 .type = SWITCH_TYPE_INT,
1139 .name = "enable_vlan",
1140 .description = "Enable VLAN mode",
1141 .set = ar8216_sw_set_vlan,
1142 .get = ar8216_sw_get_vlan,
1143 .max = 1
1144 },
1145 };
1146
1147 static struct switch_attr ar8216_port[] = {
1148 };
1149
1150 static struct switch_attr ar8216_vlan[] = {
1151 {
1152 .type = SWITCH_TYPE_INT,
1153 .name = "vid",
1154 .description = "VLAN ID (0-4094)",
1155 .set = ar8216_sw_set_vid,
1156 .get = ar8216_sw_get_vid,
1157 .max = 4094,
1158 },
1159 };
1160
1161 static const struct switch_dev_ops ar8216_sw_ops = {
1162 .attr_global = {
1163 .attr = ar8216_globals,
1164 .n_attr = ARRAY_SIZE(ar8216_globals),
1165 },
1166 .attr_port = {
1167 .attr = ar8216_port,
1168 .n_attr = ARRAY_SIZE(ar8216_port),
1169 },
1170 .attr_vlan = {
1171 .attr = ar8216_vlan,
1172 .n_attr = ARRAY_SIZE(ar8216_vlan),
1173 },
1174 .get_port_pvid = ar8216_sw_get_pvid,
1175 .set_port_pvid = ar8216_sw_set_pvid,
1176 .get_vlan_ports = ar8216_sw_get_ports,
1177 .set_vlan_ports = ar8216_sw_set_ports,
1178 .apply_config = ar8216_sw_hw_apply,
1179 .reset_switch = ar8216_sw_reset_switch,
1180 .get_port_link = ar8216_sw_get_port_link,
1181 };
1182
1183 static int
1184 ar8216_id_chip(struct ar8216_priv *priv)
1185 {
1186 u32 val;
1187 u16 id;
1188 int i;
1189
1190 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1191 if (val == ~0)
1192 return -ENODEV;
1193
1194 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1195 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1196 u16 t;
1197
1198 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1199 if (val == ~0)
1200 return -ENODEV;
1201
1202 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1203 if (t != id)
1204 return -ENODEV;
1205 }
1206
1207 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1208 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1209
1210 switch (priv->chip_ver) {
1211 case AR8XXX_VER_AR8216:
1212 priv->chip = &ar8216_chip;
1213 break;
1214 case AR8XXX_VER_AR8236:
1215 priv->chip = &ar8236_chip;
1216 break;
1217 case AR8XXX_VER_AR8316:
1218 priv->chip = &ar8316_chip;
1219 break;
1220 case AR8XXX_VER_AR8327:
1221 priv->mii_lo_first = true;
1222 priv->chip = &ar8327_chip;
1223 break;
1224 default:
1225 printk(KERN_DEBUG
1226 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1227 priv->chip_ver, priv->chip_rev,
1228 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1229 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1230
1231 return -ENODEV;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int
1238 ar8216_config_init(struct phy_device *pdev)
1239 {
1240 struct ar8216_priv *priv = pdev->priv;
1241 struct net_device *dev = pdev->attached_dev;
1242 struct switch_dev *swdev;
1243 int ret;
1244
1245 if (!priv) {
1246 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1247 if (priv == NULL)
1248 return -ENOMEM;
1249 }
1250
1251 priv->phy = pdev;
1252
1253 ret = ar8216_id_chip(priv);
1254 if (ret)
1255 goto err_free_priv;
1256
1257 if (pdev->addr != 0) {
1258 if (ar8xxx_has_gige(priv)) {
1259 pdev->supported |= SUPPORTED_1000baseT_Full;
1260 pdev->advertising |= ADVERTISED_1000baseT_Full;
1261 }
1262
1263 if (chip_is_ar8316(priv)) {
1264 /* check if we're attaching to the switch twice */
1265 pdev = pdev->bus->phy_map[0];
1266 if (!pdev) {
1267 kfree(priv);
1268 return 0;
1269 }
1270
1271 /* switch device has not been initialized, reuse priv */
1272 if (!pdev->priv) {
1273 priv->port4_phy = true;
1274 pdev->priv = priv;
1275 return 0;
1276 }
1277
1278 kfree(priv);
1279
1280 /* switch device has been initialized, reinit */
1281 priv = pdev->priv;
1282 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1283 priv->initialized = false;
1284 priv->port4_phy = true;
1285 ar8316_hw_init(priv);
1286 return 0;
1287 }
1288
1289 kfree(priv);
1290 return 0;
1291 }
1292
1293 if (ar8xxx_has_gige(priv))
1294 pdev->supported = SUPPORTED_1000baseT_Full;
1295 else
1296 pdev->supported = SUPPORTED_100baseT_Full;
1297 pdev->advertising = pdev->supported;
1298
1299 mutex_init(&priv->reg_mutex);
1300 priv->read = ar8216_mii_read;
1301 priv->write = ar8216_mii_write;
1302
1303 pdev->priv = priv;
1304
1305 swdev = &priv->dev;
1306 swdev->cpu_port = AR8216_PORT_CPU;
1307 swdev->ops = &ar8216_sw_ops;
1308 swdev->ports = AR8216_NUM_PORTS;
1309
1310 if (chip_is_ar8316(priv)) {
1311 swdev->name = "Atheros AR8316";
1312 swdev->vlans = AR8X16_MAX_VLANS;
1313
1314 if (priv->port4_phy) {
1315 /* port 5 connected to the other mac, therefore unusable */
1316 swdev->ports = (AR8216_NUM_PORTS - 1);
1317 }
1318 } else if (chip_is_ar8236(priv)) {
1319 swdev->name = "Atheros AR8236";
1320 swdev->vlans = AR8216_NUM_VLANS;
1321 swdev->ports = AR8216_NUM_PORTS;
1322 } else if (chip_is_ar8327(priv)) {
1323 swdev->name = "Atheros AR8327";
1324 swdev->vlans = AR8X16_MAX_VLANS;
1325 swdev->ports = AR8327_NUM_PORTS;
1326 } else {
1327 swdev->name = "Atheros AR8216";
1328 swdev->vlans = AR8216_NUM_VLANS;
1329 }
1330
1331 ret = register_switch(&priv->dev, pdev->attached_dev);
1332 if (ret)
1333 goto err_free_priv;
1334
1335 printk(KERN_INFO "%s: %s switch driver attached.\n",
1336 pdev->attached_dev->name, swdev->name);
1337
1338 priv->init = true;
1339
1340 ret = priv->chip->hw_init(priv);
1341 if (ret)
1342 goto err_free_priv;
1343
1344 ret = ar8216_sw_reset_switch(&priv->dev);
1345 if (ret)
1346 goto err_free_priv;
1347
1348 dev->phy_ptr = priv;
1349
1350 /* VID fixup only needed on ar8216 */
1351 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1352 dev->priv_flags |= IFF_NO_IP_ALIGN;
1353 dev->eth_mangle_rx = ar8216_mangle_rx;
1354 dev->eth_mangle_tx = ar8216_mangle_tx;
1355 }
1356
1357 priv->init = false;
1358
1359 return 0;
1360
1361 err_free_priv:
1362 kfree(priv);
1363 return ret;
1364 }
1365
1366 static int
1367 ar8216_read_status(struct phy_device *phydev)
1368 {
1369 struct ar8216_priv *priv = phydev->priv;
1370 struct switch_port_link link;
1371 int ret;
1372
1373 if (phydev->addr != 0)
1374 return genphy_read_status(phydev);
1375
1376 ar8216_read_port_link(priv, phydev->addr, &link);
1377 phydev->link = !!link.link;
1378 if (!phydev->link)
1379 return 0;
1380
1381 switch (link.speed) {
1382 case SWITCH_PORT_SPEED_10:
1383 phydev->speed = SPEED_10;
1384 break;
1385 case SWITCH_PORT_SPEED_100:
1386 phydev->speed = SPEED_100;
1387 break;
1388 case SWITCH_PORT_SPEED_1000:
1389 phydev->speed = SPEED_1000;
1390 break;
1391 default:
1392 phydev->speed = 0;
1393 }
1394 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1395
1396 /* flush the address translation unit */
1397 mutex_lock(&priv->reg_mutex);
1398 ret = priv->chip->atu_flush(priv);
1399 mutex_unlock(&priv->reg_mutex);
1400
1401 phydev->state = PHY_RUNNING;
1402 netif_carrier_on(phydev->attached_dev);
1403 phydev->adjust_link(phydev->attached_dev);
1404
1405 return ret;
1406 }
1407
1408 static int
1409 ar8216_config_aneg(struct phy_device *phydev)
1410 {
1411 if (phydev->addr == 0)
1412 return 0;
1413
1414 return genphy_config_aneg(phydev);
1415 }
1416
1417 static int
1418 ar8216_probe(struct phy_device *pdev)
1419 {
1420 struct ar8216_priv priv;
1421
1422 priv.phy = pdev;
1423 return ar8216_id_chip(&priv);
1424 }
1425
1426 static void
1427 ar8216_remove(struct phy_device *pdev)
1428 {
1429 struct ar8216_priv *priv = pdev->priv;
1430 struct net_device *dev = pdev->attached_dev;
1431
1432 if (!priv)
1433 return;
1434
1435 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1436 dev->eth_mangle_rx = NULL;
1437 dev->eth_mangle_tx = NULL;
1438
1439 if (pdev->addr == 0)
1440 unregister_switch(&priv->dev);
1441 kfree(priv);
1442 }
1443
1444 static struct phy_driver ar8216_driver = {
1445 .phy_id = 0x004d0000,
1446 .name = "Atheros AR8216/AR8236/AR8316",
1447 .phy_id_mask = 0xffff0000,
1448 .features = PHY_BASIC_FEATURES,
1449 .probe = ar8216_probe,
1450 .remove = ar8216_remove,
1451 .config_init = &ar8216_config_init,
1452 .config_aneg = &ar8216_config_aneg,
1453 .read_status = &ar8216_read_status,
1454 .driver = { .owner = THIS_MODULE },
1455 };
1456
1457 int __init
1458 ar8216_init(void)
1459 {
1460 return phy_driver_register(&ar8216_driver);
1461 }
1462
1463 void __exit
1464 ar8216_exit(void)
1465 {
1466 phy_driver_unregister(&ar8216_driver);
1467 }
1468
1469 module_init(ar8216_init);
1470 module_exit(ar8216_exit);
1471 MODULE_LICENSE("GPL");
1472
Staging tree of Christian Lamparter