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generic: ar8216: add support for ar724x/ar933x builtin switch
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR7240SW_NUM_PORTS 5
30 #define AR8316_NUM_VLANS 4096
31
32 /* size of the vlan table */
33 #define AR8X16_MAX_VLANS 128
34 #define AR8X16_PROBE_RETRIES 10
35 #define AR8X16_MAX_PORTS 8
36
37 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
38 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
39
40 /* Atheros specific MII registers */
41 #define MII_ATH_MMD_ADDR 0x0d
42 #define MII_ATH_MMD_DATA 0x0e
43 #define MII_ATH_DBG_ADDR 0x1d
44 #define MII_ATH_DBG_DATA 0x1e
45
46 #define AR8216_REG_CTRL 0x0000
47 #define AR8216_CTRL_REVISION BITS(0, 8)
48 #define AR8216_CTRL_REVISION_S 0
49 #define AR8216_CTRL_VERSION BITS(8, 8)
50 #define AR8216_CTRL_VERSION_S 8
51 #define AR8216_CTRL_RESET BIT(31)
52
53 #define AR8216_REG_FLOOD_MASK 0x002C
54 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
55 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
56 #define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
57 #define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
58 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
59 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
60
61 #define AR8216_REG_GLOBAL_CTRL 0x0030
62 #define AR8216_GCTRL_MTU BITS(0, 11)
63 #define AR8236_GCTRL_MTU BITS(0, 14)
64 #define AR8316_GCTRL_MTU BITS(0, 14)
65
66 #define AR8216_REG_VTU 0x0040
67 #define AR8216_VTU_OP BITS(0, 3)
68 #define AR8216_VTU_OP_NOOP 0x0
69 #define AR8216_VTU_OP_FLUSH 0x1
70 #define AR8216_VTU_OP_LOAD 0x2
71 #define AR8216_VTU_OP_PURGE 0x3
72 #define AR8216_VTU_OP_REMOVE_PORT 0x4
73 #define AR8216_VTU_ACTIVE BIT(3)
74 #define AR8216_VTU_FULL BIT(4)
75 #define AR8216_VTU_PORT BITS(8, 4)
76 #define AR8216_VTU_PORT_S 8
77 #define AR8216_VTU_VID BITS(16, 12)
78 #define AR8216_VTU_VID_S 16
79 #define AR8216_VTU_PRIO BITS(28, 3)
80 #define AR8216_VTU_PRIO_S 28
81 #define AR8216_VTU_PRIO_EN BIT(31)
82
83 #define AR8216_REG_VTU_DATA 0x0044
84 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
85 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
86 #define AR8216_VTUDATA_VALID BIT(11)
87
88 #define AR8216_REG_ATU_FUNC0 0x0050
89 #define AR8216_ATU_OP BITS(0, 3)
90 #define AR8216_ATU_OP_NOOP 0x0
91 #define AR8216_ATU_OP_FLUSH 0x1
92 #define AR8216_ATU_OP_LOAD 0x2
93 #define AR8216_ATU_OP_PURGE 0x3
94 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
95 #define AR8216_ATU_OP_FLUSH_PORT 0x5
96 #define AR8216_ATU_OP_GET_NEXT 0x6
97 #define AR8216_ATU_ACTIVE BIT(3)
98 #define AR8216_ATU_PORT_NUM BITS(8, 4)
99 #define AR8216_ATU_PORT_NUM_S 8
100 #define AR8216_ATU_FULL_VIO BIT(12)
101 #define AR8216_ATU_ADDR5 BITS(16, 8)
102 #define AR8216_ATU_ADDR5_S 16
103 #define AR8216_ATU_ADDR4 BITS(24, 8)
104 #define AR8216_ATU_ADDR4_S 24
105
106 #define AR8216_REG_ATU_FUNC1 0x0054
107 #define AR8216_ATU_ADDR3 BITS(0, 8)
108 #define AR8216_ATU_ADDR3_S 0
109 #define AR8216_ATU_ADDR2 BITS(8, 8)
110 #define AR8216_ATU_ADDR2_S 8
111 #define AR8216_ATU_ADDR1 BITS(16, 8)
112 #define AR8216_ATU_ADDR1_S 16
113 #define AR8216_ATU_ADDR0 BITS(24, 8)
114 #define AR8216_ATU_ADDR0_S 24
115
116 #define AR8216_REG_ATU_FUNC2 0x0058
117 #define AR8216_ATU_PORTS BITS(0, 6)
118 #define AR8216_ATU_PORTS_S 0
119 #define AR8216_ATU_PORT0 BIT(0)
120 #define AR8216_ATU_PORT1 BIT(1)
121 #define AR8216_ATU_PORT2 BIT(2)
122 #define AR8216_ATU_PORT3 BIT(3)
123 #define AR8216_ATU_PORT4 BIT(4)
124 #define AR8216_ATU_PORT5 BIT(5)
125 #define AR8216_ATU_STATUS BITS(16, 4)
126 #define AR8216_ATU_STATUS_S 16
127
128 #define AR8216_REG_ATU_CTRL 0x005C
129 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
130 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
131 #define AR8216_ATU_CTRL_AGE_TIME_S 0
132 #define AR8236_ATU_CTRL_RES BIT(20)
133 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
134 #define AR8216_ATU_CTRL_RESERVED BIT(19)
135 #define AR8216_ATU_CTRL_ARP_EN BIT(20)
136
137 #define AR8216_REG_TAG_PRIORITY 0x0070
138
139 #define AR8216_REG_SERVICE_TAG 0x0074
140 #define AR8216_SERVICE_TAG_M BITS(0, 16)
141
142 #define AR8216_REG_MIB_FUNC 0x0080
143 #define AR8216_MIB_TIMER BITS(0, 16)
144 #define AR8216_MIB_AT_HALF_EN BIT(16)
145 #define AR8216_MIB_BUSY BIT(17)
146 #define AR8216_MIB_FUNC BITS(24, 3)
147 #define AR8216_MIB_FUNC_S 24
148 #define AR8216_MIB_FUNC_NO_OP 0x0
149 #define AR8216_MIB_FUNC_FLUSH 0x1
150 #define AR8216_MIB_FUNC_CAPTURE 0x3
151 #define AR8236_MIB_EN BIT(30)
152
153 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
154 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
155 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
156 #define AR8216_GLOBAL_CPUPORT_EN BIT(8)
157
158 #define AR8216_REG_MDIO_CTRL 0x98
159 #define AR8216_MDIO_CTRL_DATA_M BITS(0, 16)
160 #define AR8216_MDIO_CTRL_REG_ADDR_S 16
161 #define AR8216_MDIO_CTRL_PHY_ADDR_S 21
162 #define AR8216_MDIO_CTRL_CMD_WRITE 0
163 #define AR8216_MDIO_CTRL_CMD_READ BIT(27)
164 #define AR8216_MDIO_CTRL_MASTER_EN BIT(30)
165 #define AR8216_MDIO_CTRL_BUSY BIT(31)
166
167 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
168 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
169 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
170 #define AR8216_PORT_STATUS_SPEED_S 0
171 #define AR8216_PORT_STATUS_TXMAC BIT(2)
172 #define AR8216_PORT_STATUS_RXMAC BIT(3)
173 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
174 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
175 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
176 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
177 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
178 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
179 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
180
181 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
182
183 /* port forwarding state */
184 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
185 #define AR8216_PORT_CTRL_STATE_S 0
186
187 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
188
189 /* egress 802.1q mode */
190 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
191 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
192
193 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
194 #define AR8216_PORT_CTRL_HEADER BIT(11)
195 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
196 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
197 #define AR8216_PORT_CTRL_LEARN BIT(14)
198 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
199 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
200
201 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
202
203 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
204 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
205
206 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
207 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
208
209 /* bit0 added to the priority field of egress frames */
210 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
211
212 /* port default priority */
213 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
214 #define AR8216_PORT_VLAN_PRIORITY_S 28
215
216 /* ingress 802.1q mode */
217 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
218 #define AR8216_PORT_VLAN_MODE_S 30
219
220 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
221 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
222
223 #define AR8216_STATS_RXBROAD 0x00
224 #define AR8216_STATS_RXPAUSE 0x04
225 #define AR8216_STATS_RXMULTI 0x08
226 #define AR8216_STATS_RXFCSERR 0x0c
227 #define AR8216_STATS_RXALIGNERR 0x10
228 #define AR8216_STATS_RXRUNT 0x14
229 #define AR8216_STATS_RXFRAGMENT 0x18
230 #define AR8216_STATS_RX64BYTE 0x1c
231 #define AR8216_STATS_RX128BYTE 0x20
232 #define AR8216_STATS_RX256BYTE 0x24
233 #define AR8216_STATS_RX512BYTE 0x28
234 #define AR8216_STATS_RX1024BYTE 0x2c
235 #define AR8216_STATS_RXMAXBYTE 0x30
236 #define AR8216_STATS_RXTOOLONG 0x34
237 #define AR8216_STATS_RXGOODBYTE 0x38
238 #define AR8216_STATS_RXBADBYTE 0x40
239 #define AR8216_STATS_RXOVERFLOW 0x48
240 #define AR8216_STATS_FILTERED 0x4c
241 #define AR8216_STATS_TXBROAD 0x50
242 #define AR8216_STATS_TXPAUSE 0x54
243 #define AR8216_STATS_TXMULTI 0x58
244 #define AR8216_STATS_TXUNDERRUN 0x5c
245 #define AR8216_STATS_TX64BYTE 0x60
246 #define AR8216_STATS_TX128BYTE 0x64
247 #define AR8216_STATS_TX256BYTE 0x68
248 #define AR8216_STATS_TX512BYTE 0x6c
249 #define AR8216_STATS_TX1024BYTE 0x70
250 #define AR8216_STATS_TXMAXBYTE 0x74
251 #define AR8216_STATS_TXOVERSIZE 0x78
252 #define AR8216_STATS_TXBYTE 0x7c
253 #define AR8216_STATS_TXCOLLISION 0x84
254 #define AR8216_STATS_TXABORTCOL 0x88
255 #define AR8216_STATS_TXMULTICOL 0x8c
256 #define AR8216_STATS_TXSINGLECOL 0x90
257 #define AR8216_STATS_TXEXCDEFER 0x94
258 #define AR8216_STATS_TXDEFER 0x98
259 #define AR8216_STATS_TXLATECOL 0x9c
260
261 #define AR8229_REG_OPER_MODE0 0x04
262 #define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6)
263 #define AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
264
265 #define AR8229_REG_OPER_MODE1 0x08
266 #define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
267
268 #define AR8229_REG_QM_CTRL 0x3c
269 #define AR8229_QM_CTRL_ARP_EN BIT(15)
270
271 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
272 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
273 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
274 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
275 #define AR8236_PORT_VLAN_PRIORITY_S 28
276
277 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
278 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
279 #define AR8236_PORT_VLAN2_MEMBER_S 16
280 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
281 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
282 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
283
284 #define AR8236_STATS_RXBROAD 0x00
285 #define AR8236_STATS_RXPAUSE 0x04
286 #define AR8236_STATS_RXMULTI 0x08
287 #define AR8236_STATS_RXFCSERR 0x0c
288 #define AR8236_STATS_RXALIGNERR 0x10
289 #define AR8236_STATS_RXRUNT 0x14
290 #define AR8236_STATS_RXFRAGMENT 0x18
291 #define AR8236_STATS_RX64BYTE 0x1c
292 #define AR8236_STATS_RX128BYTE 0x20
293 #define AR8236_STATS_RX256BYTE 0x24
294 #define AR8236_STATS_RX512BYTE 0x28
295 #define AR8236_STATS_RX1024BYTE 0x2c
296 #define AR8236_STATS_RX1518BYTE 0x30
297 #define AR8236_STATS_RXMAXBYTE 0x34
298 #define AR8236_STATS_RXTOOLONG 0x38
299 #define AR8236_STATS_RXGOODBYTE 0x3c
300 #define AR8236_STATS_RXBADBYTE 0x44
301 #define AR8236_STATS_RXOVERFLOW 0x4c
302 #define AR8236_STATS_FILTERED 0x50
303 #define AR8236_STATS_TXBROAD 0x54
304 #define AR8236_STATS_TXPAUSE 0x58
305 #define AR8236_STATS_TXMULTI 0x5c
306 #define AR8236_STATS_TXUNDERRUN 0x60
307 #define AR8236_STATS_TX64BYTE 0x64
308 #define AR8236_STATS_TX128BYTE 0x68
309 #define AR8236_STATS_TX256BYTE 0x6c
310 #define AR8236_STATS_TX512BYTE 0x70
311 #define AR8236_STATS_TX1024BYTE 0x74
312 #define AR8236_STATS_TX1518BYTE 0x78
313 #define AR8236_STATS_TXMAXBYTE 0x7c
314 #define AR8236_STATS_TXOVERSIZE 0x80
315 #define AR8236_STATS_TXBYTE 0x84
316 #define AR8236_STATS_TXCOLLISION 0x8c
317 #define AR8236_STATS_TXABORTCOL 0x90
318 #define AR8236_STATS_TXMULTICOL 0x94
319 #define AR8236_STATS_TXSINGLECOL 0x98
320 #define AR8236_STATS_TXEXCDEFER 0x9c
321 #define AR8236_STATS_TXDEFER 0xa0
322 #define AR8236_STATS_TXLATECOL 0xa4
323
324 #define AR8316_REG_POSTRIP 0x0008
325 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
326 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
327 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
328 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
329 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
330 #define AR8316_POSTRIP_RTL_MODE BIT(5)
331 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
332 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
333 #define AR8316_POSTRIP_SERDES_EN BIT(8)
334 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
335 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
336 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
337 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
338 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
339 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
340 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
341 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
342 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
343 #define AR8316_POSTRIP_MAN_EN BIT(18)
344 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
345 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
346 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
347 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
348 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
349 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
350 #define AR8316_POSTRIP_SPI_EN BIT(25)
351 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
352 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
353
354 /* port speed */
355 enum {
356 AR8216_PORT_SPEED_10M = 0,
357 AR8216_PORT_SPEED_100M = 1,
358 AR8216_PORT_SPEED_1000M = 2,
359 AR8216_PORT_SPEED_ERR = 3,
360 };
361
362 /* ingress 802.1q mode */
363 enum {
364 AR8216_IN_PORT_ONLY = 0,
365 AR8216_IN_PORT_FALLBACK = 1,
366 AR8216_IN_VLAN_ONLY = 2,
367 AR8216_IN_SECURE = 3
368 };
369
370 /* egress 802.1q mode */
371 enum {
372 AR8216_OUT_KEEP = 0,
373 AR8216_OUT_STRIP_VLAN = 1,
374 AR8216_OUT_ADD_VLAN = 2
375 };
376
377 /* port forwarding state */
378 enum {
379 AR8216_PORT_STATE_DISABLED = 0,
380 AR8216_PORT_STATE_BLOCK = 1,
381 AR8216_PORT_STATE_LISTEN = 2,
382 AR8216_PORT_STATE_LEARN = 3,
383 AR8216_PORT_STATE_FORWARD = 4
384 };
385
386 enum {
387 AR8XXX_VER_AR8216 = 0x01,
388 AR8XXX_VER_AR8236 = 0x03,
389 AR8XXX_VER_AR8316 = 0x10,
390 AR8XXX_VER_AR8327 = 0x12,
391 AR8XXX_VER_AR8337 = 0x13,
392 };
393
394 #define AR8XXX_NUM_ARL_RECORDS 100
395
396 enum arl_op {
397 AR8XXX_ARL_INITIALIZE,
398 AR8XXX_ARL_GET_NEXT
399 };
400
401 struct arl_entry {
402 u16 portmap;
403 u8 mac[6];
404 };
405
406 struct ar8xxx_priv;
407
408 struct ar8xxx_mib_desc {
409 unsigned int size;
410 unsigned int offset;
411 const char *name;
412 };
413
414 struct ar8xxx_chip {
415 unsigned long caps;
416 bool config_at_probe;
417 bool mii_lo_first;
418
419 /* parameters to calculate REG_PORT_STATS_BASE */
420 unsigned reg_port_stats_start;
421 unsigned reg_port_stats_length;
422
423 unsigned reg_arl_ctrl;
424
425 int (*hw_init)(struct ar8xxx_priv *priv);
426 void (*cleanup)(struct ar8xxx_priv *priv);
427
428 const char *name;
429 int vlans;
430 int ports;
431 const struct switch_dev_ops *swops;
432
433 void (*init_globals)(struct ar8xxx_priv *priv);
434 void (*init_port)(struct ar8xxx_priv *priv, int port);
435 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
436 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
437 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
438 int (*atu_flush)(struct ar8xxx_priv *priv);
439 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
440 void (*vtu_flush)(struct ar8xxx_priv *priv);
441 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
442 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
443 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
444 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
445 u32 *status, enum arl_op op);
446 int (*sw_hw_apply)(struct switch_dev *dev);
447 void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
448 int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
449 int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
450
451 const struct ar8xxx_mib_desc *mib_decs;
452 unsigned num_mibs;
453 unsigned mib_func;
454 };
455
456 struct ar8xxx_priv {
457 struct switch_dev dev;
458 struct mii_bus *mii_bus;
459 struct mii_bus *sw_mii_bus;
460 struct phy_device *phy;
461 struct device *pdev;
462
463 int (*get_port_link)(unsigned port);
464
465 const struct net_device_ops *ndo_old;
466 struct net_device_ops ndo;
467 struct mutex reg_mutex;
468 u8 chip_ver;
469 u8 chip_rev;
470 const struct ar8xxx_chip *chip;
471 void *chip_data;
472 bool initialized;
473 bool port4_phy;
474 char buf[2048];
475 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
476 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
477 bool link_up[AR8X16_MAX_PORTS];
478
479 bool init;
480
481 struct mutex mib_lock;
482 struct delayed_work mib_work;
483 int mib_next_port;
484 u64 *mib_stats;
485
486 struct list_head list;
487 unsigned int use_count;
488
489 /* all fields below are cleared on reset */
490 bool vlan;
491 u16 vlan_id[AR8X16_MAX_VLANS];
492 u8 vlan_table[AR8X16_MAX_VLANS];
493 u8 vlan_tagged;
494 u16 pvid[AR8X16_MAX_PORTS];
495 int arl_age_time;
496
497 /* mirroring */
498 bool mirror_rx;
499 bool mirror_tx;
500 int source_port;
501 int monitor_port;
502 u8 port_vlan_prio[AR8X16_MAX_PORTS];
503 };
504
505 u32
506 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
507 void
508 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
509 u32
510 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
511 void
512 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
513 u32
514 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
515
516 void
517 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
518 u16 dbg_addr, u16 *dbg_data);
519 void
520 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
521 u16 dbg_addr, u16 dbg_data);
522 void
523 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
524 u16
525 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
526 void
527 ar8xxx_phy_init(struct ar8xxx_priv *priv);
528 int
529 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
530 struct switch_val *val);
531 int
532 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
533 struct switch_val *val);
534 int
535 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
536 const struct switch_attr *attr,
537 struct switch_val *val);
538 int
539 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
540 const struct switch_attr *attr,
541 struct switch_val *val);
542 int
543 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
544 const struct switch_attr *attr,
545 struct switch_val *val);
546 int
547 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
548 const struct switch_attr *attr,
549 struct switch_val *val);
550 int
551 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
552 const struct switch_attr *attr,
553 struct switch_val *val);
554 int
555 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
556 const struct switch_attr *attr,
557 struct switch_val *val);
558 int
559 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
560 const struct switch_attr *attr,
561 struct switch_val *val);
562 int
563 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
564 const struct switch_attr *attr,
565 struct switch_val *val);
566 int
567 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
568 const struct switch_attr *attr,
569 struct switch_val *val);
570 int
571 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
572 int
573 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
574 int
575 ar8xxx_sw_hw_apply(struct switch_dev *dev);
576 int
577 ar8xxx_sw_reset_switch(struct switch_dev *dev);
578 int
579 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
580 struct switch_port_link *link);
581 int
582 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
583 const struct switch_attr *attr,
584 struct switch_val *val);
585 int
586 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val);
589 int
590 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
591 const struct switch_attr *attr,
592 struct switch_val *val);
593 int
594 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
595 const struct switch_attr *attr,
596 struct switch_val *val);
597 int
598 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
599 const struct switch_attr *attr,
600 struct switch_val *val);
601 int
602 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
603 const struct switch_attr *attr,
604 struct switch_val *val);
605 int
606 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
607 const struct switch_attr *attr,
608 struct switch_val *val);
609 int
610 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
611
612 static inline struct ar8xxx_priv *
613 swdev_to_ar8xxx(struct switch_dev *swdev)
614 {
615 return container_of(swdev, struct ar8xxx_priv, dev);
616 }
617
618 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
619 {
620 return priv->chip->caps & AR8XXX_CAP_GIGE;
621 }
622
623 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
624 {
625 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
626 }
627
628 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
629 {
630 return priv->chip_ver == AR8XXX_VER_AR8216;
631 }
632
633 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
634 {
635 return priv->chip_ver == AR8XXX_VER_AR8236;
636 }
637
638 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
639 {
640 return priv->chip_ver == AR8XXX_VER_AR8316;
641 }
642
643 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
644 {
645 return priv->chip_ver == AR8XXX_VER_AR8327;
646 }
647
648 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
649 {
650 return priv->chip_ver == AR8XXX_VER_AR8337;
651 }
652
653 static inline void
654 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
655 {
656 ar8xxx_rmw(priv, reg, 0, val);
657 }
658
659 static inline void
660 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
661 {
662 ar8xxx_rmw(priv, reg, val, 0);
663 }
664
665 static inline void
666 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
667 {
668 regaddr >>= 1;
669 *r1 = regaddr & 0x1e;
670
671 regaddr >>= 5;
672 *r2 = regaddr & 0x7;
673
674 regaddr >>= 3;
675 *page = regaddr & 0x1ff;
676 }
677
678 static inline void
679 wait_for_page_switch(void)
680 {
681 udelay(5);
682 }
683
684 #endif
Staging tree of Christian Lamparter