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linux: rtl836x: add a reset_chip callback to rtl8366_smi_ops
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366RB ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8366.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.3"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
44
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51 #define RTL8366RB_RESET_CTRL_REG 0x0100
52 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
53 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56 #define RTL8366RB_CHIP_VERSION_MASK 0xf
57 #define RTL8366RB_CHIP_ID_REG 0x0509
58 #define RTL8366RB_CHIP_ID_8366 0x5937
59
60 /* PHY registers control */
61 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64 #define RTL8366RB_PHY_CTRL_READ 1
65 #define RTL8366RB_PHY_CTRL_WRITE 0
66
67 #define RTL8366RB_PHY_REG_MASK 0x1f
68 #define RTL8366RB_PHY_PAGE_OFFSET 5
69 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70 #define RTL8366RB_PHY_NO_OFFSET 9
71 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74
75 /* LED control registers */
76 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
77 #define RTL8366RB_LED_BLINKRATE_BIT 0
78 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80 #define RTL8366RB_LED_CTRL_REG 0x0431
81 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84 #define RTL8366RB_MIB_COUNT 33
85 #define RTL8366RB_GLOBAL_MIB_COUNT 1
86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
88 #define RTL8366RB_MIB_CTRL_REG 0x13F0
89 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
111
112
113 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122 #define RTL8366RB_PORT_NUM_CPU 5
123 #define RTL8366RB_NUM_PORTS 6
124 #define RTL8366RB_NUM_VLANS 16
125 #define RTL8366RB_NUM_LEDGROUPS 4
126 #define RTL8366RB_NUM_VIDS 4096
127 #define RTL8366RB_PRIORITYMAX 7
128 #define RTL8366RB_FIDMAX 7
129
130
131 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140 RTL8366RB_PORT_2 | \
141 RTL8366RB_PORT_3 | \
142 RTL8366RB_PORT_4 | \
143 RTL8366RB_PORT_5 | \
144 RTL8366RB_PORT_CPU)
145
146 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147 RTL8366RB_PORT_2 | \
148 RTL8366RB_PORT_3 | \
149 RTL8366RB_PORT_4 | \
150 RTL8366RB_PORT_5)
151
152 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153 RTL8366RB_PORT_2 | \
154 RTL8366RB_PORT_3 | \
155 RTL8366RB_PORT_4)
156
157 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159 #define RTL8366RB_VLAN_VID_MASK 0xfff
160 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
161 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
162 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
163 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
164 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
165 #define RTL8366RB_VLAN_FID_MASK 0x7
166
167
168 /* Port ingress bandwidth control */
169 #define RTL8366RB_IB_BASE 0x0200
170 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
171 #define RTL8366RB_IB_BDTH_MASK 0x3fff
172 #define RTL8366RB_IB_PREIFG_OFFSET 14
173 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
174
175 /* Port egress bandwidth control */
176 #define RTL8366RB_EB_BASE 0x02d1
177 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
178 #define RTL8366RB_EB_BDTH_MASK 0x3fff
179 #define RTL8366RB_EB_PREIFG_REG 0x02f8
180 #define RTL8366RB_EB_PREIFG_OFFSET 9
181 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
182
183 #define RTL8366RB_BDTH_SW_MAX 1048512
184 #define RTL8366RB_BDTH_UNIT 64
185 #define RTL8366RB_BDTH_REG_DEFAULT 16383
186
187 /* QOS */
188 #define RTL8366RB_QOS_BIT 15
189 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
190 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
191 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
192
193
194 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
195 { 0, 0, 4, "IfInOctets" },
196 { 0, 4, 4, "EtherStatsOctets" },
197 { 0, 8, 2, "EtherStatsUnderSizePkts" },
198 { 0, 10, 2, "EtherFragments" },
199 { 0, 12, 2, "EtherStatsPkts64Octets" },
200 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
201 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
202 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
203 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
204 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
205 { 0, 24, 2, "EtherOversizeStats" },
206 { 0, 26, 2, "EtherStatsJabbers" },
207 { 0, 28, 2, "IfInUcastPkts" },
208 { 0, 30, 2, "EtherStatsMulticastPkts" },
209 { 0, 32, 2, "EtherStatsBroadcastPkts" },
210 { 0, 34, 2, "EtherStatsDropEvents" },
211 { 0, 36, 2, "Dot3StatsFCSErrors" },
212 { 0, 38, 2, "Dot3StatsSymbolErrors" },
213 { 0, 40, 2, "Dot3InPauseFrames" },
214 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
215 { 0, 44, 4, "IfOutOctets" },
216 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
217 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
218 { 0, 52, 2, "Dot3sDeferredTransmissions" },
219 { 0, 54, 2, "Dot3StatsLateCollisions" },
220 { 0, 56, 2, "EtherStatsCollisions" },
221 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
222 { 0, 60, 2, "Dot3OutPauseFrames" },
223 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
224 { 0, 64, 2, "Dot1dTpPortInDiscards" },
225 { 0, 66, 2, "IfOutUcastPkts" },
226 { 0, 68, 2, "IfOutMulticastPkts" },
227 { 0, 70, 2, "IfOutBroadcastPkts" },
228 };
229
230 #define REG_WR(_smi, _reg, _val) \
231 do { \
232 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
233 if (err) \
234 return err; \
235 } while (0)
236
237 #define REG_RMW(_smi, _reg, _mask, _val) \
238 do { \
239 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
240 if (err) \
241 return err; \
242 } while (0)
243
244 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
245 {
246 int timeout = 10;
247 u32 data;
248
249 rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
250 RTL8366RB_CHIP_CTRL_RESET_HW);
251 do {
252 msleep(1);
253 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
254 return -EIO;
255
256 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
257 break;
258 } while (--timeout);
259
260 if (!timeout) {
261 printk("Timeout waiting for the switch to reset\n");
262 return -EIO;
263 }
264
265 return 0;
266 }
267
268 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
269 {
270 int err;
271
272 /* set maximum packet length to 1536 bytes */
273 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
274 RTL8366RB_SGCR_MAX_LENGTH_1536);
275
276 /* enable learning for all ports */
277 REG_WR(smi, RTL8366RB_SSCR0, 0);
278
279 /* enable auto ageing for all ports */
280 REG_WR(smi, RTL8366RB_SSCR1, 0);
281
282 /*
283 * discard VLAN tagged packets if the port is not a member of
284 * the VLAN with which the packets is associated.
285 */
286 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
287
288 /* don't drop packets whose DA has not been learned */
289 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
290
291 return 0;
292 }
293
294 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
295 u32 phy_no, u32 page, u32 addr, u32 *data)
296 {
297 u32 reg;
298 int ret;
299
300 if (phy_no > RTL8366RB_PHY_NO_MAX)
301 return -EINVAL;
302
303 if (page > RTL8366RB_PHY_PAGE_MAX)
304 return -EINVAL;
305
306 if (addr > RTL8366RB_PHY_ADDR_MAX)
307 return -EINVAL;
308
309 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
310 RTL8366RB_PHY_CTRL_READ);
311 if (ret)
312 return ret;
313
314 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
315 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
316 (addr & RTL8366RB_PHY_REG_MASK);
317
318 ret = rtl8366_smi_write_reg(smi, reg, 0);
319 if (ret)
320 return ret;
321
322 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
323 if (ret)
324 return ret;
325
326 return 0;
327 }
328
329 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
330 u32 phy_no, u32 page, u32 addr, u32 data)
331 {
332 u32 reg;
333 int ret;
334
335 if (phy_no > RTL8366RB_PHY_NO_MAX)
336 return -EINVAL;
337
338 if (page > RTL8366RB_PHY_PAGE_MAX)
339 return -EINVAL;
340
341 if (addr > RTL8366RB_PHY_ADDR_MAX)
342 return -EINVAL;
343
344 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
345 RTL8366RB_PHY_CTRL_WRITE);
346 if (ret)
347 return ret;
348
349 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
350 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
351 (addr & RTL8366RB_PHY_REG_MASK);
352
353 ret = rtl8366_smi_write_reg(smi, reg, data);
354 if (ret)
355 return ret;
356
357 return 0;
358 }
359
360 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
361 int port, unsigned long long *val)
362 {
363 int i;
364 int err;
365 u32 addr, data;
366 u64 mibvalue;
367
368 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
369 return -EINVAL;
370
371 addr = RTL8366RB_MIB_COUNTER_BASE +
372 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
373 rtl8366rb_mib_counters[counter].offset;
374
375 /*
376 * Writing access counter address first
377 * then ASIC will prepare 64bits counter wait for being retrived
378 */
379 data = 0; /* writing data will be discard by ASIC */
380 err = rtl8366_smi_write_reg(smi, addr, data);
381 if (err)
382 return err;
383
384 /* read MIB control register */
385 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
386 if (err)
387 return err;
388
389 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
390 return -EBUSY;
391
392 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
393 return -EIO;
394
395 mibvalue = 0;
396 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
397 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
398 if (err)
399 return err;
400
401 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
402 }
403
404 *val = mibvalue;
405 return 0;
406 }
407
408 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
409 struct rtl8366_vlan_4k *vlan4k)
410 {
411 u32 data[3];
412 int err;
413 int i;
414
415 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
416
417 if (vid >= RTL8366RB_NUM_VIDS)
418 return -EINVAL;
419
420 /* write VID */
421 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
422 vid & RTL8366RB_VLAN_VID_MASK);
423 if (err)
424 return err;
425
426 /* write table access control word */
427 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
428 RTL8366RB_TABLE_VLAN_READ_CTRL);
429 if (err)
430 return err;
431
432 for (i = 0; i < 3; i++) {
433 err = rtl8366_smi_read_reg(smi,
434 RTL8366RB_VLAN_TABLE_READ_BASE + i,
435 &data[i]);
436 if (err)
437 return err;
438 }
439
440 vlan4k->vid = vid;
441 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
442 RTL8366RB_VLAN_UNTAG_MASK;
443 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
444 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
445
446 return 0;
447 }
448
449 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
450 const struct rtl8366_vlan_4k *vlan4k)
451 {
452 u32 data[3];
453 int err;
454 int i;
455
456 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
457 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
458 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
459 vlan4k->fid > RTL8366RB_FIDMAX)
460 return -EINVAL;
461
462 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
463 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
464 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
465 RTL8366RB_VLAN_UNTAG_SHIFT);
466 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
467
468 for (i = 0; i < 3; i++) {
469 err = rtl8366_smi_write_reg(smi,
470 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
471 data[i]);
472 if (err)
473 return err;
474 }
475
476 /* write table access control word */
477 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
478 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
479
480 return err;
481 }
482
483 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
484 struct rtl8366_vlan_mc *vlanmc)
485 {
486 u32 data[3];
487 int err;
488 int i;
489
490 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
491
492 if (index >= RTL8366RB_NUM_VLANS)
493 return -EINVAL;
494
495 for (i = 0; i < 3; i++) {
496 err = rtl8366_smi_read_reg(smi,
497 RTL8366RB_VLAN_MC_BASE(index) + i,
498 &data[i]);
499 if (err)
500 return err;
501 }
502
503 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
504 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
505 RTL8366RB_VLAN_PRIORITY_MASK;
506 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
507 RTL8366RB_VLAN_UNTAG_MASK;
508 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
509 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
510
511 return 0;
512 }
513
514 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
515 const struct rtl8366_vlan_mc *vlanmc)
516 {
517 u32 data[3];
518 int err;
519 int i;
520
521 if (index >= RTL8366RB_NUM_VLANS ||
522 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
523 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
524 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
525 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
526 vlanmc->fid > RTL8366RB_FIDMAX)
527 return -EINVAL;
528
529 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
530 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
531 RTL8366RB_VLAN_PRIORITY_SHIFT);
532 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
533 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
534 RTL8366RB_VLAN_UNTAG_SHIFT);
535 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
536
537 for (i = 0; i < 3; i++) {
538 err = rtl8366_smi_write_reg(smi,
539 RTL8366RB_VLAN_MC_BASE(index) + i,
540 data[i]);
541 if (err)
542 return err;
543 }
544
545 return 0;
546 }
547
548 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
549 {
550 u32 data;
551 int err;
552
553 if (port >= RTL8366RB_NUM_PORTS)
554 return -EINVAL;
555
556 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
557 &data);
558 if (err)
559 return err;
560
561 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
562 RTL8366RB_PORT_VLAN_CTRL_MASK;
563
564 return 0;
565
566 }
567
568 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
569 {
570 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
571 return -EINVAL;
572
573 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
574 RTL8366RB_PORT_VLAN_CTRL_MASK <<
575 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
576 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
577 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
578 }
579
580 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
581 {
582 unsigned max = RTL8366RB_NUM_VLANS;
583
584 if (smi->vlan4k_enabled)
585 max = RTL8366RB_NUM_VIDS - 1;
586
587 if (vlan == 0 || vlan >= max)
588 return 0;
589
590 return 1;
591 }
592
593 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
594 {
595 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
596 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
597 }
598
599 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
600 {
601 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
602 RTL8366RB_SGCR_EN_VLAN_4KTB,
603 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
604 }
605
606 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
607 {
608 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
609 (enable) ? 0 : (1 << port));
610 }
611
612 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
613 const struct switch_attr *attr,
614 struct switch_val *val)
615 {
616 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
617
618 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
619 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
620 }
621
622 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
623 const struct switch_attr *attr,
624 struct switch_val *val)
625 {
626 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
627 u32 data;
628
629 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
630
631 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
632
633 return 0;
634 }
635
636 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
637 const struct switch_attr *attr,
638 struct switch_val *val)
639 {
640 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
641
642 if (val->value.i >= 6)
643 return -EINVAL;
644
645 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
646 RTL8366RB_LED_BLINKRATE_MASK,
647 val->value.i);
648 }
649
650 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
651 const struct switch_attr *attr,
652 struct switch_val *val)
653 {
654 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
655 u32 data;
656
657 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
658 val->value.i = !data;
659
660 return 0;
661 }
662
663
664 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
665 const struct switch_attr *attr,
666 struct switch_val *val)
667 {
668 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
669 u32 portmask = 0;
670 int err = 0;
671
672 if (!val->value.i)
673 portmask = RTL8366RB_PORT_ALL;
674
675 /* set learning for all ports */
676 REG_WR(smi, RTL8366RB_SSCR0, portmask);
677
678 /* set auto ageing for all ports */
679 REG_WR(smi, RTL8366RB_SSCR1, portmask);
680
681 return 0;
682 }
683
684 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
685 int port,
686 struct switch_port_link *link)
687 {
688 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
689 u32 data = 0;
690 u32 speed;
691
692 if (port >= RTL8366RB_NUM_PORTS)
693 return -EINVAL;
694
695 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
696 &data);
697
698 if (port % 2)
699 data = data >> 8;
700
701 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
702 if (!link->link)
703 return 0;
704
705 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
706 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
707 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
708 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
709
710 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
711 switch (speed) {
712 case 0:
713 link->speed = SWITCH_PORT_SPEED_10;
714 break;
715 case 1:
716 link->speed = SWITCH_PORT_SPEED_100;
717 break;
718 case 2:
719 link->speed = SWITCH_PORT_SPEED_1000;
720 break;
721 default:
722 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
723 break;
724 }
725
726 return 0;
727 }
728
729 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
730 const struct switch_attr *attr,
731 struct switch_val *val)
732 {
733 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
734 u32 data;
735 u32 mask;
736 u32 reg;
737
738 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
739 return -EINVAL;
740
741 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
742 reg = RTL8366RB_LED_BLINKRATE_REG;
743 mask = 0xF << 4;
744 data = val->value.i << 4;
745 } else {
746 reg = RTL8366RB_LED_CTRL_REG;
747 mask = 0xF << (val->port_vlan * 4),
748 data = val->value.i << (val->port_vlan * 4);
749 }
750
751 return rtl8366_smi_rmwr(smi, reg, mask, data);
752 }
753
754 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
755 const struct switch_attr *attr,
756 struct switch_val *val)
757 {
758 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
759 u32 data = 0;
760
761 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
762 return -EINVAL;
763
764 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
765 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
766
767 return 0;
768 }
769
770 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
771 const struct switch_attr *attr,
772 struct switch_val *val)
773 {
774 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
775 u32 mask, data;
776
777 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
778 return -EINVAL;
779
780 mask = 1 << val->port_vlan ;
781 if (val->value.i)
782 data = mask;
783 else
784 data = 0;
785
786 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
787 }
788
789 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
790 const struct switch_attr *attr,
791 struct switch_val *val)
792 {
793 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
794 u32 data;
795
796 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
797 return -EINVAL;
798
799 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
800 if (data & (1 << val->port_vlan))
801 val->value.i = 1;
802 else
803 val->value.i = 0;
804
805 return 0;
806 }
807
808 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
809 const struct switch_attr *attr,
810 struct switch_val *val)
811 {
812 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
813
814 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
815 return -EINVAL;
816
817 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
818 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
819 else
820 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
821
822 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
823 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
824 val->value.i |
825 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
826
827 }
828
829 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
830 const struct switch_attr *attr,
831 struct switch_val *val)
832 {
833 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
834 u32 data;
835
836 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
837 return -EINVAL;
838
839 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
840 data &= RTL8366RB_IB_BDTH_MASK;
841 if (data < RTL8366RB_IB_BDTH_MASK)
842 data += 1;
843
844 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
845
846 return 0;
847 }
848
849 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
850 const struct switch_attr *attr,
851 struct switch_val *val)
852 {
853 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
854
855 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
856 return -EINVAL;
857
858 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
859 RTL8366RB_EB_PREIFG_MASK,
860 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
861
862 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
863 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
864 else
865 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
866
867 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
868 RTL8366RB_EB_BDTH_MASK, val->value.i );
869
870 }
871
872 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
873 const struct switch_attr *attr,
874 struct switch_val *val)
875 {
876 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
877 u32 data;
878
879 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
880 return -EINVAL;
881
882 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
883 data &= RTL8366RB_EB_BDTH_MASK;
884 if (data < RTL8366RB_EB_BDTH_MASK)
885 data += 1;
886
887 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
888
889 return 0;
890 }
891
892 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
893 const struct switch_attr *attr,
894 struct switch_val *val)
895 {
896 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
897 u32 data;
898
899 if (val->value.i)
900 data = RTL8366RB_QOS_MASK;
901 else
902 data = 0;
903
904 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
905 }
906
907 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
908 const struct switch_attr *attr,
909 struct switch_val *val)
910 {
911 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
912 u32 data;
913
914 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
915 if (data & RTL8366RB_QOS_MASK)
916 val->value.i = 1;
917 else
918 val->value.i = 0;
919
920 return 0;
921 }
922
923 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
924 const struct switch_attr *attr,
925 struct switch_val *val)
926 {
927 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
928
929 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
930 return -EINVAL;
931
932 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
933 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
934 }
935
936 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
937 {
938 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
939 int err;
940
941 err = rtl8366rb_reset_chip(smi);
942 if (err)
943 return err;
944
945 err = rtl8366rb_hw_init(smi);
946 if (err)
947 return err;
948
949 err = rtl8366_reset_vlan(smi);
950 if (err)
951 return err;
952
953 err = rtl8366_enable_vlan(smi, 1);
954 if (err)
955 return err;
956
957 return rtl8366_enable_all_ports(smi, 1);
958 }
959
960 static struct switch_attr rtl8366rb_globals[] = {
961 {
962 .type = SWITCH_TYPE_INT,
963 .name = "enable_learning",
964 .description = "Enable learning, enable aging",
965 .set = rtl8366rb_sw_set_learning_enable,
966 .get = rtl8366rb_sw_get_learning_enable,
967 .max = 1
968 }, {
969 .type = SWITCH_TYPE_INT,
970 .name = "enable_vlan",
971 .description = "Enable VLAN mode",
972 .set = rtl8366_sw_set_vlan_enable,
973 .get = rtl8366_sw_get_vlan_enable,
974 .max = 1,
975 .ofs = 1
976 }, {
977 .type = SWITCH_TYPE_INT,
978 .name = "enable_vlan4k",
979 .description = "Enable VLAN 4K mode",
980 .set = rtl8366_sw_set_vlan_enable,
981 .get = rtl8366_sw_get_vlan_enable,
982 .max = 1,
983 .ofs = 2
984 }, {
985 .type = SWITCH_TYPE_NOVAL,
986 .name = "reset_mibs",
987 .description = "Reset all MIB counters",
988 .set = rtl8366rb_sw_reset_mibs,
989 }, {
990 .type = SWITCH_TYPE_INT,
991 .name = "blinkrate",
992 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
993 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
994 .set = rtl8366rb_sw_set_blinkrate,
995 .get = rtl8366rb_sw_get_blinkrate,
996 .max = 5
997 }, {
998 .type = SWITCH_TYPE_INT,
999 .name = "enable_qos",
1000 .description = "Enable QOS",
1001 .set = rtl8366rb_sw_set_qos_enable,
1002 .get = rtl8366rb_sw_get_qos_enable,
1003 .max = 1
1004 },
1005 };
1006
1007 static struct switch_attr rtl8366rb_port[] = {
1008 {
1009 .type = SWITCH_TYPE_NOVAL,
1010 .name = "reset_mib",
1011 .description = "Reset single port MIB counters",
1012 .set = rtl8366rb_sw_reset_port_mibs,
1013 }, {
1014 .type = SWITCH_TYPE_STRING,
1015 .name = "mib",
1016 .description = "Get MIB counters for port",
1017 .max = 33,
1018 .set = NULL,
1019 .get = rtl8366_sw_get_port_mib,
1020 }, {
1021 .type = SWITCH_TYPE_INT,
1022 .name = "led",
1023 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1024 .max = 15,
1025 .set = rtl8366rb_sw_set_port_led,
1026 .get = rtl8366rb_sw_get_port_led,
1027 }, {
1028 .type = SWITCH_TYPE_INT,
1029 .name = "disable",
1030 .description = "Get/Set port state (enabled or disabled)",
1031 .max = 1,
1032 .set = rtl8366rb_sw_set_port_disable,
1033 .get = rtl8366rb_sw_get_port_disable,
1034 }, {
1035 .type = SWITCH_TYPE_INT,
1036 .name = "rate_in",
1037 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1038 .max = RTL8366RB_BDTH_SW_MAX,
1039 .set = rtl8366rb_sw_set_port_rate_in,
1040 .get = rtl8366rb_sw_get_port_rate_in,
1041 }, {
1042 .type = SWITCH_TYPE_INT,
1043 .name = "rate_out",
1044 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1045 .max = RTL8366RB_BDTH_SW_MAX,
1046 .set = rtl8366rb_sw_set_port_rate_out,
1047 .get = rtl8366rb_sw_get_port_rate_out,
1048 },
1049 };
1050
1051 static struct switch_attr rtl8366rb_vlan[] = {
1052 {
1053 .type = SWITCH_TYPE_STRING,
1054 .name = "info",
1055 .description = "Get vlan information",
1056 .max = 1,
1057 .set = NULL,
1058 .get = rtl8366_sw_get_vlan_info,
1059 }, {
1060 .type = SWITCH_TYPE_INT,
1061 .name = "fid",
1062 .description = "Get/Set vlan FID",
1063 .max = RTL8366RB_FIDMAX,
1064 .set = rtl8366_sw_set_vlan_fid,
1065 .get = rtl8366_sw_get_vlan_fid,
1066 },
1067 };
1068
1069 static const struct switch_dev_ops rtl8366_ops = {
1070 .attr_global = {
1071 .attr = rtl8366rb_globals,
1072 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1073 },
1074 .attr_port = {
1075 .attr = rtl8366rb_port,
1076 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1077 },
1078 .attr_vlan = {
1079 .attr = rtl8366rb_vlan,
1080 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1081 },
1082
1083 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1084 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1085 .get_port_pvid = rtl8366_sw_get_port_pvid,
1086 .set_port_pvid = rtl8366_sw_set_port_pvid,
1087 .reset_switch = rtl8366rb_sw_reset_switch,
1088 .get_port_link = rtl8366rb_sw_get_port_link,
1089 };
1090
1091 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1092 {
1093 struct switch_dev *dev = &smi->sw_dev;
1094 int err;
1095
1096 dev->name = "RTL8366RB";
1097 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1098 dev->ports = RTL8366RB_NUM_PORTS;
1099 dev->vlans = RTL8366RB_NUM_VIDS;
1100 dev->ops = &rtl8366_ops;
1101 dev->alias = dev_name(smi->parent);
1102
1103 err = register_switch(dev, NULL);
1104 if (err)
1105 dev_err(smi->parent, "switch registration failed\n");
1106
1107 return err;
1108 }
1109
1110 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1111 {
1112 unregister_switch(&smi->sw_dev);
1113 }
1114
1115 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1116 {
1117 struct rtl8366_smi *smi = bus->priv;
1118 u32 val = 0;
1119 int err;
1120
1121 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1122 if (err)
1123 return 0xffff;
1124
1125 return val;
1126 }
1127
1128 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1129 {
1130 struct rtl8366_smi *smi = bus->priv;
1131 u32 t;
1132 int err;
1133
1134 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1135 /* flush write */
1136 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1137
1138 return err;
1139 }
1140
1141 static int rtl8366rb_setup(struct rtl8366_smi *smi)
1142 {
1143 return rtl8366rb_hw_init(smi);
1144 }
1145
1146 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1147 {
1148 u32 chip_id = 0;
1149 u32 chip_ver = 0;
1150 int ret;
1151
1152 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1153 if (ret) {
1154 dev_err(smi->parent, "unable to read chip id\n");
1155 return ret;
1156 }
1157
1158 switch (chip_id) {
1159 case RTL8366RB_CHIP_ID_8366:
1160 break;
1161 default:
1162 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1163 return -ENODEV;
1164 }
1165
1166 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1167 &chip_ver);
1168 if (ret) {
1169 dev_err(smi->parent, "unable to read chip version\n");
1170 return ret;
1171 }
1172
1173 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1174 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1175
1176 return 0;
1177 }
1178
1179 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1180 .detect = rtl8366rb_detect,
1181 .reset_chip = rtl8366rb_reset_chip,
1182 .setup = rtl8366rb_setup,
1183
1184 .mii_read = rtl8366rb_mii_read,
1185 .mii_write = rtl8366rb_mii_write,
1186
1187 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1188 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1189 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1190 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1191 .get_mc_index = rtl8366rb_get_mc_index,
1192 .set_mc_index = rtl8366rb_set_mc_index,
1193 .get_mib_counter = rtl8366rb_get_mib_counter,
1194 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1195 .enable_vlan = rtl8366rb_enable_vlan,
1196 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1197 .enable_port = rtl8366rb_enable_port,
1198 };
1199
1200 static int __devinit rtl8366rb_probe(struct platform_device *pdev)
1201 {
1202 static int rtl8366_smi_version_printed;
1203 struct rtl8366_platform_data *pdata;
1204 struct rtl8366_smi *smi;
1205 int err;
1206
1207 if (!rtl8366_smi_version_printed++)
1208 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1209 " version " RTL8366RB_DRIVER_VER"\n");
1210
1211 pdata = pdev->dev.platform_data;
1212 if (!pdata) {
1213 dev_err(&pdev->dev, "no platform data specified\n");
1214 err = -EINVAL;
1215 goto err_out;
1216 }
1217
1218 smi = rtl8366_smi_alloc(&pdev->dev);
1219 if (!smi) {
1220 err = -ENOMEM;
1221 goto err_out;
1222 }
1223
1224 smi->gpio_sda = pdata->gpio_sda;
1225 smi->gpio_sck = pdata->gpio_sck;
1226 smi->clk_delay = 10;
1227 smi->cmd_read = 0xa9;
1228 smi->cmd_write = 0xa8;
1229 smi->ops = &rtl8366rb_smi_ops;
1230 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1231 smi->num_ports = RTL8366RB_NUM_PORTS;
1232 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1233 smi->mib_counters = rtl8366rb_mib_counters;
1234 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1235
1236 err = rtl8366_smi_init(smi);
1237 if (err)
1238 goto err_free_smi;
1239
1240 platform_set_drvdata(pdev, smi);
1241
1242 err = rtl8366rb_switch_init(smi);
1243 if (err)
1244 goto err_clear_drvdata;
1245
1246 return 0;
1247
1248 err_clear_drvdata:
1249 platform_set_drvdata(pdev, NULL);
1250 rtl8366_smi_cleanup(smi);
1251 err_free_smi:
1252 kfree(smi);
1253 err_out:
1254 return err;
1255 }
1256
1257 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1258 {
1259 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1260
1261 if (smi) {
1262 rtl8366rb_switch_cleanup(smi);
1263 platform_set_drvdata(pdev, NULL);
1264 rtl8366_smi_cleanup(smi);
1265 kfree(smi);
1266 }
1267
1268 return 0;
1269 }
1270
1271 static struct platform_driver rtl8366rb_driver = {
1272 .driver = {
1273 .name = RTL8366RB_DRIVER_NAME,
1274 .owner = THIS_MODULE,
1275 },
1276 .probe = rtl8366rb_probe,
1277 .remove = __devexit_p(rtl8366rb_remove),
1278 };
1279
1280 static int __init rtl8366rb_module_init(void)
1281 {
1282 return platform_driver_register(&rtl8366rb_driver);
1283 }
1284 module_init(rtl8366rb_module_init);
1285
1286 static void __exit rtl8366rb_module_exit(void)
1287 {
1288 platform_driver_unregister(&rtl8366rb_driver);
1289 }
1290 module_exit(rtl8366rb_module_exit);
1291
1292 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1293 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1294 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1295 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1296 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1297 MODULE_LICENSE("GPL v2");
1298 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
Staging tree of Christian Lamparter