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generic: rtl8366: minor cleanup
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
44
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51 #define RTL8366RB_RESET_CTRL_REG 0x0100
52 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
53 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56 #define RTL8366RB_CHIP_VERSION_MASK 0xf
57 #define RTL8366RB_CHIP_ID_REG 0x0509
58 #define RTL8366RB_CHIP_ID_8366 0x5937
59
60 /* PHY registers control */
61 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64 #define RTL8366RB_PHY_CTRL_READ 1
65 #define RTL8366RB_PHY_CTRL_WRITE 0
66
67 #define RTL8366RB_PHY_REG_MASK 0x1f
68 #define RTL8366RB_PHY_PAGE_OFFSET 5
69 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70 #define RTL8366RB_PHY_NO_OFFSET 9
71 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73 /* LED control registers */
74 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
75 #define RTL8366RB_LED_BLINKRATE_BIT 0
76 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
77
78 #define RTL8366RB_LED_CTRL_REG 0x0431
79 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
80 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
81
82 #define RTL8366RB_MIB_COUNT 33
83 #define RTL8366RB_GLOBAL_MIB_COUNT 1
84 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
85 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
86 #define RTL8366RB_MIB_CTRL_REG 0x13F0
87 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
88 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
89 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
90 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
91 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
92
93 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
94 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
95 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
96 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
97 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
98
99
100 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
101 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
102
103
104 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
105 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
106 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
107
108 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
109
110
111 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
112 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
113 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
114 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
115 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
116 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
117 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
118
119
120 #define RTL8366RB_PORT_NUM_CPU 5
121 #define RTL8366RB_NUM_PORTS 6
122 #define RTL8366RB_NUM_VLANS 16
123 #define RTL8366RB_NUM_LEDGROUPS 4
124 #define RTL8366RB_NUM_VIDS 4096
125 #define RTL8366RB_PRIORITYMAX 7
126 #define RTL8366RB_FIDMAX 7
127
128
129 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
130 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
131 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
132 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
133 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
134
135 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
136
137 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
138 RTL8366RB_PORT_2 | \
139 RTL8366RB_PORT_3 | \
140 RTL8366RB_PORT_4 | \
141 RTL8366RB_PORT_5 | \
142 RTL8366RB_PORT_CPU)
143
144 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
145 RTL8366RB_PORT_2 | \
146 RTL8366RB_PORT_3 | \
147 RTL8366RB_PORT_4 | \
148 RTL8366RB_PORT_5)
149
150 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
151 RTL8366RB_PORT_2 | \
152 RTL8366RB_PORT_3 | \
153 RTL8366RB_PORT_4)
154
155 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
156
157 struct rtl8366rb {
158 struct device *parent;
159 struct rtl8366_smi smi;
160 struct switch_dev dev;
161 };
162
163 struct rtl8366rb_vlan_mc {
164 u16 reserved2:1;
165 u16 priority:3;
166 u16 vid:12;
167 u16 untag:8;
168 u16 member:8;
169 u16 stag_mbr:8;
170 u16 stag_idx:3;
171 u16 reserved1:2;
172 u16 fid:3;
173 };
174
175 struct rtl8366rb_vlan_4k {
176 u16 reserved1:4;
177 u16 vid:12;
178 u16 untag:8;
179 u16 member:8;
180 u16 reserved2:13;
181 u16 fid:3;
182 };
183
184 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
185 { 0, 0, 4, "IfInOctets" },
186 { 0, 4, 4, "EtherStatsOctets" },
187 { 0, 8, 2, "EtherStatsUnderSizePkts" },
188 { 0, 10, 2, "EtherFragments" },
189 { 0, 12, 2, "EtherStatsPkts64Octets" },
190 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
191 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
192 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
193 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
194 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
195 { 0, 24, 2, "EtherOversizeStats" },
196 { 0, 26, 2, "EtherStatsJabbers" },
197 { 0, 28, 2, "IfInUcastPkts" },
198 { 0, 30, 2, "EtherStatsMulticastPkts" },
199 { 0, 32, 2, "EtherStatsBroadcastPkts" },
200 { 0, 34, 2, "EtherStatsDropEvents" },
201 { 0, 36, 2, "Dot3StatsFCSErrors" },
202 { 0, 38, 2, "Dot3StatsSymbolErrors" },
203 { 0, 40, 2, "Dot3InPauseFrames" },
204 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
205 { 0, 44, 4, "IfOutOctets" },
206 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
207 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
208 { 0, 52, 2, "Dot3sDeferredTransmissions" },
209 { 0, 54, 2, "Dot3StatsLateCollisions" },
210 { 0, 56, 2, "EtherStatsCollisions" },
211 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
212 { 0, 60, 2, "Dot3OutPauseFrames" },
213 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
214 { 0, 64, 2, "Dot1dTpPortInDiscards" },
215 { 0, 66, 2, "IfOutUcastPkts" },
216 { 0, 68, 2, "IfOutMulticastPkts" },
217 { 0, 70, 2, "IfOutBroadcastPkts" },
218 };
219
220 #define REG_WR(_smi, _reg, _val) \
221 do { \
222 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
223 if (err) \
224 return err; \
225 } while (0)
226
227 #define REG_RMW(_smi, _reg, _mask, _val) \
228 do { \
229 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
230 if (err) \
231 return err; \
232 } while (0)
233
234 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
235 {
236 return container_of(smi, struct rtl8366rb, smi);
237 }
238
239 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
240 {
241 return container_of(sw, struct rtl8366rb, dev);
242 }
243
244 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
245 {
246 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
247 return &rtl->smi;
248 }
249
250 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
251 {
252 int timeout = 10;
253 u32 data;
254
255 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
256 RTL8366RB_CHIP_CTRL_RESET_HW);
257 do {
258 msleep(1);
259 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
260 return -EIO;
261
262 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
263 break;
264 } while (--timeout);
265
266 if (!timeout) {
267 printk("Timeout waiting for the switch to reset\n");
268 return -EIO;
269 }
270
271 return 0;
272 }
273
274 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
275 {
276 int err;
277
278 /* set maximum packet length to 1536 bytes */
279 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
280 RTL8366RB_SGCR_MAX_LENGTH_1536);
281
282 /* enable all ports */
283 REG_WR(smi, RTL8366RB_PECR, 0);
284
285 /* disable learning for all ports */
286 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
287
288 /* disable auto ageing for all ports */
289 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
290
291 /* don't drop packets whose DA has not been learned */
292 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
293
294 return 0;
295 }
296
297 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
298 u32 phy_no, u32 page, u32 addr, u32 *data)
299 {
300 u32 reg;
301 int ret;
302
303 if (phy_no > RTL8366RB_PHY_NO_MAX)
304 return -EINVAL;
305
306 if (page > RTL8366RB_PHY_PAGE_MAX)
307 return -EINVAL;
308
309 if (addr > RTL8366RB_PHY_ADDR_MAX)
310 return -EINVAL;
311
312 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
313 RTL8366RB_PHY_CTRL_READ);
314 if (ret)
315 return ret;
316
317 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
318 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
319 (addr & RTL8366RB_PHY_REG_MASK);
320
321 ret = rtl8366_smi_write_reg(smi, reg, 0);
322 if (ret)
323 return ret;
324
325 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
326 if (ret)
327 return ret;
328
329 return 0;
330 }
331
332 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
333 u32 phy_no, u32 page, u32 addr, u32 data)
334 {
335 u32 reg;
336 int ret;
337
338 if (phy_no > RTL8366RB_PHY_NO_MAX)
339 return -EINVAL;
340
341 if (page > RTL8366RB_PHY_PAGE_MAX)
342 return -EINVAL;
343
344 if (addr > RTL8366RB_PHY_ADDR_MAX)
345 return -EINVAL;
346
347 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
348 RTL8366RB_PHY_CTRL_WRITE);
349 if (ret)
350 return ret;
351
352 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
353 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
354 (addr & RTL8366RB_PHY_REG_MASK);
355
356 ret = rtl8366_smi_write_reg(smi, reg, data);
357 if (ret)
358 return ret;
359
360 return 0;
361 }
362
363 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
364 int port, unsigned long long *val)
365 {
366 int i;
367 int err;
368 u32 addr, data;
369 u64 mibvalue;
370
371 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
372 return -EINVAL;
373
374 addr = RTL8366RB_MIB_COUNTER_BASE +
375 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
376 rtl8366rb_mib_counters[counter].offset;
377
378 /*
379 * Writing access counter address first
380 * then ASIC will prepare 64bits counter wait for being retrived
381 */
382 data = 0; /* writing data will be discard by ASIC */
383 err = rtl8366_smi_write_reg(smi, addr, data);
384 if (err)
385 return err;
386
387 /* read MIB control register */
388 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
389 if (err)
390 return err;
391
392 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
393 return -EBUSY;
394
395 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
396 return -EIO;
397
398 mibvalue = 0;
399 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
400 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
401 if (err)
402 return err;
403
404 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
405 }
406
407 *val = mibvalue;
408 return 0;
409 }
410
411 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
412 struct rtl8366_vlan_4k *vlan4k)
413 {
414 struct rtl8366rb_vlan_4k vlan4k_priv;
415 int err;
416 u32 data;
417 u16 *tableaddr;
418
419 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
420 vlan4k_priv.vid = vid;
421
422 if (vid >= RTL8366RB_NUM_VIDS)
423 return -EINVAL;
424
425 tableaddr = (u16 *)&vlan4k_priv;
426
427 /* write VID */
428 data = *tableaddr;
429 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
430 if (err)
431 return err;
432
433 /* write table access control word */
434 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
435 RTL8366RB_TABLE_VLAN_READ_CTRL);
436 if (err)
437 return err;
438
439 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
440 if (err)
441 return err;
442
443 *tableaddr = data;
444 tableaddr++;
445
446 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
447 &data);
448 if (err)
449 return err;
450
451 *tableaddr = data;
452 tableaddr++;
453
454 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
455 &data);
456 if (err)
457 return err;
458 *tableaddr = data;
459
460 vlan4k->vid = vid;
461 vlan4k->untag = vlan4k_priv.untag;
462 vlan4k->member = vlan4k_priv.member;
463 vlan4k->fid = vlan4k_priv.fid;
464
465 return 0;
466 }
467
468 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
469 const struct rtl8366_vlan_4k *vlan4k)
470 {
471 struct rtl8366rb_vlan_4k vlan4k_priv;
472 int err;
473 u32 data;
474 u16 *tableaddr;
475
476 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
477 vlan4k->member > RTL8366RB_PORT_ALL ||
478 vlan4k->untag > RTL8366RB_PORT_ALL ||
479 vlan4k->fid > RTL8366RB_FIDMAX)
480 return -EINVAL;
481
482 vlan4k_priv.vid = vlan4k->vid;
483 vlan4k_priv.untag = vlan4k->untag;
484 vlan4k_priv.member = vlan4k->member;
485 vlan4k_priv.fid = vlan4k->fid;
486
487 tableaddr = (u16 *)&vlan4k_priv;
488
489 data = *tableaddr;
490
491 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
492 if (err)
493 return err;
494
495 tableaddr++;
496
497 data = *tableaddr;
498
499 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
500 data);
501 if (err)
502 return err;
503
504 tableaddr++;
505
506 data = *tableaddr;
507
508 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
509 data);
510 if (err)
511 return err;
512
513 /* write table access control word */
514 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
515 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
516
517 return err;
518 }
519
520 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
521 struct rtl8366_vlan_mc *vlanmc)
522 {
523 struct rtl8366rb_vlan_mc vlanmc_priv;
524 int err;
525 u32 addr;
526 u32 data;
527 u16 *tableaddr;
528
529 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
530
531 if (index >= RTL8366RB_NUM_VLANS)
532 return -EINVAL;
533
534 tableaddr = (u16 *)&vlanmc_priv;
535
536 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
537 err = rtl8366_smi_read_reg(smi, addr, &data);
538 if (err)
539 return err;
540
541 *tableaddr = data;
542 tableaddr++;
543
544 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
545 err = rtl8366_smi_read_reg(smi, addr, &data);
546 if (err)
547 return err;
548
549 *tableaddr = data;
550 tableaddr++;
551
552 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
553 err = rtl8366_smi_read_reg(smi, addr, &data);
554 if (err)
555 return err;
556
557 *tableaddr = data;
558
559 vlanmc->vid = vlanmc_priv.vid;
560 vlanmc->priority = vlanmc_priv.priority;
561 vlanmc->untag = vlanmc_priv.untag;
562 vlanmc->member = vlanmc_priv.member;
563 vlanmc->fid = vlanmc_priv.fid;
564
565 return 0;
566 }
567
568 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
569 const struct rtl8366_vlan_mc *vlanmc)
570 {
571 struct rtl8366rb_vlan_mc vlanmc_priv;
572 int err;
573 u32 addr;
574 u32 data;
575 u16 *tableaddr;
576
577 if (index >= RTL8366RB_NUM_VLANS ||
578 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
579 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
580 vlanmc->member > RTL8366RB_PORT_ALL ||
581 vlanmc->untag > RTL8366RB_PORT_ALL ||
582 vlanmc->fid > RTL8366RB_FIDMAX)
583 return -EINVAL;
584
585 vlanmc_priv.vid = vlanmc->vid;
586 vlanmc_priv.priority = vlanmc->priority;
587 vlanmc_priv.untag = vlanmc->untag;
588 vlanmc_priv.member = vlanmc->member;
589 vlanmc_priv.stag_mbr = 0;
590 vlanmc_priv.stag_idx = 0;
591 vlanmc_priv.fid = vlanmc->fid;
592
593 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
594
595 tableaddr = (u16 *)&vlanmc_priv;
596 data = *tableaddr;
597
598 err = rtl8366_smi_write_reg(smi, addr, data);
599 if (err)
600 return err;
601
602 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
603
604 tableaddr++;
605 data = *tableaddr;
606
607 err = rtl8366_smi_write_reg(smi, addr, data);
608 if (err)
609 return err;
610
611 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
612
613 tableaddr++;
614 data = *tableaddr;
615
616 err = rtl8366_smi_write_reg(smi, addr, data);
617 if (err)
618 return err;
619 return 0;
620 }
621
622 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
623 {
624 u32 data;
625 int err;
626
627 if (port >= RTL8366RB_NUM_PORTS)
628 return -EINVAL;
629
630 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
631 &data);
632 if (err)
633 return err;
634
635 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
636 RTL8366RB_PORT_VLAN_CTRL_MASK;
637
638 return 0;
639
640 }
641
642 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
643 {
644 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
645 return -EINVAL;
646
647 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
648 RTL8366RB_PORT_VLAN_CTRL_MASK <<
649 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
650 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
651 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
652 }
653
654 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
655 {
656 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
657 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
658 }
659
660 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
661 {
662 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
663 RTL8366RB_SGCR_EN_VLAN_4KTB,
664 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
665 }
666
667 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
668 const struct switch_attr *attr,
669 struct switch_val *val)
670 {
671 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
672 int err = 0;
673
674 if (val->value.i == 1)
675 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
676 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
677
678 return err;
679 }
680
681 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
682 const struct switch_attr *attr,
683 struct switch_val *val)
684 {
685 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
686 u32 data;
687
688 if (attr->ofs == 1) {
689 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
690
691 if (data & RTL8366RB_SGCR_EN_VLAN)
692 val->value.i = 1;
693 else
694 val->value.i = 0;
695 } else if (attr->ofs == 2) {
696 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
697
698 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
699 val->value.i = 1;
700 else
701 val->value.i = 0;
702 }
703
704 return 0;
705 }
706
707 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
708 const struct switch_attr *attr,
709 struct switch_val *val)
710 {
711 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
712 u32 data;
713
714 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
715
716 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
717
718 return 0;
719 }
720
721 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
722 const struct switch_attr *attr,
723 struct switch_val *val)
724 {
725 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
726
727 if (val->value.i >= 6)
728 return -EINVAL;
729
730 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
731 RTL8366RB_LED_BLINKRATE_MASK,
732 val->value.i);
733 }
734
735 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
736 const struct switch_attr *attr,
737 struct switch_val *val)
738 {
739 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
740
741 if (attr->ofs == 1)
742 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
743 else
744 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
745 }
746
747 static const char *rtl8366rb_speed_str(unsigned speed)
748 {
749 switch (speed) {
750 case 0:
751 return "10baseT";
752 case 1:
753 return "100baseT";
754 case 2:
755 return "1000baseT";
756 }
757
758 return "unknown";
759 }
760
761 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
762 const struct switch_attr *attr,
763 struct switch_val *val)
764 {
765 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
766 u32 len = 0, data = 0;
767
768 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
769 return -EINVAL;
770
771 memset(smi->buf, '\0', sizeof(smi->buf));
772 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
773 (val->port_vlan / 2), &data);
774
775 if (val->port_vlan % 2)
776 data = data >> 8;
777
778 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
779 len = snprintf(smi->buf, sizeof(smi->buf),
780 "port:%d link:up speed:%s %s-duplex %s%s%s",
781 val->port_vlan,
782 rtl8366rb_speed_str(data &
783 RTL8366RB_PORT_STATUS_SPEED_MASK),
784 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
785 "full" : "half",
786 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
787 "tx-pause ": "",
788 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
789 "rx-pause " : "",
790 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
791 "nway ": "");
792 } else {
793 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
794 val->port_vlan);
795 }
796
797 val->value.s = smi->buf;
798 val->len = len;
799
800 return 0;
801 }
802
803 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
804 const struct switch_attr *attr,
805 struct switch_val *val)
806 {
807 int i;
808 u32 len = 0;
809 struct rtl8366_vlan_4k vlan4k;
810 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
811 char *buf = smi->buf;
812 int err;
813
814 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
815 return -EINVAL;
816
817 memset(buf, '\0', sizeof(smi->buf));
818
819 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
820 if (err)
821 return err;
822
823 len += snprintf(buf + len, sizeof(smi->buf) - len,
824 "VLAN %d: Ports: '", vlan4k.vid);
825
826 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
827 if (!(vlan4k.member & (1 << i)))
828 continue;
829
830 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
831 (vlan4k.untag & (1 << i)) ? "" : "t");
832 }
833
834 len += snprintf(buf + len, sizeof(smi->buf) - len,
835 "', members=%04x, untag=%04x, fid=%u",
836 vlan4k.member, vlan4k.untag, vlan4k.fid);
837
838 val->value.s = buf;
839 val->len = len;
840
841 return 0;
842 }
843
844 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
845 const struct switch_attr *attr,
846 struct switch_val *val)
847 {
848 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
849 u32 data;
850 u32 mask;
851 u32 reg;
852
853 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
854 return -EINVAL;
855
856 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
857 reg = RTL8366RB_LED_BLINKRATE_REG;
858 mask = 0xF << 4;
859 data = val->value.i << 4;
860 } else {
861 reg = RTL8366RB_LED_CTRL_REG;
862 mask = 0xF << (val->port_vlan * 4),
863 data = val->value.i << (val->port_vlan * 4);
864 }
865
866 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
867 }
868
869 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
870 const struct switch_attr *attr,
871 struct switch_val *val)
872 {
873 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
874 u32 data = 0;
875
876 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
877 return -EINVAL;
878
879 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
880 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
881
882 return 0;
883 }
884
885 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
886 const struct switch_attr *attr,
887 struct switch_val *val)
888 {
889 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
890
891 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
892 return -EINVAL;
893
894 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
895 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
896 }
897
898 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
899 const struct switch_attr *attr,
900 struct switch_val *val)
901 {
902 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
903 int i, len = 0;
904 unsigned long long counter = 0;
905 char *buf = smi->buf;
906
907 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
908 return -EINVAL;
909
910 len += snprintf(buf + len, sizeof(smi->buf) - len,
911 "Port %d MIB counters\n",
912 val->port_vlan);
913
914 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
915 len += snprintf(buf + len, sizeof(smi->buf) - len,
916 "%-36s: ", rtl8366rb_mib_counters[i].name);
917 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
918 len += snprintf(buf + len, sizeof(smi->buf) - len,
919 "%llu\n", counter);
920 else
921 len += snprintf(buf + len, sizeof(smi->buf) - len,
922 "%s\n", "error");
923 }
924
925 val->value.s = buf;
926 val->len = len;
927 return 0;
928 }
929
930 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
931 struct switch_val *val)
932 {
933 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
934 struct switch_port *port;
935 struct rtl8366_vlan_4k vlan4k;
936 int i;
937
938 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
939 return -EINVAL;
940
941 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
942
943 port = &val->value.ports[0];
944 val->len = 0;
945 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
946 if (!(vlan4k.member & BIT(i)))
947 continue;
948
949 port->id = i;
950 port->flags = (vlan4k.untag & BIT(i)) ?
951 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
952 val->len++;
953 port++;
954 }
955 return 0;
956 }
957
958 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
959 struct switch_val *val)
960 {
961 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
962 struct switch_port *port;
963 u32 member = 0;
964 u32 untag = 0;
965 int i;
966
967 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
968 return -EINVAL;
969
970 port = &val->value.ports[0];
971 for (i = 0; i < val->len; i++, port++) {
972 member |= BIT(port->id);
973
974 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
975 untag |= BIT(port->id);
976 }
977
978 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
979 }
980
981 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
982 {
983 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
984 return rtl8366_get_pvid(smi, port, val);
985 }
986
987 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
988 {
989 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
990 return rtl8366_set_pvid(smi, port, val);
991 }
992
993 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
994 {
995 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
996 int err;
997
998 err = rtl8366rb_reset_chip(smi);
999 if (err)
1000 return err;
1001
1002 err = rtl8366rb_hw_init(smi);
1003 if (err)
1004 return err;
1005
1006 return rtl8366_reset_vlan(smi);
1007 }
1008
1009 static struct switch_attr rtl8366rb_globals[] = {
1010 {
1011 .type = SWITCH_TYPE_INT,
1012 .name = "enable_vlan",
1013 .description = "Enable VLAN mode",
1014 .set = rtl8366rb_sw_set_vlan_enable,
1015 .get = rtl8366rb_sw_get_vlan_enable,
1016 .max = 1,
1017 .ofs = 1
1018 }, {
1019 .type = SWITCH_TYPE_INT,
1020 .name = "enable_vlan4k",
1021 .description = "Enable VLAN 4K mode",
1022 .set = rtl8366rb_sw_set_vlan_enable,
1023 .get = rtl8366rb_sw_get_vlan_enable,
1024 .max = 1,
1025 .ofs = 2
1026 }, {
1027 .type = SWITCH_TYPE_INT,
1028 .name = "reset_mibs",
1029 .description = "Reset all MIB counters",
1030 .set = rtl8366rb_sw_reset_mibs,
1031 .get = NULL,
1032 .max = 1
1033 }, {
1034 .type = SWITCH_TYPE_INT,
1035 .name = "blinkrate",
1036 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1037 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1038 .set = rtl8366rb_sw_set_blinkrate,
1039 .get = rtl8366rb_sw_get_blinkrate,
1040 .max = 5
1041 },
1042 };
1043
1044 static struct switch_attr rtl8366rb_port[] = {
1045 {
1046 .type = SWITCH_TYPE_STRING,
1047 .name = "link",
1048 .description = "Get port link information",
1049 .max = 1,
1050 .set = NULL,
1051 .get = rtl8366rb_sw_get_port_link,
1052 }, {
1053 .type = SWITCH_TYPE_INT,
1054 .name = "reset_mib",
1055 .description = "Reset single port MIB counters",
1056 .max = 1,
1057 .set = rtl8366rb_sw_reset_port_mibs,
1058 .get = NULL,
1059 }, {
1060 .type = SWITCH_TYPE_STRING,
1061 .name = "mib",
1062 .description = "Get MIB counters for port",
1063 .max = 33,
1064 .set = NULL,
1065 .get = rtl8366rb_sw_get_port_mib,
1066 }, {
1067 .type = SWITCH_TYPE_INT,
1068 .name = "led",
1069 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1070 .max = 15,
1071 .set = rtl8366rb_sw_set_port_led,
1072 .get = rtl8366rb_sw_get_port_led,
1073 },
1074 };
1075
1076 static struct switch_attr rtl8366rb_vlan[] = {
1077 {
1078 .type = SWITCH_TYPE_STRING,
1079 .name = "info",
1080 .description = "Get vlan information",
1081 .max = 1,
1082 .set = NULL,
1083 .get = rtl8366rb_sw_get_vlan_info,
1084 },
1085 };
1086
1087 /* template */
1088 static struct switch_dev rtl8366_switch_dev = {
1089 .name = "RTL8366S",
1090 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1091 .ports = RTL8366RB_NUM_PORTS,
1092 .vlans = RTL8366RB_NUM_VLANS,
1093 .attr_global = {
1094 .attr = rtl8366rb_globals,
1095 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1096 },
1097 .attr_port = {
1098 .attr = rtl8366rb_port,
1099 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1100 },
1101 .attr_vlan = {
1102 .attr = rtl8366rb_vlan,
1103 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1104 },
1105
1106 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1107 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1108 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1109 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1110 .reset_switch = rtl8366rb_sw_reset_switch,
1111 };
1112
1113 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1114 {
1115 struct switch_dev *dev = &rtl->dev;
1116 int err;
1117
1118 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1119 dev->priv = rtl;
1120 dev->devname = dev_name(rtl->parent);
1121
1122 err = register_switch(dev, NULL);
1123 if (err)
1124 dev_err(rtl->parent, "switch registration failed\n");
1125
1126 return err;
1127 }
1128
1129 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1130 {
1131 unregister_switch(&rtl->dev);
1132 }
1133
1134 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1135 {
1136 struct rtl8366_smi *smi = bus->priv;
1137 u32 val = 0;
1138 int err;
1139
1140 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1141 if (err)
1142 return 0xffff;
1143
1144 return val;
1145 }
1146
1147 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1148 {
1149 struct rtl8366_smi *smi = bus->priv;
1150 u32 t;
1151 int err;
1152
1153 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1154 /* flush write */
1155 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1156
1157 return err;
1158 }
1159
1160 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1161 {
1162 return (bus->read == rtl8366rb_mii_read &&
1163 bus->write == rtl8366rb_mii_write);
1164 }
1165
1166 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1167 {
1168 struct rtl8366_smi *smi = &rtl->smi;
1169 int ret;
1170
1171 ret = rtl8366rb_reset_chip(smi);
1172 if (ret)
1173 return ret;
1174
1175 ret = rtl8366rb_hw_init(smi);
1176 return ret;
1177 }
1178
1179 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1180 {
1181 u32 chip_id = 0;
1182 u32 chip_ver = 0;
1183 int ret;
1184
1185 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1186 if (ret) {
1187 dev_err(smi->parent, "unable to read chip id\n");
1188 return ret;
1189 }
1190
1191 switch (chip_id) {
1192 case RTL8366RB_CHIP_ID_8366:
1193 break;
1194 default:
1195 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1196 return -ENODEV;
1197 }
1198
1199 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1200 &chip_ver);
1201 if (ret) {
1202 dev_err(smi->parent, "unable to read chip version\n");
1203 return ret;
1204 }
1205
1206 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1207 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1208
1209 return 0;
1210 }
1211
1212 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1213 .detect = rtl8366rb_detect,
1214 .mii_read = rtl8366rb_mii_read,
1215 .mii_write = rtl8366rb_mii_write,
1216
1217 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1218 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1219 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1220 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1221 .get_mc_index = rtl8366rb_get_mc_index,
1222 .set_mc_index = rtl8366rb_set_mc_index,
1223 .get_mib_counter = rtl8366rb_get_mib_counter,
1224 };
1225
1226 static int __init rtl8366rb_probe(struct platform_device *pdev)
1227 {
1228 static int rtl8366_smi_version_printed;
1229 struct rtl8366rb_platform_data *pdata;
1230 struct rtl8366rb *rtl;
1231 struct rtl8366_smi *smi;
1232 int err;
1233
1234 if (!rtl8366_smi_version_printed++)
1235 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1236 " version " RTL8366RB_DRIVER_VER"\n");
1237
1238 pdata = pdev->dev.platform_data;
1239 if (!pdata) {
1240 dev_err(&pdev->dev, "no platform data specified\n");
1241 err = -EINVAL;
1242 goto err_out;
1243 }
1244
1245 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1246 if (!rtl) {
1247 dev_err(&pdev->dev, "no memory for private data\n");
1248 err = -ENOMEM;
1249 goto err_out;
1250 }
1251
1252 rtl->parent = &pdev->dev;
1253
1254 smi = &rtl->smi;
1255 smi->parent = &pdev->dev;
1256 smi->gpio_sda = pdata->gpio_sda;
1257 smi->gpio_sck = pdata->gpio_sck;
1258 smi->ops = &rtl8366rb_smi_ops;
1259 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1260 smi->num_ports = RTL8366RB_NUM_PORTS;
1261 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1262 smi->mib_counters = rtl8366rb_mib_counters;
1263 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1264
1265 err = rtl8366_smi_init(smi);
1266 if (err)
1267 goto err_free_rtl;
1268
1269 platform_set_drvdata(pdev, rtl);
1270
1271 err = rtl8366rb_setup(rtl);
1272 if (err)
1273 goto err_clear_drvdata;
1274
1275 err = rtl8366rb_switch_init(rtl);
1276 if (err)
1277 goto err_clear_drvdata;
1278
1279 return 0;
1280
1281 err_clear_drvdata:
1282 platform_set_drvdata(pdev, NULL);
1283 rtl8366_smi_cleanup(smi);
1284 err_free_rtl:
1285 kfree(rtl);
1286 err_out:
1287 return err;
1288 }
1289
1290 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1291 {
1292 if (!rtl8366rb_mii_bus_match(phydev->bus))
1293 return -EINVAL;
1294
1295 return 0;
1296 }
1297
1298 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1299 {
1300 return 0;
1301 }
1302
1303 static struct phy_driver rtl8366rb_phy_driver = {
1304 .phy_id = 0x001cc960,
1305 .name = "Realtek RTL8366RB",
1306 .phy_id_mask = 0x1ffffff0,
1307 .features = PHY_GBIT_FEATURES,
1308 .config_aneg = rtl8366rb_phy_config_aneg,
1309 .config_init = rtl8366rb_phy_config_init,
1310 .read_status = genphy_read_status,
1311 .driver = {
1312 .owner = THIS_MODULE,
1313 },
1314 };
1315
1316 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1317 {
1318 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1319
1320 if (rtl) {
1321 rtl8366rb_switch_cleanup(rtl);
1322 platform_set_drvdata(pdev, NULL);
1323 rtl8366_smi_cleanup(&rtl->smi);
1324 kfree(rtl);
1325 }
1326
1327 return 0;
1328 }
1329
1330 static struct platform_driver rtl8366rb_driver = {
1331 .driver = {
1332 .name = RTL8366RB_DRIVER_NAME,
1333 .owner = THIS_MODULE,
1334 },
1335 .probe = rtl8366rb_probe,
1336 .remove = __devexit_p(rtl8366rb_remove),
1337 };
1338
1339 static int __init rtl8366rb_module_init(void)
1340 {
1341 int ret;
1342 ret = platform_driver_register(&rtl8366rb_driver);
1343 if (ret)
1344 return ret;
1345
1346 ret = phy_driver_register(&rtl8366rb_phy_driver);
1347 if (ret)
1348 goto err_platform_unregister;
1349
1350 return 0;
1351
1352 err_platform_unregister:
1353 platform_driver_unregister(&rtl8366rb_driver);
1354 return ret;
1355 }
1356 module_init(rtl8366rb_module_init);
1357
1358 static void __exit rtl8366rb_module_exit(void)
1359 {
1360 phy_driver_unregister(&rtl8366rb_phy_driver);
1361 platform_driver_unregister(&rtl8366rb_driver);
1362 }
1363 module_exit(rtl8366rb_module_exit);
1364
1365 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1366 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1367 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1368 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1369 MODULE_LICENSE("GPL v2");
1370 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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