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linux: rtl836x: add a reset_chip callback to rtl8366_smi_ops
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / rtl8367.c
1 /*
2 * Platform driver for the Realtek RTL8367R/M ethernet switches
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/skbuff.h>
17 #include <linux/rtl8367.h>
18
19 #include "rtl8366_smi.h"
20
21 #define RTL8367_RESET_DELAY 1000 /* msecs*/
22
23 #define RTL8367_PHY_ADDR_MAX 8
24 #define RTL8367_PHY_REG_MAX 31
25
26 #define RTL8367_VID_MASK 0xffff
27 #define RTL8367_FID_MASK 0xfff
28 #define RTL8367_UNTAG_MASK 0xffff
29 #define RTL8367_MEMBER_MASK 0xffff
30
31 #define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p))
32 #define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4
33 #define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3
34 #define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0
35 #define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1
36 #define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2
37 #define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3
38
39 #define RTL8367_BYPASS_LINE_RATE_REG 0x03f7
40
41 #define RTL8367_TA_CTRL_REG 0x0500
42 #define RTL8367_TA_CTRL_STATUS BIT(12)
43 #define RTL8367_TA_CTRL_METHOD BIT(5)
44 #define RTL8367_TA_CTRL_CMD_SHIFT 4
45 #define RTL8367_TA_CTRL_CMD_READ 0
46 #define RTL8367_TA_CTRL_CMD_WRITE 1
47 #define RTL8367_TA_CTRL_TABLE_SHIFT 0
48 #define RTL8367_TA_CTRL_TABLE_ACLRULE 1
49 #define RTL8367_TA_CTRL_TABLE_ACLACT 2
50 #define RTL8367_TA_CTRL_TABLE_CVLAN 3
51 #define RTL8367_TA_CTRL_TABLE_L2 4
52 #define RTL8367_TA_CTRL_CVLAN_READ \
53 ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \
54 RTL8367_TA_CTRL_TABLE_CVLAN)
55 #define RTL8367_TA_CTRL_CVLAN_WRITE \
56 ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \
57 RTL8367_TA_CTRL_TABLE_CVLAN)
58
59 #define RTL8367_TA_ADDR_REG 0x0501
60 #define RTL8367_TA_ADDR_MASK 0x3fff
61
62 #define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x))
63 #define RTL8367_TA_VLAN_DATA_SIZE 4
64 #define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK
65 #define RTL8367_TA_VLAN_MEMBER_SHIFT 0
66 #define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK
67 #define RTL8367_TA_VLAN_FID_SHIFT 0
68 #define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK
69 #define RTL8367_TA_VLAN_UNTAG1_SHIFT 14
70 #define RTL8367_TA_VLAN_UNTAG1_MASK 0x3
71 #define RTL8367_TA_VLAN_UNTAG2_SHIFT 0
72 #define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff
73
74 #define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2)
75 #define RTL8367_VLAN_PVID_CTRL_MASK 0x1f
76 #define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2))
77
78 #define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4)
79 #define RTL8367_VLAN_MC_DATA_SIZE 4
80 #define RTL8367_VLAN_MC_MEMBER_SHIFT 0
81 #define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK
82 #define RTL8367_VLAN_MC_FID_SHIFT 0
83 #define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK
84 #define RTL8367_VLAN_MC_EVID_SHIFT 0
85 #define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK
86
87 #define RTL8367_VLAN_CTRL_REG 0x07a8
88 #define RTL8367_VLAN_CTRL_ENABLE BIT(0)
89
90 #define RTL8367_VLAN_INGRESS_REG 0x07a9
91
92 #define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p))
93
94 #define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x))
95
96 #define RTL8367_MIB_ADDRESS_REG 0x1004
97
98 #define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x))
99 #define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11)
100 #define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10)
101 #define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p))
102 #define RTL8367_MIB_CTRL_RESET_MASK BIT(1)
103 #define RTL8367_MIB_CTRL_BUSY_MASK BIT(0)
104
105 #define RTL8367_MIB_COUNT 36
106 #define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050
107
108 #define RTL8367_SWC0_REG 0x1200
109 #define RTL8367_SWC0_MAX_LENGTH_SHIFT 13
110 #define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13)
111 #define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3)
112 #define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0)
113 #define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1)
114 #define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2)
115 #define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3)
116
117 #define RTL8367_CHIP_NUMBER_REG 0x1300
118
119 #define RTL8367_CHIP_VER_REG 0x1301
120 #define RTL8367_CHIP_VER_RLVID_SHIFT 12
121 #define RTL8367_CHIP_VER_RLVID_MASK 0xf
122 #define RTL8367_CHIP_VER_MCID_SHIFT 8
123 #define RTL8367_CHIP_VER_MCID_MASK 0xf
124 #define RTL8367_CHIP_VER_BOID_SHIFT 4
125 #define RTL8367_CHIP_VER_BOID_MASK 0xf
126
127 #define RTL8367_CHIP_MODE_REG 0x1302
128 #define RTL8367_CHIP_MODE_MASK 0x7
129
130 #define RTL8367_CHIP_DEBUG0_REG 0x1303
131 #define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
132
133 #define RTL8367_CHIP_DEBUG1_REG 0x1304
134
135 #define RTL8367_DIS_REG 0x1305
136 #define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
137 #define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x))
138 #define RTL8367_DIS_RGMII_MASK 0x7
139
140 #define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x))
141 #define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5
142 #define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff
143 #define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3
144 #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1
145 #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7
146
147 #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x))
148 #define RTL8367_DI_FORCE_MODE BIT(12)
149 #define RTL8367_DI_FORCE_NWAY BIT(7)
150 #define RTL8367_DI_FORCE_TXPAUSE BIT(6)
151 #define RTL8367_DI_FORCE_RXPAUSE BIT(5)
152 #define RTL8367_DI_FORCE_LINK BIT(4)
153 #define RTL8367_DI_FORCE_DUPLEX BIT(2)
154 #define RTL8367_DI_FORCE_SPEED_MASK 3
155 #define RTL8367_DI_FORCE_SPEED_10 0
156 #define RTL8367_DI_FORCE_SPEED_100 1
157 #define RTL8367_DI_FORCE_SPEED_1000 2
158
159 #define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x))
160
161 #define RTL8367_CHIP_RESET_REG 0x1322
162 #define RTL8367_CHIP_RESET_SW BIT(1)
163 #define RTL8367_CHIP_RESET_HW BIT(0)
164
165 #define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p))
166 #define RTL8367_PORT_STATUS_NWAY BIT(7)
167 #define RTL8367_PORT_STATUS_TXPAUSE BIT(6)
168 #define RTL8367_PORT_STATUS_RXPAUSE BIT(5)
169 #define RTL8367_PORT_STATUS_LINK BIT(4)
170 #define RTL8367_PORT_STATUS_DUPLEX BIT(2)
171 #define RTL8367_PORT_STATUS_SPEED_MASK 0x0003
172 #define RTL8367_PORT_STATUS_SPEED_10 0
173 #define RTL8367_PORT_STATUS_SPEED_100 1
174 #define RTL8367_PORT_STATUS_SPEED_1000 2
175
176 #define RTL8367_RTL_NO_REG 0x13c0
177 #define RTL8367_RTL_NO_8367R 0x3670
178 #define RTL8367_RTL_NO_8367M 0x3671
179
180 #define RTL8367_RTL_VER_REG 0x13c1
181 #define RTL8367_RTL_VER_MASK 0xf
182
183 #define RTL8367_RTL_MAGIC_ID_REG 0x13c2
184 #define RTL8367_RTL_MAGIC_ID_VAL 0x0249
185
186 #define RTL8367_LED_SYS_CONFIG_REG 0x1b00
187 #define RTL8367_LED_MODE_REG 0x1b02
188 #define RTL8367_LED_MODE_RATE_M 0x7
189 #define RTL8367_LED_MODE_RATE_S 1
190
191 #define RTL8367_LED_CONFIG_REG 0x1b03
192 #define RTL8367_LED_CONFIG_DATA_S 12
193 #define RTL8367_LED_CONFIG_DATA_M 0x3
194 #define RTL8367_LED_CONFIG_SEL BIT(14)
195 #define RTL8367_LED_CONFIG_LED_CFG_M 0xf
196
197 #define RTL8367_PARA_LED_IO_EN1_REG 0x1b24
198 #define RTL8367_PARA_LED_IO_EN2_REG 0x1b25
199 #define RTL8367_PARA_LED_IO_EN_PMASK 0xff
200
201 #define RTL8367_IA_CTRL_REG 0x1f00
202 #define RTL8367_IA_CTRL_RW(_x) ((_x) << 1)
203 #define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0)
204 #define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1)
205 #define RTL8367_IA_CTRL_CMD_MASK BIT(0)
206
207 #define RTL8367_IA_STATUS_REG 0x1f01
208 #define RTL8367_IA_STATUS_PHY_BUSY BIT(2)
209 #define RTL8367_IA_STATUS_SDS_BUSY BIT(1)
210 #define RTL8367_IA_STATUS_MDX_BUSY BIT(0)
211
212 #define RTL8367_IA_ADDRESS_REG 0x1f02
213
214 #define RTL8367_IA_WRITE_DATA_REG 0x1f03
215 #define RTL8367_IA_READ_DATA_REG 0x1f04
216
217 #define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
218
219 #define RTL8367_CPU_PORT_NUM 9
220 #define RTL8367_NUM_PORTS 10
221 #define RTL8367_NUM_VLANS 32
222 #define RTL8367_NUM_LEDGROUPS 4
223 #define RTL8367_NUM_VIDS 4096
224 #define RTL8367_PRIORITYMAX 7
225 #define RTL8367_FIDMAX 7
226
227 #define RTL8367_PORT_0 BIT(0)
228 #define RTL8367_PORT_1 BIT(1)
229 #define RTL8367_PORT_2 BIT(2)
230 #define RTL8367_PORT_3 BIT(3)
231 #define RTL8367_PORT_4 BIT(4)
232 #define RTL8367_PORT_5 BIT(5)
233 #define RTL8367_PORT_6 BIT(6)
234 #define RTL8367_PORT_7 BIT(7)
235 #define RTL8367_PORT_E1 BIT(8) /* external port 1 */
236 #define RTL8367_PORT_E0 BIT(9) /* external port 0 */
237
238 #define RTL8367_PORTS_ALL \
239 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
240 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
241 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \
242 RTL8367_PORT_E0)
243
244 #define RTL8367_PORTS_ALL_BUT_CPU \
245 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
246 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
247 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1)
248
249 struct rtl8367_initval {
250 u16 reg;
251 u16 val;
252 };
253
254 static struct rtl8366_mib_counter rtl8367_mib_counters[] = {
255 { 0, 0, 4, "IfInOctets" },
256 { 0, 4, 2, "Dot3StatsFCSErrors" },
257 { 0, 6, 2, "Dot3StatsSymbolErrors" },
258 { 0, 8, 2, "Dot3InPauseFrames" },
259 { 0, 10, 2, "Dot3ControlInUnknownOpcodes" },
260 { 0, 12, 2, "EtherStatsFragments" },
261 { 0, 14, 2, "EtherStatsJabbers" },
262 { 0, 16, 2, "IfInUcastPkts" },
263 { 0, 18, 2, "EtherStatsDropEvents" },
264 { 0, 20, 4, "EtherStatsOctets" },
265
266 { 0, 24, 2, "EtherStatsUnderSizePkts" },
267 { 0, 26, 2, "EtherOversizeStats" },
268 { 0, 28, 2, "EtherStatsPkts64Octets" },
269 { 0, 30, 2, "EtherStatsPkts65to127Octets" },
270 { 0, 32, 2, "EtherStatsPkts128to255Octets" },
271 { 0, 34, 2, "EtherStatsPkts256to511Octets" },
272 { 0, 36, 2, "EtherStatsPkts512to1023Octets" },
273 { 0, 38, 2, "EtherStatsPkts1024to1518Octets" },
274 { 0, 40, 2, "EtherStatsMulticastPkts" },
275 { 0, 42, 2, "EtherStatsBroadcastPkts" },
276
277 { 0, 44, 4, "IfOutOctets" },
278
279 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
280 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
281 { 0, 52, 2, "Dot3sDeferredTransmissions" },
282 { 0, 54, 2, "Dot3StatsLateCollisions" },
283 { 0, 56, 2, "EtherStatsCollisions" },
284 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
285 { 0, 60, 2, "Dot3OutPauseFrames" },
286 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
287 { 0, 64, 2, "Dot1dTpPortInDiscards" },
288 { 0, 66, 2, "IfOutUcastPkts" },
289 { 0, 68, 2, "IfOutMulticastPkts" },
290 { 0, 70, 2, "IfOutBroadcastPkts" },
291 { 0, 72, 2, "OutOampduPkts" },
292 { 0, 74, 2, "InOampduPkts" },
293 { 0, 76, 2, "PktgenPkts" },
294 };
295
296 #define REG_RD(_smi, _reg, _val) \
297 do { \
298 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
299 if (err) \
300 return err; \
301 } while (0)
302
303 #define REG_WR(_smi, _reg, _val) \
304 do { \
305 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
306 if (err) \
307 return err; \
308 } while (0)
309
310 #define REG_RMW(_smi, _reg, _mask, _val) \
311 do { \
312 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
313 if (err) \
314 return err; \
315 } while (0)
316
317 static const struct rtl8367_initval rtl8367_initvals_0_0[] = {
318 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
319 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
320 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
321 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
322 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
323 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
324 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
325 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
326 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
327 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
328 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
329 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
330 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
331 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
332 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
333 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
334 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
335 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
336 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
337 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
338 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
339 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
340 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8},
341 {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277},
342 {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277},
343 {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4},
344 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
345 {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8},
346 {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8},
347 {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b},
348 {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b},
349 {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b},
350 {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b},
351 {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000},
352 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
353 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
354 {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
355 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
356 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
357 {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940},
358 };
359
360 static const struct rtl8367_initval rtl8367_initvals_0_1[] = {
361 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
362 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
363 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
364 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
365 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
366 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
367 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
368 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
369 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
370 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
371 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
372 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
373 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
374 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
375 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
376 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
377 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
378 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
379 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
380 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
381 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
382 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
383 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0},
384 {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb},
385 {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb},
386 {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138},
387 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
388 {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0},
389 {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0},
390 {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190},
391 {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190},
392 {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190},
393 {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190},
394 {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000},
395 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
396 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
397 {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
398 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
399 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
400 {0x133f, 0x0010},
401 };
402
403 static const struct rtl8367_initval rtl8367_initvals_1_0[] = {
404 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
405 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
406 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
407 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
408 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
409 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
410 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
411 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
412 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
413 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
414 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
415 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
416 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
417 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
418 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
419 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
420 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
421 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
422 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
423 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
424 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
425 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
426 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
427 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
428 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
429 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
430 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
431 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
432 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
433 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
434 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
435 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
436 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
437 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
438 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
439 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
440 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
441 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
442 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
443 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
444 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
445 {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230},
446 {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230},
447 {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4},
448 {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8},
449 {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8},
450 {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8},
451 {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8},
452 {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000},
453 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000},
454 {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100},
455 {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040},
456 {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
457 {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340},
458 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940},
459 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
460 };
461
462 static const struct rtl8367_initval rtl8367_initvals_1_1[] = {
463 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
464 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
465 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
466 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
467 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
468 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
469 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
470 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
471 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
472 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
473 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
474 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
475 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
476 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
477 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
478 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
479 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
480 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
481 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
482 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
483 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
484 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
485 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
486 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
487 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
488 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
489 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
490 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
491 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
492 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
493 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
494 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
495 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
496 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
497 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
498 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
499 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
500 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
501 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
502 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
503 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
504 {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000},
505 {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000},
506 {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040},
507 {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040},
508 {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040},
509 {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000},
510 {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE},
511 {0x1B03, 0x0876},
512 };
513
514 static const struct rtl8367_initval rtl8367_initvals_2_0[] = {
515 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
516 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
517 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
518 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
519 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
520 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
521 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
522 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
523 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
524 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
525 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
526 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
527 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
528 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
529 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
530 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
531 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
532 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
533 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
534 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
535 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
536 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
537 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
538 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
539 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
540 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
541 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
542 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
543 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
544 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
545 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
546 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
547 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
548 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
549 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
550 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
551 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
552 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16},
553 {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244},
554 {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244},
555 {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0},
556 {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8},
557 {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8},
558 {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8},
559 {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8},
560 {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000},
561 {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00},
562 {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100},
563 {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040},
564 {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940},
565 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
566 };
567
568 static const struct rtl8367_initval rtl8367_initvals_2_1[] = {
569 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
570 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
571 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
572 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
573 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
574 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
575 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
576 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
577 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
578 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
579 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
580 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
581 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
582 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
583 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
584 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
585 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
586 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
587 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
588 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
589 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
590 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
591 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
592 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
593 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
594 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
595 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
596 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
597 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
598 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
599 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
600 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
601 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
602 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
603 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
604 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
605 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
606 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000},
607 {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210},
608 {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000},
609 {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040},
610 {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040},
611 {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
612 {0x130c, 0x0050},
613 };
614
615 static int rtl8367_write_initvals(struct rtl8366_smi *smi,
616 const struct rtl8367_initval *initvals,
617 int count)
618 {
619 int err;
620 int i;
621
622 for (i = 0; i < count; i++)
623 REG_WR(smi, initvals[i].reg, initvals[i].val);
624
625 return 0;
626 }
627
628 static int rtl8367_read_phy_reg(struct rtl8366_smi *smi,
629 u32 phy_addr, u32 phy_reg, u32 *val)
630 {
631 int timeout;
632 u32 data;
633 int err;
634
635 if (phy_addr > RTL8367_PHY_ADDR_MAX)
636 return -EINVAL;
637
638 if (phy_reg > RTL8367_PHY_REG_MAX)
639 return -EINVAL;
640
641 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
642 if (data & RTL8367_IA_STATUS_PHY_BUSY)
643 return -ETIMEDOUT;
644
645 /* prepare address */
646 REG_WR(smi, RTL8367_IA_ADDRESS_REG,
647 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));
648
649 /* send read command */
650 REG_WR(smi, RTL8367_IA_CTRL_REG,
651 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_READ);
652
653 timeout = 5;
654 do {
655 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
656 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
657 break;
658
659 if (timeout--) {
660 dev_err(smi->parent, "phy read timed out\n");
661 return -ETIMEDOUT;
662 }
663
664 udelay(1);
665 } while (1);
666
667 /* read data */
668 REG_RD(smi, RTL8367_IA_READ_DATA_REG, val);
669
670 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
671 phy_addr, phy_reg, *val);
672 return 0;
673 }
674
675 static int rtl8367_write_phy_reg(struct rtl8366_smi *smi,
676 u32 phy_addr, u32 phy_reg, u32 val)
677 {
678 int timeout;
679 u32 data;
680 int err;
681
682 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
683 phy_addr, phy_reg, val);
684
685 if (phy_addr > RTL8367_PHY_ADDR_MAX)
686 return -EINVAL;
687
688 if (phy_reg > RTL8367_PHY_REG_MAX)
689 return -EINVAL;
690
691 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
692 if (data & RTL8367_IA_STATUS_PHY_BUSY)
693 return -ETIMEDOUT;
694
695 /* preapre data */
696 REG_WR(smi, RTL8367_IA_WRITE_DATA_REG, val);
697
698 /* prepare address */
699 REG_WR(smi, RTL8367_IA_ADDRESS_REG,
700 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));
701
702 /* send write command */
703 REG_WR(smi, RTL8367_IA_CTRL_REG,
704 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_WRITE);
705
706 timeout = 5;
707 do {
708 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
709 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
710 break;
711
712 if (timeout--) {
713 dev_err(smi->parent, "phy write timed out\n");
714 return -ETIMEDOUT;
715 }
716
717 udelay(1);
718 } while (1);
719
720 return 0;
721 }
722
723 static int rtl8367_init_regs0(struct rtl8366_smi *smi, unsigned mode)
724 {
725 const struct rtl8367_initval *initvals;
726 int count;
727 int err;
728
729 switch (mode) {
730 case 0:
731 initvals = rtl8367_initvals_0_0;
732 count = ARRAY_SIZE(rtl8367_initvals_0_0);
733 break;
734
735 case 1:
736 case 2:
737 initvals = rtl8367_initvals_0_1;
738 count = ARRAY_SIZE(rtl8367_initvals_0_1);
739 break;
740
741 default:
742 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
743 return -ENODEV;
744 }
745
746 err = rtl8367_write_initvals(smi, initvals, count);
747 if (err)
748 return err;
749
750 /* TODO: complete this */
751
752 return 0;
753 }
754
755 static int rtl8367_init_regs1(struct rtl8366_smi *smi, unsigned mode)
756 {
757 const struct rtl8367_initval *initvals;
758 int count;
759
760 switch (mode) {
761 case 0:
762 initvals = rtl8367_initvals_1_0;
763 count = ARRAY_SIZE(rtl8367_initvals_1_0);
764 break;
765
766 case 1:
767 case 2:
768 initvals = rtl8367_initvals_1_1;
769 count = ARRAY_SIZE(rtl8367_initvals_1_1);
770 break;
771
772 default:
773 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
774 return -ENODEV;
775 }
776
777 return rtl8367_write_initvals(smi, initvals, count);
778 }
779
780 static int rtl8367_init_regs2(struct rtl8366_smi *smi, unsigned mode)
781 {
782 const struct rtl8367_initval *initvals;
783 int count;
784
785 switch (mode) {
786 case 0:
787 initvals = rtl8367_initvals_2_0;
788 count = ARRAY_SIZE(rtl8367_initvals_2_0);
789 break;
790
791 case 1:
792 case 2:
793 initvals = rtl8367_initvals_2_1;
794 count = ARRAY_SIZE(rtl8367_initvals_2_1);
795 break;
796
797 default:
798 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
799 return -ENODEV;
800 }
801
802 return rtl8367_write_initvals(smi, initvals, count);
803 }
804
805 static int rtl8367_init_regs(struct rtl8366_smi *smi)
806 {
807 u32 data;
808 u32 rlvid;
809 u32 mode;
810 int err;
811
812 REG_WR(smi, RTL8367_RTL_MAGIC_ID_REG, RTL8367_RTL_MAGIC_ID_VAL);
813
814 REG_RD(smi, RTL8367_CHIP_VER_REG, &data);
815 rlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) &
816 RTL8367_CHIP_VER_RLVID_MASK;
817
818 REG_RD(smi, RTL8367_CHIP_MODE_REG, &data);
819 mode = data & RTL8367_CHIP_MODE_MASK;
820
821 switch (rlvid) {
822 case 0:
823 err = rtl8367_init_regs0(smi, mode);
824 break;
825
826 case 1:
827 err = rtl8367_write_phy_reg(smi, 0, 31, 5);
828 if (err)
829 break;
830
831 err = rtl8367_write_phy_reg(smi, 0, 5, 0x3ffe);
832 if (err)
833 break;
834
835 err = rtl8367_read_phy_reg(smi, 0, 6, &data);
836 if (err)
837 break;
838
839 if (data == 0x94eb) {
840 err = rtl8367_init_regs1(smi, mode);
841 } else if (data == 0x2104) {
842 err = rtl8367_init_regs2(smi, mode);
843 } else {
844 dev_err(smi->parent, "unknow phy data %04x\n", data);
845 return -ENODEV;
846 }
847
848 break;
849
850 default:
851 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
852 err = -ENODEV;
853 break;
854 }
855
856 return err;
857 }
858
859 static int rtl8367_reset_chip(struct rtl8366_smi *smi)
860 {
861 int timeout = 10;
862 int err;
863 u32 data;
864
865 REG_WR(smi, RTL8367_CHIP_RESET_REG, RTL8367_CHIP_RESET_HW);
866 msleep(RTL8367_RESET_DELAY);
867
868 do {
869 REG_RD(smi, RTL8367_CHIP_RESET_REG, &data);
870 if (!(data & RTL8367_CHIP_RESET_HW))
871 break;
872
873 msleep(1);
874 } while (--timeout);
875
876 if (!timeout) {
877 dev_err(smi->parent, "chip reset timed out\n");
878 return -ETIMEDOUT;
879 }
880
881 return 0;
882 }
883
884 static int rtl8367_extif_set_mode(struct rtl8366_smi *smi, int id,
885 enum rtl8367_extif_mode mode)
886 {
887 int err;
888
889 /* set port mode */
890 switch (mode) {
891 case RTL8367_EXTIF_MODE_RGMII:
892 case RTL8367_EXTIF_MODE_RGMII_33V:
893 REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367);
894 REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777);
895 break;
896
897 case RTL8367_EXTIF_MODE_TMII_MAC:
898 case RTL8367_EXTIF_MODE_TMII_PHY:
899 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,
900 BIT((id + 1) % 2), BIT((id + 1) % 2));
901 break;
902
903 case RTL8367_EXTIF_MODE_GMII:
904 REG_RMW(smi, RTL8367_CHIP_DEBUG0_REG,
905 RTL8367_CHIP_DEBUG0_DUMMY0(id),
906 RTL8367_CHIP_DEBUG0_DUMMY0(id));
907 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), BIT(6));
908 break;
909
910 case RTL8367_EXTIF_MODE_MII_MAC:
911 case RTL8367_EXTIF_MODE_MII_PHY:
912 case RTL8367_EXTIF_MODE_DISABLED:
913 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,
914 BIT((id + 1) % 2), 0);
915 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), 0);
916 break;
917
918 default:
919 dev_err(smi->parent,
920 "invalid mode for external interface %d\n", id);
921 return -EINVAL;
922 }
923
924 REG_RMW(smi, RTL8367_DIS_REG,
925 RTL8367_DIS_RGMII_MASK << RTL8367_DIS_RGMII_SHIFT(id),
926 mode << RTL8367_DIS_RGMII_SHIFT(id));
927
928 return 0;
929 }
930
931 static int rtl8367_extif_set_force(struct rtl8366_smi *smi, int id,
932 struct rtl8367_port_ability *pa)
933 {
934 u32 mask;
935 u32 val;
936 int err;
937
938 mask = (RTL8367_DI_FORCE_MODE |
939 RTL8367_DI_FORCE_NWAY |
940 RTL8367_DI_FORCE_TXPAUSE |
941 RTL8367_DI_FORCE_RXPAUSE |
942 RTL8367_DI_FORCE_LINK |
943 RTL8367_DI_FORCE_DUPLEX |
944 RTL8367_DI_FORCE_SPEED_MASK);
945
946 val = pa->speed;
947 val |= pa->force_mode ? RTL8367_DI_FORCE_MODE : 0;
948 val |= pa->nway ? RTL8367_DI_FORCE_NWAY : 0;
949 val |= pa->txpause ? RTL8367_DI_FORCE_TXPAUSE : 0;
950 val |= pa->rxpause ? RTL8367_DI_FORCE_RXPAUSE : 0;
951 val |= pa->link ? RTL8367_DI_FORCE_LINK : 0;
952 val |= pa->duplex ? RTL8367_DI_FORCE_DUPLEX : 0;
953
954 REG_RMW(smi, RTL8367_DI_FORCE_REG(id), mask, val);
955
956 return 0;
957 }
958
959 static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
960 unsigned txdelay, unsigned rxdelay)
961 {
962 u32 mask;
963 u32 val;
964 int err;
965
966 mask = (RTL8367_EXT_RGMXF_RXDELAY_MASK |
967 (RTL8367_EXT_RGMXF_TXDELAY_MASK <<
968 RTL8367_EXT_RGMXF_TXDELAY_SHIFT));
969
970 val = rxdelay;
971 val |= txdelay << RTL8367_EXT_RGMXF_TXDELAY_SHIFT;
972
973 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), mask, val);
974
975 return 0;
976 }
977
978 static int rtl8367_extif_init(struct rtl8366_smi *smi, int id,
979 struct rtl8367_extif_config *cfg)
980 {
981 enum rtl8367_extif_mode mode;
982 int err;
983
984 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
985
986 err = rtl8367_extif_set_mode(smi, id, mode);
987 if (err)
988 return err;
989
990 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
991 err = rtl8367_extif_set_force(smi, id, &cfg->ability);
992 if (err)
993 return err;
994
995 err = rtl8367_extif_set_rgmii_delay(smi, id, cfg->txdelay,
996 cfg->rxdelay);
997 if (err)
998 return err;
999 }
1000
1001 return 0;
1002 }
1003
1004 static int rtl8367_led_group_set_ports(struct rtl8366_smi *smi,
1005 unsigned int group, u16 port_mask)
1006 {
1007 u32 reg;
1008 u32 s;
1009 int err;
1010
1011 port_mask &= RTL8367_PARA_LED_IO_EN_PMASK;
1012 s = (group % 2) * 8;
1013 reg = RTL8367_PARA_LED_IO_EN1_REG + (group / 2);
1014
1015 REG_RMW(smi, reg, (RTL8367_PARA_LED_IO_EN_PMASK << s), port_mask << s);
1016
1017 return 0;
1018 }
1019
1020 static int rtl8367_led_group_set_mode(struct rtl8366_smi *smi,
1021 unsigned int mode)
1022 {
1023 u16 mask;
1024 u16 set;
1025 int err;
1026
1027 mode &= RTL8367_LED_CONFIG_DATA_M;
1028
1029 mask = (RTL8367_LED_CONFIG_DATA_M << RTL8367_LED_CONFIG_DATA_S) |
1030 RTL8367_LED_CONFIG_SEL;
1031 set = (mode << RTL8367_LED_CONFIG_DATA_S) | RTL8367_LED_CONFIG_SEL;
1032
1033 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);
1034
1035 return 0;
1036 }
1037
1038 static int rtl8367_led_group_set_config(struct rtl8366_smi *smi,
1039 unsigned int led, unsigned int cfg)
1040 {
1041 u16 mask;
1042 u16 set;
1043 int err;
1044
1045 mask = (RTL8367_LED_CONFIG_LED_CFG_M << (led * 4)) |
1046 RTL8367_LED_CONFIG_SEL;
1047 set = (cfg & RTL8367_LED_CONFIG_LED_CFG_M) << (led * 4);
1048
1049 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);
1050 return 0;
1051 }
1052
1053 static int rtl8367_led_op_select_parallel(struct rtl8366_smi *smi)
1054 {
1055 int err;
1056
1057 REG_WR(smi, RTL8367_LED_SYS_CONFIG_REG, 0x1472);
1058 return 0;
1059 }
1060
1061 static int rtl8367_led_blinkrate_set(struct rtl8366_smi *smi, unsigned int rate)
1062 {
1063 u16 mask;
1064 u16 set;
1065 int err;
1066
1067 mask = RTL8367_LED_MODE_RATE_M << RTL8367_LED_MODE_RATE_S;
1068 set = (rate & RTL8367_LED_MODE_RATE_M) << RTL8367_LED_MODE_RATE_S;
1069 REG_RMW(smi, RTL8367_LED_MODE_REG, mask, set);
1070
1071 return 0;
1072 }
1073
1074 static int rtl8367_hw_init(struct rtl8366_smi *smi)
1075 {
1076 struct rtl8367_platform_data *pdata;
1077 int err;
1078 int i;
1079
1080 pdata = smi->parent->platform_data;
1081
1082 err = rtl8367_init_regs(smi);
1083 if (err)
1084 return err;
1085
1086 /* initialize external interfaces */
1087 err = rtl8367_extif_init(smi, 0, pdata->extif0_cfg);
1088 if (err)
1089 return err;
1090
1091 err = rtl8367_extif_init(smi, 1, pdata->extif1_cfg);
1092 if (err)
1093 return err;
1094
1095 /* set maximum packet length to 1536 bytes */
1096 REG_RMW(smi, RTL8367_SWC0_REG, RTL8367_SWC0_MAX_LENGTH_MASK,
1097 RTL8367_SWC0_MAX_LENGTH_1536);
1098
1099 /*
1100 * discard VLAN tagged packets if the port is not a member of
1101 * the VLAN with which the packets is associated.
1102 */
1103 REG_WR(smi, RTL8367_VLAN_INGRESS_REG, RTL8367_PORTS_ALL);
1104
1105 /*
1106 * Setup egress tag mode for each port.
1107 */
1108 for (i = 0; i < RTL8367_NUM_PORTS; i++)
1109 REG_RMW(smi,
1110 RTL8367_PORT_CFG_REG(i),
1111 RTL8367_PORT_CFG_EGRESS_MODE_MASK <<
1112 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT,
1113 RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL <<
1114 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT);
1115
1116 /* setup LEDs */
1117 err = rtl8367_led_group_set_ports(smi, 0, RTL8367_PORTS_ALL);
1118 if (err)
1119 return err;
1120
1121 err = rtl8367_led_group_set_mode(smi, 0);
1122 if (err)
1123 return err;
1124
1125 err = rtl8367_led_op_select_parallel(smi);
1126 if (err)
1127 return err;
1128
1129 err = rtl8367_led_blinkrate_set(smi, 1);
1130 if (err)
1131 return err;
1132
1133 err = rtl8367_led_group_set_config(smi, 0, 2);
1134 if (err)
1135 return err;
1136
1137 return 0;
1138 }
1139
1140 static int rtl8367_get_mib_counter(struct rtl8366_smi *smi, int counter,
1141 int port, unsigned long long *val)
1142 {
1143 struct rtl8366_mib_counter *mib;
1144 int offset;
1145 int i;
1146 int err;
1147 u32 addr, data;
1148 u64 mibvalue;
1149
1150 if (port > RTL8367_NUM_PORTS || counter >= RTL8367_MIB_COUNT)
1151 return -EINVAL;
1152
1153 mib = &rtl8367_mib_counters[counter];
1154 addr = RTL8367_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
1155
1156 /*
1157 * Writing access counter address first
1158 * then ASIC will prepare 64bits counter wait for being retrived
1159 */
1160 REG_WR(smi, RTL8367_MIB_ADDRESS_REG, addr >> 2);
1161
1162 /* read MIB control register */
1163 REG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data);
1164
1165 if (data & RTL8367_MIB_CTRL_BUSY_MASK)
1166 return -EBUSY;
1167
1168 if (data & RTL8367_MIB_CTRL_RESET_MASK)
1169 return -EIO;
1170
1171 if (mib->length == 4)
1172 offset = 3;
1173 else
1174 offset = (mib->offset + 1) % 4;
1175
1176 mibvalue = 0;
1177 for (i = 0; i < mib->length; i++) {
1178 REG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data);
1179 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1180 }
1181
1182 *val = mibvalue;
1183 return 0;
1184 }
1185
1186 static int rtl8367_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1187 struct rtl8366_vlan_4k *vlan4k)
1188 {
1189 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1190 int err;
1191 int i;
1192
1193 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1194
1195 if (vid >= RTL8367_NUM_VIDS)
1196 return -EINVAL;
1197
1198 /* write VID */
1199 REG_WR(smi, RTL8367_TA_ADDR_REG, vid);
1200
1201 /* write table access control word */
1202 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_READ);
1203
1204 for (i = 0; i < ARRAY_SIZE(data); i++)
1205 REG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]);
1206
1207 vlan4k->vid = vid;
1208 vlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) &
1209 RTL8367_TA_VLAN_MEMBER_MASK;
1210 vlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) &
1211 RTL8367_TA_VLAN_FID_MASK;
1212 vlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) &
1213 RTL8367_TA_VLAN_UNTAG1_MASK;
1214 vlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) &
1215 RTL8367_TA_VLAN_UNTAG2_MASK) << 2;
1216
1217 return 0;
1218 }
1219
1220 static int rtl8367_set_vlan_4k(struct rtl8366_smi *smi,
1221 const struct rtl8366_vlan_4k *vlan4k)
1222 {
1223 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1224 int err;
1225 int i;
1226
1227 if (vlan4k->vid >= RTL8367_NUM_VIDS ||
1228 vlan4k->member > RTL8367_TA_VLAN_MEMBER_MASK ||
1229 vlan4k->untag > RTL8367_UNTAG_MASK ||
1230 vlan4k->fid > RTL8367_FIDMAX)
1231 return -EINVAL;
1232
1233 data[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) <<
1234 RTL8367_TA_VLAN_MEMBER_SHIFT;
1235 data[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) <<
1236 RTL8367_TA_VLAN_FID_SHIFT;
1237 data[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) <<
1238 RTL8367_TA_VLAN_UNTAG1_SHIFT;
1239 data[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) <<
1240 RTL8367_TA_VLAN_UNTAG2_SHIFT;
1241
1242 for (i = 0; i < ARRAY_SIZE(data); i++)
1243 REG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]);
1244
1245 /* write VID */
1246 REG_WR(smi, RTL8367_TA_ADDR_REG,
1247 vlan4k->vid & RTL8367_TA_VLAN_VID_MASK);
1248
1249 /* write table access control word */
1250 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_WRITE);
1251
1252 return 0;
1253 }
1254
1255 static int rtl8367_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1256 struct rtl8366_vlan_mc *vlanmc)
1257 {
1258 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1259 int err;
1260 int i;
1261
1262 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1263
1264 if (index >= RTL8367_NUM_VLANS)
1265 return -EINVAL;
1266
1267 for (i = 0; i < ARRAY_SIZE(data); i++)
1268 REG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]);
1269
1270 vlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) &
1271 RTL8367_VLAN_MC_MEMBER_MASK;
1272 vlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) &
1273 RTL8367_VLAN_MC_FID_MASK;
1274 vlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) &
1275 RTL8367_VLAN_MC_EVID_MASK;
1276
1277 return 0;
1278 }
1279
1280 static int rtl8367_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1281 const struct rtl8366_vlan_mc *vlanmc)
1282 {
1283 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1284 int err;
1285 int i;
1286
1287 if (index >= RTL8367_NUM_VLANS ||
1288 vlanmc->vid >= RTL8367_NUM_VIDS ||
1289 vlanmc->priority > RTL8367_PRIORITYMAX ||
1290 vlanmc->member > RTL8367_VLAN_MC_MEMBER_MASK ||
1291 vlanmc->untag > RTL8367_UNTAG_MASK ||
1292 vlanmc->fid > RTL8367_FIDMAX)
1293 return -EINVAL;
1294
1295 data[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) <<
1296 RTL8367_VLAN_MC_MEMBER_SHIFT;
1297 data[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) <<
1298 RTL8367_VLAN_MC_FID_SHIFT;
1299 data[2] = 0;
1300 data[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) <<
1301 RTL8367_VLAN_MC_EVID_SHIFT;
1302
1303 for (i = 0; i < ARRAY_SIZE(data); i++)
1304 REG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]);
1305
1306 return 0;
1307 }
1308
1309 static int rtl8367_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1310 {
1311 u32 data;
1312 int err;
1313
1314 if (port >= RTL8367_NUM_PORTS)
1315 return -EINVAL;
1316
1317 REG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data);
1318
1319 *val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) &
1320 RTL8367_VLAN_PVID_CTRL_MASK;
1321
1322 return 0;
1323 }
1324
1325 static int rtl8367_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1326 {
1327 if (port >= RTL8367_NUM_PORTS || index >= RTL8367_NUM_VLANS)
1328 return -EINVAL;
1329
1330 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_PVID_CTRL_REG(port),
1331 RTL8367_VLAN_PVID_CTRL_MASK <<
1332 RTL8367_VLAN_PVID_CTRL_SHIFT(port),
1333 (index & RTL8367_VLAN_PVID_CTRL_MASK) <<
1334 RTL8367_VLAN_PVID_CTRL_SHIFT(port));
1335 }
1336
1337 static int rtl8367_enable_vlan(struct rtl8366_smi *smi, int enable)
1338 {
1339 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_CTRL_REG,
1340 RTL8367_VLAN_CTRL_ENABLE,
1341 (enable) ? RTL8367_VLAN_CTRL_ENABLE : 0);
1342 }
1343
1344 static int rtl8367_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1345 {
1346 return 0;
1347 }
1348
1349 static int rtl8367_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1350 {
1351 unsigned max = RTL8367_NUM_VLANS;
1352
1353 if (vlan == 0 || vlan >= max)
1354 return 0;
1355
1356 return 1;
1357 }
1358
1359 static int rtl8367_enable_port(struct rtl8366_smi *smi, int port, int enable)
1360 {
1361 int err;
1362
1363 REG_WR(smi, RTL8367_PORT_ISOLATION_REG(port),
1364 (enable) ? RTL8367_PORTS_ALL : 0);
1365
1366 return 0;
1367 }
1368
1369 static int rtl8367_sw_reset_mibs(struct switch_dev *dev,
1370 const struct switch_attr *attr,
1371 struct switch_val *val)
1372 {
1373 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1374
1375 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(0), 0,
1376 RTL8367_MIB_CTRL_GLOBAL_RESET_MASK);
1377 }
1378
1379 static int rtl8367_sw_get_port_link(struct switch_dev *dev,
1380 int port,
1381 struct switch_port_link *link)
1382 {
1383 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1384 u32 data = 0;
1385 u32 speed;
1386
1387 if (port >= RTL8367_NUM_PORTS)
1388 return -EINVAL;
1389
1390 rtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data);
1391
1392 link->link = !!(data & RTL8367_PORT_STATUS_LINK);
1393 if (!link->link)
1394 return 0;
1395
1396 link->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX);
1397 link->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE);
1398 link->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE);
1399 link->aneg = !!(data & RTL8367_PORT_STATUS_NWAY);
1400
1401 speed = (data & RTL8367_PORT_STATUS_SPEED_MASK);
1402 switch (speed) {
1403 case 0:
1404 link->speed = SWITCH_PORT_SPEED_10;
1405 break;
1406 case 1:
1407 link->speed = SWITCH_PORT_SPEED_100;
1408 break;
1409 case 2:
1410 link->speed = SWITCH_PORT_SPEED_1000;
1411 break;
1412 default:
1413 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1414 break;
1415 }
1416
1417 return 0;
1418 }
1419
1420 static int rtl8367_sw_get_max_length(struct switch_dev *dev,
1421 const struct switch_attr *attr,
1422 struct switch_val *val)
1423 {
1424 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1425 u32 data;
1426
1427 rtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data);
1428 val->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >>
1429 RTL8367_SWC0_MAX_LENGTH_SHIFT;
1430
1431 return 0;
1432 }
1433
1434 static int rtl8367_sw_set_max_length(struct switch_dev *dev,
1435 const struct switch_attr *attr,
1436 struct switch_val *val)
1437 {
1438 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1439 u32 max_len;
1440
1441 switch (val->value.i) {
1442 case 0:
1443 max_len = RTL8367_SWC0_MAX_LENGTH_1522;
1444 break;
1445 case 1:
1446 max_len = RTL8367_SWC0_MAX_LENGTH_1536;
1447 break;
1448 case 2:
1449 max_len = RTL8367_SWC0_MAX_LENGTH_1552;
1450 break;
1451 case 3:
1452 max_len = RTL8367_SWC0_MAX_LENGTH_16000;
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 return rtl8366_smi_rmwr(smi, RTL8367_SWC0_REG,
1459 RTL8367_SWC0_MAX_LENGTH_MASK, max_len);
1460 }
1461
1462
1463 static int rtl8367_sw_reset_port_mibs(struct switch_dev *dev,
1464 const struct switch_attr *attr,
1465 struct switch_val *val)
1466 {
1467 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1468 int port;
1469
1470 port = val->port_vlan;
1471 if (port >= RTL8367_NUM_PORTS)
1472 return -EINVAL;
1473
1474 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(port / 8), 0,
1475 RTL8367_MIB_CTRL_PORT_RESET_MASK(port % 8));
1476 }
1477
1478 static int rtl8367_sw_reset_switch(struct switch_dev *dev)
1479 {
1480 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1481 int err;
1482
1483 err = rtl8367_reset_chip(smi);
1484 if (err)
1485 return err;
1486
1487
1488 err = rtl8367_hw_init(smi);
1489 if (err)
1490 return err;
1491
1492 err = rtl8366_reset_vlan(smi);
1493 if (err)
1494 return err;
1495
1496 err = rtl8366_enable_vlan(smi, 1);
1497 if (err)
1498 return err;
1499
1500 return rtl8366_enable_all_ports(smi, 1);
1501 }
1502
1503 static struct switch_attr rtl8367_globals[] = {
1504 {
1505 .type = SWITCH_TYPE_INT,
1506 .name = "enable_vlan",
1507 .description = "Enable VLAN mode",
1508 .set = rtl8366_sw_set_vlan_enable,
1509 .get = rtl8366_sw_get_vlan_enable,
1510 .max = 1,
1511 .ofs = 1
1512 }, {
1513 .type = SWITCH_TYPE_INT,
1514 .name = "enable_vlan4k",
1515 .description = "Enable VLAN 4K mode",
1516 .set = rtl8366_sw_set_vlan_enable,
1517 .get = rtl8366_sw_get_vlan_enable,
1518 .max = 1,
1519 .ofs = 2
1520 }, {
1521 .type = SWITCH_TYPE_NOVAL,
1522 .name = "reset_mibs",
1523 .description = "Reset all MIB counters",
1524 .set = rtl8367_sw_reset_mibs,
1525 }, {
1526 .type = SWITCH_TYPE_INT,
1527 .name = "max_length",
1528 .description = "Get/Set the maximum length of valid packets"
1529 "(0:1522, 1:1536, 2:1552, 3:16000)",
1530 .set = rtl8367_sw_set_max_length,
1531 .get = rtl8367_sw_get_max_length,
1532 .max = 3,
1533 }
1534 };
1535
1536 static struct switch_attr rtl8367_port[] = {
1537 {
1538 .type = SWITCH_TYPE_NOVAL,
1539 .name = "reset_mib",
1540 .description = "Reset single port MIB counters",
1541 .set = rtl8367_sw_reset_port_mibs,
1542 }, {
1543 .type = SWITCH_TYPE_STRING,
1544 .name = "mib",
1545 .description = "Get MIB counters for port",
1546 .max = 33,
1547 .set = NULL,
1548 .get = rtl8366_sw_get_port_mib,
1549 },
1550 };
1551
1552 static struct switch_attr rtl8367_vlan[] = {
1553 {
1554 .type = SWITCH_TYPE_STRING,
1555 .name = "info",
1556 .description = "Get vlan information",
1557 .max = 1,
1558 .set = NULL,
1559 .get = rtl8366_sw_get_vlan_info,
1560 },
1561 };
1562
1563 static const struct switch_dev_ops rtl8366m_ops = {
1564 .attr_global = {
1565 .attr = rtl8367_globals,
1566 .n_attr = ARRAY_SIZE(rtl8367_globals),
1567 },
1568 .attr_port = {
1569 .attr = rtl8367_port,
1570 .n_attr = ARRAY_SIZE(rtl8367_port),
1571 },
1572 .attr_vlan = {
1573 .attr = rtl8367_vlan,
1574 .n_attr = ARRAY_SIZE(rtl8367_vlan),
1575 },
1576
1577 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1578 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1579 .get_port_pvid = rtl8366_sw_get_port_pvid,
1580 .set_port_pvid = rtl8366_sw_set_port_pvid,
1581 .reset_switch = rtl8367_sw_reset_switch,
1582 .get_port_link = rtl8367_sw_get_port_link,
1583 };
1584
1585 static int rtl8367_switch_init(struct rtl8366_smi *smi)
1586 {
1587 struct switch_dev *dev = &smi->sw_dev;
1588 int err;
1589
1590 dev->name = "RTL8367";
1591 dev->cpu_port = RTL8367_CPU_PORT_NUM;
1592 dev->ports = RTL8367_NUM_PORTS;
1593 dev->vlans = RTL8367_NUM_VIDS;
1594 dev->ops = &rtl8366m_ops;
1595 dev->alias = dev_name(smi->parent);
1596
1597 err = register_switch(dev, NULL);
1598 if (err)
1599 dev_err(smi->parent, "switch registration failed\n");
1600
1601 return err;
1602 }
1603
1604 static void rtl8367_switch_cleanup(struct rtl8366_smi *smi)
1605 {
1606 unregister_switch(&smi->sw_dev);
1607 }
1608
1609 static int rtl8367_mii_read(struct mii_bus *bus, int addr, int reg)
1610 {
1611 struct rtl8366_smi *smi = bus->priv;
1612 u32 val = 0;
1613 int err;
1614
1615 err = rtl8367_read_phy_reg(smi, addr, reg, &val);
1616 if (err)
1617 return 0xffff;
1618
1619 return val;
1620 }
1621
1622 static int rtl8367_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1623 {
1624 struct rtl8366_smi *smi = bus->priv;
1625 u32 t;
1626 int err;
1627
1628 err = rtl8367_write_phy_reg(smi, addr, reg, val);
1629 if (err)
1630 return err;
1631
1632 /* flush write */
1633 (void) rtl8367_read_phy_reg(smi, addr, reg, &t);
1634
1635 return err;
1636 }
1637
1638 static int rtl8367_setup(struct rtl8366_smi *smi)
1639 {
1640 return rtl8367_hw_init(smi);
1641 }
1642
1643 static int rtl8367_detect(struct rtl8366_smi *smi)
1644 {
1645 u32 rtl_no = 0;
1646 u32 rtl_ver = 0;
1647 char *chip_name;
1648 int ret;
1649
1650 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_NO_REG, &rtl_no);
1651 if (ret) {
1652 dev_err(smi->parent, "unable to read chip number\n");
1653 return ret;
1654 }
1655
1656 switch (rtl_no) {
1657 case RTL8367_RTL_NO_8367R:
1658 chip_name = "8367R";
1659 break;
1660 case RTL8367_RTL_NO_8367M:
1661 chip_name = "8367M";
1662 break;
1663 default:
1664 dev_err(smi->parent, "unknown chip number (%04x)\n", rtl_no);
1665 return -ENODEV;
1666 }
1667
1668 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_VER_REG, &rtl_ver);
1669 if (ret) {
1670 dev_err(smi->parent, "unable to read chip version\n");
1671 return ret;
1672 }
1673
1674 dev_info(smi->parent, "RTL%s ver. %u chip found\n",
1675 chip_name, rtl_ver & RTL8367_RTL_VER_MASK);
1676
1677 return 0;
1678 }
1679
1680 static struct rtl8366_smi_ops rtl8367_smi_ops = {
1681 .detect = rtl8367_detect,
1682 .reset_chip = rtl8367_reset_chip,
1683 .setup = rtl8367_setup,
1684
1685 .mii_read = rtl8367_mii_read,
1686 .mii_write = rtl8367_mii_write,
1687
1688 .get_vlan_mc = rtl8367_get_vlan_mc,
1689 .set_vlan_mc = rtl8367_set_vlan_mc,
1690 .get_vlan_4k = rtl8367_get_vlan_4k,
1691 .set_vlan_4k = rtl8367_set_vlan_4k,
1692 .get_mc_index = rtl8367_get_mc_index,
1693 .set_mc_index = rtl8367_set_mc_index,
1694 .get_mib_counter = rtl8367_get_mib_counter,
1695 .is_vlan_valid = rtl8367_is_vlan_valid,
1696 .enable_vlan = rtl8367_enable_vlan,
1697 .enable_vlan4k = rtl8367_enable_vlan4k,
1698 .enable_port = rtl8367_enable_port,
1699 };
1700
1701 static int __devinit rtl8367_probe(struct platform_device *pdev)
1702 {
1703 struct rtl8367_platform_data *pdata;
1704 struct rtl8366_smi *smi;
1705 int err;
1706
1707 pdata = pdev->dev.platform_data;
1708 if (!pdata) {
1709 dev_err(&pdev->dev, "no platform data specified\n");
1710 err = -EINVAL;
1711 goto err_out;
1712 }
1713
1714 smi = rtl8366_smi_alloc(&pdev->dev);
1715 if (!smi) {
1716 err = -ENOMEM;
1717 goto err_out;
1718 }
1719
1720 smi->gpio_sda = pdata->gpio_sda;
1721 smi->gpio_sck = pdata->gpio_sck;
1722 smi->clk_delay = 1500;
1723 smi->cmd_read = 0xb9;
1724 smi->cmd_write = 0xb8;
1725 smi->ops = &rtl8367_smi_ops;
1726 smi->cpu_port = RTL8367_CPU_PORT_NUM;
1727 smi->num_ports = RTL8367_NUM_PORTS;
1728 smi->num_vlan_mc = RTL8367_NUM_VLANS;
1729 smi->mib_counters = rtl8367_mib_counters;
1730 smi->num_mib_counters = ARRAY_SIZE(rtl8367_mib_counters);
1731
1732 err = rtl8366_smi_init(smi);
1733 if (err)
1734 goto err_free_smi;
1735
1736 platform_set_drvdata(pdev, smi);
1737
1738 err = rtl8367_switch_init(smi);
1739 if (err)
1740 goto err_clear_drvdata;
1741
1742 return 0;
1743
1744 err_clear_drvdata:
1745 platform_set_drvdata(pdev, NULL);
1746 rtl8366_smi_cleanup(smi);
1747 err_free_smi:
1748 kfree(smi);
1749 err_out:
1750 return err;
1751 }
1752
1753 static int __devexit rtl8367_remove(struct platform_device *pdev)
1754 {
1755 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1756
1757 if (smi) {
1758 rtl8367_switch_cleanup(smi);
1759 platform_set_drvdata(pdev, NULL);
1760 rtl8366_smi_cleanup(smi);
1761 kfree(smi);
1762 }
1763
1764 return 0;
1765 }
1766
1767 static void rtl8367_shutdown(struct platform_device *pdev)
1768 {
1769 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1770
1771 if (smi)
1772 rtl8367_reset_chip(smi);
1773 }
1774
1775 static struct platform_driver rtl8367_driver = {
1776 .driver = {
1777 .name = RTL8367_DRIVER_NAME,
1778 .owner = THIS_MODULE,
1779 },
1780 .probe = rtl8367_probe,
1781 .remove = __devexit_p(rtl8367_remove),
1782 .shutdown = rtl8367_shutdown,
1783 };
1784
1785 static int __init rtl8367_module_init(void)
1786 {
1787 return platform_driver_register(&rtl8367_driver);
1788 }
1789 module_init(rtl8367_module_init);
1790
1791 static void __exit rtl8367_module_exit(void)
1792 {
1793 platform_driver_unregister(&rtl8367_driver);
1794 }
1795 module_exit(rtl8367_module_exit);
1796
1797 MODULE_DESCRIPTION(RTL8367_DRIVER_DESC);
1798 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1799 MODULE_LICENSE("GPL v2");
1800 MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME);
Staging tree of Christian Lamparter