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generic: fold yaffs_git_2010_10_20 patch to generic/files
[openwrt/staging/chunkeey.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/bcma/Kconfig
32 +++ b/drivers/bcma/Kconfig
33 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
34
35 config BCMA_DRIVER_PCI_HOSTMODE
36 bool "Driver for PCI core working in hostmode"
37 - depends on BCMA && MIPS
38 + depends on BCMA && MIPS && BCMA_HOST_PCI
39 help
40 PCI core hostmode operation (external PCI bus).
41
42 @@ -46,6 +46,25 @@ config BCMA_DRIVER_MIPS
43
44 If unsure, say N
45
46 +config BCMA_SFLASH
47 + bool
48 + depends on BCMA_DRIVER_MIPS
49 + default y
50 +
51 +config BCMA_NFLASH
52 + bool
53 + depends on BCMA_DRIVER_MIPS
54 + default y
55 +
56 +config BCMA_DRIVER_GMAC_CMN
57 + bool "BCMA Broadcom GBIT MAC COMMON core driver"
58 + depends on BCMA
59 + help
60 + Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
61 + specific Advanced Microcontroller Bus.
62 +
63 + If unsure, say N
64 +
65 config BCMA_DEBUG
66 bool "BCMA debugging"
67 depends on BCMA
68 --- a/drivers/bcma/Makefile
69 +++ b/drivers/bcma/Makefile
70 @@ -1,8 +1,11 @@
71 bcma-y += main.o scan.o core.o sprom.o
72 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
73 +bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
74 +bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
75 bcma-y += driver_pci.o
76 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
77 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
78 +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
79 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
80 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
81 obj-$(CONFIG_BCMA) += bcma.o
82 --- a/drivers/bcma/bcma_private.h
83 +++ b/drivers/bcma/bcma_private.h
84 @@ -10,10 +10,19 @@
85
86 #define BCMA_CORE_SIZE 0x1000
87
88 +#define bcma_err(bus, fmt, ...) \
89 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
90 +#define bcma_warn(bus, fmt, ...) \
91 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
92 +#define bcma_info(bus, fmt, ...) \
93 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
94 +#define bcma_debug(bus, fmt, ...) \
95 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
96 +
97 struct bcma_bus;
98
99 /* main.c */
100 -int bcma_bus_register(struct bcma_bus *bus);
101 +int __devinit bcma_bus_register(struct bcma_bus *bus);
102 void bcma_bus_unregister(struct bcma_bus *bus);
103 int __init bcma_bus_early_register(struct bcma_bus *bus,
104 struct bcma_device *core_cc,
105 @@ -42,14 +51,42 @@ void bcma_chipco_serial_init(struct bcma
106 u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
107 u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
108
109 +#ifdef CONFIG_BCMA_SFLASH
110 +/* driver_chipcommon_sflash.c */
111 +int bcma_sflash_init(struct bcma_drv_cc *cc);
112 +extern struct platform_device bcma_sflash_dev;
113 +#else
114 +static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
115 +{
116 + bcma_err(cc->core->bus, "Serial flash not supported\n");
117 + return 0;
118 +}
119 +#endif /* CONFIG_BCMA_SFLASH */
120 +
121 +#ifdef CONFIG_BCMA_NFLASH
122 +/* driver_chipcommon_nflash.c */
123 +int bcma_nflash_init(struct bcma_drv_cc *cc);
124 +extern struct platform_device bcma_nflash_dev;
125 +#else
126 +static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
127 +{
128 + bcma_err(cc->core->bus, "NAND flash not supported\n");
129 + return 0;
130 +}
131 +#endif /* CONFIG_BCMA_NFLASH */
132 +
133 #ifdef CONFIG_BCMA_HOST_PCI
134 /* host_pci.c */
135 extern int __init bcma_host_pci_init(void);
136 extern void __exit bcma_host_pci_exit(void);
137 #endif /* CONFIG_BCMA_HOST_PCI */
138
139 +/* driver_pci.c */
140 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
141 +
142 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
143 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
144 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
145 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
146 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
147
148 #endif
149 --- a/drivers/bcma/core.c
150 +++ b/drivers/bcma/core.c
151 @@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
152 udelay(10);
153
154 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
155 + bcma_aread32(core, BCMA_RESET_CTL);
156 udelay(1);
157 }
158 EXPORT_SYMBOL_GPL(bcma_core_disable);
159 @@ -64,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
160 switch (clkmode) {
161 case BCMA_CLKMODE_FAST:
162 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
163 - udelay(64);
164 + usleep_range(64, 300);
165 for (i = 0; i < 1500; i++) {
166 if (bcma_read32(core, BCMA_CLKCTLST) &
167 BCMA_CLKCTLST_HAVEHT) {
168 @@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma
169 udelay(10);
170 }
171 if (i)
172 - pr_err("HT force timeout\n");
173 + bcma_err(core->bus, "HT force timeout\n");
174 break;
175 case BCMA_CLKMODE_DYNAMIC:
176 - pr_warn("Dynamic clockmode not supported yet!\n");
177 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
178 break;
179 }
180 }
181 @@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic
182 udelay(10);
183 }
184 if (i)
185 - pr_err("PLL enable timeout\n");
186 + bcma_err(core->bus, "PLL enable timeout\n");
187 } else {
188 - pr_warn("Disabling PLL not supported yet!\n");
189 + bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
190 }
191 }
192 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
193 @@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm
194 else
195 return BCMA_DMA_TRANSLATION_DMA32_CMT;
196 default:
197 - pr_err("DMA translation unknown for host %d\n",
198 - core->bus->hosttype);
199 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
200 + core->bus->hosttype);
201 }
202 return BCMA_DMA_TRANSLATION_NONE;
203 }
204 --- a/drivers/bcma/driver_chipcommon.c
205 +++ b/drivers/bcma/driver_chipcommon.c
206 @@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
207 return value;
208 }
209
210 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
211 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
212 {
213 - u32 leddc_on = 10;
214 - u32 leddc_off = 90;
215 -
216 - if (cc->setup_done)
217 + if (cc->early_setup_done)
218 return;
219
220 if (cc->core->id.rev >= 11)
221 @@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
222 if (cc->core->id.rev >= 35)
223 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
224
225 + if (cc->capabilities & BCMA_CC_CAP_PMU)
226 + bcma_pmu_early_init(cc);
227 +
228 + cc->early_setup_done = true;
229 +}
230 +
231 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
232 +{
233 + u32 leddc_on = 10;
234 + u32 leddc_off = 90;
235 +
236 + if (cc->setup_done)
237 + return;
238 +
239 + bcma_core_chipcommon_early_init(cc);
240 +
241 if (cc->core->id.rev >= 20) {
242 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
243 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
244 @@ -44,7 +57,7 @@ void bcma_core_chipcommon_init(struct bc
245 if (cc->capabilities & BCMA_CC_CAP_PMU)
246 bcma_pmu_init(cc);
247 if (cc->capabilities & BCMA_CC_CAP_PCTL)
248 - pr_err("Power control not implemented!\n");
249 + bcma_err(cc->core->bus, "Power control not implemented!\n");
250
251 if (cc->core->id.rev >= 16) {
252 if (cc->core->bus->sprom.leddc_on_time &&
253 @@ -137,8 +150,7 @@ void bcma_chipco_serial_init(struct bcma
254 | BCMA_CC_CORECTL_UARTCLKEN);
255 }
256 } else {
257 - pr_err("serial not supported on this device ccrev: 0x%x\n",
258 - ccrev);
259 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
260 return;
261 }
262
263 --- /dev/null
264 +++ b/drivers/bcma/driver_chipcommon_nflash.c
265 @@ -0,0 +1,44 @@
266 +/*
267 + * Broadcom specific AMBA
268 + * ChipCommon NAND flash interface
269 + *
270 + * Licensed under the GNU/GPL. See COPYING for details.
271 + */
272 +
273 +#include <linux/platform_device.h>
274 +#include <linux/bcma/bcma.h>
275 +
276 +#include "bcma_private.h"
277 +
278 +struct platform_device bcma_nflash_dev = {
279 + .name = "bcma_nflash",
280 + .num_resources = 0,
281 +};
282 +
283 +/* Initialize NAND flash access */
284 +int bcma_nflash_init(struct bcma_drv_cc *cc)
285 +{
286 + struct bcma_bus *bus = cc->core->bus;
287 +
288 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
289 + cc->core->id.rev != 0x38) {
290 + bcma_err(bus, "NAND flash on unsupported board!\n");
291 + return -ENOTSUPP;
292 + }
293 +
294 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
295 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
296 + return -ENODEV;
297 + }
298 +
299 + cc->nflash.present = true;
300 + if (cc->core->id.rev == 38 &&
301 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
302 + cc->nflash.boot = true;
303 +
304 + /* Prepare platform device, but don't register it yet. It's too early,
305 + * malloc (required by device_private_init) is not available yet. */
306 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
307 +
308 + return 0;
309 +}
310 --- a/drivers/bcma/driver_chipcommon_pmu.c
311 +++ b/drivers/bcma/driver_chipcommon_pmu.c
312 @@ -3,7 +3,8 @@
313 * ChipCommon Power Management Unit driver
314 *
315 * Copyright 2009, Michael Buesch <m@bues.ch>
316 - * Copyright 2007, Broadcom Corporation
317 + * Copyright 2007, 2011, Broadcom Corporation
318 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
319 *
320 * Licensed under the GNU/GPL. See COPYING for details.
321 */
322 @@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b
323 }
324 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
325
326 -static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
327 -{
328 - struct bcma_bus *bus = cc->core->bus;
329 -
330 - switch (bus->chipinfo.id) {
331 - case 0x4313:
332 - case 0x4331:
333 - case 43224:
334 - case 43225:
335 - break;
336 - default:
337 - pr_err("PLL init unknown for device 0x%04X\n",
338 - bus->chipinfo.id);
339 - }
340 -}
341 -
342 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
343 {
344 struct bcma_bus *bus = cc->core->bus;
345 u32 min_msk = 0, max_msk = 0;
346
347 switch (bus->chipinfo.id) {
348 - case 0x4313:
349 + case BCMA_CHIP_ID_BCM4313:
350 min_msk = 0x200D;
351 max_msk = 0xFFFF;
352 break;
353 - case 43224:
354 - case 43225:
355 - break;
356 default:
357 - pr_err("PMU resource config unknown for device 0x%04X\n",
358 - bus->chipinfo.id);
359 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
360 + bus->chipinfo.id);
361 }
362
363 /* Set the resource masks. */
364 @@ -93,22 +75,12 @@ static void bcma_pmu_resources_init(stru
365 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
366 if (max_msk)
367 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
368 -}
369 -
370 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
371 -{
372 - struct bcma_bus *bus = cc->core->bus;
373
374 - switch (bus->chipinfo.id) {
375 - case 0x4313:
376 - case 0x4331:
377 - case 43224:
378 - case 43225:
379 - break;
380 - default:
381 - pr_err("PMU switch/regulators init unknown for device "
382 - "0x%04X\n", bus->chipinfo.id);
383 - }
384 + /*
385 + * Add some delay; allow resources to come up and settle.
386 + * Delay is required for SoC (early init).
387 + */
388 + mdelay(2);
389 }
390
391 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
392 @@ -122,51 +94,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
393 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
394 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
395 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
396 + else if (bus->chipinfo.rev > 0)
397 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
398 } else {
399 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
400 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
401 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
402 }
403 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
404 }
405
406 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
407 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
408 {
409 struct bcma_bus *bus = cc->core->bus;
410
411 switch (bus->chipinfo.id) {
412 - case 0x4313:
413 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
414 + case BCMA_CHIP_ID_BCM4313:
415 + /* enable 12 mA drive strenth for 4313 and set chipControl
416 + register bit 1 */
417 + bcma_chipco_chipctl_maskset(cc, 0,
418 + ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
419 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
420 break;
421 - case 0x4331:
422 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
423 + case BCMA_CHIP_ID_BCM4331:
424 + case BCMA_CHIP_ID_BCM43431:
425 + /* Ext PA lines must be enabled for tx on BCM4331 */
426 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
427 break;
428 - case 43224:
429 + case BCMA_CHIP_ID_BCM43224:
430 + case BCMA_CHIP_ID_BCM43421:
431 + /* enable 12 mA drive strenth for 43224 and set chipControl
432 + register bit 15 */
433 if (bus->chipinfo.rev == 0) {
434 - pr_err("Workarounds for 43224 rev 0 not fully "
435 - "implemented\n");
436 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
437 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
438 + ~BCMA_CCTRL_43224_GPIO_TOGGLE,
439 + BCMA_CCTRL_43224_GPIO_TOGGLE);
440 + bcma_chipco_chipctl_maskset(cc, 0,
441 + ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
442 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
443 } else {
444 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
445 + bcma_chipco_chipctl_maskset(cc, 0,
446 + ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
447 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
448 }
449 break;
450 - case 43225:
451 - break;
452 default:
453 - pr_err("Workarounds unknown for device 0x%04X\n",
454 - bus->chipinfo.id);
455 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
456 + bus->chipinfo.id);
457 }
458 }
459
460 -void bcma_pmu_init(struct bcma_drv_cc *cc)
461 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
462 {
463 u32 pmucap;
464
465 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
466 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
467
468 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
469 - pmucap);
470 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
471 + cc->pmu.rev, pmucap);
472 +}
473
474 +void bcma_pmu_init(struct bcma_drv_cc *cc)
475 +{
476 if (cc->pmu.rev == 1)
477 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
478 ~BCMA_CC_PMU_CTL_NOILPONW);
479 @@ -174,12 +164,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
480 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
481 BCMA_CC_PMU_CTL_NOILPONW);
482
483 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
484 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
485 -
486 - bcma_pmu_pll_init(cc);
487 bcma_pmu_resources_init(cc);
488 - bcma_pmu_swreg_init(cc);
489 bcma_pmu_workarounds(cc);
490 }
491
492 @@ -188,23 +173,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
493 struct bcma_bus *bus = cc->core->bus;
494
495 switch (bus->chipinfo.id) {
496 - case 0x4716:
497 - case 0x4748:
498 - case 47162:
499 - case 0x4313:
500 - case 0x5357:
501 - case 0x4749:
502 - case 53572:
503 + case BCMA_CHIP_ID_BCM4716:
504 + case BCMA_CHIP_ID_BCM4748:
505 + case BCMA_CHIP_ID_BCM47162:
506 + case BCMA_CHIP_ID_BCM4313:
507 + case BCMA_CHIP_ID_BCM5357:
508 + case BCMA_CHIP_ID_BCM4749:
509 + case BCMA_CHIP_ID_BCM53572:
510 /* always 20Mhz */
511 return 20000 * 1000;
512 - case 0x5356:
513 - case 0x5300:
514 + case BCMA_CHIP_ID_BCM5356:
515 + case BCMA_CHIP_ID_BCM4706:
516 /* always 25Mhz */
517 return 25000 * 1000;
518 default:
519 - pr_warn("No ALP clock specified for %04X device, "
520 - "pmu rev. %d, using default %d Hz\n",
521 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
522 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
523 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
524 }
525 return BCMA_CC_PMU_ALP_CLOCK;
526 }
527 @@ -221,7 +205,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
528
529 BUG_ON(!m || m > 4);
530
531 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
532 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
533 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
534 /* Detect failure in clock setting */
535 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
536 if (tmp & 0x40000)
537 @@ -247,33 +232,62 @@ static u32 bcma_pmu_clock(struct bcma_dr
538 return (fc / div) * 1000000;
539 }
540
541 +static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
542 +{
543 + u32 tmp, ndiv, p1div, p2div;
544 + u32 clock;
545 +
546 + BUG_ON(!m || m > 4);
547 +
548 + /* Get N, P1 and P2 dividers to determine CPU clock */
549 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
550 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
551 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
552 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
553 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
554 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
555 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
556 +
557 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
558 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
559 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
560 + clock = (25000000 / 4) * ndiv * p2div / p1div;
561 + else
562 + /* Fixed reference clock 25MHz and m = 2 */
563 + clock = (25000000 / 2) * ndiv * p2div / p1div;
564 +
565 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
566 + clock = clock / 4;
567 +
568 + return clock;
569 +}
570 +
571 /* query bus clock frequency for PMU-enabled chipcommon */
572 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
573 +static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
574 {
575 struct bcma_bus *bus = cc->core->bus;
576
577 switch (bus->chipinfo.id) {
578 - case 0x4716:
579 - case 0x4748:
580 - case 47162:
581 + case BCMA_CHIP_ID_BCM4716:
582 + case BCMA_CHIP_ID_BCM4748:
583 + case BCMA_CHIP_ID_BCM47162:
584 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
585 BCMA_CC_PMU5_MAINPLL_SSB);
586 - case 0x5356:
587 + case BCMA_CHIP_ID_BCM5356:
588 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
589 BCMA_CC_PMU5_MAINPLL_SSB);
590 - case 0x5357:
591 - case 0x4749:
592 + case BCMA_CHIP_ID_BCM5357:
593 + case BCMA_CHIP_ID_BCM4749:
594 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
595 BCMA_CC_PMU5_MAINPLL_SSB);
596 - case 0x5300:
597 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
598 - BCMA_CC_PMU5_MAINPLL_SSB);
599 - case 53572:
600 + case BCMA_CHIP_ID_BCM4706:
601 + return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
602 + BCMA_CC_PMU5_MAINPLL_SSB);
603 + case BCMA_CHIP_ID_BCM53572:
604 return 75000000;
605 default:
606 - pr_warn("No backplane clock specified for %04X device, "
607 - "pmu rev. %d, using default %d Hz\n",
608 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
609 + bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
610 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
611 }
612 return BCMA_CC_PMU_HT_CLOCK;
613 }
614 @@ -283,17 +297,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
615 {
616 struct bcma_bus *bus = cc->core->bus;
617
618 - if (bus->chipinfo.id == 53572)
619 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
620 return 300000000;
621
622 if (cc->pmu.rev >= 5) {
623 u32 pll;
624 switch (bus->chipinfo.id) {
625 - case 0x5356:
626 + case BCMA_CHIP_ID_BCM4706:
627 + return bcma_pmu_clock_bcm4706(cc,
628 + BCMA_CC_PMU4706_MAINPLL_PLL0,
629 + BCMA_CC_PMU5_MAINPLL_CPU);
630 + case BCMA_CHIP_ID_BCM5356:
631 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
632 break;
633 - case 0x5357:
634 - case 0x4749:
635 + case BCMA_CHIP_ID_BCM5357:
636 + case BCMA_CHIP_ID_BCM4749:
637 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
638 break;
639 default:
640 @@ -301,10 +319,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
641 break;
642 }
643
644 - /* TODO: if (bus->chipinfo.id == 0x5300)
645 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
646 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
647 }
648
649 return bcma_pmu_get_clockcontrol(cc);
650 }
651 +
652 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
653 + u32 value)
654 +{
655 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
656 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
657 +}
658 +
659 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
660 +{
661 + u32 tmp = 0;
662 + u8 phypll_offset = 0;
663 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
664 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
665 + struct bcma_bus *bus = cc->core->bus;
666 +
667 + switch (bus->chipinfo.id) {
668 + case BCMA_CHIP_ID_BCM5357:
669 + case BCMA_CHIP_ID_BCM4749:
670 + case BCMA_CHIP_ID_BCM53572:
671 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
672 +
673 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
674 + so offset PLL0_PLLCTL[02] by 6 */
675 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
676 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
677 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
678 +
679 + /* RMW only the P1 divider */
680 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
681 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
682 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
683 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
684 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
685 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
686 +
687 + /* RMW only the int feedback divider */
688 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
689 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
690 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
691 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
692 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
693 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
694 +
695 + tmp = 1 << 10;
696 + break;
697 +
698 + case BCMA_CHIP_ID_BCM4331:
699 + case BCMA_CHIP_ID_BCM43431:
700 + if (spuravoid == 2) {
701 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
702 + 0x11500014);
703 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
704 + 0x0FC00a08);
705 + } else if (spuravoid == 1) {
706 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
707 + 0x11500014);
708 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
709 + 0x0F600a08);
710 + } else {
711 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
712 + 0x11100014);
713 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
714 + 0x03000a08);
715 + }
716 + tmp = 1 << 10;
717 + break;
718 +
719 + case BCMA_CHIP_ID_BCM43224:
720 + case BCMA_CHIP_ID_BCM43225:
721 + case BCMA_CHIP_ID_BCM43421:
722 + if (spuravoid == 1) {
723 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
724 + 0x11500010);
725 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
726 + 0x000C0C06);
727 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
728 + 0x0F600a08);
729 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
730 + 0x00000000);
731 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
732 + 0x2001E920);
733 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
734 + 0x88888815);
735 + } else {
736 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
737 + 0x11100010);
738 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
739 + 0x000c0c06);
740 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
741 + 0x03000a08);
742 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
743 + 0x00000000);
744 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
745 + 0x200005c0);
746 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
747 + 0x88888815);
748 + }
749 + tmp = 1 << 10;
750 + break;
751 +
752 + case BCMA_CHIP_ID_BCM4716:
753 + case BCMA_CHIP_ID_BCM4748:
754 + case BCMA_CHIP_ID_BCM47162:
755 + if (spuravoid == 1) {
756 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
757 + 0x11500060);
758 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
759 + 0x080C0C06);
760 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
761 + 0x0F600000);
762 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
763 + 0x00000000);
764 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
765 + 0x2001E924);
766 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
767 + 0x88888815);
768 + } else {
769 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
770 + 0x11100060);
771 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
772 + 0x080c0c06);
773 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
774 + 0x03000000);
775 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
776 + 0x00000000);
777 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
778 + 0x200005c0);
779 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
780 + 0x88888815);
781 + }
782 +
783 + tmp = 3 << 9;
784 + break;
785 +
786 + case BCMA_CHIP_ID_BCM43227:
787 + case BCMA_CHIP_ID_BCM43228:
788 + case BCMA_CHIP_ID_BCM43428:
789 + /* LCNXN */
790 + /* PLL Settings for spur avoidance on/off mode,
791 + no on2 support for 43228A0 */
792 + if (spuravoid == 1) {
793 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
794 + 0x01100014);
795 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
796 + 0x040C0C06);
797 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
798 + 0x03140A08);
799 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
800 + 0x00333333);
801 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
802 + 0x202C2820);
803 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
804 + 0x88888815);
805 + } else {
806 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
807 + 0x11100014);
808 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
809 + 0x040c0c06);
810 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
811 + 0x03000a08);
812 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
813 + 0x00000000);
814 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
815 + 0x200005c0);
816 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
817 + 0x88888815);
818 + }
819 + tmp = 1 << 10;
820 + break;
821 + default:
822 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
823 + bus->chipinfo.id);
824 + break;
825 + }
826 +
827 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
828 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
829 +}
830 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
831 --- /dev/null
832 +++ b/drivers/bcma/driver_chipcommon_sflash.c
833 @@ -0,0 +1,165 @@
834 +/*
835 + * Broadcom specific AMBA
836 + * ChipCommon serial flash interface
837 + *
838 + * Licensed under the GNU/GPL. See COPYING for details.
839 + */
840 +
841 +#include <linux/platform_device.h>
842 +#include <linux/bcma/bcma.h>
843 +
844 +#include "bcma_private.h"
845 +
846 +static struct resource bcma_sflash_resource = {
847 + .name = "bcma_sflash",
848 + .start = BCMA_SOC_FLASH2,
849 + .end = 0,
850 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
851 +};
852 +
853 +struct platform_device bcma_sflash_dev = {
854 + .name = "bcma_sflash",
855 + .resource = &bcma_sflash_resource,
856 + .num_resources = 1,
857 +};
858 +
859 +struct bcma_sflash_tbl_e {
860 + char *name;
861 + u32 id;
862 + u32 blocksize;
863 + u16 numblocks;
864 +};
865 +
866 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
867 + { "M25P20", 0x11, 0x10000, 4, },
868 + { "M25P40", 0x12, 0x10000, 8, },
869 +
870 + { "M25P16", 0x14, 0x10000, 32, },
871 + { "M25P32", 0x14, 0x10000, 64, },
872 + { "M25P64", 0x16, 0x10000, 128, },
873 + { "M25FL128", 0x17, 0x10000, 256, },
874 + { 0 },
875 +};
876 +
877 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
878 + { "SST25WF512", 1, 0x1000, 16, },
879 + { "SST25VF512", 0x48, 0x1000, 16, },
880 + { "SST25WF010", 2, 0x1000, 32, },
881 + { "SST25VF010", 0x49, 0x1000, 32, },
882 + { "SST25WF020", 3, 0x1000, 64, },
883 + { "SST25VF020", 0x43, 0x1000, 64, },
884 + { "SST25WF040", 4, 0x1000, 128, },
885 + { "SST25VF040", 0x44, 0x1000, 128, },
886 + { "SST25VF040B", 0x8d, 0x1000, 128, },
887 + { "SST25WF080", 5, 0x1000, 256, },
888 + { "SST25VF080B", 0x8e, 0x1000, 256, },
889 + { "SST25VF016", 0x41, 0x1000, 512, },
890 + { "SST25VF032", 0x4a, 0x1000, 1024, },
891 + { "SST25VF064", 0x4b, 0x1000, 2048, },
892 + { 0 },
893 +};
894 +
895 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
896 + { "AT45DB011", 0xc, 256, 512, },
897 + { "AT45DB021", 0x14, 256, 1024, },
898 + { "AT45DB041", 0x1c, 256, 2048, },
899 + { "AT45DB081", 0x24, 256, 4096, },
900 + { "AT45DB161", 0x2c, 512, 4096, },
901 + { "AT45DB321", 0x34, 512, 8192, },
902 + { "AT45DB642", 0x3c, 1024, 8192, },
903 + { 0 },
904 +};
905 +
906 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
907 +{
908 + int i;
909 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
910 + BCMA_CC_FLASHCTL_START | opcode);
911 + for (i = 0; i < 1000; i++) {
912 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
913 + BCMA_CC_FLASHCTL_BUSY))
914 + return;
915 + cpu_relax();
916 + }
917 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
918 +}
919 +
920 +/* Initialize serial flash access */
921 +int bcma_sflash_init(struct bcma_drv_cc *cc)
922 +{
923 + struct bcma_bus *bus = cc->core->bus;
924 + struct bcma_sflash *sflash = &cc->sflash;
925 + struct bcma_sflash_tbl_e *e;
926 + u32 id, id2;
927 +
928 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
929 + case BCMA_CC_FLASHT_STSER:
930 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
931 +
932 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
933 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
934 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
935 +
936 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
937 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
938 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
939 +
940 + switch (id) {
941 + case 0xbf:
942 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
943 + if (e->id == id2)
944 + break;
945 + }
946 + break;
947 + case 0x13:
948 + return -ENOTSUPP;
949 + default:
950 + for (e = bcma_sflash_st_tbl; e->name; e++) {
951 + if (e->id == id)
952 + break;
953 + }
954 + break;
955 + }
956 + if (!e->name) {
957 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
958 + return -ENOTSUPP;
959 + }
960 +
961 + break;
962 + case BCMA_CC_FLASHT_ATSER:
963 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
964 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
965 +
966 + for (e = bcma_sflash_at_tbl; e->name; e++) {
967 + if (e->id == id)
968 + break;
969 + }
970 + if (!e->name) {
971 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
972 + return -ENOTSUPP;
973 + }
974 +
975 + break;
976 + default:
977 + bcma_err(bus, "Unsupported flash type\n");
978 + return -ENOTSUPP;
979 + }
980 +
981 + sflash->window = BCMA_SOC_FLASH2;
982 + sflash->blocksize = e->blocksize;
983 + sflash->numblocks = e->numblocks;
984 + sflash->size = sflash->blocksize * sflash->numblocks;
985 + sflash->present = true;
986 +
987 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
988 + e->name, sflash->size / 1024, sflash->blocksize,
989 + sflash->numblocks);
990 +
991 + /* Prepare platform device, but don't register it yet. It's too early,
992 + * malloc (required by device_private_init) is not available yet. */
993 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
994 + sflash->size;
995 + bcma_sflash_dev.dev.platform_data = sflash;
996 +
997 + return 0;
998 +}
999 --- /dev/null
1000 +++ b/drivers/bcma/driver_gmac_cmn.c
1001 @@ -0,0 +1,14 @@
1002 +/*
1003 + * Broadcom specific AMBA
1004 + * GBIT MAC COMMON Core
1005 + *
1006 + * Licensed under the GNU/GPL. See COPYING for details.
1007 + */
1008 +
1009 +#include "bcma_private.h"
1010 +#include <linux/bcma/bcma.h>
1011 +
1012 +void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
1013 +{
1014 + mutex_init(&gc->phy_mutex);
1015 +}
1016 --- a/drivers/bcma/driver_mips.c
1017 +++ b/drivers/bcma/driver_mips.c
1018 @@ -22,15 +22,15 @@
1019 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1020 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1021 {
1022 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
1023 - dev->id.id == BCMA_CORE_MIPS_74K;
1024 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
1025 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
1026 }
1027
1028 /* The 5357b0 hangs when reading USB20H DMP registers */
1029 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
1030 {
1031 - return (dev->bus->chipinfo.id == 0x5357 ||
1032 - dev->bus->chipinfo.id == 0x4749) &&
1033 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1034 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
1035 dev->bus->chipinfo.pkg == 11 &&
1036 dev->id.id == BCMA_CORE_USB20_HOST;
1037 }
1038 @@ -131,7 +131,7 @@ static void bcma_core_mips_set_irq(struc
1039 /* backplane irq line is in use, find out who uses
1040 * it and set user to irq 0
1041 */
1042 - list_for_each_entry_reverse(core, &bus->cores, list) {
1043 + list_for_each_entry(core, &bus->cores, list) {
1044 if ((1 << bcma_core_mips_irqflag(core)) ==
1045 oldirqflag) {
1046 bcma_core_mips_set_irq(core, 0);
1047 @@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struc
1048 1 << irqflag);
1049 }
1050
1051 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
1052 - dev->id.id, oldirq + 2, irq + 2);
1053 + bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1054 + dev->id.id, oldirq + 2, irq + 2);
1055 }
1056
1057 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1058 @@ -161,7 +161,7 @@ static void bcma_core_mips_dump_irq(stru
1059 {
1060 struct bcma_device *core;
1061
1062 - list_for_each_entry_reverse(core, &bus->cores, list) {
1063 + list_for_each_entry(core, &bus->cores, list) {
1064 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
1065 }
1066 }
1067 @@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1068 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1069 return bcma_pmu_get_clockcpu(&bus->drv_cc);
1070
1071 - pr_err("No PMU available, need this to get the cpu clock\n");
1072 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1073 return 0;
1074 }
1075 EXPORT_SYMBOL(bcma_cpu_clock);
1076 @@ -181,26 +181,50 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1077 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1078 {
1079 struct bcma_bus *bus = mcore->core->bus;
1080 + struct bcma_drv_cc *cc = &bus->drv_cc;
1081
1082 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1083 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1084 case BCMA_CC_FLASHT_STSER:
1085 case BCMA_CC_FLASHT_ATSER:
1086 - pr_err("Serial flash not supported.\n");
1087 + bcma_debug(bus, "Found serial flash\n");
1088 + bcma_sflash_init(cc);
1089 break;
1090 case BCMA_CC_FLASHT_PARA:
1091 - pr_info("found parallel flash.\n");
1092 - bus->drv_cc.pflash.window = 0x1c000000;
1093 - bus->drv_cc.pflash.window_size = 0x02000000;
1094 + bcma_debug(bus, "Found parallel flash\n");
1095 + cc->pflash.present = true;
1096 + cc->pflash.window = BCMA_SOC_FLASH2;
1097 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1098
1099 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1100 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1101 BCMA_CC_FLASH_CFG_DS) == 0)
1102 - bus->drv_cc.pflash.buswidth = 1;
1103 + cc->pflash.buswidth = 1;
1104 else
1105 - bus->drv_cc.pflash.buswidth = 2;
1106 + cc->pflash.buswidth = 2;
1107 break;
1108 default:
1109 - pr_err("flash not supported.\n");
1110 + bcma_err(bus, "Flash type not supported\n");
1111 }
1112 +
1113 + if (cc->core->id.rev == 38 ||
1114 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1115 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1116 + bcma_debug(bus, "Found NAND flash\n");
1117 + bcma_nflash_init(cc);
1118 + }
1119 + }
1120 +}
1121 +
1122 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1123 +{
1124 + struct bcma_bus *bus = mcore->core->bus;
1125 +
1126 + if (mcore->early_setup_done)
1127 + return;
1128 +
1129 + bcma_chipco_serial_init(&bus->drv_cc);
1130 + bcma_core_mips_flash_detect(mcore);
1131 +
1132 + mcore->early_setup_done = true;
1133 }
1134
1135 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1136 @@ -209,13 +233,17 @@ void bcma_core_mips_init(struct bcma_drv
1137 struct bcma_device *core;
1138 bus = mcore->core->bus;
1139
1140 - pr_info("Initializing MIPS core...\n");
1141 + if (mcore->setup_done)
1142 + return;
1143 +
1144 + bcma_info(bus, "Initializing MIPS core...\n");
1145 +
1146 + bcma_core_mips_early_init(mcore);
1147
1148 - if (!mcore->setup_done)
1149 - mcore->assigned_irqs = 1;
1150 + mcore->assigned_irqs = 1;
1151
1152 /* Assign IRQs to all cores on the bus */
1153 - list_for_each_entry_reverse(core, &bus->cores, list) {
1154 + list_for_each_entry(core, &bus->cores, list) {
1155 int mips_irq;
1156 if (core->irq)
1157 continue;
1158 @@ -244,13 +272,8 @@ void bcma_core_mips_init(struct bcma_drv
1159 break;
1160 }
1161 }
1162 - pr_info("IRQ reconfiguration done\n");
1163 + bcma_info(bus, "IRQ reconfiguration done\n");
1164 bcma_core_mips_dump_irq(bus);
1165
1166 - if (mcore->setup_done)
1167 - return;
1168 -
1169 - bcma_chipco_serial_init(&bus->drv_cc);
1170 - bcma_core_mips_flash_detect(mcore);
1171 mcore->setup_done = true;
1172 }
1173 --- a/drivers/bcma/driver_pci.c
1174 +++ b/drivers/bcma/driver_pci.c
1175 @@ -2,8 +2,9 @@
1176 * Broadcom specific AMBA
1177 * PCI Core
1178 *
1179 - * Copyright 2005, Broadcom Corporation
1180 + * Copyright 2005, 2011, Broadcom Corporation
1181 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1182 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1183 *
1184 * Licensed under the GNU/GPL. See COPYING for details.
1185 */
1186 @@ -16,120 +17,124 @@
1187 * R/W ops.
1188 **************************************************/
1189
1190 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1191 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1192 {
1193 - pcicore_write32(pc, 0x130, address);
1194 - pcicore_read32(pc, 0x130);
1195 - return pcicore_read32(pc, 0x134);
1196 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1197 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1198 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
1199 }
1200
1201 -#if 0
1202 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
1203 {
1204 - pcicore_write32(pc, 0x130, address);
1205 - pcicore_read32(pc, 0x130);
1206 - pcicore_write32(pc, 0x134, data);
1207 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1208 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1209 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1210 }
1211 -#endif
1212
1213 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1214 {
1215 - const u16 mdio_control = 0x128;
1216 - const u16 mdio_data = 0x12C;
1217 u32 v;
1218 int i;
1219
1220 - v = (1 << 30); /* Start of Transaction */
1221 - v |= (1 << 28); /* Write Transaction */
1222 - v |= (1 << 17); /* Turnaround */
1223 - v |= (0x1F << 18);
1224 + v = BCMA_CORE_PCI_MDIODATA_START;
1225 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1226 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1227 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1228 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
1229 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1230 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1231 v |= (phy << 4);
1232 - pcicore_write32(pc, mdio_data, v);
1233 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1234
1235 udelay(10);
1236 for (i = 0; i < 200; i++) {
1237 - v = pcicore_read32(pc, mdio_control);
1238 - if (v & 0x100 /* Trans complete */)
1239 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1240 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1241 break;
1242 - msleep(1);
1243 + usleep_range(1000, 2000);
1244 }
1245 }
1246
1247 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1248 {
1249 - const u16 mdio_control = 0x128;
1250 - const u16 mdio_data = 0x12C;
1251 int max_retries = 10;
1252 u16 ret = 0;
1253 u32 v;
1254 int i;
1255
1256 - v = 0x80; /* Enable Preamble Sequence */
1257 - v |= 0x2; /* MDIO Clock Divisor */
1258 - pcicore_write32(pc, mdio_control, v);
1259 + /* enable mdio access to SERDES */
1260 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1261 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1262 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1263
1264 if (pc->core->id.rev >= 10) {
1265 max_retries = 200;
1266 bcma_pcie_mdio_set_phy(pc, device);
1267 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1268 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1269 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1270 + } else {
1271 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1272 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1273 }
1274
1275 - v = (1 << 30); /* Start of Transaction */
1276 - v |= (1 << 29); /* Read Transaction */
1277 - v |= (1 << 17); /* Turnaround */
1278 - if (pc->core->id.rev < 10)
1279 - v |= (u32)device << 22;
1280 - v |= (u32)address << 18;
1281 - pcicore_write32(pc, mdio_data, v);
1282 + v = BCMA_CORE_PCI_MDIODATA_START;
1283 + v |= BCMA_CORE_PCI_MDIODATA_READ;
1284 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1285 +
1286 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1287 /* Wait for the device to complete the transaction */
1288 udelay(10);
1289 for (i = 0; i < max_retries; i++) {
1290 - v = pcicore_read32(pc, mdio_control);
1291 - if (v & 0x100 /* Trans complete */) {
1292 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1293 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
1294 udelay(10);
1295 - ret = pcicore_read32(pc, mdio_data);
1296 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1297 break;
1298 }
1299 - msleep(1);
1300 + usleep_range(1000, 2000);
1301 }
1302 - pcicore_write32(pc, mdio_control, 0);
1303 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1304 return ret;
1305 }
1306
1307 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1308 u8 address, u16 data)
1309 {
1310 - const u16 mdio_control = 0x128;
1311 - const u16 mdio_data = 0x12C;
1312 int max_retries = 10;
1313 u32 v;
1314 int i;
1315
1316 - v = 0x80; /* Enable Preamble Sequence */
1317 - v |= 0x2; /* MDIO Clock Divisor */
1318 - pcicore_write32(pc, mdio_control, v);
1319 + /* enable mdio access to SERDES */
1320 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1321 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1322 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1323
1324 if (pc->core->id.rev >= 10) {
1325 max_retries = 200;
1326 bcma_pcie_mdio_set_phy(pc, device);
1327 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1328 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1329 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1330 + } else {
1331 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1332 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1333 }
1334
1335 - v = (1 << 30); /* Start of Transaction */
1336 - v |= (1 << 28); /* Write Transaction */
1337 - v |= (1 << 17); /* Turnaround */
1338 - if (pc->core->id.rev < 10)
1339 - v |= (u32)device << 22;
1340 - v |= (u32)address << 18;
1341 + v = BCMA_CORE_PCI_MDIODATA_START;
1342 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1343 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1344 v |= data;
1345 - pcicore_write32(pc, mdio_data, v);
1346 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1347 /* Wait for the device to complete the transaction */
1348 udelay(10);
1349 for (i = 0; i < max_retries; i++) {
1350 - v = pcicore_read32(pc, mdio_control);
1351 - if (v & 0x100 /* Trans complete */)
1352 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1353 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1354 break;
1355 - msleep(1);
1356 + usleep_range(1000, 2000);
1357 }
1358 - pcicore_write32(pc, mdio_control, 0);
1359 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1360 }
1361
1362 /**************************************************
1363 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
1364
1365 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
1366 {
1367 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1368 + u32 tmp;
1369 +
1370 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
1371 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
1372 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
1373 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
1374 + else
1375 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
1376 }
1377
1378 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
1379 {
1380 - const u8 serdes_pll_device = 0x1D;
1381 - const u8 serdes_rx_device = 0x1F;
1382 u16 tmp;
1383
1384 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1385 - bcma_pcicore_polarity_workaround(pc));
1386 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1387 - if (tmp & 0x4000)
1388 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1389 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
1390 + BCMA_CORE_PCI_SERDES_RX_CTRL,
1391 + bcma_pcicore_polarity_workaround(pc));
1392 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1393 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
1394 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
1395 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1396 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
1397 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
1398 +}
1399 +
1400 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
1401 +{
1402 + struct bcma_device *core = pc->core;
1403 + u16 val16, core_index;
1404 + uint regoff;
1405 +
1406 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
1407 + core_index = (u16)core->core_index;
1408 +
1409 + val16 = pcicore_read16(pc, regoff);
1410 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
1411 + != core_index) {
1412 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
1413 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
1414 + pcicore_write16(pc, regoff, val16);
1415 + }
1416 +}
1417 +
1418 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
1419 +/* Needs to happen when coming out of 'standby'/'hibernate' */
1420 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
1421 +{
1422 + u16 val16;
1423 + uint regoff;
1424 +
1425 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
1426 +
1427 + val16 = pcicore_read16(pc, regoff);
1428 +
1429 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
1430 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
1431 + pcicore_write16(pc, regoff, val16);
1432 + }
1433 }
1434
1435 /**************************************************
1436 * Init.
1437 **************************************************/
1438
1439 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1440 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1441 {
1442 + bcma_core_pci_fixcfg(pc);
1443 bcma_pcicore_serdes_workaround(pc);
1444 + bcma_core_pci_config_fixup(pc);
1445 }
1446
1447 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
1448 -{
1449 - struct bcma_bus *bus = pc->core->bus;
1450 - u16 chipid_top;
1451 -
1452 - chipid_top = (bus->chipinfo.id & 0xFF00);
1453 - if (chipid_top != 0x4700 &&
1454 - chipid_top != 0x5300)
1455 - return false;
1456 -
1457 -#ifdef CONFIG_SSB_DRIVER_PCICORE
1458 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
1459 - return false;
1460 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
1461 -
1462 -#if 0
1463 - /* TODO: on BCMA we use address from EROM instead of magic formula */
1464 - u32 tmp;
1465 - return !mips_busprobe32(tmp, (bus->mmio +
1466 - (pc->core->core_index * BCMA_CORE_SIZE)));
1467 -#endif
1468 -
1469 - return true;
1470 -}
1471 -
1472 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
1473 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
1474 {
1475 if (pc->setup_done)
1476 return;
1477
1478 - if (bcma_core_pci_is_in_hostmode(pc)) {
1479 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1480 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
1481 + if (pc->hostmode)
1482 bcma_core_pci_hostmode_init(pc);
1483 -#else
1484 - pr_err("Driver compiled without support for hostmode PCI\n");
1485 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
1486 - } else {
1487 - bcma_core_pci_clientmode_init(pc);
1488 - }
1489
1490 - pc->setup_done = true;
1491 + if (!pc->hostmode)
1492 + bcma_core_pci_clientmode_init(pc);
1493 }
1494
1495 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1496 bool enable)
1497 {
1498 - struct pci_dev *pdev = pc->core->bus->host_pci;
1499 + struct pci_dev *pdev;
1500 u32 coremask, tmp;
1501 int err = 0;
1502
1503 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1504 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1505 /* This bcma device is not on a PCI host-bus. So the IRQs are
1506 * not routed through the PCI core.
1507 * So we must not enable routing through the PCI core. */
1508 goto out;
1509 }
1510
1511 + pdev = pc->core->bus->host_pci;
1512 +
1513 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
1514 if (err)
1515 goto out;
1516 @@ -236,3 +261,17 @@ out:
1517 return err;
1518 }
1519 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1520 +
1521 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1522 +{
1523 + u32 w;
1524 +
1525 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1526 + if (extend)
1527 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1528 + else
1529 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1530 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1531 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1532 +}
1533 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1534 --- a/drivers/bcma/driver_pci_host.c
1535 +++ b/drivers/bcma/driver_pci_host.c
1536 @@ -2,13 +2,596 @@
1537 * Broadcom specific AMBA
1538 * PCI Core in hostmode
1539 *
1540 + * Copyright 2005 - 2011, Broadcom Corporation
1541 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1542 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1543 + *
1544 * Licensed under the GNU/GPL. See COPYING for details.
1545 */
1546
1547 #include "bcma_private.h"
1548 +#include <linux/pci.h>
1549 +#include <linux/export.h>
1550 #include <linux/bcma/bcma.h>
1551 +#include <asm/paccess.h>
1552 +
1553 +/* Probe a 32bit value on the bus and catch bus exceptions.
1554 + * Returns nonzero on a bus exception.
1555 + * This is MIPS specific */
1556 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
1557 +
1558 +/* Assume one-hot slot wiring */
1559 +#define BCMA_PCI_SLOT_MAX 16
1560 +#define PCI_CONFIG_SPACE_SIZE 256
1561 +
1562 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
1563 +{
1564 + struct bcma_bus *bus = pc->core->bus;
1565 + u16 chipid_top;
1566 + u32 tmp;
1567 +
1568 + chipid_top = (bus->chipinfo.id & 0xFF00);
1569 + if (chipid_top != 0x4700 &&
1570 + chipid_top != 0x5300)
1571 + return false;
1572 +
1573 + bcma_core_enable(pc->core, 0);
1574 +
1575 + return !mips_busprobe32(tmp, pc->core->io_addr);
1576 +}
1577 +
1578 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
1579 +{
1580 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1581 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1582 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
1583 +}
1584 +
1585 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
1586 + u32 data)
1587 +{
1588 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1589 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1590 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
1591 +}
1592 +
1593 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
1594 + unsigned int func, unsigned int off)
1595 +{
1596 + u32 addr = 0;
1597 +
1598 + /* Issue config commands only when the data link is up (atleast
1599 + * one external pcie device is present).
1600 + */
1601 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
1602 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
1603 + goto out;
1604 +
1605 + /* Type 0 transaction */
1606 + /* Slide the PCI window to the appropriate slot */
1607 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1608 + /* Calculate the address */
1609 + addr = pc->host_controller->host_cfg_addr;
1610 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
1611 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
1612 + addr |= (off & ~3);
1613 +
1614 +out:
1615 + return addr;
1616 +}
1617
1618 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1619 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
1620 + unsigned int func, unsigned int off,
1621 + void *buf, int len)
1622 {
1623 - pr_err("No support for PCI core in hostmode yet\n");
1624 + int err = -EINVAL;
1625 + u32 addr, val;
1626 + void __iomem *mmio = 0;
1627 +
1628 + WARN_ON(!pc->hostmode);
1629 + if (unlikely(len != 1 && len != 2 && len != 4))
1630 + goto out;
1631 + if (dev == 0) {
1632 + /* we support only two functions on device 0 */
1633 + if (func > 1)
1634 + return -EINVAL;
1635 +
1636 + /* accesses to config registers with offsets >= 256
1637 + * requires indirect access.
1638 + */
1639 + if (off >= PCI_CONFIG_SPACE_SIZE) {
1640 + addr = (func << 12);
1641 + addr |= (off & 0x0FFF);
1642 + val = bcma_pcie_read_config(pc, addr);
1643 + } else {
1644 + addr = BCMA_CORE_PCI_PCICFG0;
1645 + addr |= (func << 8);
1646 + addr |= (off & 0xfc);
1647 + val = pcicore_read32(pc, addr);
1648 + }
1649 + } else {
1650 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1651 + if (unlikely(!addr))
1652 + goto out;
1653 + err = -ENOMEM;
1654 + mmio = ioremap_nocache(addr, sizeof(val));
1655 + if (!mmio)
1656 + goto out;
1657 +
1658 + if (mips_busprobe32(val, mmio)) {
1659 + val = 0xffffffff;
1660 + goto unmap;
1661 + }
1662 +
1663 + val = readl(mmio);
1664 + }
1665 + val >>= (8 * (off & 3));
1666 +
1667 + switch (len) {
1668 + case 1:
1669 + *((u8 *)buf) = (u8)val;
1670 + break;
1671 + case 2:
1672 + *((u16 *)buf) = (u16)val;
1673 + break;
1674 + case 4:
1675 + *((u32 *)buf) = (u32)val;
1676 + break;
1677 + }
1678 + err = 0;
1679 +unmap:
1680 + if (mmio)
1681 + iounmap(mmio);
1682 +out:
1683 + return err;
1684 +}
1685 +
1686 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
1687 + unsigned int func, unsigned int off,
1688 + const void *buf, int len)
1689 +{
1690 + int err = -EINVAL;
1691 + u32 addr = 0, val = 0;
1692 + void __iomem *mmio = 0;
1693 + u16 chipid = pc->core->bus->chipinfo.id;
1694 +
1695 + WARN_ON(!pc->hostmode);
1696 + if (unlikely(len != 1 && len != 2 && len != 4))
1697 + goto out;
1698 + if (dev == 0) {
1699 + /* accesses to config registers with offsets >= 256
1700 + * requires indirect access.
1701 + */
1702 + if (off < PCI_CONFIG_SPACE_SIZE) {
1703 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1704 + addr |= (func << 8);
1705 + addr |= (off & 0xfc);
1706 + mmio = ioremap_nocache(addr, sizeof(val));
1707 + if (!mmio)
1708 + goto out;
1709 + }
1710 + } else {
1711 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1712 + if (unlikely(!addr))
1713 + goto out;
1714 + err = -ENOMEM;
1715 + mmio = ioremap_nocache(addr, sizeof(val));
1716 + if (!mmio)
1717 + goto out;
1718 +
1719 + if (mips_busprobe32(val, mmio)) {
1720 + val = 0xffffffff;
1721 + goto unmap;
1722 + }
1723 + }
1724 +
1725 + switch (len) {
1726 + case 1:
1727 + val = readl(mmio);
1728 + val &= ~(0xFF << (8 * (off & 3)));
1729 + val |= *((const u8 *)buf) << (8 * (off & 3));
1730 + break;
1731 + case 2:
1732 + val = readl(mmio);
1733 + val &= ~(0xFFFF << (8 * (off & 3)));
1734 + val |= *((const u16 *)buf) << (8 * (off & 3));
1735 + break;
1736 + case 4:
1737 + val = *((const u32 *)buf);
1738 + break;
1739 + }
1740 + if (dev == 0 && !addr) {
1741 + /* accesses to config registers with offsets >= 256
1742 + * requires indirect access.
1743 + */
1744 + addr = (func << 12);
1745 + addr |= (off & 0x0FFF);
1746 + bcma_pcie_write_config(pc, addr, val);
1747 + } else {
1748 + writel(val, mmio);
1749 +
1750 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
1751 + chipid == BCMA_CHIP_ID_BCM4748)
1752 + readl(mmio);
1753 + }
1754 +
1755 + err = 0;
1756 +unmap:
1757 + if (mmio)
1758 + iounmap(mmio);
1759 +out:
1760 + return err;
1761 +}
1762 +
1763 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
1764 + unsigned int devfn,
1765 + int reg, int size, u32 *val)
1766 +{
1767 + unsigned long flags;
1768 + int err;
1769 + struct bcma_drv_pci *pc;
1770 + struct bcma_drv_pci_host *pc_host;
1771 +
1772 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1773 + pc = pc_host->pdev;
1774 +
1775 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1776 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
1777 + PCI_FUNC(devfn), reg, val, size);
1778 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1779 +
1780 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1781 +}
1782 +
1783 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
1784 + unsigned int devfn,
1785 + int reg, int size, u32 val)
1786 +{
1787 + unsigned long flags;
1788 + int err;
1789 + struct bcma_drv_pci *pc;
1790 + struct bcma_drv_pci_host *pc_host;
1791 +
1792 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1793 + pc = pc_host->pdev;
1794 +
1795 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1796 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
1797 + PCI_FUNC(devfn), reg, &val, size);
1798 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1799 +
1800 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1801 +}
1802 +
1803 +/* return cap_offset if requested capability exists in the PCI config space */
1804 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
1805 + unsigned int dev,
1806 + unsigned int func, u8 req_cap_id,
1807 + unsigned char *buf, u32 *buflen)
1808 +{
1809 + u8 cap_id;
1810 + u8 cap_ptr = 0;
1811 + u32 bufsize;
1812 + u8 byte_val;
1813 +
1814 + /* check for Header type 0 */
1815 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1816 + sizeof(u8));
1817 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1818 + return cap_ptr;
1819 +
1820 + /* check if the capability pointer field exists */
1821 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
1822 + sizeof(u8));
1823 + if (!(byte_val & PCI_STATUS_CAP_LIST))
1824 + return cap_ptr;
1825 +
1826 + /* check if the capability pointer is 0x00 */
1827 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
1828 + sizeof(u8));
1829 + if (cap_ptr == 0x00)
1830 + return cap_ptr;
1831 +
1832 + /* loop thr'u the capability list and see if the requested capabilty
1833 + * exists */
1834 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
1835 + while (cap_id != req_cap_id) {
1836 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
1837 + sizeof(u8));
1838 + if (cap_ptr == 0x00)
1839 + return cap_ptr;
1840 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
1841 + sizeof(u8));
1842 + }
1843 +
1844 + /* found the caller requested capability */
1845 + if ((buf != NULL) && (buflen != NULL)) {
1846 + u8 cap_data;
1847 +
1848 + bufsize = *buflen;
1849 + if (!bufsize)
1850 + return cap_ptr;
1851 +
1852 + *buflen = 0;
1853 +
1854 + /* copy the cpability data excluding cap ID and next ptr */
1855 + cap_data = cap_ptr + 2;
1856 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
1857 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
1858 + *buflen = bufsize;
1859 + while (bufsize--) {
1860 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
1861 + sizeof(u8));
1862 + cap_data++;
1863 + buf++;
1864 + }
1865 + }
1866 +
1867 + return cap_ptr;
1868 +}
1869 +
1870 +/* If the root port is capable of returning Config Request
1871 + * Retry Status (CRS) Completion Status to software then
1872 + * enable the feature.
1873 + */
1874 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
1875 +{
1876 + struct bcma_bus *bus = pc->core->bus;
1877 + u8 cap_ptr, root_ctrl, root_cap, dev;
1878 + u16 val16;
1879 + int i;
1880 +
1881 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
1882 + NULL);
1883 + root_cap = cap_ptr + PCI_EXP_RTCAP;
1884 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
1885 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
1886 + /* Enable CRS software visibility */
1887 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
1888 + val16 = PCI_EXP_RTCTL_CRSSVE;
1889 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
1890 + sizeof(u16));
1891 +
1892 + /* Initiate a configuration request to read the vendor id
1893 + * field of the device function's config space header after
1894 + * 100 ms wait time from the end of Reset. If the device is
1895 + * not done with its internal initialization, it must at
1896 + * least return a completion TLP, with a completion status
1897 + * of "Configuration Request Retry Status (CRS)". The root
1898 + * complex must complete the request to the host by returning
1899 + * a read-data value of 0001h for the Vendor ID field and
1900 + * all 1s for any additional bytes included in the request.
1901 + * Poll using the config reads for max wait time of 1 sec or
1902 + * until we receive the successful completion status. Repeat
1903 + * the procedure for all the devices.
1904 + */
1905 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
1906 + for (i = 0; i < 100000; i++) {
1907 + bcma_extpci_read_config(pc, dev, 0,
1908 + PCI_VENDOR_ID, &val16,
1909 + sizeof(val16));
1910 + if (val16 != 0x1)
1911 + break;
1912 + udelay(10);
1913 + }
1914 + if (val16 == 0x1)
1915 + bcma_err(bus, "PCI: Broken device in slot %d\n",
1916 + dev);
1917 + }
1918 + }
1919 +}
1920 +
1921 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1922 +{
1923 + struct bcma_bus *bus = pc->core->bus;
1924 + struct bcma_drv_pci_host *pc_host;
1925 + u32 tmp;
1926 + u32 pci_membase_1G;
1927 + unsigned long io_map_base;
1928 +
1929 + bcma_info(bus, "PCIEcore in host mode found\n");
1930 +
1931 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1932 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1933 + return;
1934 + }
1935 +
1936 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1937 + if (!pc_host) {
1938 + bcma_err(bus, "can not allocate memory");
1939 + return;
1940 + }
1941 +
1942 + pc->host_controller = pc_host;
1943 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
1944 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1945 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
1946 + pc_host->pdev = pc;
1947 +
1948 + pci_membase_1G = BCMA_SOC_PCI_DMA;
1949 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
1950 +
1951 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
1952 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
1953 +
1954 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
1955 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
1956 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
1957 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
1958 +
1959 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
1960 + pc_host->io_resource.start = 0x100;
1961 + pc_host->io_resource.end = 0x7FF;
1962 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1963 +
1964 + /* Reset RC */
1965 + usleep_range(3000, 5000);
1966 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1967 + usleep_range(1000, 2000);
1968 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1969 + BCMA_CORE_PCI_CTL_RST_OE);
1970 +
1971 + /* 64 MB I/O access window. On 4716, use
1972 + * sbtopcie0 to access the device registers. We
1973 + * can't use address match 2 (1 GB window) region
1974 + * as mips can't generate 64-bit address on the
1975 + * backplane.
1976 + */
1977 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
1978 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
1979 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1980 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1981 + BCMA_SOC_PCI_MEM_SZ - 1;
1982 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1983 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
1984 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1985 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
1986 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
1987 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
1988 + if (pc->core->core_unit == 0) {
1989 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1990 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1991 + BCMA_SOC_PCI_MEM_SZ - 1;
1992 + pc_host->io_resource.start = 0x100;
1993 + pc_host->io_resource.end = 0x47F;
1994 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1995 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1996 + tmp | BCMA_SOC_PCI_MEM);
1997 + } else if (pc->core->core_unit == 1) {
1998 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1999 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
2000 + BCMA_SOC_PCI_MEM_SZ - 1;
2001 + pc_host->io_resource.start = 0x480;
2002 + pc_host->io_resource.end = 0x7FF;
2003 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
2004 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
2005 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2006 + tmp | BCMA_SOC_PCI1_MEM);
2007 + }
2008 + } else
2009 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2010 + BCMA_CORE_PCI_SBTOPCI_IO);
2011 +
2012 + /* 64 MB configuration access window */
2013 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2014 +
2015 + /* 1 GB memory access window */
2016 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
2017 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
2018 +
2019 +
2020 + /* As per PCI Express Base Spec 1.1 we need to wait for
2021 + * at least 100 ms from the end of a reset (cold/warm/hot)
2022 + * before issuing configuration requests to PCI Express
2023 + * devices.
2024 + */
2025 + msleep(100);
2026 +
2027 + bcma_core_pci_enable_crs(pc);
2028 +
2029 + /* Enable PCI bridge BAR0 memory & master access */
2030 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2031 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
2032 +
2033 + /* Enable PCI interrupts */
2034 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
2035 +
2036 + /* Ok, ready to run, register it to the system.
2037 + * The following needs change, if we want to port hostmode
2038 + * to non-MIPS platform. */
2039 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
2040 + resource_size(&pc_host->mem_resource));
2041 + pc_host->pci_controller.io_map_base = io_map_base;
2042 + set_io_port_base(pc_host->pci_controller.io_map_base);
2043 + /* Give some time to the PCI controller to configure itself with the new
2044 + * values. Not waiting at this point causes crashes of the machine. */
2045 + usleep_range(10000, 15000);
2046 + register_pci_controller(&pc_host->pci_controller);
2047 + return;
2048 +}
2049 +
2050 +/* Early PCI fixup for a device on the PCI-core bridge. */
2051 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
2052 +{
2053 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2054 + /* This is not a device on the PCI-core bridge. */
2055 + return;
2056 + }
2057 + if (PCI_SLOT(dev->devfn) != 0)
2058 + return;
2059 +
2060 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
2061 +
2062 + /* Enable PCI bridge bus mastering and memory space */
2063 + pci_set_master(dev);
2064 + if (pcibios_enable_device(dev, ~0) < 0) {
2065 + pr_err("PCI: BCMA bridge enable failed\n");
2066 + return;
2067 + }
2068 +
2069 + /* Enable PCI bridge BAR1 prefetch and burst */
2070 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
2071 +}
2072 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
2073 +
2074 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
2075 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
2076 +{
2077 + struct resource *res;
2078 + int pos;
2079 +
2080 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2081 + /* This is not a device on the PCI-core bridge. */
2082 + return;
2083 + }
2084 + if (PCI_SLOT(dev->devfn) == 0)
2085 + return;
2086 +
2087 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
2088 +
2089 + for (pos = 0; pos < 6; pos++) {
2090 + res = &dev->resource[pos];
2091 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
2092 + pci_assign_resource(dev, pos);
2093 + }
2094 +}
2095 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
2096 +
2097 +/* This function is called when doing a pci_enable_device().
2098 + * We must first check if the device is a device on the PCI-core bridge. */
2099 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
2100 +{
2101 + struct bcma_drv_pci_host *pc_host;
2102 +
2103 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2104 + /* This is not a device on the PCI-core bridge. */
2105 + return -ENODEV;
2106 + }
2107 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2108 + pci_ops);
2109 +
2110 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
2111 +
2112 + /* Fix up interrupt lines */
2113 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
2114 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2115 +
2116 + return 0;
2117 +}
2118 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
2119 +
2120 +/* PCI device IRQ mapping. */
2121 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
2122 +{
2123 + struct bcma_drv_pci_host *pc_host;
2124 +
2125 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2126 + /* This is not a device on the PCI-core bridge. */
2127 + return -ENODEV;
2128 + }
2129 +
2130 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2131 + pci_ops);
2132 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
2133 }
2134 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
2135 --- a/drivers/bcma/host_pci.c
2136 +++ b/drivers/bcma/host_pci.c
2137 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
2138 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
2139 core->wrap);
2140 core->bus->mapped_core = core;
2141 - pr_debug("Switched to core: 0x%X\n", core->id.id);
2142 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
2143 }
2144
2145 /* Provides access to the requested core. Returns base offset that has to be
2146 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
2147 }
2148
2149 #ifdef CONFIG_BCMA_BLOCKIO
2150 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2151 - size_t count, u16 offset, u8 reg_width)
2152 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2153 + size_t count, u16 offset, u8 reg_width)
2154 {
2155 void __iomem *addr = core->bus->mmio + offset;
2156 if (core->bus->mapped_core != core)
2157 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
2158 }
2159 }
2160
2161 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
2162 - size_t count, u16 offset, u8 reg_width)
2163 +static void bcma_host_pci_block_write(struct bcma_device *core,
2164 + const void *buffer, size_t count,
2165 + u16 offset, u8 reg_width)
2166 {
2167 void __iomem *addr = core->bus->mmio + offset;
2168 if (core->bus->mapped_core != core)
2169 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
2170 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
2171 }
2172
2173 -const struct bcma_host_ops bcma_host_pci_ops = {
2174 +static const struct bcma_host_ops bcma_host_pci_ops = {
2175 .read8 = bcma_host_pci_read8,
2176 .read16 = bcma_host_pci_read16,
2177 .read32 = bcma_host_pci_read32,
2178 @@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci
2179 .awrite32 = bcma_host_pci_awrite32,
2180 };
2181
2182 -static int bcma_host_pci_probe(struct pci_dev *dev,
2183 - const struct pci_device_id *id)
2184 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
2185 + const struct pci_device_id *id)
2186 {
2187 struct bcma_bus *bus;
2188 int err = -ENOMEM;
2189 @@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc
2190
2191 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
2192 if (!pci_is_pcie(dev))
2193 - pr_err("PCI card detected, report problems.\n");
2194 + bcma_err(bus, "PCI card detected, report problems.\n");
2195
2196 /* Map MMIO */
2197 err = -ENOMEM;
2198 @@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc
2199 bus->hosttype = BCMA_HOSTTYPE_PCI;
2200 bus->ops = &bcma_host_pci_ops;
2201
2202 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
2203 + bus->boardinfo.type = bus->host_pci->subsystem_device;
2204 +
2205 /* Register */
2206 err = bcma_bus_register(bus);
2207 if (err)
2208 @@ -222,7 +226,7 @@ err_kfree_bus:
2209 return err;
2210 }
2211
2212 -static void bcma_host_pci_remove(struct pci_dev *dev)
2213 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
2214 {
2215 struct bcma_bus *bus = pci_get_drvdata(dev);
2216
2217 @@ -265,9 +269,12 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
2218
2219 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
2220 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
2221 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
2222 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
2223 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
2224 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
2225 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
2226 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
2227 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
2228 { 0, },
2229 };
2230 @@ -277,7 +284,7 @@ static struct pci_driver bcma_pci_bridge
2231 .name = "bcma-pci-bridge",
2232 .id_table = bcma_pci_bridge_tbl,
2233 .probe = bcma_host_pci_probe,
2234 - .remove = bcma_host_pci_remove,
2235 + .remove = __devexit_p(bcma_host_pci_remove),
2236 .driver.pm = BCMA_PM_OPS,
2237 };
2238
2239 --- a/drivers/bcma/host_soc.c
2240 +++ b/drivers/bcma/host_soc.c
2241 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
2242 writel(value, core->io_wrap + offset);
2243 }
2244
2245 -const struct bcma_host_ops bcma_host_soc_ops = {
2246 +static const struct bcma_host_ops bcma_host_soc_ops = {
2247 .read8 = bcma_host_soc_read8,
2248 .read16 = bcma_host_soc_read16,
2249 .read32 = bcma_host_soc_read32,
2250 --- a/drivers/bcma/main.c
2251 +++ b/drivers/bcma/main.c
2252 @@ -7,12 +7,19 @@
2253
2254 #include "bcma_private.h"
2255 #include <linux/module.h>
2256 +#include <linux/platform_device.h>
2257 #include <linux/bcma/bcma.h>
2258 #include <linux/slab.h>
2259
2260 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
2261 MODULE_LICENSE("GPL");
2262
2263 +/* contains the number the next bus should get. */
2264 +static unsigned int bcma_bus_next_num = 0;
2265 +
2266 +/* bcma_buses_mutex locks the bcma_bus_next_num */
2267 +static DEFINE_MUTEX(bcma_buses_mutex);
2268 +
2269 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
2270 static int bcma_device_probe(struct device *dev);
2271 static int bcma_device_remove(struct device *dev);
2272 @@ -55,7 +62,14 @@ static struct bus_type bcma_bus_type = {
2273 .dev_attrs = bcma_device_attrs,
2274 };
2275
2276 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2277 +static u16 bcma_cc_core_id(struct bcma_bus *bus)
2278 +{
2279 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
2280 + return BCMA_CORE_4706_CHIPCOMMON;
2281 + return BCMA_CORE_CHIPCOMMON;
2282 +}
2283 +
2284 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2285 {
2286 struct bcma_device *core;
2287
2288 @@ -65,6 +79,19 @@ static struct bcma_device *bcma_find_cor
2289 }
2290 return NULL;
2291 }
2292 +EXPORT_SYMBOL_GPL(bcma_find_core);
2293 +
2294 +static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
2295 + u8 unit)
2296 +{
2297 + struct bcma_device *core;
2298 +
2299 + list_for_each_entry(core, &bus->cores, list) {
2300 + if (core->id.id == coreid && core->core_unit == unit)
2301 + return core;
2302 + }
2303 + return NULL;
2304 +}
2305
2306 static void bcma_release_core_dev(struct device *dev)
2307 {
2308 @@ -84,16 +111,18 @@ static int bcma_register_cores(struct bc
2309 list_for_each_entry(core, &bus->cores, list) {
2310 /* We support that cores ourself */
2311 switch (core->id.id) {
2312 + case BCMA_CORE_4706_CHIPCOMMON:
2313 case BCMA_CORE_CHIPCOMMON:
2314 case BCMA_CORE_PCI:
2315 case BCMA_CORE_PCIE:
2316 case BCMA_CORE_MIPS_74K:
2317 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
2318 continue;
2319 }
2320
2321 core->dev.release = bcma_release_core_dev;
2322 core->dev.bus = &bcma_bus_type;
2323 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
2324 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2325
2326 switch (bus->hosttype) {
2327 case BCMA_HOSTTYPE_PCI:
2328 @@ -111,41 +140,77 @@ static int bcma_register_cores(struct bc
2329
2330 err = device_register(&core->dev);
2331 if (err) {
2332 - pr_err("Could not register dev for core 0x%03X\n",
2333 - core->id.id);
2334 + bcma_err(bus,
2335 + "Could not register dev for core 0x%03X\n",
2336 + core->id.id);
2337 continue;
2338 }
2339 core->dev_registered = true;
2340 dev_id++;
2341 }
2342
2343 +#ifdef CONFIG_BCMA_SFLASH
2344 + if (bus->drv_cc.sflash.present) {
2345 + err = platform_device_register(&bcma_sflash_dev);
2346 + if (err)
2347 + bcma_err(bus, "Error registering serial flash\n");
2348 + }
2349 +#endif
2350 +
2351 +#ifdef CONFIG_BCMA_NFLASH
2352 + if (bus->drv_cc.nflash.present) {
2353 + err = platform_device_register(&bcma_nflash_dev);
2354 + if (err)
2355 + bcma_err(bus, "Error registering NAND flash\n");
2356 + }
2357 +#endif
2358 +
2359 return 0;
2360 }
2361
2362 static void bcma_unregister_cores(struct bcma_bus *bus)
2363 {
2364 - struct bcma_device *core;
2365 + struct bcma_device *core, *tmp;
2366
2367 - list_for_each_entry(core, &bus->cores, list) {
2368 + list_for_each_entry_safe(core, tmp, &bus->cores, list) {
2369 + list_del(&core->list);
2370 if (core->dev_registered)
2371 device_unregister(&core->dev);
2372 }
2373 }
2374
2375 -int bcma_bus_register(struct bcma_bus *bus)
2376 +int __devinit bcma_bus_register(struct bcma_bus *bus)
2377 {
2378 int err;
2379 struct bcma_device *core;
2380
2381 + mutex_lock(&bcma_buses_mutex);
2382 + bus->num = bcma_bus_next_num++;
2383 + mutex_unlock(&bcma_buses_mutex);
2384 +
2385 /* Scan for devices (cores) */
2386 err = bcma_bus_scan(bus);
2387 if (err) {
2388 - pr_err("Failed to scan: %d\n", err);
2389 + bcma_err(bus, "Failed to scan: %d\n", err);
2390 return -1;
2391 }
2392
2393 + /* Early init CC core */
2394 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2395 + if (core) {
2396 + bus->drv_cc.core = core;
2397 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2398 + }
2399 +
2400 + /* Try to get SPROM */
2401 + err = bcma_sprom_get(bus);
2402 + if (err == -ENOENT) {
2403 + bcma_err(bus, "No SPROM available\n");
2404 + } else if (err)
2405 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
2406 +
2407 /* Init CC core */
2408 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
2409 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2410 if (core) {
2411 bus->drv_cc.core = core;
2412 bcma_core_chipcommon_init(&bus->drv_cc);
2413 @@ -159,30 +224,47 @@ int bcma_bus_register(struct bcma_bus *b
2414 }
2415
2416 /* Init PCIE core */
2417 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
2418 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
2419 if (core) {
2420 - bus->drv_pci.core = core;
2421 - bcma_core_pci_init(&bus->drv_pci);
2422 + bus->drv_pci[0].core = core;
2423 + bcma_core_pci_init(&bus->drv_pci[0]);
2424 }
2425
2426 - /* Try to get SPROM */
2427 - err = bcma_sprom_get(bus);
2428 - if (err == -ENOENT) {
2429 - pr_err("No SPROM available\n");
2430 - } else if (err)
2431 - pr_err("Failed to get SPROM: %d\n", err);
2432 + /* Init PCIE core */
2433 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
2434 + if (core) {
2435 + bus->drv_pci[1].core = core;
2436 + bcma_core_pci_init(&bus->drv_pci[1]);
2437 + }
2438 +
2439 + /* Init GBIT MAC COMMON core */
2440 + core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
2441 + if (core) {
2442 + bus->drv_gmac_cmn.core = core;
2443 + bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
2444 + }
2445
2446 /* Register found cores */
2447 bcma_register_cores(bus);
2448
2449 - pr_info("Bus registered\n");
2450 + bcma_info(bus, "Bus registered\n");
2451
2452 return 0;
2453 }
2454
2455 void bcma_bus_unregister(struct bcma_bus *bus)
2456 {
2457 + struct bcma_device *cores[3];
2458 +
2459 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2460 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
2461 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
2462 +
2463 bcma_unregister_cores(bus);
2464 +
2465 + kfree(cores[2]);
2466 + kfree(cores[1]);
2467 + kfree(cores[0]);
2468 }
2469
2470 int __init bcma_bus_early_register(struct bcma_bus *bus,
2471 @@ -196,14 +278,14 @@ int __init bcma_bus_early_register(struc
2472 bcma_init_bus(bus);
2473
2474 match.manuf = BCMA_MANUF_BCM;
2475 - match.id = BCMA_CORE_CHIPCOMMON;
2476 + match.id = bcma_cc_core_id(bus);
2477 match.class = BCMA_CL_SIM;
2478 match.rev = BCMA_ANY_REV;
2479
2480 /* Scan for chip common core */
2481 err = bcma_bus_scan_early(bus, &match, core_cc);
2482 if (err) {
2483 - pr_err("Failed to scan for common core: %d\n", err);
2484 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
2485 return -1;
2486 }
2487
2488 @@ -215,25 +297,25 @@ int __init bcma_bus_early_register(struc
2489 /* Scan for mips core */
2490 err = bcma_bus_scan_early(bus, &match, core_mips);
2491 if (err) {
2492 - pr_err("Failed to scan for mips core: %d\n", err);
2493 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
2494 return -1;
2495 }
2496
2497 - /* Init CC core */
2498 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
2499 + /* Early init CC core */
2500 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2501 if (core) {
2502 bus->drv_cc.core = core;
2503 - bcma_core_chipcommon_init(&bus->drv_cc);
2504 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2505 }
2506
2507 - /* Init MIPS core */
2508 + /* Early init MIPS core */
2509 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2510 if (core) {
2511 bus->drv_mips.core = core;
2512 - bcma_core_mips_init(&bus->drv_mips);
2513 + bcma_core_mips_early_init(&bus->drv_mips);
2514 }
2515
2516 - pr_info("Early bus registered\n");
2517 + bcma_info(bus, "Early bus registered\n");
2518
2519 return 0;
2520 }
2521 @@ -259,8 +341,7 @@ int bcma_bus_resume(struct bcma_bus *bus
2522 struct bcma_device *core;
2523
2524 /* Init CC core */
2525 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
2526 - if (core) {
2527 + if (bus->drv_cc.core) {
2528 bus->drv_cc.setup_done = false;
2529 bcma_core_chipcommon_init(&bus->drv_cc);
2530 }
2531 --- a/drivers/bcma/scan.c
2532 +++ b/drivers/bcma/scan.c
2533 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
2534 u16 id;
2535 const char *name;
2536 };
2537 -struct bcma_device_id_name bcma_device_names[] = {
2538 +
2539 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
2540 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
2541 + { BCMA_CORE_ARM_1176, "ARM 1176" },
2542 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
2543 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
2544 +};
2545 +
2546 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
2547 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
2548 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
2549 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
2550 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
2551 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
2552 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
2553 { BCMA_CORE_INVALID, "Invalid" },
2554 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
2555 { BCMA_CORE_ILINE20, "ILine 20" },
2556 { BCMA_CORE_SRAM, "SRAM" },
2557 { BCMA_CORE_SDRAM, "SDRAM" },
2558 { BCMA_CORE_PCI, "PCI" },
2559 - { BCMA_CORE_MIPS, "MIPS" },
2560 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
2561 { BCMA_CORE_V90, "V90" },
2562 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
2563 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
2564 { BCMA_CORE_PHY_A, "PHY A" },
2565 { BCMA_CORE_PHY_B, "PHY B" },
2566 { BCMA_CORE_PHY_G, "PHY G" },
2567 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
2568 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
2569 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
2570 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
2571 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
2572 { BCMA_CORE_PHY_N, "PHY N" },
2573 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
2574 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
2575 - { BCMA_CORE_ARM_1176, "ARM 1176" },
2576 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
2577 { BCMA_CORE_PHY_LP, "PHY LP" },
2578 { BCMA_CORE_PMU, "PMU" },
2579 { BCMA_CORE_PHY_SSN, "PHY SSN" },
2580 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
2581 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
2582 { BCMA_CORE_PHY_HT, "PHY HT" },
2583 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
2584 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
2585 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
2586 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
2587 @@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
2588 { BCMA_CORE_SHIM, "SHIM" },
2589 { BCMA_CORE_DEFAULT, "Default" },
2590 };
2591 -const char *bcma_device_name(struct bcma_device_id *id)
2592 +
2593 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
2594 + { BCMA_CORE_MIPS, "MIPS" },
2595 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
2596 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
2597 +};
2598 +
2599 +static const char *bcma_device_name(const struct bcma_device_id *id)
2600 {
2601 - int i;
2602 + const struct bcma_device_id_name *names;
2603 + int size, i;
2604
2605 - if (id->manuf == BCMA_MANUF_BCM) {
2606 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
2607 - if (bcma_device_names[i].id == id->id)
2608 - return bcma_device_names[i].name;
2609 - }
2610 + /* search manufacturer specific names */
2611 + switch (id->manuf) {
2612 + case BCMA_MANUF_ARM:
2613 + names = bcma_arm_device_names;
2614 + size = ARRAY_SIZE(bcma_arm_device_names);
2615 + break;
2616 + case BCMA_MANUF_BCM:
2617 + names = bcma_bcm_device_names;
2618 + size = ARRAY_SIZE(bcma_bcm_device_names);
2619 + break;
2620 + case BCMA_MANUF_MIPS:
2621 + names = bcma_mips_device_names;
2622 + size = ARRAY_SIZE(bcma_mips_device_names);
2623 + break;
2624 + default:
2625 + return "UNKNOWN";
2626 }
2627 +
2628 + for (i = 0; i < size; i++) {
2629 + if (names[i].id == id->id)
2630 + return names[i].name;
2631 + }
2632 +
2633 return "UNKNOWN";
2634 }
2635
2636 @@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
2637 return NULL;
2638 }
2639
2640 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
2641 +{
2642 + struct bcma_device *core;
2643 +
2644 + list_for_each_entry_reverse(core, &bus->cores, list) {
2645 + if (core->id.id == coreid)
2646 + return core;
2647 + }
2648 + return NULL;
2649 +}
2650 +
2651 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
2652 struct bcma_device_id *match, int core_num,
2653 struct bcma_device *core)
2654 @@ -252,11 +295,15 @@ static int bcma_get_next_core(struct bcm
2655
2656 /* check if component is a core at all */
2657 if (wrappers[0] + wrappers[1] == 0) {
2658 - /* we could save addrl of the router
2659 - if (cid == BCMA_CORE_OOB_ROUTER)
2660 - */
2661 - bcma_erom_skip_component(bus, eromptr);
2662 - return -ENXIO;
2663 + /* Some specific cores don't need wrappers */
2664 + switch (core->id.id) {
2665 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
2666 + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
2667 + break;
2668 + default:
2669 + bcma_erom_skip_component(bus, eromptr);
2670 + return -ENXIO;
2671 + }
2672 }
2673
2674 if (bcma_erom_is_bridge(bus, eromptr)) {
2675 @@ -286,6 +333,23 @@ static int bcma_get_next_core(struct bcm
2676 return -EILSEQ;
2677 }
2678
2679 + /* First Slave Address Descriptor should be port 0:
2680 + * the main register space for the core
2681 + */
2682 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
2683 + if (tmp <= 0) {
2684 + /* Try again to see if it is a bridge */
2685 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2686 + SCAN_ADDR_TYPE_BRIDGE, 0);
2687 + if (tmp <= 0) {
2688 + return -EILSEQ;
2689 + } else {
2690 + bcma_info(bus, "Bridge found\n");
2691 + return -ENXIO;
2692 + }
2693 + }
2694 + core->addr = tmp;
2695 +
2696 /* get & parse slave ports */
2697 for (i = 0; i < ports[1]; i++) {
2698 for (j = 0; ; j++) {
2699 @@ -298,7 +362,7 @@ static int bcma_get_next_core(struct bcm
2700 break;
2701 } else {
2702 if (i == 0 && j == 0)
2703 - core->addr = tmp;
2704 + core->addr1 = tmp;
2705 }
2706 }
2707 }
2708 @@ -353,6 +417,7 @@ static int bcma_get_next_core(struct bcm
2709 void bcma_init_bus(struct bcma_bus *bus)
2710 {
2711 s32 tmp;
2712 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
2713
2714 if (bus->init_done)
2715 return;
2716 @@ -363,9 +428,12 @@ void bcma_init_bus(struct bcma_bus *bus)
2717 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
2718
2719 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
2720 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2721 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2722 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2723 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2724 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2725 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2726 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2727 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
2728 +
2729 bus->init_done = true;
2730 }
2731
2732 @@ -392,9 +460,12 @@ int bcma_bus_scan(struct bcma_bus *bus)
2733 bcma_scan_switch_core(bus, erombase);
2734
2735 while (eromptr < eromend) {
2736 + struct bcma_device *other_core;
2737 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
2738 - if (!core)
2739 - return -ENOMEM;
2740 + if (!core) {
2741 + err = -ENOMEM;
2742 + goto out;
2743 + }
2744 INIT_LIST_HEAD(&core->list);
2745 core->bus = bus;
2746
2747 @@ -409,25 +480,28 @@ int bcma_bus_scan(struct bcma_bus *bus)
2748 } else if (err == -ESPIPE) {
2749 break;
2750 }
2751 - return err;
2752 + goto out;
2753 }
2754
2755 core->core_index = core_num++;
2756 bus->nr_cores++;
2757 + other_core = bcma_find_core_reverse(bus, core->id.id);
2758 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
2759
2760 - pr_info("Core %d found: %s "
2761 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2762 - core->core_index, bcma_device_name(&core->id),
2763 - core->id.manuf, core->id.id, core->id.rev,
2764 - core->id.class);
2765 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2766 + core->core_index, bcma_device_name(&core->id),
2767 + core->id.manuf, core->id.id, core->id.rev,
2768 + core->id.class);
2769
2770 - list_add(&core->list, &bus->cores);
2771 + list_add_tail(&core->list, &bus->cores);
2772 }
2773
2774 + err = 0;
2775 +out:
2776 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2777 iounmap(eromptr);
2778
2779 - return 0;
2780 + return err;
2781 }
2782
2783 int __init bcma_bus_scan_early(struct bcma_bus *bus,
2784 @@ -467,21 +541,21 @@ int __init bcma_bus_scan_early(struct bc
2785 else if (err == -ESPIPE)
2786 break;
2787 else if (err < 0)
2788 - return err;
2789 + goto out;
2790
2791 core->core_index = core_num++;
2792 bus->nr_cores++;
2793 - pr_info("Core %d found: %s "
2794 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2795 - core->core_index, bcma_device_name(&core->id),
2796 - core->id.manuf, core->id.id, core->id.rev,
2797 - core->id.class);
2798 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2799 + core->core_index, bcma_device_name(&core->id),
2800 + core->id.manuf, core->id.id, core->id.rev,
2801 + core->id.class);
2802
2803 - list_add(&core->list, &bus->cores);
2804 + list_add_tail(&core->list, &bus->cores);
2805 err = 0;
2806 break;
2807 }
2808
2809 +out:
2810 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2811 iounmap(eromptr);
2812
2813 --- a/drivers/bcma/scan.h
2814 +++ b/drivers/bcma/scan.h
2815 @@ -27,7 +27,7 @@
2816 #define SCAN_CIB_NMW 0x0007C000
2817 #define SCAN_CIB_NMW_SHIFT 14
2818 #define SCAN_CIB_NSW 0x00F80000
2819 -#define SCAN_CIB_NSW_SHIFT 17
2820 +#define SCAN_CIB_NSW_SHIFT 19
2821 #define SCAN_CIB_REV 0xFF000000
2822 #define SCAN_CIB_REV_SHIFT 24
2823
2824 --- a/drivers/bcma/sprom.c
2825 +++ b/drivers/bcma/sprom.c
2826 @@ -2,6 +2,8 @@
2827 * Broadcom specific AMBA
2828 * SPROM reading
2829 *
2830 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2831 + *
2832 * Licensed under the GNU/GPL. See COPYING for details.
2833 */
2834
2835 @@ -14,7 +16,57 @@
2836 #include <linux/dma-mapping.h>
2837 #include <linux/slab.h>
2838
2839 -#define SPOFF(offset) ((offset) / sizeof(u16))
2840 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
2841 +
2842 +/**
2843 + * bcma_arch_register_fallback_sprom - Registers a method providing a
2844 + * fallback SPROM if no SPROM is found.
2845 + *
2846 + * @sprom_callback: The callback function.
2847 + *
2848 + * With this function the architecture implementation may register a
2849 + * callback handler which fills the SPROM data structure. The fallback is
2850 + * used for PCI based BCMA devices, where no valid SPROM can be found
2851 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
2852 + * to controll the system bus.
2853 + *
2854 + * This function is useful for weird architectures that have a half-assed
2855 + * BCMA device hardwired to their PCI bus.
2856 + *
2857 + * This function is available for architecture code, only. So it is not
2858 + * exported.
2859 + */
2860 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
2861 + struct ssb_sprom *out))
2862 +{
2863 + if (get_fallback_sprom)
2864 + return -EEXIST;
2865 + get_fallback_sprom = sprom_callback;
2866 +
2867 + return 0;
2868 +}
2869 +
2870 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
2871 + struct ssb_sprom *out)
2872 +{
2873 + int err;
2874 +
2875 + if (!get_fallback_sprom) {
2876 + err = -ENOENT;
2877 + goto fail;
2878 + }
2879 +
2880 + err = get_fallback_sprom(bus, out);
2881 + if (err)
2882 + goto fail;
2883 +
2884 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
2885 + bus->sprom.revision);
2886 + return 0;
2887 +fail:
2888 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
2889 + return err;
2890 +}
2891
2892 /**************************************************
2893 * R/W ops.
2894 @@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
2895 * SPROM extraction.
2896 **************************************************/
2897
2898 +#define SPOFF(offset) ((offset) / sizeof(u16))
2899 +
2900 +#define SPEX(_field, _offset, _mask, _shift) \
2901 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
2902 +
2903 +#define SPEX32(_field, _offset, _mask, _shift) \
2904 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
2905 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
2906 +
2907 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
2908 + do { \
2909 + SPEX(_field[0], _offset + 0, _mask, _shift); \
2910 + SPEX(_field[1], _offset + 2, _mask, _shift); \
2911 + SPEX(_field[2], _offset + 4, _mask, _shift); \
2912 + SPEX(_field[3], _offset + 6, _mask, _shift); \
2913 + SPEX(_field[4], _offset + 8, _mask, _shift); \
2914 + SPEX(_field[5], _offset + 10, _mask, _shift); \
2915 + SPEX(_field[6], _offset + 12, _mask, _shift); \
2916 + SPEX(_field[7], _offset + 14, _mask, _shift); \
2917 + } while (0)
2918 +
2919 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
2920 {
2921 - u16 v;
2922 + u16 v, o;
2923 int i;
2924 + u16 pwr_info_offset[] = {
2925 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
2926 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
2927 + };
2928 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2929 + ARRAY_SIZE(bus->sprom.core_pwr_info));
2930
2931 bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2932 SSB_SPROM_REVISION_REV;
2933 @@ -137,107 +216,390 @@ static void bcma_sprom_extract_r8(struct
2934 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
2935 }
2936
2937 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
2938 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2939 +
2940 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2941 + SSB_SPROM4_TXPID2G0_SHIFT);
2942 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
2943 + SSB_SPROM4_TXPID2G1_SHIFT);
2944 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
2945 + SSB_SPROM4_TXPID2G2_SHIFT);
2946 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
2947 + SSB_SPROM4_TXPID2G3_SHIFT);
2948 +
2949 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
2950 + SSB_SPROM4_TXPID5GL0_SHIFT);
2951 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
2952 + SSB_SPROM4_TXPID5GL1_SHIFT);
2953 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
2954 + SSB_SPROM4_TXPID5GL2_SHIFT);
2955 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
2956 + SSB_SPROM4_TXPID5GL3_SHIFT);
2957 +
2958 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
2959 + SSB_SPROM4_TXPID5G0_SHIFT);
2960 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
2961 + SSB_SPROM4_TXPID5G1_SHIFT);
2962 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
2963 + SSB_SPROM4_TXPID5G2_SHIFT);
2964 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
2965 + SSB_SPROM4_TXPID5G3_SHIFT);
2966 +
2967 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
2968 + SSB_SPROM4_TXPID5GH0_SHIFT);
2969 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
2970 + SSB_SPROM4_TXPID5GH1_SHIFT);
2971 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
2972 + SSB_SPROM4_TXPID5GH2_SHIFT);
2973 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
2974 + SSB_SPROM4_TXPID5GH3_SHIFT);
2975 +
2976 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
2977 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
2978 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
2979 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
2980 +
2981 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
2982 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
2983 +
2984 + /* Extract cores power info info */
2985 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
2986 + o = pwr_info_offset[i];
2987 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2988 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
2989 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2990 + SSB_SPROM8_2G_MAXP, 0);
2991 +
2992 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
2993 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
2994 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
2995 +
2996 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2997 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
2998 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2999 + SSB_SPROM8_5G_MAXP, 0);
3000 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
3001 + SSB_SPROM8_5GH_MAXP, 0);
3002 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
3003 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
3004 +
3005 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
3006 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
3007 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
3008 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
3009 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
3010 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
3011 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
3012 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
3013 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
3014 + }
3015
3016 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3017 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
3018 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3019 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
3020 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3021 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
3022 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3023 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
3024 -
3025 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3026 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
3027 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3028 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
3029 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3030 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
3031 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3032 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
3033 -
3034 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3035 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
3036 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3037 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
3038 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3039 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
3040 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3041 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
3042 -
3043 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3044 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
3045 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3046 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
3047 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3048 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
3049 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3050 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
3051 -
3052 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
3053 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
3054 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
3055 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
3056 -
3057 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
3058 -
3059 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3060 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3061 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3062 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3063 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3064 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3065 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3066 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3067 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3068 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3069 -
3070 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3071 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3072 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3073 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3074 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3075 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3076 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3077 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3078 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3079 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3080 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
3081 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3082 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
3083 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3084 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
3085 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3086 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
3087 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3088 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
3089 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3090 +
3091 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
3092 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3093 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
3094 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3095 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
3096 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3097 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
3098 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3099 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
3100 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3101 +
3102 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
3103 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
3104 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
3105 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
3106 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
3107 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
3108 + SSB_SPROM8_ITSSI_BG_SHIFT);
3109 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
3110 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
3111 + SSB_SPROM8_ITSSI_A_SHIFT);
3112 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
3113 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
3114 + SSB_SPROM8_MAXP_AL_SHIFT);
3115 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
3116 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
3117 + SSB_SPROM8_GPIOA_P1_SHIFT);
3118 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
3119 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
3120 + SSB_SPROM8_GPIOB_P3_SHIFT);
3121 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
3122 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
3123 + SSB_SPROM8_TRI5G_SHIFT);
3124 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
3125 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
3126 + SSB_SPROM8_TRI5GH_SHIFT);
3127 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
3128 + SSB_SPROM8_RXPO2G_SHIFT);
3129 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
3130 + SSB_SPROM8_RXPO5G_SHIFT);
3131 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
3132 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
3133 + SSB_SPROM8_RSSISMC2G_SHIFT);
3134 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
3135 + SSB_SPROM8_RSSISAV2G_SHIFT);
3136 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
3137 + SSB_SPROM8_BXA2G_SHIFT);
3138 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
3139 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
3140 + SSB_SPROM8_RSSISMC5G_SHIFT);
3141 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
3142 + SSB_SPROM8_RSSISAV5G_SHIFT);
3143 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
3144 + SSB_SPROM8_BXA5G_SHIFT);
3145 +
3146 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
3147 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
3148 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
3149 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
3150 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
3151 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
3152 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
3153 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
3154 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
3155 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
3156 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
3157 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
3158 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
3159 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
3160 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
3161 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
3162 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
3163 +
3164 + /* Extract the antenna gain values. */
3165 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
3166 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
3167 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
3168 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
3169 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
3170 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
3171 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
3172 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
3173 +
3174 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
3175 + SSB_SPROM8_LEDDC_ON_SHIFT);
3176 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
3177 + SSB_SPROM8_LEDDC_OFF_SHIFT);
3178 +
3179 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
3180 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
3181 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
3182 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
3183 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
3184 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
3185 +
3186 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
3187 +
3188 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
3189 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
3190 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
3191 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
3192 +
3193 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
3194 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
3195 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
3196 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
3197 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
3198 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
3199 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
3200 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
3201 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
3202 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
3203 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
3204 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
3205 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
3206 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
3207 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
3208 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
3209 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
3210 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
3211 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
3212 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
3213 +
3214 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
3215 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
3216 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
3217 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
3218 +
3219 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
3220 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
3221 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
3222 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
3223 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
3224 + SSB_SPROM8_TEMPDELTA_PHYCAL,
3225 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
3226 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
3227 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
3228 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
3229 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
3230 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
3231 +}
3232 +
3233 +/*
3234 + * Indicates the presence of external SPROM.
3235 + */
3236 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
3237 +{
3238 + u32 chip_status;
3239 + u32 srom_control;
3240 + u32 present_mask;
3241 +
3242 + if (bus->drv_cc.core->id.rev >= 31) {
3243 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3244 + return false;
3245 +
3246 + srom_control = bcma_read32(bus->drv_cc.core,
3247 + BCMA_CC_SROM_CONTROL);
3248 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
3249 + }
3250 +
3251 + /* older chipcommon revisions use chip status register */
3252 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3253 + switch (bus->chipinfo.id) {
3254 + case BCMA_CHIP_ID_BCM4313:
3255 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
3256 + break;
3257 +
3258 + case BCMA_CHIP_ID_BCM4331:
3259 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
3260 + break;
3261 +
3262 + default:
3263 + return true;
3264 + }
3265 +
3266 + return chip_status & present_mask;
3267 +}
3268 +
3269 +/*
3270 + * Indicates that on-chip OTP memory is present and enabled.
3271 + */
3272 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
3273 +{
3274 + u32 chip_status;
3275 + u32 otpsize = 0;
3276 + bool present;
3277 +
3278 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3279 + switch (bus->chipinfo.id) {
3280 + case BCMA_CHIP_ID_BCM4313:
3281 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
3282 + break;
3283 +
3284 + case BCMA_CHIP_ID_BCM4331:
3285 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
3286 + break;
3287 +
3288 + case BCMA_CHIP_ID_BCM43224:
3289 + case BCMA_CHIP_ID_BCM43225:
3290 + /* for these chips OTP is always available */
3291 + present = true;
3292 + break;
3293 + case BCMA_CHIP_ID_BCM43227:
3294 + case BCMA_CHIP_ID_BCM43228:
3295 + case BCMA_CHIP_ID_BCM43428:
3296 + present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
3297 + break;
3298 + default:
3299 + present = false;
3300 + break;
3301 + }
3302 +
3303 + if (present) {
3304 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
3305 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
3306 + }
3307 +
3308 + return otpsize != 0;
3309 +}
3310 +
3311 +/*
3312 + * Verify OTP is filled and determine the byte
3313 + * offset where SPROM data is located.
3314 + *
3315 + * On error, returns 0; byte offset otherwise.
3316 + */
3317 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
3318 +{
3319 + struct bcma_device *cc = bus->drv_cc.core;
3320 + u32 offset;
3321 +
3322 + /* verify OTP status */
3323 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
3324 + return 0;
3325 +
3326 + /* obtain bit offset from otplayout register */
3327 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
3328 + return BCMA_CC_SPROM + (offset >> 3);
3329 }
3330
3331 int bcma_sprom_get(struct bcma_bus *bus)
3332 {
3333 - u16 offset;
3334 + u16 offset = BCMA_CC_SPROM;
3335 u16 *sprom;
3336 int err = 0;
3337
3338 if (!bus->drv_cc.core)
3339 return -EOPNOTSUPP;
3340
3341 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3342 - return -ENOENT;
3343 + if (!bcma_sprom_ext_available(bus)) {
3344 + bool sprom_onchip;
3345 +
3346 + /*
3347 + * External SPROM takes precedence so check
3348 + * on-chip OTP only when no external SPROM
3349 + * is present.
3350 + */
3351 + sprom_onchip = bcma_sprom_onchip_available(bus);
3352 + if (sprom_onchip) {
3353 + /* determine offset */
3354 + offset = bcma_sprom_onchip_offset(bus);
3355 + }
3356 + if (!offset || !sprom_onchip) {
3357 + /*
3358 + * Maybe there is no SPROM on the device?
3359 + * Now we ask the arch code if there is some sprom
3360 + * available for this device in some other storage.
3361 + */
3362 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3363 + return err;
3364 + }
3365 + }
3366
3367 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
3368 GFP_KERNEL);
3369 if (!sprom)
3370 return -ENOMEM;
3371
3372 - if (bus->chipinfo.id == 0x4331)
3373 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3374 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3375 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
3376
3377 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
3378 - * According to brcm80211 this applies to cards with PCIe rev >= 6
3379 - * TODO: understand this condition and use it */
3380 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
3381 - BCMA_CC_SPROM_PCIE6;
3382 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
3383 bcma_sprom_read(bus, offset, sprom);
3384
3385 - if (bus->chipinfo.id == 0x4331)
3386 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3387 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3388 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
3389
3390 err = bcma_sprom_valid(sprom);
3391 - if (err)
3392 + if (err) {
3393 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
3394 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3395 goto out;
3396 + }
3397
3398 bcma_sprom_extract_r8(bus, sprom);
3399
3400 --- a/include/linux/bcma/bcma.h
3401 +++ b/include/linux/bcma/bcma.h
3402 @@ -7,9 +7,10 @@
3403 #include <linux/bcma/bcma_driver_chipcommon.h>
3404 #include <linux/bcma/bcma_driver_pci.h>
3405 #include <linux/bcma/bcma_driver_mips.h>
3406 +#include <linux/bcma/bcma_driver_gmac_cmn.h>
3407 #include <linux/ssb/ssb.h> /* SPROM sharing */
3408
3409 -#include "bcma_regs.h"
3410 +#include <linux/bcma/bcma_regs.h>
3411
3412 struct bcma_device;
3413 struct bcma_bus;
3414 @@ -26,6 +27,11 @@ struct bcma_chipinfo {
3415 u8 pkg;
3416 };
3417
3418 +struct bcma_boardinfo {
3419 + u16 vendor;
3420 + u16 type;
3421 +};
3422 +
3423 enum bcma_clkmode {
3424 BCMA_CLKMODE_FAST,
3425 BCMA_CLKMODE_DYNAMIC,
3426 @@ -65,6 +71,13 @@ struct bcma_host_ops {
3427
3428 /* Core-ID values. */
3429 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
3430 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
3431 +#define BCMA_CORE_4706_SOC_RAM 0x50E
3432 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
3433 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
3434 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
3435 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
3436 +#define BCMA_CORE_DDR23_PHY 0x5DD
3437 #define BCMA_CORE_INVALID 0x700
3438 #define BCMA_CORE_CHIPCOMMON 0x800
3439 #define BCMA_CORE_ILINE20 0x801
3440 @@ -125,6 +138,36 @@ struct bcma_host_ops {
3441
3442 #define BCMA_MAX_NR_CORES 16
3443
3444 +/* Chip IDs of PCIe devices */
3445 +#define BCMA_CHIP_ID_BCM4313 0x4313
3446 +#define BCMA_CHIP_ID_BCM43224 43224
3447 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
3448 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
3449 +#define BCMA_CHIP_ID_BCM43225 43225
3450 +#define BCMA_CHIP_ID_BCM43227 43227
3451 +#define BCMA_CHIP_ID_BCM43228 43228
3452 +#define BCMA_CHIP_ID_BCM43421 43421
3453 +#define BCMA_CHIP_ID_BCM43428 43428
3454 +#define BCMA_CHIP_ID_BCM43431 43431
3455 +#define BCMA_CHIP_ID_BCM43460 43460
3456 +#define BCMA_CHIP_ID_BCM4331 0x4331
3457 +#define BCMA_CHIP_ID_BCM6362 0x6362
3458 +#define BCMA_CHIP_ID_BCM4360 0x4360
3459 +#define BCMA_CHIP_ID_BCM4352 0x4352
3460 +
3461 +/* Chip IDs of SoCs */
3462 +#define BCMA_CHIP_ID_BCM4706 0x5300
3463 +#define BCMA_CHIP_ID_BCM4716 0x4716
3464 +#define BCMA_PKG_ID_BCM4716 8
3465 +#define BCMA_PKG_ID_BCM4717 9
3466 +#define BCMA_PKG_ID_BCM4718 10
3467 +#define BCMA_CHIP_ID_BCM47162 47162
3468 +#define BCMA_CHIP_ID_BCM4748 0x4748
3469 +#define BCMA_CHIP_ID_BCM4749 0x4749
3470 +#define BCMA_CHIP_ID_BCM5356 0x5356
3471 +#define BCMA_CHIP_ID_BCM5357 0x5357
3472 +#define BCMA_CHIP_ID_BCM53572 53572
3473 +
3474 struct bcma_device {
3475 struct bcma_bus *bus;
3476 struct bcma_device_id id;
3477 @@ -136,8 +179,10 @@ struct bcma_device {
3478 bool dev_registered;
3479
3480 u8 core_index;
3481 + u8 core_unit;
3482
3483 u32 addr;
3484 + u32 addr1;
3485 u32 wrap;
3486
3487 void __iomem *io_addr;
3488 @@ -175,6 +220,12 @@ int __bcma_driver_register(struct bcma_d
3489
3490 extern void bcma_driver_unregister(struct bcma_driver *drv);
3491
3492 +/* Set a fallback SPROM.
3493 + * See kdoc at the function definition for complete documentation. */
3494 +extern int bcma_arch_register_fallback_sprom(
3495 + int (*sprom_callback)(struct bcma_bus *bus,
3496 + struct ssb_sprom *out));
3497 +
3498 struct bcma_bus {
3499 /* The MMIO area. */
3500 void __iomem *mmio;
3501 @@ -191,14 +242,18 @@ struct bcma_bus {
3502
3503 struct bcma_chipinfo chipinfo;
3504
3505 + struct bcma_boardinfo boardinfo;
3506 +
3507 struct bcma_device *mapped_core;
3508 struct list_head cores;
3509 u8 nr_cores;
3510 u8 init_done:1;
3511 + u8 num;
3512
3513 struct bcma_drv_cc drv_cc;
3514 - struct bcma_drv_pci drv_pci;
3515 + struct bcma_drv_pci drv_pci[2];
3516 struct bcma_drv_mips drv_mips;
3517 + struct bcma_drv_gmac_cmn drv_gmac_cmn;
3518
3519 /* We decided to share SPROM struct with SSB as long as we do not need
3520 * any hacks for BCMA. This simplifies drivers code. */
3521 @@ -282,6 +337,7 @@ static inline void bcma_maskset16(struct
3522 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
3523 }
3524
3525 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
3526 extern bool bcma_core_is_enabled(struct bcma_device *core);
3527 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
3528 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
3529 --- a/include/linux/bcma/bcma_driver_chipcommon.h
3530 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
3531 @@ -24,7 +24,7 @@
3532 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
3533 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
3534 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
3535 -#define BCMA_CC_FLASHT_NFLASH 0x00000200
3536 +#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
3537 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
3538 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
3539 #define BCMA_PLLTYPE_NONE 0x00000000
3540 @@ -45,6 +45,7 @@
3541 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
3542 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
3543 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
3544 +#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
3545 #define BCMA_CC_CORECTL 0x0008
3546 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
3547 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3548 @@ -56,6 +57,9 @@
3549 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
3550 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
3551 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
3552 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
3553 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
3554 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
3555 #define BCMA_CC_OTPC 0x0014 /* OTP control */
3556 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
3557 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
3558 @@ -72,6 +76,8 @@
3559 #define BCMA_CC_OTPP_READ 0x40000000
3560 #define BCMA_CC_OTPP_START 0x80000000
3561 #define BCMA_CC_OTPP_BUSY 0x80000000
3562 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
3563 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
3564 #define BCMA_CC_IRQSTAT 0x0020
3565 #define BCMA_CC_IRQMASK 0x0024
3566 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
3567 @@ -79,6 +85,22 @@
3568 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
3569 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
3570 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
3571 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
3572 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
3573 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
3574 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
3575 +#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
3576 +#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
3577 +#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
3578 +#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
3579 +#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
3580 +#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
3581 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
3582 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
3583 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
3584 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
3585 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
3586 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
3587 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
3588 #define BCMA_CC_JCMD_START 0x80000000
3589 #define BCMA_CC_JCMD_BUSY 0x80000000
3590 @@ -108,10 +130,58 @@
3591 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
3592 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
3593 #define BCMA_CC_FLASHCTL 0x0040
3594 +/* Start/busy bit in flashcontrol */
3595 +#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
3596 +#define BCMA_CC_FLASHCTL_ACTION 0x00000700
3597 +#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
3598 #define BCMA_CC_FLASHCTL_START 0x80000000
3599 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
3600 +/* Flashcontrol action + opcodes for ST flashes */
3601 +#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
3602 +#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
3603 +#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
3604 +#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
3605 +#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
3606 +#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
3607 +#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
3608 +#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
3609 +#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
3610 +#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
3611 +#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
3612 +#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
3613 +/* Flashcontrol action + opcodes for Atmel flashes */
3614 +#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
3615 +#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
3616 +#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
3617 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
3618 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
3619 +#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
3620 +#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
3621 +#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
3622 +#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
3623 +#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
3624 +#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
3625 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
3626 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
3627 +#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
3628 +#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
3629 +#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
3630 +#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
3631 +#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
3632 +#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
3633 #define BCMA_CC_FLASHADDR 0x0044
3634 #define BCMA_CC_FLASHDATA 0x0048
3635 +/* Status register bits for ST flashes */
3636 +#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
3637 +#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
3638 +#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
3639 +#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
3640 +#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
3641 +/* Status register bits for Atmel flashes */
3642 +#define BCMA_CC_FLASHDATA_AT_READY 0x80
3643 +#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
3644 +#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
3645 +#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
3646 #define BCMA_CC_BCAST_ADDR 0x0050
3647 #define BCMA_CC_BCAST_DATA 0x0054
3648 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3649 @@ -181,6 +251,45 @@
3650 #define BCMA_CC_FLASH_CFG 0x0128
3651 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
3652 #define BCMA_CC_FLASH_WAITCNT 0x012C
3653 +#define BCMA_CC_SROM_CONTROL 0x0190
3654 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
3655 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
3656 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
3657 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
3658 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
3659 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
3660 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
3661 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
3662 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
3663 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
3664 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
3665 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
3666 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
3667 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
3668 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
3669 +/* Block 0x140 - 0x190 registers are chipset specific */
3670 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
3671 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
3672 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
3673 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
3674 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
3675 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
3676 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
3677 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
3678 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
3679 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
3680 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
3681 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
3682 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
3683 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
3684 +/* NAND flash registers for BCM4706 (corerev = 31) */
3685 +#define BCMA_CC_NFLASH_CTL 0x01A0
3686 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
3687 +#define BCMA_CC_NFLASH_CONF 0x01A4
3688 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
3689 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
3690 +#define BCMA_CC_NFLASH_DATA 0x01B0
3691 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
3692 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
3693 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3694 #define BCMA_CC_UART0_DATA 0x0300
3695 @@ -240,7 +349,60 @@
3696 #define BCMA_CC_PLLCTL_ADDR 0x0660
3697 #define BCMA_CC_PLLCTL_DATA 0x0664
3698 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
3699 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
3700 +/* NAND flash MLC controller registers (corerev >= 38) */
3701 +#define BCMA_CC_NAND_REVISION 0x0C00
3702 +#define BCMA_CC_NAND_CMD_START 0x0C04
3703 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
3704 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
3705 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
3706 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
3707 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
3708 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
3709 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
3710 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
3711 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
3712 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
3713 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
3714 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
3715 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
3716 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
3717 +#define BCMA_CC_NAND_CONFIG 0x0C48
3718 +#define BCMA_CC_NAND_TIMING_1 0x0C50
3719 +#define BCMA_CC_NAND_TIMING_2 0x0C54
3720 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
3721 +#define BCMA_CC_NAND_DEVID 0x0C60
3722 +#define BCMA_CC_NAND_DEVID_X 0x0C64
3723 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
3724 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
3725 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
3726 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
3727 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
3728 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
3729 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
3730 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
3731 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
3732 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
3733 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
3734 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
3735 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
3736 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
3737 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
3738 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
3739 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
3740 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
3741 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
3742 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
3743 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
3744 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
3745 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
3746 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
3747 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
3748 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
3749 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
3750 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
3751 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
3752 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
3753 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
3754
3755 /* Divider allocation in 4716/47162/5356 */
3756 #define BCMA_CC_PMU5_MAINPLL_CPU 1
3757 @@ -256,6 +418,15 @@
3758
3759 /* 4706 PMU */
3760 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
3761 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
3762 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
3763 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
3764 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
3765 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
3766 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
3767 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
3768 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
3769 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
3770
3771 /* ALP clock on pre-PMU chips */
3772 #define BCMA_CC_PMU_ALP_CLOCK 20000000
3773 @@ -284,6 +455,19 @@
3774 #define BCMA_CC_PPL_PCHI_OFF 5
3775 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
3776
3777 +#define BCMA_CC_PMU_PLL_CTL0 0
3778 +#define BCMA_CC_PMU_PLL_CTL1 1
3779 +#define BCMA_CC_PMU_PLL_CTL2 2
3780 +#define BCMA_CC_PMU_PLL_CTL3 3
3781 +#define BCMA_CC_PMU_PLL_CTL4 4
3782 +#define BCMA_CC_PMU_PLL_CTL5 5
3783 +
3784 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
3785 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
3786 +
3787 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
3788 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
3789 +
3790 /* BCM4331 ChipControl numbers. */
3791 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
3792 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
3793 @@ -297,9 +481,25 @@
3794 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
3795 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
3796 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
3797 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
3798 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
3799 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
3800
3801 +/* 43224 chip-specific ChipControl register bits */
3802 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
3803 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
3804 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
3805 +
3806 +/* 4313 Chip specific ChipControl register bits */
3807 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
3808 +
3809 +/* BCM5357 ChipControl register bits */
3810 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
3811 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
3812 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
3813 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
3814 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
3815 +
3816 /* Data for the PMU, if available.
3817 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
3818 */
3819 @@ -310,11 +510,35 @@ struct bcma_chipcommon_pmu {
3820
3821 #ifdef CONFIG_BCMA_DRIVER_MIPS
3822 struct bcma_pflash {
3823 + bool present;
3824 u8 buswidth;
3825 u32 window;
3826 u32 window_size;
3827 };
3828
3829 +#ifdef CONFIG_BCMA_SFLASH
3830 +struct bcma_sflash {
3831 + bool present;
3832 + u32 window;
3833 + u32 blocksize;
3834 + u16 numblocks;
3835 + u32 size;
3836 +
3837 + struct mtd_info *mtd;
3838 +};
3839 +#endif
3840 +
3841 +#ifdef CONFIG_BCMA_NFLASH
3842 +struct mtd_info;
3843 +
3844 +struct bcma_nflash {
3845 + bool present;
3846 + bool boot; /* This is the flash the SoC boots from */
3847 +
3848 + struct mtd_info *mtd;
3849 +};
3850 +#endif
3851 +
3852 struct bcma_serial_port {
3853 void *regs;
3854 unsigned long clockspeed;
3855 @@ -330,11 +554,18 @@ struct bcma_drv_cc {
3856 u32 capabilities;
3857 u32 capabilities_ext;
3858 u8 setup_done:1;
3859 + u8 early_setup_done:1;
3860 /* Fast Powerup Delay constant */
3861 u16 fast_pwrup_delay;
3862 struct bcma_chipcommon_pmu pmu;
3863 #ifdef CONFIG_BCMA_DRIVER_MIPS
3864 struct bcma_pflash pflash;
3865 +#ifdef CONFIG_BCMA_SFLASH
3866 + struct bcma_sflash sflash;
3867 +#endif
3868 +#ifdef CONFIG_BCMA_NFLASH
3869 + struct bcma_nflash nflash;
3870 +#endif
3871
3872 int nr_serial_ports;
3873 struct bcma_serial_port serial_ports[4];
3874 @@ -355,6 +586,7 @@ struct bcma_drv_cc {
3875 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
3876
3877 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
3878 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
3879
3880 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
3881 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
3882 @@ -378,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
3883
3884 /* PMU support */
3885 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
3886 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
3887
3888 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
3889 u32 value);
3890 @@ -387,5 +620,6 @@ extern void bcma_chipco_chipctl_maskset(
3891 u32 offset, u32 mask, u32 set);
3892 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
3893 u32 offset, u32 mask, u32 set);
3894 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
3895
3896 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
3897 --- /dev/null
3898 +++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
3899 @@ -0,0 +1,100 @@
3900 +#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
3901 +#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
3902 +
3903 +#include <linux/types.h>
3904 +
3905 +#define BCMA_GMAC_CMN_STAG0 0x000
3906 +#define BCMA_GMAC_CMN_STAG1 0x004
3907 +#define BCMA_GMAC_CMN_STAG2 0x008
3908 +#define BCMA_GMAC_CMN_STAG3 0x00C
3909 +#define BCMA_GMAC_CMN_PARSER_CTL 0x020
3910 +#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
3911 +#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
3912 +#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
3913 +#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
3914 +#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
3915 +#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
3916 +#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
3917 +#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
3918 +#define BCMA_GMAC_CMN_PA_START 0x40000000
3919 +#define BCMA_GMAC_CMN_PHY_CTL 0x104
3920 +#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
3921 +#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
3922 +#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
3923 +#define BCMA_GMAC_CMN_PC_MTE 0x00800000
3924 +#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
3925 +#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
3926 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
3927 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
3928 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
3929 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
3930 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
3931 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
3932 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
3933 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
3934 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
3935 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
3936 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
3937 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
3938 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
3939 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
3940 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
3941 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
3942 +#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
3943 +#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
3944 +#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
3945 +#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
3946 +#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
3947 +#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
3948 +#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
3949 +#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
3950 +#define BCMA_GMAC_CMN_UDF_0_A8 0x308
3951 +#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
3952 +#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
3953 +#define BCMA_GMAC_CMN_UDF_1_A8 0x318
3954 +#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
3955 +#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
3956 +#define BCMA_GMAC_CMN_UDF_2_A8 0x328
3957 +#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
3958 +#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
3959 +#define BCMA_GMAC_CMN_UDF_0_B8 0x338
3960 +#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
3961 +#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
3962 +#define BCMA_GMAC_CMN_UDF_1_B8 0x348
3963 +#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
3964 +#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
3965 +#define BCMA_GMAC_CMN_UDF_2_B8 0x358
3966 +#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
3967 +#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
3968 +#define BCMA_GMAC_CMN_UDF_0_C8 0x368
3969 +#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
3970 +#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
3971 +#define BCMA_GMAC_CMN_UDF_1_C8 0x378
3972 +#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
3973 +#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
3974 +#define BCMA_GMAC_CMN_UDF_2_C8 0x388
3975 +#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
3976 +#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
3977 +#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
3978 +
3979 +struct bcma_drv_gmac_cmn {
3980 + struct bcma_device *core;
3981 +
3982 + /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
3983 + * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
3984 + struct mutex phy_mutex;
3985 +};
3986 +
3987 +/* Register access */
3988 +#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
3989 +#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
3990 +#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
3991 +#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
3992 +
3993 +#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
3994 +extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
3995 +#else
3996 +static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
3997 +#endif
3998 +
3999 +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
4000 --- a/include/linux/bcma/bcma_driver_mips.h
4001 +++ b/include/linux/bcma/bcma_driver_mips.h
4002 @@ -35,13 +35,16 @@ struct bcma_device;
4003 struct bcma_drv_mips {
4004 struct bcma_device *core;
4005 u8 setup_done:1;
4006 + u8 early_setup_done:1;
4007 unsigned int assigned_irqs;
4008 };
4009
4010 #ifdef CONFIG_BCMA_DRIVER_MIPS
4011 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
4012 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
4013 #else
4014 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
4015 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
4016 #endif
4017
4018 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
4019 --- a/include/linux/bcma/bcma_driver_pci.h
4020 +++ b/include/linux/bcma/bcma_driver_pci.h
4021 @@ -53,11 +53,47 @@ struct pci_dev;
4022 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
4023 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
4024 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
4025 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
4026 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
4027 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
4028 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
4029 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
4030 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
4031 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
4032 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
4033 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
4034 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
4035 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
4036 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
4037 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
4038 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
4039 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
4040 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
4041 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
4042 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
4043 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
4044 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
4045 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
4046 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
4047 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
4048 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
4049 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
4050 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
4051 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
4052 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
4053 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
4054 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
4055 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
4056 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
4057 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
4058 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
4059 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
4060 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
4061 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
4062 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
4063 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
4064 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
4065 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
4066
4067 /* SBtoPCIx */
4068 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
4069 @@ -72,20 +108,118 @@ struct pci_dev;
4070 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
4071 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
4072
4073 +/* PCIE protocol PHY diagnostic registers */
4074 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
4075 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
4076 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
4077 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
4078 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
4079 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
4080 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
4081 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
4082 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
4083 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
4084 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
4085 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
4086 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
4087 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
4088 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
4089 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
4090 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
4091 +
4092 +/* PCIE protocol DLLP diagnostic registers */
4093 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
4094 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
4095 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
4096 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
4097 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
4098 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
4099 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
4100 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
4101 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
4102 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
4103 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
4104 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
4105 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
4106 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
4107 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
4108 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
4109 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
4110 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
4111 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
4112 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
4113 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
4114 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
4115 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
4116 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
4117 +
4118 +/* SERDES RX registers */
4119 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
4120 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
4121 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
4122 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
4123 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
4124 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
4125 +
4126 +/* SERDES PLL registers */
4127 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
4128 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
4129 +
4130 /* PCIcore specific boardflags */
4131 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
4132
4133 +/* PCIE Config space accessing MACROS */
4134 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
4135 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
4136 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
4137 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
4138 +
4139 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
4140 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
4141 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
4142 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
4143 +
4144 +/* PCIE Root Capability Register bits (Host mode only) */
4145 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
4146 +
4147 +struct bcma_drv_pci;
4148 +
4149 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4150 +struct bcma_drv_pci_host {
4151 + struct bcma_drv_pci *pdev;
4152 +
4153 + u32 host_cfg_addr;
4154 + spinlock_t cfgspace_lock;
4155 +
4156 + struct pci_controller pci_controller;
4157 + struct pci_ops pci_ops;
4158 + struct resource mem_resource;
4159 + struct resource io_resource;
4160 +};
4161 +#endif
4162 +
4163 struct bcma_drv_pci {
4164 struct bcma_device *core;
4165 u8 setup_done:1;
4166 + u8 hostmode:1;
4167 +
4168 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4169 + struct bcma_drv_pci_host *host_controller;
4170 +#endif
4171 };
4172
4173 /* Register access */
4174 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
4175 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
4176 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
4177 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
4178
4179 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
4180 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
4181 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
4182 struct bcma_device *core, bool enable);
4183 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
4184 +
4185 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
4186 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
4187
4188 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
4189 --- a/include/linux/bcma/bcma_regs.h
4190 +++ b/include/linux/bcma/bcma_regs.h
4191 @@ -11,11 +11,13 @@
4192 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
4193 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
4194 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
4195 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
4196 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
4197 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
4198 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
4199 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
4200 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
4201 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
4202 /* Is there any BCM4328 on BCMA bus? */
4203 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
4204 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
4205 @@ -56,4 +58,36 @@
4206 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
4207 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
4208
4209 +/* SiliconBackplane Address Map.
4210 + * All regions may not exist on all chips.
4211 + */
4212 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
4213 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4214 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
4215 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4216 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
4217 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
4218 +
4219 +
4220 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4221 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4222 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
4223 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
4224 + * (2 ZettaBytes), low 32 bits
4225 + */
4226 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
4227 + * (2 ZettaBytes), high 32 bits
4228 + */
4229 +
4230 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4231 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4232 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
4233 + * (2 ZettaBytes), high 32 bits
4234 + */
4235 +
4236 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
4237 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
4238 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
4239 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
4240 +
4241 #endif /* LINUX_BCMA_REGS_H_ */
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