target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi

   1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
   2  * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  */
  17
  18 #include "qcom-ipq4019.dtsi"
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/input/input.h>
  21 #include <dt-bindings/soc/qcom,tcsr.h>
  22
  23 / {
  24         model = "Netgear EX61X0v2";
  25         compatible = "netgear,ex61x0v2";
  26
  27         soc {
  28                 rng@22000 {
  29                         status = "okay";
  30                 };
  31
  32                 mdio@90000 {
  33                         status = "okay";
  34                 };
  35
  36                 ess-psgmii@98000 {
  37                         status = "okay";
  38                 };
  39
  40                 tcsr@1949000 {
  41                         compatible = "qcom,tcsr";
  42                         reg = <0x1949000 0x100>;
  43                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  44                 };
  45
  46                 ess_tcsr@1953000 {
  47                         compatible = "qcom,tcsr";
  48                         reg = <0x1953000 0x1000>;
  49                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  50                 };
  51
  52                 tcsr@1957000 {
  53                         compatible = "qcom,tcsr";
  54                         reg = <0x1957000 0x100>;
  55                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  56                 };
  57
  58                 crypto@8e3a000 {
  59                         status = "okay";
  60                 };
  61
  62                 watchdog@b017000 {
  63                         status = "okay";
  64                 };
  65
  66                 ess-switch@c000000 {
  67                         status = "okay";
  68                 };
  69
  70                 edma@c080000 {
  71                         status = "okay";
  72                         qcom,num_gmac = <1>;
  73                 };
  74         };
  75
  76         aliases {
  77                 led-boot = &power_amber;
  78                 led-failsafe = &power_amber;
  79                 led-running = &power_green;
  80                 led-upgrade = &power_amber;
  81                 label-mac-device = &gmac0;
  82         };
  83
  84         keys {
  85                 compatible = "gpio-keys";
  86
  87                 wps {
  88                         label = "wps";
  89                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  90                         linux,code = <KEY_WPS_BUTTON>;
  91                 };
  92
  93                 reset {
  94                         label = "reset";
  95                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  96                         linux,code = <KEY_RESTART>;
  97                 };
  98         };
  99
 100         led_spi {
 101                 compatible = "spi-gpio";
 102                 #address-cells = <1>;
 103                 #size-cells = <0>;
 104
 105                 sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
 106                 mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 107                 num-chipselects = <0>;
 108
 109                 led_gpio: led_gpio@0 {
 110                         compatible = "fairchild,74hc595";
 111                         reg = <0>;
 112                         gpio-controller;
 113                         #gpio-cells = <2>;
 114                         registers-number = <1>;
 115                         spi-max-frequency = <1000000>;
 116                 };
 117         };
 118
 119         leds {
 120                 compatible = "gpio-leds";
 121
 122                 power_amber: power_amber {
 123                         label = "amber:power";
 124                         gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 125                 };
 126
 127                 power_green: power_green {
 128                         label = "green:power";
 129                         gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 130                 };
 131
 132                 right {
 133                         label = "blue:right";
 134                         gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 135                 };
 136
 137                 left {
 138                         label = "blue:left";
 139                         gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 140                 };
 141
 142                 client_green {
 143                         label = "green:client";
 144                         gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 145                 };
 146
 147                 client_red {
 148                         label = "red:client";
 149                         gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 150                 };
 151
 152                 router_green {
 153                         label = "green:router";
 154                         gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
 155                 };
 156
 157                 router_red {
 158                         label = "red:router";
 159                         gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 160                 };
 161
 162                 wps {
 163                         label = "green:wps";
 164                         gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 165                 };
 166         };
 167 };
 168
 169 &tlmm {
 170         serial_pins: serial_pinmux {
 171                 mux {
 172                         pins = "gpio60", "gpio61";
 173                         function = "blsp_uart0";
 174                         bias-disable;
 175                 };
 176         };
 177
 178         spi_0_pins: spi_0_pinmux {
 179                 pin {
 180                         function = "blsp_spi0";
 181                         pins = "gpio55", "gpio56", "gpio57";
 182                         drive-strength = <12>;
 183                         bias-disable;
 184                 };
 185                 pin_cs {
 186                         function = "gpio";
 187                         pins = "gpio54";
 188                         drive-strength = <2>;
 189                         bias-disable;
 190                         output-high;
 191                 };
 192         };
 193 };
 194
 195 &blsp1_spi1 {
 196         pinctrl-0 = <&spi_0_pins>;
 197         pinctrl-names = "default";
 198         status = "okay";
 199         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 200
 201         mx25l12805d@0 {
 202                 compatible = "jedec,spi-nor";
 203                 reg = <0>;
 204                 spi-max-frequency = <45000000>;
 205
 206                 partitions {
 207                         compatible = "fixed-partitions";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210
 211                         partition0@0 {
 212                                 label = "SBL1";
 213                                 reg = <0x00000000 0x00040000>;
 214                                 read-only;
 215                         };
 216
 217                         partition1@40000 {
 218                                 label = "MIBIB";
 219                                 reg = <0x00040000 0x00020000>;
 220                                 read-only;
 221                         };
 222
 223                         partition2@60000 {
 224                                 label = "QSEE";
 225                                 reg = <0x00060000 0x00060000>;
 226                                 read-only;
 227                         };
 228
 229                         partition3@c0000 {
 230                                 label = "CDT";
 231                                 reg = <0x000c0000 0x00010000>;
 232                                 read-only;
 233                         };
 234
 235                         partition4@d0000 {
 236                                 label = "DDRPARAMS";
 237                                 reg = <0x000d0000 0x00010000>;
 238                                 read-only;
 239                         };
 240
 241                         partition5@E0000 {
 242                                 label = "APPSBLENV";
 243                                 reg = <0x000e0000 0x00010000>;
 244                                 read-only;
 245                         };
 246
 247                         partition6@F0000 {
 248                                 label = "APPSBL";
 249                                 reg = <0x000f0000 0x00080000>;
 250                                 read-only;
 251                         };
 252
 253                         partition7@170000 {
 254                                 label = "ART";
 255                                 reg = <0x00170000 0x00010000>;
 256                                 compatible = "nvmem-cells";
 257                                 read-only;
 258                                 #address-cells = <1>;
 259                                 #size-cells = <1>;
 260
 261                                 precal_art_1000: precal@1000 {
 262                                         reg = <0x1000 0x2f20>;
 263                                 };
 264
 265                                 precal_art_5000: precal@5000 {
 266                                         reg = <0x5000 0x2f20>;
 267                                 };
 268                         };
 269
 270                         partition8@180000 {
 271                                 label = "config";
 272                                 reg = <0x00180000 0x00010000>;
 273                                 read-only;
 274                         };
 275
 276                         partition9@190000 {
 277                                 label = "pot";
 278                                 reg = <0x00190000 0x00010000>;
 279                                 read-only;
 280                         };
 281
 282                         partition10@1a0000 {
 283                                 compatible = "nvmem-cells";
 284                                 label = "dnidata";
 285                                 reg = <0x001a0000 0x00010000>;
 286                                 read-only;
 287
 288                                 #address-cells = <1>;
 289                                 #size-cells = <1>;
 290
 291                                 macaddr_dnidata_0: macaddr@0 {
 292                                         reg = <0x0 0x6>;
 293                                 };
 294
 295                                 macaddr_dnidata_c: macaddr@c {
 296                                         reg = <0xc 0x6>;
 297                                 };
 298                         };
 299
 300                         partition11@1b0000 {
 301                                 compatible = "denx,fit";
 302                                 label = "firmware";
 303                                 reg = <0x001b0000 0x00e10000>;
 304                         };
 305
 306                         partition12@fc0000 {
 307                                 label = "language";
 308                                 reg = <0x00fc0000 0x00040000>;
 309                                 read-only;
 310                         };
 311                 };
 312         };
 313 };
 314
 315 &blsp1_uart1 {
 316         pinctrl-0 = <&serial_pins>;
 317         pinctrl-names = "default";
 318         status = "okay";
 319 };
 320
 321 &blsp_dma {
 322         status = "okay";
 323 };
 324
 325 &cryptobam {
 326         status = "okay";
 327 };
 328
 329 &wifi0 {
 330         status = "okay";
 331         nvmem-cell-names = "pre-calibration", "mac-address";
 332         nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
 333 };
 334
 335 &wifi1 {
 336         status = "okay";
 337         nvmem-cell-names = "pre-calibration", "mac-address";
 338         nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
 339 };