projects / openwrt / staging / chunkeey.git / blob
? search:


1cf105d81e2aff8c8606b0e98a98578216d9c9a2
[openwrt/staging/chunkeey.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acpu0_aux>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 operating-points-v2 = <&opp_table0>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acpu1_aux>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 clock-latency = <100000>;
53 cpu-supply = <&smb208_s2b>;
54 operating-points-v2 = <&opp_table0>;
55 voltage-tolerance = <5>;
56 cooling-min-state = <0>;
57 cooling-max-state = <10>;
58 #cooling-cells = <2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 L2: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 qcom,saw = <&saw_l2>;
66 };
67
68 qcom,l2 {
69 qcom,l2-rates = <384000000 1000000000 1200000000>;
70 qcom,l2-cpufreq = <384000000 600000000 1200000000>;
71 qcom,l2-volt = <1100000 1100000 1150000>;
72 qcom,l2-supply = <&smb208_s1a>;
73 };
74
75 idle-states {
76 CPU_SPC: spc {
77 compatible = "qcom,idle-state-spc",
78 "arm,idle-state";
79 status = "okay";
80 entry-latency-us = <400>;
81 exit-latency-us = <900>;
82 min-residency-us = <3000>;
83 };
84 };
85 };
86
87 opp_table0: opp_table0 {
88 compatible = "operating-points-v2-qcom-cpu";
89 nvmem-cells = <&speedbin_efuse>;
90
91 opp-384000000 {
92 opp-hz = /bits/ 64 <384000000>;
93 opp-microvolt-speed0-pvs0-v0 = <1000000>;
94 opp-microvolt-speed0-pvs1-v0 = <925000>;
95 opp-microvolt-speed0-pvs2-v0 = <875000>;
96 opp-microvolt-speed0-pvs3-v0 = <800000>;
97 opp-supported-hw = <0x1>;
98 clock-latency-ns = <100000>;
99 };
100
101 opp-600000000 {
102 opp-hz = /bits/ 64 <600000000>;
103 opp-microvolt-speed0-pvs0-v0 = <1050000>;
104 opp-microvolt-speed0-pvs1-v0 = <975000>;
105 opp-microvolt-speed0-pvs2-v0 = <925000>;
106 opp-microvolt-speed0-pvs3-v0 = <850000>;
107 opp-supported-hw = <0x1>;
108 clock-latency-ns = <100000>;
109 };
110
111 opp-800000000 {
112 opp-hz = /bits/ 64 <800000000>;
113 opp-microvolt-speed0-pvs0-v0 = <1100000>;
114 opp-microvolt-speed0-pvs1-v0 = <1025000>;
115 opp-microvolt-speed0-pvs2-v0 = <995000>;
116 opp-microvolt-speed0-pvs3-v0 = <900000>;
117 opp-supported-hw = <0x1>;
118 clock-latency-ns = <100000>;
119 };
120
121 opp-1000000000 {
122 opp-hz = /bits/ 64 <1000000000>;
123 opp-microvolt-speed0-pvs0-v0 = <1150000>;
124 opp-microvolt-speed0-pvs1-v0 = <1075000>;
125 opp-microvolt-speed0-pvs2-v0 = <1025000>;
126 opp-microvolt-speed0-pvs3-v0 = <950000>;
127 opp-supported-hw = <0x1>;
128 clock-latency-ns = <100000>;
129 };
130
131 opp-1200000000 {
132 opp-hz = /bits/ 64 <1200000000>;
133 opp-microvolt-speed0-pvs0-v0 = <1200000>;
134 opp-microvolt-speed0-pvs1-v0 = <1125000>;
135 opp-microvolt-speed0-pvs2-v0 = <1075000>;
136 opp-microvolt-speed0-pvs3-v0 = <1000000>;
137 opp-supported-hw = <0x1>;
138 clock-latency-ns = <100000>;
139 };
140
141 opp-1400000000 {
142 opp-hz = /bits/ 64 <1400000000>;
143 opp-microvolt-speed0-pvs0-v0 = <1250000>;
144 opp-microvolt-speed0-pvs1-v0 = <1175000>;
145 opp-microvolt-speed0-pvs2-v0 = <1125000>;
146 opp-microvolt-speed0-pvs3-v0 = <1050000>;
147 opp-supported-hw = <0x1>;
148 clock-latency-ns = <100000>;
149 };
150
151 };
152
153 thermal-zones {
154 tsens_tz_sensor0 {
155 polling-delay-passive = <0>;
156 polling-delay = <0>;
157 thermal-sensors = <&tsens 0>;
158
159 trips {
160 cpu-critical-hi {
161 temperature = <125000>;
162 hysteresis = <2000>;
163 type = "critical_high";
164 };
165
166 cpu-config-hi {
167 temperature = <105000>;
168 hysteresis = <2000>;
169 type = "configurable_hi";
170 };
171
172 cpu-config-lo {
173 temperature = <95000>;
174 hysteresis = <2000>;
175 type = "configurable_lo";
176 };
177
178 cpu-critical-low {
179 temperature = <0>;
180 hysteresis = <2000>;
181 type = "critical_low";
182 };
183 };
184 };
185
186 tsens_tz_sensor1 {
187 polling-delay-passive = <0>;
188 polling-delay = <0>;
189 thermal-sensors = <&tsens 1>;
190
191 trips {
192 cpu-critical-hi {
193 temperature = <125000>;
194 hysteresis = <2000>;
195 type = "critical_high";
196 };
197
198 cpu-config-hi {
199 temperature = <105000>;
200 hysteresis = <2000>;
201 type = "configurable_hi";
202 };
203
204 cpu-config-lo {
205 temperature = <95000>;
206 hysteresis = <2000>;
207 type = "configurable_lo";
208 };
209
210 cpu-critical-low {
211 temperature = <0>;
212 hysteresis = <2000>;
213 type = "critical_low";
214 };
215 };
216 };
217
218 tsens_tz_sensor2 {
219 polling-delay-passive = <0>;
220 polling-delay = <0>;
221 thermal-sensors = <&tsens 2>;
222
223 trips {
224 cpu-critical-hi {
225 temperature = <125000>;
226 hysteresis = <2000>;
227 type = "critical_high";
228 };
229
230 cpu-config-hi {
231 temperature = <105000>;
232 hysteresis = <2000>;
233 type = "configurable_hi";
234 };
235
236 cpu-config-lo {
237 temperature = <95000>;
238 hysteresis = <2000>;
239 type = "configurable_lo";
240 };
241
242 cpu-critical-low {
243 temperature = <0>;
244 hysteresis = <2000>;
245 type = "critical_low";
246 };
247 };
248 };
249
250 tsens_tz_sensor3 {
251 polling-delay-passive = <0>;
252 polling-delay = <0>;
253 thermal-sensors = <&tsens 3>;
254
255 trips {
256 cpu-critical-hi {
257 temperature = <125000>;
258 hysteresis = <2000>;
259 type = "critical_high";
260 };
261
262 cpu-config-hi {
263 temperature = <105000>;
264 hysteresis = <2000>;
265 type = "configurable_hi";
266 };
267
268 cpu-config-lo {
269 temperature = <95000>;
270 hysteresis = <2000>;
271 type = "configurable_lo";
272 };
273
274 cpu-critical-low {
275 temperature = <0>;
276 hysteresis = <2000>;
277 type = "critical_low";
278 };
279 };
280 };
281
282 tsens_tz_sensor4 {
283 polling-delay-passive = <0>;
284 polling-delay = <0>;
285 thermal-sensors = <&tsens 4>;
286
287 trips {
288 cpu-critical-hi {
289 temperature = <125000>;
290 hysteresis = <2000>;
291 type = "critical_high";
292 };
293
294 cpu-config-hi {
295 temperature = <105000>;
296 hysteresis = <2000>;
297 type = "configurable_hi";
298 };
299
300 cpu-config-lo {
301 temperature = <95000>;
302 hysteresis = <2000>;
303 type = "configurable_lo";
304 };
305
306 cpu-critical-low {
307 temperature = <0>;
308 hysteresis = <2000>;
309 type = "critical_low";
310 };
311 };
312 };
313
314 tsens_tz_sensor5 {
315 polling-delay-passive = <0>;
316 polling-delay = <0>;
317 thermal-sensors = <&tsens 5>;
318
319 trips {
320 cpu-critical-hi {
321 temperature = <125000>;
322 hysteresis = <2000>;
323 type = "critical_high";
324 };
325
326 cpu-config-hi {
327 temperature = <105000>;
328 hysteresis = <2000>;
329 type = "configurable_hi";
330 };
331
332 cpu-config-lo {
333 temperature = <95000>;
334 hysteresis = <2000>;
335 type = "configurable_lo";
336 };
337
338 cpu-critical-low {
339 temperature = <0>;
340 hysteresis = <2000>;
341 type = "critical_low";
342 };
343 };
344 };
345
346 tsens_tz_sensor6 {
347 polling-delay-passive = <0>;
348 polling-delay = <0>;
349 thermal-sensors = <&tsens 6>;
350
351 trips {
352 cpu-critical-hi {
353 temperature = <125000>;
354 hysteresis = <2000>;
355 type = "critical_high";
356 };
357
358 cpu-config-hi {
359 temperature = <105000>;
360 hysteresis = <2000>;
361 type = "configurable_hi";
362 };
363
364 cpu-config-lo {
365 temperature = <95000>;
366 hysteresis = <2000>;
367 type = "configurable_lo";
368 };
369
370 cpu-critical-low {
371 temperature = <0>;
372 hysteresis = <2000>;
373 type = "critical_low";
374 };
375 };
376 };
377
378 tsens_tz_sensor7 {
379 polling-delay-passive = <0>;
380 polling-delay = <0>;
381 thermal-sensors = <&tsens 7>;
382
383 trips {
384 cpu-critical-hi {
385 temperature = <125000>;
386 hysteresis = <2000>;
387 type = "critical_high";
388 };
389
390 cpu-config-hi {
391 temperature = <105000>;
392 hysteresis = <2000>;
393 type = "configurable_hi";
394 };
395
396 cpu-config-lo {
397 temperature = <95000>;
398 hysteresis = <2000>;
399 type = "configurable_lo";
400 };
401
402 cpu-critical-low {
403 temperature = <0>;
404 hysteresis = <2000>;
405 type = "critical_low";
406 };
407 };
408 };
409
410 tsens_tz_sensor8 {
411 polling-delay-passive = <0>;
412 polling-delay = <0>;
413 thermal-sensors = <&tsens 8>;
414
415 trips {
416 cpu-critical-hi {
417 temperature = <125000>;
418 hysteresis = <2000>;
419 type = "critical_high";
420 };
421
422 cpu-config-hi {
423 temperature = <105000>;
424 hysteresis = <2000>;
425 type = "configurable_hi";
426 };
427
428 cpu-config-lo {
429 temperature = <95000>;
430 hysteresis = <2000>;
431 type = "configurable_lo";
432 };
433
434 cpu-critical-low {
435 temperature = <0>;
436 hysteresis = <2000>;
437 type = "critical_low";
438 };
439 };
440 };
441
442 tsens_tz_sensor9 {
443 polling-delay-passive = <0>;
444 polling-delay = <0>;
445 thermal-sensors = <&tsens 9>;
446
447 trips {
448 cpu-critical-hi {
449 temperature = <125000>;
450 hysteresis = <2000>;
451 type = "critical_high";
452 };
453
454 cpu-config-hi {
455 temperature = <105000>;
456 hysteresis = <2000>;
457 type = "configurable_hi";
458 };
459
460 cpu-config-lo {
461 temperature = <95000>;
462 hysteresis = <2000>;
463 type = "configurable_lo";
464 };
465
466 cpu-critical-low {
467 temperature = <0>;
468 hysteresis = <2000>;
469 type = "critical_low";
470 };
471 };
472 };
473
474 tsens_tz_sensor10 {
475 polling-delay-passive = <0>;
476 polling-delay = <0>;
477 thermal-sensors = <&tsens 10>;
478
479 trips {
480 cpu-critical-hi {
481 temperature = <125000>;
482 hysteresis = <2000>;
483 type = "critical_high";
484 };
485
486 cpu-config-hi {
487 temperature = <105000>;
488 hysteresis = <2000>;
489 type = "configurable_hi";
490 };
491
492 cpu-config-lo {
493 temperature = <95000>;
494 hysteresis = <2000>;
495 type = "configurable_lo";
496 };
497
498 cpu-critical-low {
499 temperature = <0>;
500 hysteresis = <2000>;
501 type = "critical_low";
502 };
503 };
504 };
505 };
506
507 cpu-pmu {
508 compatible = "qcom,krait-pmu";
509 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
510 IRQ_TYPE_LEVEL_HIGH)>;
511 };
512
513 reserved-memory {
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges;
517
518 nss@40000000 {
519 reg = <0x40000000 0x1000000>;
520 no-map;
521 };
522
523 smem: smem@41000000 {
524 reg = <0x41000000 0x200000>;
525 no-map;
526 };
527 };
528
529 clocks {
530 cxo_board {
531 compatible = "fixed-clock";
532 #clock-cells = <0>;
533 clock-frequency = <25000000>;
534 };
535
536 pxo_board {
537 compatible = "fixed-clock";
538 #clock-cells = <0>;
539 clock-frequency = <25000000>;
540 };
541
542 sleep_clk: sleep_clk {
543 compatible = "fixed-clock";
544 clock-frequency = <32768>;
545 #clock-cells = <0>;
546 };
547 };
548
549 firmware {
550 scm {
551 compatible = "qcom,scm-ipq806x";
552 };
553 };
554
555 soc: soc {
556 #address-cells = <1>;
557 #size-cells = <1>;
558 ranges;
559 compatible = "simple-bus";
560
561 lpass@28100000 {
562 compatible = "qcom,lpass-cpu";
563 status = "disabled";
564 clocks = <&lcc AHBIX_CLK>,
565 <&lcc MI2S_OSR_CLK>,
566 <&lcc MI2S_BIT_CLK>;
567 clock-names = "ahbix-clk",
568 "mi2s-osr-clk",
569 "mi2s-bit-clk";
570 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
571 interrupt-names = "lpass-irq-lpaif";
572 reg = <0x28100000 0x10000>;
573 reg-names = "lpass-lpaif";
574 };
575
576 qfprom: qfprom@700000 {
577 compatible = "qcom,qfprom", "syscon";
578 reg = <0x700000 0x1000>;
579 #address-cells = <1>;
580 #size-cells = <1>;
581 status = "okay";
582 tsens_calib: calib@400 {
583 reg = <0x400 0xb>;
584 };
585 tsens_backup: backup@410 {
586 reg = <0x410 0xb>;
587 };
588 speedbin_efuse: speedbin@0c0 {
589 reg = <0x0c0 0x4>;
590 };
591 };
592
593 rpm@108000 {
594 compatible = "qcom,rpm-ipq8064";
595 reg = <0x108000 0x1000>;
596 qcom,ipc = <&l2cc 0x8 2>;
597
598 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
601 interrupt-names = "ack",
602 "err",
603 "wakeup";
604
605 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
606 clock-names = "ram";
607
608 #address-cells = <1>;
609 #size-cells = <0>;
610
611 rpmcc: clock-controller {
612 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
613 #clock-cells = <1>;
614 };
615
616 regulators {
617 compatible = "qcom,rpm-smb208-regulators";
618
619 smb208_s1a: s1a {
620 regulator-min-microvolt = <1050000>;
621 regulator-max-microvolt = <1150000>;
622
623 qcom,switch-mode-frequency = <1200000>;
624
625 };
626
627 smb208_s1b: s1b {
628 regulator-min-microvolt = <1050000>;
629 regulator-max-microvolt = <1150000>;
630
631 qcom,switch-mode-frequency = <1200000>;
632 };
633
634 smb208_s2a: s2a {
635 regulator-min-microvolt = < 800000>;
636 regulator-max-microvolt = <1250000>;
637
638 qcom,switch-mode-frequency = <1200000>;
639 };
640
641 smb208_s2b: s2b {
642 regulator-min-microvolt = < 800000>;
643 regulator-max-microvolt = <1250000>;
644
645 qcom,switch-mode-frequency = <1200000>;
646 };
647 };
648 };
649
650 rng@1a500000 {
651 compatible = "qcom,prng";
652 reg = <0x1a500000 0x200>;
653 clocks = <&gcc PRNG_CLK>;
654 clock-names = "core";
655 };
656
657 qcom_pinmux: pinmux@800000 {
658 compatible = "qcom,ipq8064-pinctrl";
659 reg = <0x800000 0x4000>;
660
661 gpio-controller;
662 #gpio-cells = <2>;
663 interrupt-controller;
664 #interrupt-cells = <2>;
665 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
666
667 pcie0_pins: pcie0_pinmux {
668 mux {
669 pins = "gpio3";
670 function = "pcie1_rst";
671 drive-strength = <12>;
672 bias-disable;
673 };
674 };
675
676 pcie1_pins: pcie1_pinmux {
677 mux {
678 pins = "gpio48";
679 function = "pcie2_rst";
680 drive-strength = <12>;
681 bias-disable;
682 };
683 };
684
685 pcie2_pins: pcie2_pinmux {
686 mux {
687 pins = "gpio63";
688 function = "pcie3_rst";
689 drive-strength = <12>;
690 bias-disable;
691 output-low;
692 };
693 };
694
695 spi_pins: spi_pins {
696 mux {
697 pins = "gpio18", "gpio19", "gpio21";
698 function = "gsbi5";
699 drive-strength = <10>;
700 bias-none;
701 };
702 };
703
704 leds_pins: leds_pins {
705 mux {
706 pins = "gpio7", "gpio8", "gpio9",
707 "gpio26", "gpio53";
708 function = "gpio";
709 drive-strength = <2>;
710 bias-pull-down;
711 output-low;
712 };
713 };
714
715 buttons_pins: buttons_pins {
716 mux {
717 pins = "gpio54";
718 drive-strength = <2>;
719 bias-pull-up;
720 };
721 };
722 };
723
724 intc: interrupt-controller@2000000 {
725 compatible = "qcom,msm-qgic2";
726 interrupt-controller;
727 #interrupt-cells = <3>;
728 reg = <0x02000000 0x1000>,
729 <0x02002000 0x1000>;
730 };
731
732 timer@200a000 {
733 compatible = "qcom,kpss-timer",
734 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
735 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
736 IRQ_TYPE_EDGE_RISING)>,
737 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
738 IRQ_TYPE_EDGE_RISING)>,
739 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
740 IRQ_TYPE_EDGE_RISING)>,
741 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
742 IRQ_TYPE_EDGE_RISING)>,
743 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
744 IRQ_TYPE_EDGE_RISING)>;
745 reg = <0x0200a000 0x100>;
746 clock-frequency = <25000000>,
747 <32768>;
748 clocks = <&sleep_clk>;
749 clock-names = "sleep";
750 cpu-offset = <0x80000>;
751 };
752
753 acpu0_aux: clock-controller@2088000 {
754 compatible = "qcom,kpss-acc-v1";
755 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
756 clock-output-names = "acpu0_aux";
757 };
758
759 acpu1_aux: clock-controller@2098000 {
760 compatible = "qcom,kpss-acc-v1";
761 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
762 clock-output-names = "acpu1_aux";
763 };
764
765 l2cc: clock-controller@2011000 {
766 compatible = "qcom,kpss-gcc", "syscon";
767 reg = <0x2011000 0x1000>;
768 clock-output-names = "acpu_l2_aux";
769 };
770
771 kraitcc: clock-controller {
772 compatible = "qcom,krait-cc-v1";
773 #clock-cells = <1>;
774 };
775
776 saw0: regulator@2089000 {
777 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
778 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
779 regulator;
780 };
781
782 saw1: regulator@2099000 {
783 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
784 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
785 regulator;
786 };
787
788 saw_l2: regulator@02012000 {
789 compatible = "qcom,saw2", "syscon";
790 reg = <0x02012000 0x1000>;
791 regulator;
792 };
793
794 sic_non_secure: sic-non-secure@12100000 {
795 compatible = "syscon";
796 reg = <0x12100000 0x10000>;
797 };
798
799 gsbi2: gsbi@12480000 {
800 compatible = "qcom,gsbi-v1.0.0";
801 cell-index = <2>;
802 reg = <0x12480000 0x100>;
803 clocks = <&gcc GSBI2_H_CLK>;
804 clock-names = "iface";
805 #address-cells = <1>;
806 #size-cells = <1>;
807 ranges;
808 status = "disabled";
809
810 syscon-tcsr = <&tcsr>;
811
812 uart2: serial@12490000 {
813 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
814 reg = <0x12490000 0x1000>,
815 <0x12480000 0x1000>;
816 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
818 clock-names = "core", "iface";
819 status = "disabled";
820 };
821
822 i2c@124a0000 {
823 compatible = "qcom,i2c-qup-v1.1.1";
824 reg = <0x124a0000 0x1000>;
825 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
826
827 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
828 clock-names = "core", "iface";
829 status = "disabled";
830
831 #address-cells = <1>;
832 #size-cells = <0>;
833 };
834
835 };
836
837 gsbi4: gsbi@16300000 {
838 compatible = "qcom,gsbi-v1.0.0";
839 cell-index = <4>;
840 reg = <0x16300000 0x100>;
841 clocks = <&gcc GSBI4_H_CLK>;
842 clock-names = "iface";
843 #address-cells = <1>;
844 #size-cells = <1>;
845 ranges;
846 status = "disabled";
847
848 syscon-tcsr = <&tcsr>;
849
850 gsbi4_serial: serial@16340000 {
851 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
852 reg = <0x16340000 0x1000>,
853 <0x16300000 0x1000>;
854 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
856 clock-names = "core", "iface";
857 status = "disabled";
858 };
859
860 i2c@16380000 {
861 compatible = "qcom,i2c-qup-v1.1.1";
862 reg = <0x16380000 0x1000>;
863 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
864
865 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
866 clock-names = "core", "iface";
867 status = "disabled";
868
869 #address-cells = <1>;
870 #size-cells = <0>;
871 };
872 };
873
874 gsbi5: gsbi@1a200000 {
875 compatible = "qcom,gsbi-v1.0.0";
876 cell-index = <5>;
877 reg = <0x1a200000 0x100>;
878 clocks = <&gcc GSBI5_H_CLK>;
879 clock-names = "iface";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 ranges;
883 status = "disabled";
884
885 syscon-tcsr = <&tcsr>;
886
887 uart5: serial@1a240000 {
888 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
889 reg = <0x1a240000 0x1000>,
890 <0x1a200000 0x1000>;
891 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
893 clock-names = "core", "iface";
894 status = "disabled";
895 };
896
897 i2c@1a280000 {
898 compatible = "qcom,i2c-qup-v1.1.1";
899 reg = <0x1a280000 0x1000>;
900 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
901
902 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
903 clock-names = "core", "iface";
904 status = "disabled";
905
906 #address-cells = <1>;
907 #size-cells = <0>;
908 };
909
910 spi@1a280000 {
911 compatible = "qcom,spi-qup-v1.1.1";
912 reg = <0x1a280000 0x1000>;
913 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
914
915 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
916 clock-names = "core", "iface";
917 status = "disabled";
918
919 #address-cells = <1>;
920 #size-cells = <0>;
921 };
922 };
923
924 gsbi7: gsbi@16600000 {
925 status = "disabled";
926 compatible = "qcom,gsbi-v1.0.0";
927 cell-index = <7>;
928 reg = <0x16600000 0x100>;
929 clocks = <&gcc GSBI7_H_CLK>;
930 clock-names = "iface";
931 #address-cells = <1>;
932 #size-cells = <1>;
933 ranges;
934 syscon-tcsr = <&tcsr>;
935
936 gsbi7_serial: serial@16640000 {
937 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
938 reg = <0x16640000 0x1000>,
939 <0x16600000 0x1000>;
940 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
942 clock-names = "core", "iface";
943 status = "disabled";
944 };
945 };
946
947 sata_phy: sata-phy@1b400000 {
948 compatible = "qcom,ipq806x-sata-phy";
949 reg = <0x1b400000 0x200>;
950
951 clocks = <&gcc SATA_PHY_CFG_CLK>;
952 clock-names = "cfg";
953
954 #phy-cells = <0>;
955 status = "disabled";
956 };
957
958 sata: sata@29000000 {
959 compatible = "qcom,ipq806x-ahci", "generic-ahci";
960 reg = <0x29000000 0x180>;
961
962 ports-implemented = <0x1>;
963
964 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
965
966 clocks = <&gcc SFAB_SATA_S_H_CLK>,
967 <&gcc SATA_H_CLK>,
968 <&gcc SATA_A_CLK>,
969 <&gcc SATA_RXOOB_CLK>,
970 <&gcc SATA_PMALIVE_CLK>;
971 clock-names = "slave_face", "iface", "core",
972 "rxoob", "pmalive";
973
974 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
975 assigned-clock-rates = <100000000>, <100000000>;
976
977 phys = <&sata_phy>;
978 phy-names = "sata-phy";
979 status = "disabled";
980 };
981
982 qcom,ssbi@500000 {
983 compatible = "qcom,ssbi";
984 reg = <0x00500000 0x1000>;
985 qcom,controller-type = "pmic-arbiter";
986 };
987
988 gcc: clock-controller@900000 {
989 compatible = "qcom,gcc-ipq8064";
990 reg = <0x00900000 0x4000>;
991 #clock-cells = <1>;
992 #reset-cells = <1>;
993 #power-domain-cells = <1>;
994 };
995
996 tsens: thermal-sensor@900000 {
997 compatible = "qcom,ipq8064-tsens";
998 reg = <0x900000 0x3680>;
999 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1000 nvmem-cell-names = "calib", "calib_backup";
1001 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1002 #thermal-sensor-cells = <1>;
1003 };
1004
1005 tcsr: syscon@1a400000 {
1006 compatible = "qcom,tcsr-ipq8064", "syscon";
1007 reg = <0x1a400000 0x100>;
1008 };
1009
1010 lcc: clock-controller@28000000 {
1011 compatible = "qcom,lcc-ipq8064";
1012 reg = <0x28000000 0x1000>;
1013 #clock-cells = <1>;
1014 #reset-cells = <1>;
1015 };
1016
1017 sfpb_mutex_block: syscon@1200600 {
1018 compatible = "syscon";
1019 reg = <0x01200600 0x100>;
1020 };
1021
1022 hs_phy_0: hs_phy_0 {
1023 compatible = "qcom,dwc3-hs-usb-phy";
1024 regmap = <&usb3_0>;
1025 clocks = <&gcc USB30_0_UTMI_CLK>;
1026 clock-names = "ref";
1027 #phy-cells = <0>;
1028 };
1029
1030 ss_phy_0: ss_phy_0 {
1031 compatible = "qcom,dwc3-ss-usb-phy";
1032 regmap = <&usb3_0>;
1033 clocks = <&gcc USB30_0_MASTER_CLK>;
1034 clock-names = "ref";
1035 #phy-cells = <0>;
1036 };
1037
1038 usb3_0: usb3@110f8800 {
1039 compatible = "qcom,dwc3", "syscon";
1040 #address-cells = <1>;
1041 #size-cells = <1>;
1042 reg = <0x110f8800 0x8000>;
1043 clocks = <&gcc USB30_0_MASTER_CLK>;
1044 clock-names = "core";
1045
1046 ranges;
1047
1048 resets = <&gcc USB30_0_MASTER_RESET>;
1049 reset-names = "master";
1050
1051 status = "disabled";
1052
1053 dwc3_0: dwc3@11000000 {
1054 compatible = "snps,dwc3";
1055 reg = <0x11000000 0xcd00>;
1056 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1057 phys = <&hs_phy_0>, <&ss_phy_0>;
1058 phy-names = "usb2-phy", "usb3-phy";
1059 dr_mode = "host";
1060 snps,dis_u3_susphy_quirk;
1061 };
1062 };
1063
1064 hs_phy_1: hs_phy_1 {
1065 compatible = "qcom,dwc3-hs-usb-phy";
1066 regmap = <&usb3_1>;
1067 clocks = <&gcc USB30_1_UTMI_CLK>;
1068 clock-names = "ref";
1069 #phy-cells = <0>;
1070 };
1071
1072 ss_phy_1: ss_phy_1 {
1073 compatible = "qcom,dwc3-ss-usb-phy";
1074 regmap = <&usb3_1>;
1075 clocks = <&gcc USB30_1_MASTER_CLK>;
1076 clock-names = "ref";
1077 #phy-cells = <0>;
1078 };
1079
1080 usb3_1: usb3@100f8800 {
1081 compatible = "qcom,dwc3", "syscon";
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 reg = <0x100f8800 0x8000>;
1085 clocks = <&gcc USB30_1_MASTER_CLK>;
1086 clock-names = "core";
1087
1088 ranges;
1089
1090 resets = <&gcc USB30_1_MASTER_RESET>;
1091 reset-names = "master";
1092
1093 status = "disabled";
1094
1095 dwc3_1: dwc3@10000000 {
1096 compatible = "snps,dwc3";
1097 reg = <0x10000000 0xcd00>;
1098 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1099 phys = <&hs_phy_1>, <&ss_phy_1>;
1100 phy-names = "usb2-phy", "usb3-phy";
1101 dr_mode = "host";
1102 snps,dis_u3_susphy_quirk;
1103 };
1104 };
1105
1106 pcie0: pci@1b500000 {
1107 compatible = "qcom,pcie-ipq8064";
1108 reg = <0x1b500000 0x1000
1109 0x1b502000 0x80
1110 0x1b600000 0x100
1111 0x0ff00000 0x100000>;
1112 reg-names = "dbi", "elbi", "parf", "config";
1113 device_type = "pci";
1114 linux,pci-domain = <0>;
1115 bus-range = <0x00 0xff>;
1116 num-lanes = <1>;
1117 #address-cells = <3>;
1118 #size-cells = <2>;
1119
1120 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1121 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1122
1123 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1124 interrupt-names = "msi";
1125 #interrupt-cells = <1>;
1126 interrupt-map-mask = <0 0 0 0x7>;
1127 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1128 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1129 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1130 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1131
1132 clocks = <&gcc PCIE_A_CLK>,
1133 <&gcc PCIE_H_CLK>,
1134 <&gcc PCIE_PHY_CLK>,
1135 <&gcc PCIE_AUX_CLK>,
1136 <&gcc PCIE_ALT_REF_CLK>;
1137 clock-names = "core", "iface", "phy", "aux", "ref";
1138
1139 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1140 assigned-clock-rates = <100000000>;
1141
1142 resets = <&gcc PCIE_ACLK_RESET>,
1143 <&gcc PCIE_HCLK_RESET>,
1144 <&gcc PCIE_POR_RESET>,
1145 <&gcc PCIE_PCI_RESET>,
1146 <&gcc PCIE_PHY_RESET>,
1147 <&gcc PCIE_EXT_RESET>;
1148 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1149
1150 pinctrl-0 = <&pcie0_pins>;
1151 pinctrl-names = "default";
1152
1153 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1154
1155 phy-tx0-term-offset = <7>;
1156
1157 status = "disabled";
1158 };
1159
1160 pcie1: pci@1b700000 {
1161 compatible = "qcom,pcie-ipq8064";
1162 reg = <0x1b700000 0x1000
1163 0x1b702000 0x80
1164 0x1b800000 0x100
1165 0x31f00000 0x100000>;
1166 reg-names = "dbi", "elbi", "parf", "config";
1167 device_type = "pci";
1168 linux,pci-domain = <1>;
1169 bus-range = <0x00 0xff>;
1170 num-lanes = <1>;
1171 #address-cells = <3>;
1172 #size-cells = <2>;
1173
1174 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1175 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1176
1177 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "msi";
1179 #interrupt-cells = <1>;
1180 interrupt-map-mask = <0 0 0 0x7>;
1181 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1182 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1183 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1184 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1185
1186 clocks = <&gcc PCIE_1_A_CLK>,
1187 <&gcc PCIE_1_H_CLK>,
1188 <&gcc PCIE_1_PHY_CLK>,
1189 <&gcc PCIE_1_AUX_CLK>,
1190 <&gcc PCIE_1_ALT_REF_CLK>;
1191 clock-names = "core", "iface", "phy", "aux", "ref";
1192
1193 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1194 assigned-clock-rates = <100000000>;
1195
1196 resets = <&gcc PCIE_1_ACLK_RESET>,
1197 <&gcc PCIE_1_HCLK_RESET>,
1198 <&gcc PCIE_1_POR_RESET>,
1199 <&gcc PCIE_1_PCI_RESET>,
1200 <&gcc PCIE_1_PHY_RESET>,
1201 <&gcc PCIE_1_EXT_RESET>;
1202 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1203
1204 pinctrl-0 = <&pcie1_pins>;
1205 pinctrl-names = "default";
1206
1207 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1208
1209 phy-tx0-term-offset = <7>;
1210
1211 status = "disabled";
1212 };
1213
1214 pcie2: pci@1b900000 {
1215 compatible = "qcom,pcie-ipq8064";
1216 reg = <0x1b900000 0x1000
1217 0x1b902000 0x80
1218 0x1ba00000 0x100
1219 0x35f00000 0x100000>;
1220 reg-names = "dbi", "elbi", "parf", "config";
1221 device_type = "pci";
1222 linux,pci-domain = <2>;
1223 bus-range = <0x00 0xff>;
1224 num-lanes = <1>;
1225 #address-cells = <3>;
1226 #size-cells = <2>;
1227
1228 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1229 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1230
1231 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1232 interrupt-names = "msi";
1233 #interrupt-cells = <1>;
1234 interrupt-map-mask = <0 0 0 0x7>;
1235 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1236 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1237 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1238 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1239
1240 clocks = <&gcc PCIE_2_A_CLK>,
1241 <&gcc PCIE_2_H_CLK>,
1242 <&gcc PCIE_2_PHY_CLK>,
1243 <&gcc PCIE_2_AUX_CLK>,
1244 <&gcc PCIE_2_ALT_REF_CLK>;
1245 clock-names = "core", "iface", "phy", "aux", "ref";
1246
1247 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1248 assigned-clock-rates = <100000000>;
1249
1250 resets = <&gcc PCIE_2_ACLK_RESET>,
1251 <&gcc PCIE_2_HCLK_RESET>,
1252 <&gcc PCIE_2_POR_RESET>,
1253 <&gcc PCIE_2_PCI_RESET>,
1254 <&gcc PCIE_2_PHY_RESET>,
1255 <&gcc PCIE_2_EXT_RESET>;
1256 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1257
1258 pinctrl-0 = <&pcie2_pins>;
1259 pinctrl-names = "default";
1260
1261 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1262
1263 phy-tx0-term-offset = <7>;
1264
1265 status = "disabled";
1266 };
1267
1268 adm_dma: dma@18300000 {
1269 compatible = "qcom,adm";
1270 reg = <0x18300000 0x100000>;
1271 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1272 #dma-cells = <1>;
1273
1274 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1275 clock-names = "core", "iface";
1276
1277 resets = <&gcc ADM0_RESET>,
1278 <&gcc ADM0_PBUS_RESET>,
1279 <&gcc ADM0_C0_RESET>,
1280 <&gcc ADM0_C1_RESET>,
1281 <&gcc ADM0_C2_RESET>;
1282 reset-names = "clk", "pbus", "c0", "c1", "c2";
1283 qcom,ee = <0>;
1284
1285 status = "disabled";
1286 };
1287
1288 nand: nand@1ac00000 {
1289 compatible = "qcom,ipq806x-nand";
1290 reg = <0x1ac00000 0x800>;
1291
1292 clocks = <&gcc EBI2_CLK>,
1293 <&gcc EBI2_AON_CLK>;
1294 clock-names = "core", "aon";
1295
1296 dmas = <&adm_dma 3>;
1297 dma-names = "rxtx";
1298 qcom,cmd-crci = <15>;
1299 qcom,data-crci = <3>;
1300
1301 status = "disabled";
1302
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 };
1306
1307 nss_common: syscon@03000000 {
1308 compatible = "syscon";
1309 reg = <0x03000000 0x0000FFFF>;
1310 };
1311
1312 qsgmii_csr: syscon@1bb00000 {
1313 compatible = "syscon";
1314 reg = <0x1bb00000 0x000001FF>;
1315 };
1316
1317 stmmac_axi_setup: stmmac-axi-config {
1318 snps,wr_osr_lmt = <7>;
1319 snps,rd_osr_lmt = <7>;
1320 snps,blen = <16 0 0 0 0 0 0>;
1321 };
1322
1323 gmac0: ethernet@37000000 {
1324 device_type = "network";
1325 compatible = "qcom,ipq806x-gmac";
1326 reg = <0x37000000 0x200000>;
1327 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1328 interrupt-names = "macirq";
1329
1330 snps,axi-config = <&stmmac_axi_setup>;
1331 snps,pbl = <32>;
1332 snps,aal = <1>;
1333
1334 qcom,nss-common = <&nss_common>;
1335 qcom,qsgmii-csr = <&qsgmii_csr>;
1336
1337 clocks = <&gcc GMAC_CORE1_CLK>;
1338 clock-names = "stmmaceth";
1339
1340 resets = <&gcc GMAC_CORE1_RESET>;
1341 reset-names = "stmmaceth";
1342
1343 status = "disabled";
1344 };
1345
1346 gmac1: ethernet@37200000 {
1347 device_type = "network";
1348 compatible = "qcom,ipq806x-gmac";
1349 reg = <0x37200000 0x200000>;
1350 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1351 interrupt-names = "macirq";
1352
1353 snps,axi-config = <&stmmac_axi_setup>;
1354 snps,pbl = <32>;
1355 snps,aal = <1>;
1356
1357 qcom,nss-common = <&nss_common>;
1358 qcom,qsgmii-csr = <&qsgmii_csr>;
1359
1360 clocks = <&gcc GMAC_CORE2_CLK>;
1361 clock-names = "stmmaceth";
1362
1363 resets = <&gcc GMAC_CORE2_RESET>;
1364 reset-names = "stmmaceth";
1365
1366 status = "disabled";
1367 };
1368
1369 gmac2: ethernet@37400000 {
1370 device_type = "network";
1371 compatible = "qcom,ipq806x-gmac";
1372 reg = <0x37400000 0x200000>;
1373 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "macirq";
1375
1376 snps,axi-config = <&stmmac_axi_setup>;
1377 snps,pbl = <32>;
1378 snps,aal = <1>;
1379
1380 qcom,nss-common = <&nss_common>;
1381 qcom,qsgmii-csr = <&qsgmii_csr>;
1382
1383 clocks = <&gcc GMAC_CORE3_CLK>;
1384 clock-names = "stmmaceth";
1385
1386 resets = <&gcc GMAC_CORE3_RESET>;
1387 reset-names = "stmmaceth";
1388
1389 status = "disabled";
1390 };
1391
1392 gmac3: ethernet@37600000 {
1393 device_type = "network";
1394 compatible = "qcom,ipq806x-gmac";
1395 reg = <0x37600000 0x200000>;
1396 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1397 interrupt-names = "macirq";
1398
1399 snps,axi-config = <&stmmac_axi_setup>;
1400 snps,pbl = <32>;
1401 snps,aal = <1>;
1402
1403 qcom,nss-common = <&nss_common>;
1404 qcom,qsgmii-csr = <&qsgmii_csr>;
1405
1406 clocks = <&gcc GMAC_CORE4_CLK>;
1407 clock-names = "stmmaceth";
1408
1409 resets = <&gcc GMAC_CORE4_RESET>;
1410 reset-names = "stmmaceth";
1411
1412 status = "disabled";
1413 };
1414
1415 /* Temporary fixed regulator */
1416 vsdcc_fixed: vsdcc-regulator {
1417 compatible = "regulator-fixed";
1418 regulator-name = "SDCC Power";
1419 regulator-min-microvolt = <3300000>;
1420 regulator-max-microvolt = <3300000>;
1421 regulator-always-on;
1422 };
1423
1424 sdcc1bam:dma@12402000 {
1425 compatible = "qcom,bam-v1.3.0";
1426 reg = <0x12402000 0x8000>;
1427 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1428 clocks = <&gcc SDC1_H_CLK>;
1429 clock-names = "bam_clk";
1430 #dma-cells = <1>;
1431 qcom,ee = <0>;
1432 };
1433
1434 sdcc3bam:dma@12182000 {
1435 compatible = "qcom,bam-v1.3.0";
1436 reg = <0x12182000 0x8000>;
1437 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&gcc SDC3_H_CLK>;
1439 clock-names = "bam_clk";
1440 #dma-cells = <1>;
1441 qcom,ee = <0>;
1442 };
1443
1444 amba {
1445 compatible = "arm,amba-bus";
1446 #address-cells = <1>;
1447 #size-cells = <1>;
1448 ranges;
1449 sdcc1: sdcc@12400000 {
1450 status = "disabled";
1451 compatible = "arm,pl18x", "arm,primecell";
1452 arm,primecell-periphid = <0x00051180>;
1453 reg = <0x12400000 0x2000>;
1454 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1455 interrupt-names = "cmd_irq";
1456 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1457 clock-names = "mclk", "apb_pclk";
1458 bus-width = <8>;
1459 max-frequency = <96000000>;
1460 non-removable;
1461 cap-sd-highspeed;
1462 cap-mmc-highspeed;
1463 vmmc-supply = <&vsdcc_fixed>;
1464 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1465 dma-names = "tx", "rx";
1466 };
1467
1468 sdcc3: sdcc@12180000 {
1469 compatible = "arm,pl18x", "arm,primecell";
1470 arm,primecell-periphid = <0x00051180>;
1471 status = "disabled";
1472 reg = <0x12180000 0x2000>;
1473 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1474 interrupt-names = "cmd_irq";
1475 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1476 clock-names = "mclk", "apb_pclk";
1477 bus-width = <8>;
1478 cap-sd-highspeed;
1479 cap-mmc-highspeed;
1480 max-frequency = <192000000>;
1481 #mmc-ddr-1_8v;
1482 sd-uhs-sdr104;
1483 sd-uhs-ddr50;
1484 vqmmc-supply = <&vsdcc_fixed>;
1485 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1486 dma-names = "tx", "rx";
1487 };
1488 };
1489 };
1490
1491 sfpb_mutex: sfpb-mutex {
1492 compatible = "qcom,sfpb-mutex";
1493 syscon = <&sfpb_mutex_block 4 4>;
1494
1495 #hwlock-cells = <1>;
1496 };
1497
1498 smem {
1499 compatible = "qcom,smem";
1500 memory-region = <&smem>;
1501 hwlocks = <&sfpb_mutex 3>;
1502 };
1503 };
Staging tree of Christian Lamparter