target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch

   1 --- a/drivers/pci/host/pcie-qcom.c
   2 +++ b/drivers/pci/host/pcie-qcom.c
   3 @@ -29,8 +29,53 @@
   4
   5  #include "pcie-designware.h"
   6
   7 +/* DBI registers */
   8 +#define PCIE20_CAP                             0x70
   9 +#define PCIE20_CAP_LINKCTRLSTATUS              (PCIE20_CAP + 0x10)
  10 +
  11 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0                0x818
  12 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
  13 +
  14 +#define PCIE20_PLR_IATU_VIEWPORT               0x900
  15 +#define PCIE20_PLR_IATU_REGION_OUTBOUND                (0x0 << 31)
  16 +#define PCIE20_PLR_IATU_REGION_INDEX(x)                (x << 0)
  17 +
  18 +#define PCIE20_PLR_IATU_CTRL1                  0x904
  19 +#define PCIE20_PLR_IATU_TYPE_CFG0              (0x4 << 0)
  20 +#define PCIE20_PLR_IATU_TYPE_MEM               (0x0 << 0)
  21 +
  22 +#define PCIE20_PLR_IATU_CTRL2                  0x908
  23 +#define PCIE20_PLR_IATU_ENABLE                 BIT(31)
  24 +
  25 +#define PCIE20_PLR_IATU_LBAR                   0x90C
  26 +#define PCIE20_PLR_IATU_UBAR                   0x910
  27 +#define PCIE20_PLR_IATU_LAR                    0x914
  28 +#define PCIE20_PLR_IATU_LTAR                   0x918
  29 +#define PCIE20_PLR_IATU_UTAR                   0x91c
  30 +
  31 +#define MSM_PCIE_DEV_CFG_ADDR                  0x01000000
  32 +
  33 +/* PARF registers */
  34 +#define PCIE20_PARF_PCS_DEEMPH                 0x34
  35 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)           (x << 16)
  36 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)     (x << 8)
  37 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)       (x << 0)
  38 +
  39 +#define PCIE20_PARF_PCS_SWING                  0x38
  40 +#define PCS_SWING_TX_SWING_FULL(x)             (x << 8)
  41 +#define PCS_SWING_TX_SWING_LOW(x)              (x << 0)
  42 +
  43  #define PCIE20_PARF_PHY_CTRL                   0x40
  44 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      (0x1f << 16)
  45 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                (x << 16)
  46 +
  47  #define PCIE20_PARF_PHY_REFCLK                 0x4C
  48 +#define REF_SSP_EN                             BIT(16)
  49 +#define REF_USE_PAD                            BIT(12)
  50 +
  51 +#define PCIE20_PARF_CONFIG_BITS                        0x50
  52 +#define PHY_RX0_EQ(x)                          (x << 24)
  53 +
  54  #define PCIE20_PARF_DBI_BASE_ADDR              0x168
  55  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE                0x16c
  56  #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT      0x178
  57 @@ -39,9 +84,6 @@
  58  #define PCIE20_ELBI_SYS_STTS                   0x08
  59  #define XMLH_LINK_UP                           BIT(10)
  60
  61 -#define PCIE20_CAP                             0x70
  62 -#define PCIE20_CAP_LINKCTRLSTATUS              (PCIE20_CAP + 0x10)
  63 -
  64  #define PERST_DELAY_MIN_US                     1000
  65  #define PERST_DELAY_MAX_US                     1005
  66
  67 @@ -56,14 +98,18 @@ struct qcom_pcie_resources_v0 {
  68         struct clk *iface_clk;
  69         struct clk *core_clk;
  70         struct clk *phy_clk;
  71 +       struct clk *aux_clk;
  72 +       struct clk *ref_clk;
  73         struct reset_control *pci_reset;
  74         struct reset_control *axi_reset;
  75         struct reset_control *ahb_reset;
  76         struct reset_control *por_reset;
  77         struct reset_control *phy_reset;
  78 +       struct reset_control *ext_reset;
  79         struct regulator *vdda;
  80         struct regulator *vdda_phy;
  81         struct regulator *vdda_refclk;
  82 +       uint8_t phy_tx0_term_offset;
  83  };
  84
  85  struct qcom_pcie_resources_v1 {
  86 @@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_
  87         reset_control_assert(res->axi_reset);
  88         reset_control_assert(res->ahb_reset);
  89         reset_control_assert(res->por_reset);
  90 -       reset_control_assert(res->pci_reset);
  91 +       reset_control_assert(res->phy_reset);
  92 +       reset_control_assert(res->ext_reset);
  93         clk_disable_unprepare(res->iface_clk);
  94         clk_disable_unprepare(res->core_clk);
  95         clk_disable_unprepare(res->phy_clk);
  96 +       clk_disable_unprepare(res->aux_clk);
  97 +       clk_disable_unprepare(res->ref_clk);
  98         regulator_disable(res->vdda);
  99         regulator_disable(res->vdda_phy);
 100         regulator_disable(res->vdda_refclk);
 101 @@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0
 102                 goto err_vdda_phy;
 103         }
 104
 105 +       ret = reset_control_deassert(res->ext_reset);
 106 +       if (ret) {
 107 +               dev_err(dev, "cannot assert ext reset\n");
 108 +               goto err_reset_ext;
 109 +       }
 110 +
 111         ret = clk_prepare_enable(res->iface_clk);
 112         if (ret) {
 113                 dev_err(dev, "cannot prepare/enable iface clock\n");
 114 @@ -219,21 +274,40 @@ static int qcom_pcie_enable_resources_v0
 115                 goto err_clk_phy;
 116         }
 117
 118 +       ret = clk_prepare_enable(res->aux_clk);
 119 +       if (ret) {
 120 +               dev_err(dev, "cannot prepare/enable aux clock\n");
 121 +               goto err_clk_aux;
 122 +       }
 123 +
 124 +       ret = clk_prepare_enable(res->ref_clk);
 125 +       if (ret) {
 126 +               dev_err(dev, "cannot prepare/enable ref clock\n");
 127 +               goto err_clk_ref;
 128 +       }
 129 +
 130         ret = reset_control_deassert(res->ahb_reset);
 131         if (ret) {
 132                 dev_err(dev, "cannot deassert ahb reset\n");
 133                 goto err_reset_ahb;
 134         }
 135 +       udelay(1);
 136
 137         return 0;
 138
 139  err_reset_ahb:
 140 +       clk_disable_unprepare(res->ref_clk);
 141 +err_clk_ref:
 142 +       clk_disable_unprepare(res->aux_clk);
 143 +err_clk_aux:
 144         clk_disable_unprepare(res->phy_clk);
 145  err_clk_phy:
 146         clk_disable_unprepare(res->core_clk);
 147  err_clk_core:
 148         clk_disable_unprepare(res->iface_clk);
 149  err_iface:
 150 +       reset_control_assert(res->ext_reset);
 151 +err_reset_ext:
 152         regulator_disable(res->vdda_phy);
 153  err_vdda_phy:
 154         regulator_disable(res->vdda_refclk);
 155 @@ -329,6 +403,14 @@ static int qcom_pcie_get_resources_v0(st
 156         if (IS_ERR(res->phy_clk))
 157                 return PTR_ERR(res->phy_clk);
 158
 159 +       res->aux_clk = devm_clk_get(dev, "aux");
 160 +       if (IS_ERR(res->aux_clk))
 161 +               return PTR_ERR(res->aux_clk);
 162 +
 163 +       res->ref_clk = devm_clk_get(dev, "ref");
 164 +       if (IS_ERR(res->ref_clk))
 165 +               return PTR_ERR(res->ref_clk);
 166 +
 167         res->pci_reset = devm_reset_control_get(dev, "pci");
 168         if (IS_ERR(res->pci_reset))
 169                 return PTR_ERR(res->pci_reset);
 170 @@ -349,6 +431,14 @@ static int qcom_pcie_get_resources_v0(st
 171         if (IS_ERR(res->phy_reset))
 172                 return PTR_ERR(res->phy_reset);
 173
 174 +       res->ext_reset = devm_reset_control_get(dev, "ext");
 175 +       if (IS_ERR(res->ext_reset))
 176 +               return PTR_ERR(res->ext_reset);
 177 +
 178 +       if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
 179 +                               &res->phy_tx0_term_offset))
 180 +               res->phy_tx0_term_offset = 0;
 181 +
 182         return 0;
 183  }
 184
 185 @@ -461,6 +551,57 @@ err_res:
 186         qcom_pcie_disable_resources_v1(pcie);
 187  }
 188
 189 +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
 190 +{
 191 +       struct pcie_port *pp = &pcie->pp;
 192 +
 193 +       /*
 194 +        * program and enable address translation region 0 (device config
 195 +        * address space); region type config;
 196 +        * axi config address range to device config address range
 197 +        */
 198 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
 199 +              PCIE20_PLR_IATU_REGION_INDEX(0),
 200 +              pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
 201 +
 202 +       writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
 203 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
 204 +       writel(pp->cfg0_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
 205 +       writel((pp->cfg0_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
 206 +       writel((pp->cfg0_mod_base + pp->cfg0_size - 1),
 207 +              pcie->dbi + PCIE20_PLR_IATU_LAR);
 208 +       writel(busdev, pcie->dbi + PCIE20_PLR_IATU_LTAR);
 209 +       writel(0, pcie->dbi + PCIE20_PLR_IATU_UTAR);
 210 +}
 211 +
 212 +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
 213 +{
 214 +       struct pcie_port *pp = &pcie->pp;
 215 +
 216 +       /*
 217 +        * program and enable address translation region 2 (device resource
 218 +        * address space); region type memory;
 219 +        * axi device bar address range to device bar address range
 220 +        */
 221 +       writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
 222 +              PCIE20_PLR_IATU_REGION_INDEX(2),
 223 +              pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
 224 +
 225 +       writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
 226 +       writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
 227 +       writel(pp->mem_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
 228 +       writel((pp->mem_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
 229 +       writel(pp->mem_mod_base + pp->mem_size - 1,
 230 +              pcie->dbi + PCIE20_PLR_IATU_LAR);
 231 +       writel(pp->mem_bus_addr, pcie->dbi + PCIE20_PLR_IATU_LTAR);
 232 +       writel(upper_32_bits(pp->mem_bus_addr),
 233 +              pcie->dbi + PCIE20_PLR_IATU_UTAR);
 234 +
 235 +       /* 256B PCIE buffer setting */
 236 +       writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 237 +       writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 238 +}
 239 +
 240  static void qcom_pcie_host_init_v0(struct pcie_port *pp)
 241  {
 242         struct qcom_pcie *pcie = to_qcom_pcie(pp);
 243 @@ -470,15 +611,34 @@ static void qcom_pcie_host_init_v0(struc
 244
 245         qcom_ep_reset_assert(pcie);
 246
 247 +       reset_control_assert(res->ahb_reset);
 248 +
 249         ret = qcom_pcie_enable_resources_v0(pcie);
 250         if (ret)
 251                 return;
 252
 253         writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
 254
 255 -       /* enable external reference clock */
 256 -       writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
 257 +       /* Set Tx termination offset */
 258 +       writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
 259 +                     PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
 260 +                     PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
 261 +
 262 +       /* PARF programming */
 263 +       writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
 264 +              PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
 265 +              PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
 266 +              pcie->parf + PCIE20_PARF_PCS_DEEMPH);
 267 +       writel(PCS_SWING_TX_SWING_FULL(0x78) |
 268 +              PCS_SWING_TX_SWING_LOW(0x78),
 269 +              pcie->parf + PCIE20_PARF_PCS_SWING);
 270 +       writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
 271 +
 272 +       /* Enable reference clock */
 273 +       writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
 274 +                     REF_USE_PAD, REF_SSP_EN);
 275
 276 +       /* De-assert PHY, PCIe, POR and AXI resets */
 277         ret = reset_control_deassert(res->phy_reset);
 278         if (ret) {
 279                 dev_err(dev, "cannot deassert phy reset\n");
 280 @@ -517,6 +677,9 @@ static void qcom_pcie_host_init_v0(struc
 281         if (ret)
 282                 goto err;
 283
 284 +       qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
 285 +       qcom_pcie_prog_viewport_mem2_outbound(pcie);
 286 +
 287         return;
 288  err:
 289         qcom_ep_reset_assert(pcie);