target/linux/ipq806x/patches/0046-mmc-sdhci-msm-Qualcomm-SDHCI-binding-documentation.patch

   1 From 8a70c89b2fbb635a8d4fec302165343827aeed9f Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Mon, 10 Mar 2014 17:37:11 +0200
   4 Subject: [PATCH 046/182] mmc: sdhci-msm: Qualcomm SDHCI binding documentation
   5
   6 This patch adds the device-tree binding documentation for Qualcomm
   7 SDHCI driver. It contains the differences between the core properties
   8 in mmc.txt and the properties used by the sdhci-msm driver.
   9
  10 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  11 Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
  12 Signed-off-by: Chris Ball <chris@printf.net>
  13 ---
  14  .../devicetree/bindings/mmc/sdhci-msm.txt          |   55 ++++++++++++++++++++
  15  1 file changed, 55 insertions(+)
  16  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
  17
  18 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
  19 new file mode 100644
  20 index 0000000..81b33b5
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
  23 @@ -0,0 +1,55 @@
  24 +* Qualcomm SDHCI controller (sdhci-msm)
  25 +
  26 +This file documents differences between the core properties in mmc.txt
  27 +and the properties used by the sdhci-msm driver.
  28 +
  29 +Required properties:
  30 +- compatible: Should contain "qcom,sdhci-msm-v4".
  31 +- reg: Base address and length of the register in the following order:
  32 +       - Host controller register map (required)
  33 +       - SD Core register map (required)
  34 +- interrupts: Should contain an interrupt-specifiers for the interrupts:
  35 +       - Host controller interrupt (required)
  36 +- pinctrl-names: Should contain only one value - "default".
  37 +- pinctrl-0: Should specify pin control groups used for this controller.
  38 +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
  39 +- clock-names: Should contain the following:
  40 +       "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
  41 +       "core"  - SDC MMC clock (MCLK) (required)
  42 +       "bus"   - SDCC bus voter clock (optional)
  43 +
  44 +Example:
  45 +
  46 +       sdhc_1: sdhci@f9824900 {
  47 +               compatible = "qcom,sdhci-msm-v4";
  48 +               reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
  49 +               interrupts = <0 123 0>;
  50 +               bus-width = <8>;
  51 +               non-removable;
  52 +
  53 +               vmmc = <&pm8941_l20>;
  54 +               vqmmc = <&pm8941_s3>;
  55 +
  56 +               pinctrl-names = "default";
  57 +               pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
  58 +
  59 +               clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
  60 +               clock-names = "core", "iface";
  61 +       };
  62 +
  63 +       sdhc_2: sdhci@f98a4900 {
  64 +               compatible = "qcom,sdhci-msm-v4";
  65 +               reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  66 +               interrupts = <0 125 0>;
  67 +               bus-width = <4>;
  68 +               cd-gpios = <&msmgpio 62 0x1>;
  69 +
  70 +               vmmc = <&pm8941_l21>;
  71 +               vqmmc = <&pm8941_l13>;
  72 +
  73 +               pinctrl-names = "default";
  74 +               pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
  75 +
  76 +               clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
  77 +               clock-names = "core", "iface";
  78 +       };
  79 --
  80 1.7.10.4
  81