1 From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001
2 From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
3 Date: Mon, 23 Oct 2017 12:10:33 +0800
4 Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks
6 Add MT2712 clock dt-bindings, include topckgen, apmixedsys,
7 infracfg, pericfg, mcucfg and subsystem clocks.
9 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
10 Acked-by: Rob Herring <robh@kernel.org>
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
13 include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++
14 1 file changed, 427 insertions(+)
15 create mode 100644 include/dt-bindings/clock/mt2712-clk.h
17 diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
19 index 000000000000..48a8e797a617
21 +++ b/include/dt-bindings/clock/mt2712-clk.h
24 + * Copyright (c) 2017 MediaTek Inc.
25 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
27 + * This program is free software; you can redistribute it and/or modify
28 + * it under the terms of the GNU General Public License version 2 as
29 + * published by the Free Software Foundation.
31 + * This program is distributed in the hope that it will be useful,
32 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 + * GNU General Public License for more details.
37 +#ifndef _DT_BINDINGS_CLK_MT2712_H
38 +#define _DT_BINDINGS_CLK_MT2712_H
42 +#define CLK_APMIXED_MAINPLL 0
43 +#define CLK_APMIXED_UNIVPLL 1
44 +#define CLK_APMIXED_VCODECPLL 2
45 +#define CLK_APMIXED_VENCPLL 3
46 +#define CLK_APMIXED_APLL1 4
47 +#define CLK_APMIXED_APLL2 5
48 +#define CLK_APMIXED_LVDSPLL 6
49 +#define CLK_APMIXED_LVDSPLL2 7
50 +#define CLK_APMIXED_MSDCPLL 8
51 +#define CLK_APMIXED_MSDCPLL2 9
52 +#define CLK_APMIXED_TVDPLL 10
53 +#define CLK_APMIXED_MMPLL 11
54 +#define CLK_APMIXED_ARMCA35PLL 12
55 +#define CLK_APMIXED_ARMCA72PLL 13
56 +#define CLK_APMIXED_ETHERPLL 14
57 +#define CLK_APMIXED_NR_CLK 15
61 +#define CLK_TOP_ARMCA35PLL 0
62 +#define CLK_TOP_ARMCA35PLL_600M 1
63 +#define CLK_TOP_ARMCA35PLL_400M 2
64 +#define CLK_TOP_ARMCA72PLL 3
65 +#define CLK_TOP_SYSPLL 4
66 +#define CLK_TOP_SYSPLL_D2 5
67 +#define CLK_TOP_SYSPLL1_D2 6
68 +#define CLK_TOP_SYSPLL1_D4 7
69 +#define CLK_TOP_SYSPLL1_D8 8
70 +#define CLK_TOP_SYSPLL1_D16 9
71 +#define CLK_TOP_SYSPLL_D3 10
72 +#define CLK_TOP_SYSPLL2_D2 11
73 +#define CLK_TOP_SYSPLL2_D4 12
74 +#define CLK_TOP_SYSPLL_D5 13
75 +#define CLK_TOP_SYSPLL3_D2 14
76 +#define CLK_TOP_SYSPLL3_D4 15
77 +#define CLK_TOP_SYSPLL_D7 16
78 +#define CLK_TOP_SYSPLL4_D2 17
79 +#define CLK_TOP_SYSPLL4_D4 18
80 +#define CLK_TOP_UNIVPLL 19
81 +#define CLK_TOP_UNIVPLL_D7 20
82 +#define CLK_TOP_UNIVPLL_D26 21
83 +#define CLK_TOP_UNIVPLL_D52 22
84 +#define CLK_TOP_UNIVPLL_D104 23
85 +#define CLK_TOP_UNIVPLL_D208 24
86 +#define CLK_TOP_UNIVPLL_D2 25
87 +#define CLK_TOP_UNIVPLL1_D2 26
88 +#define CLK_TOP_UNIVPLL1_D4 27
89 +#define CLK_TOP_UNIVPLL1_D8 28
90 +#define CLK_TOP_UNIVPLL_D3 29
91 +#define CLK_TOP_UNIVPLL2_D2 30
92 +#define CLK_TOP_UNIVPLL2_D4 31
93 +#define CLK_TOP_UNIVPLL2_D8 32
94 +#define CLK_TOP_UNIVPLL_D5 33
95 +#define CLK_TOP_UNIVPLL3_D2 34
96 +#define CLK_TOP_UNIVPLL3_D4 35
97 +#define CLK_TOP_UNIVPLL3_D8 36
98 +#define CLK_TOP_F_MP0_PLL1 37
99 +#define CLK_TOP_F_MP0_PLL2 38
100 +#define CLK_TOP_F_BIG_PLL1 39
101 +#define CLK_TOP_F_BIG_PLL2 40
102 +#define CLK_TOP_F_BUS_PLL1 41
103 +#define CLK_TOP_F_BUS_PLL2 42
104 +#define CLK_TOP_APLL1 43
105 +#define CLK_TOP_APLL1_D2 44
106 +#define CLK_TOP_APLL1_D4 45
107 +#define CLK_TOP_APLL1_D8 46
108 +#define CLK_TOP_APLL1_D16 47
109 +#define CLK_TOP_APLL2 48
110 +#define CLK_TOP_APLL2_D2 49
111 +#define CLK_TOP_APLL2_D4 50
112 +#define CLK_TOP_APLL2_D8 51
113 +#define CLK_TOP_APLL2_D16 52
114 +#define CLK_TOP_LVDSPLL 53
115 +#define CLK_TOP_LVDSPLL_D2 54
116 +#define CLK_TOP_LVDSPLL_D4 55
117 +#define CLK_TOP_LVDSPLL_D8 56
118 +#define CLK_TOP_LVDSPLL2 57
119 +#define CLK_TOP_LVDSPLL2_D2 58
120 +#define CLK_TOP_LVDSPLL2_D4 59
121 +#define CLK_TOP_LVDSPLL2_D8 60
122 +#define CLK_TOP_ETHERPLL_125M 61
123 +#define CLK_TOP_ETHERPLL_50M 62
124 +#define CLK_TOP_CVBS 63
125 +#define CLK_TOP_CVBS_D2 64
126 +#define CLK_TOP_SYS_26M 65
127 +#define CLK_TOP_MMPLL 66
128 +#define CLK_TOP_MMPLL_D2 67
129 +#define CLK_TOP_VENCPLL 68
130 +#define CLK_TOP_VENCPLL_D2 69
131 +#define CLK_TOP_VCODECPLL 70
132 +#define CLK_TOP_VCODECPLL_D2 71
133 +#define CLK_TOP_TVDPLL 72
134 +#define CLK_TOP_TVDPLL_D2 73
135 +#define CLK_TOP_TVDPLL_D4 74
136 +#define CLK_TOP_TVDPLL_D8 75
137 +#define CLK_TOP_TVDPLL_429M 76
138 +#define CLK_TOP_TVDPLL_429M_D2 77
139 +#define CLK_TOP_TVDPLL_429M_D4 78
140 +#define CLK_TOP_MSDCPLL 79
141 +#define CLK_TOP_MSDCPLL_D2 80
142 +#define CLK_TOP_MSDCPLL_D4 81
143 +#define CLK_TOP_MSDCPLL2 82
144 +#define CLK_TOP_MSDCPLL2_D2 83
145 +#define CLK_TOP_MSDCPLL2_D4 84
146 +#define CLK_TOP_CLK26M_D2 85
147 +#define CLK_TOP_D2A_ULCLK_6P5M 86
148 +#define CLK_TOP_VPLL3_DPIX 87
149 +#define CLK_TOP_VPLL_DPIX 88
150 +#define CLK_TOP_LTEPLL_FS26M 89
151 +#define CLK_TOP_DMPLL 90
152 +#define CLK_TOP_DSI0_LNTC 91
153 +#define CLK_TOP_DSI1_LNTC 92
154 +#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
155 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
156 +#define CLK_TOP_CLKRTC_EXT 95
157 +#define CLK_TOP_CLKRTC_INT 96
158 +#define CLK_TOP_CSI0 97
159 +#define CLK_TOP_CVBSPLL 98
160 +#define CLK_TOP_AXI_SEL 99
161 +#define CLK_TOP_MEM_SEL 100
162 +#define CLK_TOP_MM_SEL 101
163 +#define CLK_TOP_PWM_SEL 102
164 +#define CLK_TOP_VDEC_SEL 103
165 +#define CLK_TOP_VENC_SEL 104
166 +#define CLK_TOP_MFG_SEL 105
167 +#define CLK_TOP_CAMTG_SEL 106
168 +#define CLK_TOP_UART_SEL 107
169 +#define CLK_TOP_SPI_SEL 108
170 +#define CLK_TOP_USB20_SEL 109
171 +#define CLK_TOP_USB30_SEL 110
172 +#define CLK_TOP_MSDC50_0_HCLK_SEL 111
173 +#define CLK_TOP_MSDC50_0_SEL 112
174 +#define CLK_TOP_MSDC30_1_SEL 113
175 +#define CLK_TOP_MSDC30_2_SEL 114
176 +#define CLK_TOP_MSDC30_3_SEL 115
177 +#define CLK_TOP_AUDIO_SEL 116
178 +#define CLK_TOP_AUD_INTBUS_SEL 117
179 +#define CLK_TOP_PMICSPI_SEL 118
180 +#define CLK_TOP_DPILVDS1_SEL 119
181 +#define CLK_TOP_ATB_SEL 120
182 +#define CLK_TOP_NR_SEL 121
183 +#define CLK_TOP_NFI2X_SEL 122
184 +#define CLK_TOP_IRDA_SEL 123
185 +#define CLK_TOP_CCI400_SEL 124
186 +#define CLK_TOP_AUD_1_SEL 125
187 +#define CLK_TOP_AUD_2_SEL 126
188 +#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
189 +#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
190 +#define CLK_TOP_SCAM_SEL 129
191 +#define CLK_TOP_NFIECC_SEL 130
192 +#define CLK_TOP_PE2_MAC_P0_SEL 131
193 +#define CLK_TOP_PE2_MAC_P1_SEL 132
194 +#define CLK_TOP_DPILVDS_SEL 133
195 +#define CLK_TOP_MSDC50_3_HCLK_SEL 134
196 +#define CLK_TOP_HDCP_SEL 135
197 +#define CLK_TOP_HDCP_24M_SEL 136
198 +#define CLK_TOP_RTC_SEL 137
199 +#define CLK_TOP_SPINOR_SEL 138
200 +#define CLK_TOP_APLL_SEL 139
201 +#define CLK_TOP_APLL2_SEL 140
202 +#define CLK_TOP_A1SYS_HP_SEL 141
203 +#define CLK_TOP_A2SYS_HP_SEL 142
204 +#define CLK_TOP_ASM_L_SEL 143
205 +#define CLK_TOP_ASM_M_SEL 144
206 +#define CLK_TOP_ASM_H_SEL 145
207 +#define CLK_TOP_I2SO1_SEL 146
208 +#define CLK_TOP_I2SO2_SEL 147
209 +#define CLK_TOP_I2SO3_SEL 148
210 +#define CLK_TOP_TDMO0_SEL 149
211 +#define CLK_TOP_TDMO1_SEL 150
212 +#define CLK_TOP_I2SI1_SEL 151
213 +#define CLK_TOP_I2SI2_SEL 152
214 +#define CLK_TOP_I2SI3_SEL 153
215 +#define CLK_TOP_ETHER_125M_SEL 154
216 +#define CLK_TOP_ETHER_50M_SEL 155
217 +#define CLK_TOP_JPGDEC_SEL 156
218 +#define CLK_TOP_SPISLV_SEL 157
219 +#define CLK_TOP_ETHER_50M_RMII_SEL 158
220 +#define CLK_TOP_CAM2TG_SEL 159
221 +#define CLK_TOP_DI_SEL 160
222 +#define CLK_TOP_TVD_SEL 161
223 +#define CLK_TOP_I2C_SEL 162
224 +#define CLK_TOP_PWM_INFRA_SEL 163
225 +#define CLK_TOP_MSDC0P_AES_SEL 164
226 +#define CLK_TOP_CMSYS_SEL 165
227 +#define CLK_TOP_GCPU_SEL 166
228 +#define CLK_TOP_AUD_APLL1_SEL 167
229 +#define CLK_TOP_AUD_APLL2_SEL 168
230 +#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
231 +#define CLK_TOP_APLL_DIV0 170
232 +#define CLK_TOP_APLL_DIV1 171
233 +#define CLK_TOP_APLL_DIV2 172
234 +#define CLK_TOP_APLL_DIV3 173
235 +#define CLK_TOP_APLL_DIV4 174
236 +#define CLK_TOP_APLL_DIV5 175
237 +#define CLK_TOP_APLL_DIV6 176
238 +#define CLK_TOP_APLL_DIV7 177
239 +#define CLK_TOP_APLL_DIV_PDN0 178
240 +#define CLK_TOP_APLL_DIV_PDN1 179
241 +#define CLK_TOP_APLL_DIV_PDN2 180
242 +#define CLK_TOP_APLL_DIV_PDN3 181
243 +#define CLK_TOP_APLL_DIV_PDN4 182
244 +#define CLK_TOP_APLL_DIV_PDN5 183
245 +#define CLK_TOP_APLL_DIV_PDN6 184
246 +#define CLK_TOP_APLL_DIV_PDN7 185
247 +#define CLK_TOP_NR_CLK 186
251 +#define CLK_INFRA_DBGCLK 0
252 +#define CLK_INFRA_GCE 1
253 +#define CLK_INFRA_M4U 2
254 +#define CLK_INFRA_KP 3
255 +#define CLK_INFRA_AO_SPI0 4
256 +#define CLK_INFRA_AO_SPI1 5
257 +#define CLK_INFRA_AO_UART5 6
258 +#define CLK_INFRA_NR_CLK 7
262 +#define CLK_PERI_NFI 0
263 +#define CLK_PERI_THERM 1
264 +#define CLK_PERI_PWM0 2
265 +#define CLK_PERI_PWM1 3
266 +#define CLK_PERI_PWM2 4
267 +#define CLK_PERI_PWM3 5
268 +#define CLK_PERI_PWM4 6
269 +#define CLK_PERI_PWM5 7
270 +#define CLK_PERI_PWM6 8
271 +#define CLK_PERI_PWM7 9
272 +#define CLK_PERI_PWM 10
273 +#define CLK_PERI_AP_DMA 11
274 +#define CLK_PERI_MSDC30_0 12
275 +#define CLK_PERI_MSDC30_1 13
276 +#define CLK_PERI_MSDC30_2 14
277 +#define CLK_PERI_MSDC30_3 15
278 +#define CLK_PERI_UART0 16
279 +#define CLK_PERI_UART1 17
280 +#define CLK_PERI_UART2 18
281 +#define CLK_PERI_UART3 19
282 +#define CLK_PERI_I2C0 20
283 +#define CLK_PERI_I2C1 21
284 +#define CLK_PERI_I2C2 22
285 +#define CLK_PERI_I2C3 23
286 +#define CLK_PERI_I2C4 24
287 +#define CLK_PERI_AUXADC 25
288 +#define CLK_PERI_SPI0 26
289 +#define CLK_PERI_SPI 27
290 +#define CLK_PERI_I2C5 28
291 +#define CLK_PERI_SPI2 29
292 +#define CLK_PERI_SPI3 30
293 +#define CLK_PERI_SPI5 31
294 +#define CLK_PERI_UART4 32
295 +#define CLK_PERI_SFLASH 33
296 +#define CLK_PERI_GMAC 34
297 +#define CLK_PERI_PCIE0 35
298 +#define CLK_PERI_PCIE1 36
299 +#define CLK_PERI_GMAC_PCLK 37
300 +#define CLK_PERI_MSDC50_0_EN 38
301 +#define CLK_PERI_MSDC30_1_EN 39
302 +#define CLK_PERI_MSDC30_2_EN 40
303 +#define CLK_PERI_MSDC30_3_EN 41
304 +#define CLK_PERI_MSDC50_0_HCLK_EN 42
305 +#define CLK_PERI_MSDC50_3_HCLK_EN 43
306 +#define CLK_PERI_NR_CLK 44
310 +#define CLK_MCU_MP0_SEL 0
311 +#define CLK_MCU_MP2_SEL 1
312 +#define CLK_MCU_BUS_SEL 2
313 +#define CLK_MCU_NR_CLK 3
317 +#define CLK_MFG_BG3D 0
318 +#define CLK_MFG_NR_CLK 1
322 +#define CLK_MM_SMI_COMMON 0
323 +#define CLK_MM_SMI_LARB0 1
324 +#define CLK_MM_CAM_MDP 2
325 +#define CLK_MM_MDP_RDMA0 3
326 +#define CLK_MM_MDP_RDMA1 4
327 +#define CLK_MM_MDP_RSZ0 5
328 +#define CLK_MM_MDP_RSZ1 6
329 +#define CLK_MM_MDP_RSZ2 7
330 +#define CLK_MM_MDP_TDSHP0 8
331 +#define CLK_MM_MDP_TDSHP1 9
332 +#define CLK_MM_MDP_CROP 10
333 +#define CLK_MM_MDP_WDMA 11
334 +#define CLK_MM_MDP_WROT0 12
335 +#define CLK_MM_MDP_WROT1 13
336 +#define CLK_MM_FAKE_ENG 14
337 +#define CLK_MM_MUTEX_32K 15
338 +#define CLK_MM_DISP_OVL0 16
339 +#define CLK_MM_DISP_OVL1 17
340 +#define CLK_MM_DISP_RDMA0 18
341 +#define CLK_MM_DISP_RDMA1 19
342 +#define CLK_MM_DISP_RDMA2 20
343 +#define CLK_MM_DISP_WDMA0 21
344 +#define CLK_MM_DISP_WDMA1 22
345 +#define CLK_MM_DISP_COLOR0 23
346 +#define CLK_MM_DISP_COLOR1 24
347 +#define CLK_MM_DISP_AAL 25
348 +#define CLK_MM_DISP_GAMMA 26
349 +#define CLK_MM_DISP_UFOE 27
350 +#define CLK_MM_DISP_SPLIT0 28
351 +#define CLK_MM_DISP_OD 29
352 +#define CLK_MM_DISP_PWM0_MM 30
353 +#define CLK_MM_DISP_PWM0_26M 31
354 +#define CLK_MM_DISP_PWM1_MM 32
355 +#define CLK_MM_DISP_PWM1_26M 33
356 +#define CLK_MM_DSI0_ENGINE 34
357 +#define CLK_MM_DSI0_DIGITAL 35
358 +#define CLK_MM_DSI1_ENGINE 36
359 +#define CLK_MM_DSI1_DIGITAL 37
360 +#define CLK_MM_DPI_PIXEL 38
361 +#define CLK_MM_DPI_ENGINE 39
362 +#define CLK_MM_DPI1_PIXEL 40
363 +#define CLK_MM_DPI1_ENGINE 41
364 +#define CLK_MM_LVDS_PIXEL 42
365 +#define CLK_MM_LVDS_CTS 43
366 +#define CLK_MM_SMI_LARB4 44
367 +#define CLK_MM_SMI_COMMON1 45
368 +#define CLK_MM_SMI_LARB5 46
369 +#define CLK_MM_MDP_RDMA2 47
370 +#define CLK_MM_MDP_TDSHP2 48
371 +#define CLK_MM_DISP_OVL2 49
372 +#define CLK_MM_DISP_WDMA2 50
373 +#define CLK_MM_DISP_COLOR2 51
374 +#define CLK_MM_DISP_AAL1 52
375 +#define CLK_MM_DISP_OD1 53
376 +#define CLK_MM_LVDS1_PIXEL 54
377 +#define CLK_MM_LVDS1_CTS 55
378 +#define CLK_MM_SMI_LARB7 56
379 +#define CLK_MM_MDP_RDMA3 57
380 +#define CLK_MM_MDP_WROT2 58
381 +#define CLK_MM_DSI2 59
382 +#define CLK_MM_DSI2_DIGITAL 60
383 +#define CLK_MM_DSI3 61
384 +#define CLK_MM_DSI3_DIGITAL 62
385 +#define CLK_MM_NR_CLK 63
389 +#define CLK_IMG_SMI_LARB2 0
390 +#define CLK_IMG_SENINF_SCAM_EN 1
391 +#define CLK_IMG_SENINF_CAM_EN 2
392 +#define CLK_IMG_CAM_SV_EN 3
393 +#define CLK_IMG_CAM_SV1_EN 4
394 +#define CLK_IMG_CAM_SV2_EN 5
395 +#define CLK_IMG_NR_CLK 6
399 +#define CLK_BDP_BRIDGE_B 0
400 +#define CLK_BDP_BRIDGE_DRAM 1
401 +#define CLK_BDP_LARB_DRAM 2
402 +#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
403 +#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
404 +#define CLK_BDP_WR_CHANNEL_VDI_B 5
405 +#define CLK_BDP_MT_B 6
406 +#define CLK_BDP_DISPFMT_27M 7
407 +#define CLK_BDP_DISPFMT_27M_VDOUT 8
408 +#define CLK_BDP_DISPFMT_27_74_74 9
409 +#define CLK_BDP_DISPFMT_2FS 10
410 +#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
411 +#define CLK_BDP_DISPFMT_B 12
412 +#define CLK_BDP_VDO_DRAM 13
413 +#define CLK_BDP_VDO_2FS 14
414 +#define CLK_BDP_VDO_B 15
415 +#define CLK_BDP_WR_CHANNEL_DI_PXL 16
416 +#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
417 +#define CLK_BDP_WR_CHANNEL_DI_B 18
418 +#define CLK_BDP_NR_AGENT 19
419 +#define CLK_BDP_NR_DRAM 20
420 +#define CLK_BDP_NR_B 21
421 +#define CLK_BDP_BRIDGE_RT_B 22
422 +#define CLK_BDP_BRIDGE_RT_DRAM 23
423 +#define CLK_BDP_LARB_RT_DRAM 24
424 +#define CLK_BDP_TVD_TDC 25
425 +#define CLK_BDP_TVD_54 26
426 +#define CLK_BDP_TVD_CBUS 27
427 +#define CLK_BDP_NR_CLK 28
431 +#define CLK_VDEC_CKEN 0
432 +#define CLK_VDEC_LARB1_CKEN 1
433 +#define CLK_VDEC_IMGRZ_CKEN 2
434 +#define CLK_VDEC_NR_CLK 3
438 +#define CLK_VENC_SMI_COMMON_CON 0
439 +#define CLK_VENC_VENC 1
440 +#define CLK_VENC_SMI_LARB6 2
441 +#define CLK_VENC_NR_CLK 3
445 +#define CLK_JPGDEC_JPGDEC1 0
446 +#define CLK_JPGDEC_JPGDEC 1
447 +#define CLK_JPGDEC_NR_CLK 2
449 +#endif /* _DT_BINDINGS_CLK_MT2712_H */
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