1 From ea009d063f7a3d70831788046c7285a4af4ab82d Mon Sep 17 00:00:00 2001
2 From: Chen Zhong <chen.zhong@mediatek.com>
3 Date: Thu, 5 Oct 2017 11:50:25 +0800
4 Subject: [PATCH 149/224] clk: mediatek: add clocks dt-bindings required header
7 Add the required header for the entire clocks dt-bindings exported
8 from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys
9 and audsys which could be found on MT7622 SoC.
11 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
12 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 include/dt-bindings/clock/mt7622-clk.h | 289 +++++++++++++++++++++++++++++++++
16 1 file changed, 289 insertions(+)
17 create mode 100644 include/dt-bindings/clock/mt7622-clk.h
20 +++ b/include/dt-bindings/clock/mt7622-clk.h
23 + * Copyright (c) 2017 MediaTek Inc.
24 + * Author: Chen Zhong <chen.zhong@mediatek.com>
26 + * This program is free software; you can redistribute it and/or modify
27 + * it under the terms of the GNU General Public License version 2 as
28 + * published by the Free Software Foundation.
30 + * This program is distributed in the hope that it will be useful,
31 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 + * GNU General Public License for more details.
36 +#ifndef _DT_BINDINGS_CLK_MT7622_H
37 +#define _DT_BINDINGS_CLK_MT7622_H
41 +#define CLK_TOP_TO_U2_PHY 0
42 +#define CLK_TOP_TO_U2_PHY_1P 1
43 +#define CLK_TOP_PCIE0_PIPE_EN 2
44 +#define CLK_TOP_PCIE1_PIPE_EN 3
45 +#define CLK_TOP_SSUSB_TX250M 4
46 +#define CLK_TOP_SSUSB_EQ_RX250M 5
47 +#define CLK_TOP_SSUSB_CDR_REF 6
48 +#define CLK_TOP_SSUSB_CDR_FB 7
49 +#define CLK_TOP_SATA_ASIC 8
50 +#define CLK_TOP_SATA_RBC 9
51 +#define CLK_TOP_TO_USB3_SYS 10
52 +#define CLK_TOP_P1_1MHZ 11
53 +#define CLK_TOP_4MHZ 12
54 +#define CLK_TOP_P0_1MHZ 13
55 +#define CLK_TOP_TXCLK_SRC_PRE 14
56 +#define CLK_TOP_RTC 15
57 +#define CLK_TOP_MEMPLL 16
58 +#define CLK_TOP_DMPLL 17
59 +#define CLK_TOP_SYSPLL_D2 18
60 +#define CLK_TOP_SYSPLL1_D2 19
61 +#define CLK_TOP_SYSPLL1_D4 20
62 +#define CLK_TOP_SYSPLL1_D8 21
63 +#define CLK_TOP_SYSPLL2_D4 22
64 +#define CLK_TOP_SYSPLL2_D8 23
65 +#define CLK_TOP_SYSPLL_D5 24
66 +#define CLK_TOP_SYSPLL3_D2 25
67 +#define CLK_TOP_SYSPLL3_D4 26
68 +#define CLK_TOP_SYSPLL4_D2 27
69 +#define CLK_TOP_SYSPLL4_D4 28
70 +#define CLK_TOP_SYSPLL4_D16 29
71 +#define CLK_TOP_UNIVPLL 30
72 +#define CLK_TOP_UNIVPLL_D2 31
73 +#define CLK_TOP_UNIVPLL1_D2 32
74 +#define CLK_TOP_UNIVPLL1_D4 33
75 +#define CLK_TOP_UNIVPLL1_D8 34
76 +#define CLK_TOP_UNIVPLL1_D16 35
77 +#define CLK_TOP_UNIVPLL2_D2 36
78 +#define CLK_TOP_UNIVPLL2_D4 37
79 +#define CLK_TOP_UNIVPLL2_D8 38
80 +#define CLK_TOP_UNIVPLL2_D16 39
81 +#define CLK_TOP_UNIVPLL_D5 40
82 +#define CLK_TOP_UNIVPLL3_D2 41
83 +#define CLK_TOP_UNIVPLL3_D4 42
84 +#define CLK_TOP_UNIVPLL3_D16 43
85 +#define CLK_TOP_UNIVPLL_D7 44
86 +#define CLK_TOP_UNIVPLL_D80_D4 45
87 +#define CLK_TOP_UNIV48M 46
88 +#define CLK_TOP_SGMIIPLL 47
89 +#define CLK_TOP_SGMIIPLL_D2 48
90 +#define CLK_TOP_AUD1PLL 49
91 +#define CLK_TOP_AUD2PLL 50
92 +#define CLK_TOP_AUD_I2S2_MCK 51
93 +#define CLK_TOP_TO_USB3_REF 52
94 +#define CLK_TOP_PCIE1_MAC_EN 53
95 +#define CLK_TOP_PCIE0_MAC_EN 54
96 +#define CLK_TOP_ETH_500M 55
97 +#define CLK_TOP_AXI_SEL 56
98 +#define CLK_TOP_MEM_SEL 57
99 +#define CLK_TOP_DDRPHYCFG_SEL 58
100 +#define CLK_TOP_ETH_SEL 59
101 +#define CLK_TOP_PWM_SEL 60
102 +#define CLK_TOP_F10M_REF_SEL 61
103 +#define CLK_TOP_NFI_INFRA_SEL 62
104 +#define CLK_TOP_FLASH_SEL 63
105 +#define CLK_TOP_UART_SEL 64
106 +#define CLK_TOP_SPI0_SEL 65
107 +#define CLK_TOP_SPI1_SEL 66
108 +#define CLK_TOP_MSDC50_0_SEL 67
109 +#define CLK_TOP_MSDC30_0_SEL 68
110 +#define CLK_TOP_MSDC30_1_SEL 69
111 +#define CLK_TOP_A1SYS_HP_SEL 70
112 +#define CLK_TOP_A2SYS_HP_SEL 71
113 +#define CLK_TOP_INTDIR_SEL 72
114 +#define CLK_TOP_AUD_INTBUS_SEL 73
115 +#define CLK_TOP_PMICSPI_SEL 74
116 +#define CLK_TOP_SCP_SEL 75
117 +#define CLK_TOP_ATB_SEL 76
118 +#define CLK_TOP_HIF_SEL 77
119 +#define CLK_TOP_AUDIO_SEL 78
120 +#define CLK_TOP_U2_SEL 79
121 +#define CLK_TOP_AUD1_SEL 80
122 +#define CLK_TOP_AUD2_SEL 81
123 +#define CLK_TOP_IRRX_SEL 82
124 +#define CLK_TOP_IRTX_SEL 83
125 +#define CLK_TOP_ASM_L_SEL 84
126 +#define CLK_TOP_ASM_M_SEL 85
127 +#define CLK_TOP_ASM_H_SEL 86
128 +#define CLK_TOP_APLL1_SEL 87
129 +#define CLK_TOP_APLL2_SEL 88
130 +#define CLK_TOP_I2S0_MCK_SEL 89
131 +#define CLK_TOP_I2S1_MCK_SEL 90
132 +#define CLK_TOP_I2S2_MCK_SEL 91
133 +#define CLK_TOP_I2S3_MCK_SEL 92
134 +#define CLK_TOP_APLL1_DIV 93
135 +#define CLK_TOP_APLL2_DIV 94
136 +#define CLK_TOP_I2S0_MCK_DIV 95
137 +#define CLK_TOP_I2S1_MCK_DIV 96
138 +#define CLK_TOP_I2S2_MCK_DIV 97
139 +#define CLK_TOP_I2S3_MCK_DIV 98
140 +#define CLK_TOP_A1SYS_HP_DIV 99
141 +#define CLK_TOP_A2SYS_HP_DIV 100
142 +#define CLK_TOP_APLL1_DIV_PD 101
143 +#define CLK_TOP_APLL2_DIV_PD 102
144 +#define CLK_TOP_I2S0_MCK_DIV_PD 103
145 +#define CLK_TOP_I2S1_MCK_DIV_PD 104
146 +#define CLK_TOP_I2S2_MCK_DIV_PD 105
147 +#define CLK_TOP_I2S3_MCK_DIV_PD 106
148 +#define CLK_TOP_A1SYS_HP_DIV_PD 107
149 +#define CLK_TOP_A2SYS_HP_DIV_PD 108
150 +#define CLK_TOP_NR_CLK 109
154 +#define CLK_INFRA_MUX1_SEL 0
155 +#define CLK_INFRA_DBGCLK_PD 1
156 +#define CLK_INFRA_AUDIO_PD 2
157 +#define CLK_INFRA_IRRX_PD 3
158 +#define CLK_INFRA_APXGPT_PD 4
159 +#define CLK_INFRA_PMIC_PD 5
160 +#define CLK_INFRA_TRNG 6
161 +#define CLK_INFRA_NR_CLK 7
165 +#define CLK_PERIBUS_SEL 0
166 +#define CLK_PERI_THERM_PD 1
167 +#define CLK_PERI_PWM1_PD 2
168 +#define CLK_PERI_PWM2_PD 3
169 +#define CLK_PERI_PWM3_PD 4
170 +#define CLK_PERI_PWM4_PD 5
171 +#define CLK_PERI_PWM5_PD 6
172 +#define CLK_PERI_PWM6_PD 7
173 +#define CLK_PERI_PWM7_PD 8
174 +#define CLK_PERI_PWM_PD 9
175 +#define CLK_PERI_AP_DMA_PD 10
176 +#define CLK_PERI_MSDC30_0_PD 11
177 +#define CLK_PERI_MSDC30_1_PD 12
178 +#define CLK_PERI_UART0_PD 13
179 +#define CLK_PERI_UART1_PD 14
180 +#define CLK_PERI_UART2_PD 15
181 +#define CLK_PERI_UART3_PD 16
182 +#define CLK_PERI_UART4_PD 17
183 +#define CLK_PERI_BTIF_PD 18
184 +#define CLK_PERI_I2C0_PD 19
185 +#define CLK_PERI_I2C1_PD 20
186 +#define CLK_PERI_I2C2_PD 21
187 +#define CLK_PERI_SPI1_PD 22
188 +#define CLK_PERI_AUXADC_PD 23
189 +#define CLK_PERI_SPI0_PD 24
190 +#define CLK_PERI_SNFI_PD 25
191 +#define CLK_PERI_NFI_PD 26
192 +#define CLK_PERI_NFIECC_PD 27
193 +#define CLK_PERI_FLASH_PD 28
194 +#define CLK_PERI_IRTX_PD 29
195 +#define CLK_PERI_NR_CLK 30
199 +#define CLK_APMIXED_ARMPLL 0
200 +#define CLK_APMIXED_MAINPLL 1
201 +#define CLK_APMIXED_UNIV2PLL 2
202 +#define CLK_APMIXED_ETH1PLL 3
203 +#define CLK_APMIXED_ETH2PLL 4
204 +#define CLK_APMIXED_AUD1PLL 5
205 +#define CLK_APMIXED_AUD2PLL 6
206 +#define CLK_APMIXED_TRGPLL 7
207 +#define CLK_APMIXED_SGMIPLL 8
208 +#define CLK_APMIXED_MAIN_CORE_EN 9
209 +#define CLK_APMIXED_NR_CLK 10
213 +#define CLK_AUDIO_AFE 0
214 +#define CLK_AUDIO_HDMI 1
215 +#define CLK_AUDIO_SPDF 2
216 +#define CLK_AUDIO_APLL 3
217 +#define CLK_AUDIO_I2SIN1 4
218 +#define CLK_AUDIO_I2SIN2 5
219 +#define CLK_AUDIO_I2SIN3 6
220 +#define CLK_AUDIO_I2SIN4 7
221 +#define CLK_AUDIO_I2SO1 8
222 +#define CLK_AUDIO_I2SO2 9
223 +#define CLK_AUDIO_I2SO3 10
224 +#define CLK_AUDIO_I2SO4 11
225 +#define CLK_AUDIO_ASRCI1 12
226 +#define CLK_AUDIO_ASRCI2 13
227 +#define CLK_AUDIO_ASRCO1 14
228 +#define CLK_AUDIO_ASRCO2 15
229 +#define CLK_AUDIO_INTDIR 16
230 +#define CLK_AUDIO_A1SYS 17
231 +#define CLK_AUDIO_A2SYS 18
232 +#define CLK_AUDIO_UL1 19
233 +#define CLK_AUDIO_UL2 20
234 +#define CLK_AUDIO_UL3 21
235 +#define CLK_AUDIO_UL4 22
236 +#define CLK_AUDIO_UL5 23
237 +#define CLK_AUDIO_UL6 24
238 +#define CLK_AUDIO_DL1 25
239 +#define CLK_AUDIO_DL2 26
240 +#define CLK_AUDIO_DL3 27
241 +#define CLK_AUDIO_DL4 28
242 +#define CLK_AUDIO_DL5 29
243 +#define CLK_AUDIO_DL6 30
244 +#define CLK_AUDIO_DLMCH 31
245 +#define CLK_AUDIO_ARB1 32
246 +#define CLK_AUDIO_AWB 33
247 +#define CLK_AUDIO_AWB2 34
248 +#define CLK_AUDIO_DAI 35
249 +#define CLK_AUDIO_MOD 36
250 +#define CLK_AUDIO_ASRCI3 37
251 +#define CLK_AUDIO_ASRCI4 38
252 +#define CLK_AUDIO_ASRCO3 39
253 +#define CLK_AUDIO_ASRCO4 40
254 +#define CLK_AUDIO_MEM_ASRC1 41
255 +#define CLK_AUDIO_MEM_ASRC2 42
256 +#define CLK_AUDIO_MEM_ASRC3 43
257 +#define CLK_AUDIO_MEM_ASRC4 44
258 +#define CLK_AUDIO_MEM_ASRC5 45
259 +#define CLK_AUDIO_NR_CLK 46
263 +#define CLK_SSUSB_U2_PHY_1P_EN 0
264 +#define CLK_SSUSB_U2_PHY_EN 1
265 +#define CLK_SSUSB_REF_EN 2
266 +#define CLK_SSUSB_SYS_EN 3
267 +#define CLK_SSUSB_MCU_EN 4
268 +#define CLK_SSUSB_DMA_EN 5
269 +#define CLK_SSUSB_NR_CLK 6
273 +#define CLK_PCIE_P1_AUX_EN 0
274 +#define CLK_PCIE_P1_OBFF_EN 1
275 +#define CLK_PCIE_P1_AHB_EN 2
276 +#define CLK_PCIE_P1_AXI_EN 3
277 +#define CLK_PCIE_P1_MAC_EN 4
278 +#define CLK_PCIE_P1_PIPE_EN 5
279 +#define CLK_PCIE_P0_AUX_EN 6
280 +#define CLK_PCIE_P0_OBFF_EN 7
281 +#define CLK_PCIE_P0_AHB_EN 8
282 +#define CLK_PCIE_P0_AXI_EN 9
283 +#define CLK_PCIE_P0_MAC_EN 10
284 +#define CLK_PCIE_P0_PIPE_EN 11
285 +#define CLK_SATA_AHB_EN 12
286 +#define CLK_SATA_AXI_EN 13
287 +#define CLK_SATA_ASIC_EN 14
288 +#define CLK_SATA_RBC_EN 15
289 +#define CLK_SATA_PM_EN 16
290 +#define CLK_PCIE_NR_CLK 17
294 +#define CLK_ETH_HSDMA_EN 0
295 +#define CLK_ETH_ESW_EN 1
296 +#define CLK_ETH_GP2_EN 2
297 +#define CLK_ETH_GP1_EN 3
298 +#define CLK_ETH_GP0_EN 4
299 +#define CLK_ETH_NR_CLK 5
303 +#define CLK_SGMII_TX250M_EN 0
304 +#define CLK_SGMII_RX250M_EN 1
305 +#define CLK_SGMII_CDR_REF 2
306 +#define CLK_SGMII_CDR_FB 3
307 +#define CLK_SGMII_NR_CLK 4
309 +#endif /* _DT_BINDINGS_CLK_MT7622_H */
projects / openwrt / staging / chunkeey.git / blob