target/linux/mediatek/patches-4.19/0001-arm-dts-mediatek-add-basic-support-for-MT7629-SoC.patch

   1 From acb69c6600c3df52f0b3610801f3fd44c4392333 Mon Sep 17 00:00:00 2001
   2 Message-Id: <acb69c6600c3df52f0b3610801f3fd44c4392333.1559210220.git.ryder.lee@mediatek.com>
   3 From: Ryder Lee <ryder.lee@mediatek.com>
   4 Date: Wed, 13 Mar 2019 16:42:15 +0800
   5 Subject: [PATCH] arm: dts: mediatek: add basic support for MT7629 SoC
   6
   7 This adds basic support for MT7629 reference board.
   8
   9 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
  10 ---
  11  include/dt-bindings/reset/mt7629-resets.h |  71 ++++
  12  4 files changed, 704 insertions(+)
  13  create mode 100644 include/dt-bindings/reset/mt7629-resets.h
  14
  15 diff --git a/include/dt-bindings/reset/mt7629-resets.h b/include/dt-bindings/reset/mt7629-resets.h
  16 new file mode 100644
  17 index 000000000000..6bb85734f68d
  18 --- /dev/null
  19 +++ b/include/dt-bindings/reset/mt7629-resets.h
  20 @@ -0,0 +1,71 @@
  21 +/* SPDX-License-Identifier: GPL-2.0 */
  22 +/*
  23 + * Copyright (C) 2019 MediaTek Inc.
  24 + */
  25 +
  26 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
  27 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
  28 +
  29 +/* INFRACFG resets */
  30 +#define MT7629_INFRA_EMI_MPU_RST               0
  31 +#define MT7629_INFRA_UART5_RST                 2
  32 +#define MT7629_INFRA_CIRQ_EINT_RST             3
  33 +#define MT7629_INFRA_APXGPT_RST                        4
  34 +#define MT7629_INFRA_SCPSYS_RST                        5
  35 +#define MT7629_INFRA_KP_RST                    6
  36 +#define MT7629_INFRA_SPI1_RST                  7
  37 +#define MT7629_INFRA_SPI4_RST                  8
  38 +#define MT7629_INFRA_SYSTIMER_RST              9
  39 +#define MT7629_INFRA_IRRX_RST                  10
  40 +#define MT7629_INFRA_AO_BUS_RST                        16
  41 +#define MT7629_INFRA_EMI_RST                   32
  42 +#define MT7629_INFRA_APMIXED_RST               35
  43 +#define MT7629_INFRA_MIPI_RST                  36
  44 +#define MT7629_INFRA_TRNG_RST                  37
  45 +#define MT7629_INFRA_SYSCIRQ_RST               38
  46 +#define MT7629_INFRA_MIPI_CSI_RST              39
  47 +#define MT7629_INFRA_GCE_FAXI_RST              40
  48 +#define MT7629_INFRA_I2C_SRAM_RST              41
  49 +#define MT7629_INFRA_IOMMU_RST                 47
  50 +
  51 +/* PERICFG resets */
  52 +#define MT7629_PERI_UART0_SW_RST               0
  53 +#define MT7629_PERI_UART1_SW_RST               1
  54 +#define MT7629_PERI_UART2_SW_RST               2
  55 +#define MT7629_PERI_BTIF_SW_RST                        6
  56 +#define MT7629_PERI_PWN_SW_RST                 8
  57 +#define MT7629_PERI_DMA_SW_RST                 11
  58 +#define MT7629_PERI_NFI_SW_RST                 14
  59 +#define MT7629_PERI_I2C0_SW_RST                        22
  60 +#define MT7629_PERI_SPI0_SW_RST                        33
  61 +#define MT7629_PERI_SPI1_SW_RST                        34
  62 +#define MT7629_PERI_FLASHIF_SW_RST             36
  63 +
  64 +/* PCIe Subsystem resets */
  65 +#define MT7629_PCIE1_CORE_RST                  19
  66 +#define MT7629_PCIE1_MMIO_RST                  20
  67 +#define MT7629_PCIE1_HRST                      21
  68 +#define MT7629_PCIE1_USER_RST                  22
  69 +#define MT7629_PCIE1_PIPE_RST                  23
  70 +#define MT7629_PCIE0_CORE_RST                  27
  71 +#define MT7629_PCIE0_MMIO_RST                  28
  72 +#define MT7629_PCIE0_HRST                      29
  73 +#define MT7629_PCIE0_USER_RST                  30
  74 +#define MT7629_PCIE0_PIPE_RST                  31
  75 +
  76 +/* SSUSB Subsystem resets */
  77 +#define MT7629_SSUSB_PHY_PWR_RST               3
  78 +#define MT7629_SSUSB_MAC_PWR_RST               4
  79 +
  80 +/* ETH Subsystem resets */
  81 +#define MT7629_ETHSYS_SYS_RST                  0
  82 +#define MT7629_ETHSYS_MCM_RST                  2
  83 +#define MT7629_ETHSYS_HSDMA_RST                        5
  84 +#define MT7629_ETHSYS_FE_RST                   6
  85 +#define MT7629_ETHSYS_ESW_RST                  16
  86 +#define MT7629_ETHSYS_GMAC_RST                 23
  87 +#define MT7629_ETHSYS_EPHY_RST                 24
  88 +#define MT7629_ETHSYS_CRYPTO_RST               29
  89 +#define MT7629_ETHSYS_PPE_RST                  31
  90 +
  91 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
  92 --
  93 2.18.0
  94