target/linux/mediatek/patches-4.19/0227-arm-dts-Add-Unielec-U7623-DTS.patch

   1 From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Sun, 17 Jun 2018 14:41:47 +0200
   4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
   5
   6 ---
   7  arch/arm/boot/dts/Makefile                         |   1 +
   8  .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  18 +
   9  .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 366 +++++++++++++++++++++
  10  3 files changed, 385 insertions(+)
  11  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  12  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  13
  14 --- a/arch/arm/boot/dts/Makefile
  15 +++ b/arch/arm/boot/dts/Makefile
  16 @@ -1193,6 +1193,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  17         mt7623a-rfb-nand.dtb \
  18         mt7623n-rfb-emmc.dtb \
  19         mt7623n-bananapi-bpi-r2.dtb \
  20 +       mt7623a-unielec-u7623-02-emmc-512M.dtb \
  21         mt8127-moose.dtb \
  22         mt8135-evbp1.dtb
  23  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
  24 --- /dev/null
  25 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  26 @@ -0,0 +1,18 @@
  27 +/*
  28 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  29 + *
  30 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  31 + */
  32 +
  33 +/dts-v1/;
  34 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
  35 +
  36 +/ {
  37 +       model = "UniElec U7623-02 eMMC (512M RAM)";
  38 +       compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
  39 +
  40 +       memory@80000000 {
  41 +               device_type = "memory";
  42 +               reg = <0 0x80000000 0 0x20000000>;
  43 +       };
  44 +};
  45 --- /dev/null
  46 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  47 @@ -0,0 +1,366 @@
  48 +/*
  49 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  50 + *
  51 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  52 + */
  53 +
  54 +#include <dt-bindings/input/input.h>
  55 +#include "mt7623.dtsi"
  56 +#include "mt6323.dtsi"
  57 +
  58 +/ {
  59 +       compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
  60 +
  61 +       aliases {
  62 +               serial2 = &uart2;
  63 +       };
  64 +
  65 +       chosen {
  66 +               bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  67 +               stdout-path = "serial2:115200n8";
  68 +       };
  69 +
  70 +       cpus {
  71 +               cpu@0 {
  72 +                       proc-supply = <&mt6323_vproc_reg>;
  73 +               };
  74 +
  75 +               cpu@1 {
  76 +                       proc-supply = <&mt6323_vproc_reg>;
  77 +               };
  78 +
  79 +               cpu@2 {
  80 +                       proc-supply = <&mt6323_vproc_reg>;
  81 +               };
  82 +
  83 +               cpu@3 {
  84 +                       proc-supply = <&mt6323_vproc_reg>;
  85 +               };
  86 +       };
  87 +
  88 +       reg_1p8v: regulator-1p8v {
  89 +               compatible = "regulator-fixed";
  90 +               regulator-name = "fixed-1.8V";
  91 +               regulator-min-microvolt = <1800000>;
  92 +               regulator-max-microvolt = <1800000>;
  93 +               regulator-boot-on;
  94 +               regulator-always-on;
  95 +       };
  96 +
  97 +       reg_3p3v: regulator-3p3v {
  98 +               compatible = "regulator-fixed";
  99 +               regulator-name = "fixed-3.3V";
 100 +               regulator-min-microvolt = <3300000>;
 101 +               regulator-max-microvolt = <3300000>;
 102 +               regulator-boot-on;
 103 +               regulator-always-on;
 104 +       };
 105 +
 106 +       reg_5v: regulator-5v {
 107 +               compatible = "regulator-fixed";
 108 +               regulator-name = "fixed-5V";
 109 +               regulator-min-microvolt = <5000000>;
 110 +               regulator-max-microvolt = <5000000>;
 111 +               regulator-boot-on;
 112 +               regulator-always-on;
 113 +       };
 114 +
 115 +       gpio-keys {
 116 +               compatible = "gpio-keys";
 117 +               pinctrl-names = "default";
 118 +               pinctrl-0 = <&key_pins_a>;
 119 +
 120 +               factory {
 121 +                       label = "factory";
 122 +                       linux,code = <KEY_RESTART>;
 123 +                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 124 +               };
 125 +       };
 126 +
 127 +       leds {
 128 +               compatible = "gpio-leds";
 129 +               pinctrl-names = "default";
 130 +               pinctrl-0 = <&led_pins_unielec>;
 131 +
 132 +               led3 {
 133 +                       label = "u7623-01:green:led3";
 134 +                       gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 135 +                       default-state = "off";
 136 +               };
 137 +
 138 +               led4 {
 139 +                       label = "u7623-01:green:led4";
 140 +                       gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 141 +                       default-state = "off";
 142 +               };
 143 +       };
 144 +
 145 +       mt7530: switch@0 {
 146 +               compatible = "mediatek,mt7530";
 147 +               #address-cells = <1>;
 148 +               #size-cells = <0>;
 149 +       };
 150 +};
 151 +
 152 +&crypto {
 153 +       status = "okay";
 154 +};
 155 +
 156 +&eth {
 157 +       status = "okay";
 158 +
 159 +       gmac0: mac@0 {
 160 +               compatible = "mediatek,eth-mac";
 161 +               reg = <0>;
 162 +               phy-mode = "trgmii";
 163 +
 164 +               fixed-link {
 165 +                       speed = <1000>;
 166 +                       full-duplex;
 167 +                       pause;
 168 +               };
 169 +       };
 170 +
 171 +       mdio: mdio-bus {
 172 +               #address-cells = <1>;
 173 +               #size-cells = <0>;
 174 +               phy5: ethernet-phy@5 {
 175 +                       reg = <5>;
 176 +                       phy-mode = "rgmii-rxid";
 177 +               };
 178 +       };
 179 +};
 180 +
 181 +&mt7530 {
 182 +       compatible = "mediatek,mt7530";
 183 +       #address-cells = <1>;
 184 +       #size-cells = <0>;
 185 +       reg = <0>;
 186 +       pinctrl-names = "default";
 187 +       mediatek,mcm;
 188 +       resets = <&ethsys 2>;
 189 +       reset-names = "mcm";
 190 +       core-supply = <&mt6323_vpa_reg>;
 191 +       io-supply = <&mt6323_vemc3v3_reg>;
 192 +
 193 +       dsa,mii-bus = <&mdio>;
 194 +
 195 +       ports {
 196 +               #address-cells = <1>;
 197 +               #size-cells = <0>;
 198 +               reg = <0>;
 199 +
 200 +               port@0 {
 201 +                       reg = <0>;
 202 +                       label = "lan0";
 203 +                       cpu = <&cpu_port0>;
 204 +               };
 205 +
 206 +               port@1 {
 207 +                       reg = <1>;
 208 +                       label = "lan1";
 209 +                       cpu = <&cpu_port0>;
 210 +               };
 211 +
 212 +               port@2 {
 213 +                       reg = <2>;
 214 +                       label = "lan2";
 215 +                       cpu = <&cpu_port0>;
 216 +               };
 217 +
 218 +               port@3 {
 219 +                       reg = <3>;
 220 +                       label = "lan3";
 221 +                       cpu = <&cpu_port0>;
 222 +               };
 223 +
 224 +               port@4 {
 225 +                       reg = <4>;
 226 +                       label = "wan";
 227 +                       cpu = <&cpu_port0>;
 228 +               };
 229 +
 230 +               cpu_port0: port@6 {
 231 +                       reg = <6>;
 232 +                       label = "cpu";
 233 +                       ethernet = <&gmac0>;
 234 +                       phy-mode = "trgmii";
 235 +
 236 +                       fixed-link {
 237 +                               speed = <1000>;
 238 +                               full-duplex;
 239 +                       };
 240 +               };
 241 +       };
 242 +};
 243 +
 244 +&mmc0 {
 245 +       pinctrl-names = "default", "state_uhs";
 246 +       pinctrl-0 = <&mmc0_pins_default>;
 247 +       pinctrl-1 = <&mmc0_pins_uhs>;
 248 +       status = "okay";
 249 +       bus-width = <8>;
 250 +       max-frequency = <50000000>;
 251 +       cap-mmc-highspeed;
 252 +       vmmc-supply = <&reg_3p3v>;
 253 +       vqmmc-supply = <&reg_1p8v>;
 254 +       non-removable;
 255 +};
 256 +
 257 +&pio {
 258 +       key_pins_a: keys-alt {
 259 +               pins-keys {
 260 +                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
 261 +                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
 262 +                       input-enable;
 263 +               };
 264 +       };
 265 +
 266 +       led_pins_unielec: leds-unielec {
 267 +               pins-leds {
 268 +                       pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
 269 +                                <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 270 +               };
 271 +       };
 272 +
 273 +       mmc0_pins_default: mmc0default {
 274 +               pins_cmd_dat {
 275 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 276 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 277 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 278 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 279 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 280 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 281 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 282 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 283 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 284 +                       input-enable;
 285 +                       bias-pull-up;
 286 +               };
 287 +
 288 +               pins_clk {
 289 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 290 +                       bias-pull-down;
 291 +               };
 292 +
 293 +               pins_rst {
 294 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 295 +                       bias-pull-up;
 296 +               };
 297 +       };
 298 +
 299 +       mmc0_pins_uhs: mmc0 {
 300 +               pins_cmd_dat {
 301 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 302 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 303 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 304 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 305 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 306 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 307 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 308 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 309 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 310 +                       input-enable;
 311 +                       drive-strength = <MTK_DRIVE_2mA>;
 312 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 313 +               };
 314 +
 315 +               pins_clk {
 316 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 317 +                       drive-strength = <MTK_DRIVE_2mA>;
 318 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 319 +               };
 320 +
 321 +               pins_rst {
 322 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 323 +                       bias-pull-up;
 324 +               };
 325 +       };
 326 +
 327 +       pwm_pins_a: pwm@0 {
 328 +               pins_pwm {
 329 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 330 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 331 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 332 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 333 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 334 +               };
 335 +       };
 336 +
 337 +       uart2_pins_b: uart@2 {
 338 +               pins_dat {
 339 +                       pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
 340 +                                <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
 341 +               };
 342 +       };
 343 +
 344 +       pcie_default: pcie_pin_default {
 345 +               pins_cmd_dat {
 346 +                       pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
 347 +                                <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
 348 +                       bias-disable;
 349 +               };
 350 +       };
 351 +};
 352 +
 353 +&pwm {
 354 +       pinctrl-names = "default";
 355 +       pinctrl-0 = <&pwm_pins_a>;
 356 +       status = "okay";
 357 +};
 358 +
 359 +&pwrap {
 360 +       mt6323 {
 361 +               mt6323led: led {
 362 +                       compatible = "mediatek,mt6323-led";
 363 +                       #address-cells = <1>;
 364 +                       #size-cells = <0>;
 365 +
 366 +                       led@0 {
 367 +                               reg = <0>;
 368 +                               label = "led0";
 369 +                               default-state = "off";
 370 +                       };
 371 +               };
 372 +       };
 373 +};
 374 +
 375 +&uart2 {
 376 +       pinctrl-names = "default";
 377 +       pinctrl-0 = <&uart2_pins_b>;
 378 +       status = "okay";
 379 +};
 380 +
 381 +&usb1 {
 382 +       vusb33-supply = <&reg_3p3v>;
 383 +       vbus-supply = <&reg_3p3v>;
 384 +       status = "okay";
 385 +};
 386 +
 387 +&u3phy1 {
 388 +       status = "okay";
 389 +};
 390 +
 391 +&u3phy2 {
 392 +       status = "okay";
 393 +       mediatek,phy-switch = <&hifsys>;
 394 +};
 395 +
 396 +&pcie {
 397 +       pinctrl-names = "default";
 398 +       pinctrl-0 = <&pcie_default>;
 399 +       status = "okay";
 400 +
 401 +       pcie@1,0 {
 402 +               status = "okay";
 403 +       };
 404 +
 405 +       pcie@2,0 {
 406 +               status = "okay";
 407 +       };
 408 +};
 409 +
 410 +&pcie1_phy {
 411 +       status = "okay";
 412 +};
 413 +