target/linux/mediatek/patches/0009-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch

   1 From 87043a64dd5185dc076b3c3ab2e421b3a8c47798 Mon Sep 17 00:00:00 2001
   2 From: Sascha Hauer <s.hauer@pengutronix.de>
   3 Date: Thu, 23 Apr 2015 10:35:43 +0200
   4 Subject: [PATCH 09/76] dt-bindings: ARM: Mediatek: Document devicetree
   5  bindings for clock/reset controllers
   6
   7 This adds the binding documentation for the apmixedsys, perisys and
   8 infracfg controllers found on Mediatek SoCs.
   9
  10 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
  11 ---
  12  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |   23 +++++++++++++++
  13  .../bindings/arm/mediatek/mediatek,infracfg.txt    |   30 ++++++++++++++++++++
  14  .../bindings/arm/mediatek/mediatek,pericfg.txt     |   30 ++++++++++++++++++++
  15  .../bindings/arm/mediatek/mediatek,topckgen.txt    |   23 +++++++++++++++
  16  4 files changed, 106 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  18  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  19  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
  20  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
  21
  22 --- /dev/null
  23 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
  24 @@ -0,0 +1,23 @@
  25 +Mediatek apmixedsys controller
  26 +==============================
  27 +
  28 +The Mediatek apmixedsys controller provides the PLLs to the system.
  29 +
  30 +Required Properties:
  31 +
  32 +- compatible: Should be:
  33 +       - "mediatek,mt8135-apmixedsys"
  34 +       - "mediatek,mt8173-apmixedsys"
  35 +- #clock-cells: Must be 1
  36 +
  37 +The apmixedsys controller uses the common clk binding from
  38 +Documentation/devicetree/bindings/clock/clock-bindings.txt
  39 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  40 +
  41 +Example:
  42 +
  43 +apmixedsys: apmixedsys@10209000 {
  44 +       compatible = "mediatek,mt8173-apmixedsys";
  45 +       reg = <0 0x10209000 0 0x1000>;
  46 +       #clock-cells = <1>;
  47 +};
  48 --- /dev/null
  49 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
  50 @@ -0,0 +1,30 @@
  51 +Mediatek infracfg controller
  52 +============================
  53 +
  54 +The Mediatek infracfg controller provides various clocks and reset
  55 +outputs to the system.
  56 +
  57 +Required Properties:
  58 +
  59 +- compatible: Should be:
  60 +       - "mediatek,mt8135-infracfg", "syscon"
  61 +       - "mediatek,mt8173-infracfg", "syscon"
  62 +- #clock-cells: Must be 1
  63 +- #reset-cells: Must be 1
  64 +
  65 +The infracfg controller uses the common clk binding from
  66 +Documentation/devicetree/bindings/clock/clock-bindings.txt
  67 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  68 +Also it uses the common reset controller binding from
  69 +Documentation/devicetree/bindings/reset/reset.txt.
  70 +The available reset outputs are defined in
  71 +dt-bindings/reset-controller/mt*-resets.h
  72 +
  73 +Example:
  74 +
  75 +infracfg: infracfg@10001000 {
  76 +       compatible = "mediatek,mt8173-infracfg", "syscon";
  77 +       reg = <0 0x10001000 0 0x1000>;
  78 +       #clock-cells = <1>;
  79 +       #reset-cells = <1>;
  80 +};
  81 --- /dev/null
  82 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
  83 @@ -0,0 +1,30 @@
  84 +Mediatek pericfg controller
  85 +===========================
  86 +
  87 +The Mediatek pericfg controller provides various clocks and reset
  88 +outputs to the system.
  89 +
  90 +Required Properties:
  91 +
  92 +- compatible: Should be:
  93 +       - "mediatek,mt8135-pericfg", "syscon"
  94 +       - "mediatek,mt8173-pericfg", "syscon"
  95 +- #clock-cells: Must be 1
  96 +- #reset-cells: Must be 1
  97 +
  98 +The pericfg controller uses the common clk binding from
  99 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 100 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 101 +Also it uses the common reset controller binding from
 102 +Documentation/devicetree/bindings/reset/reset.txt.
 103 +The available reset outputs are defined in
 104 +dt-bindings/reset-controller/mt*-resets.h
 105 +
 106 +Example:
 107 +
 108 +pericfg: pericfg@10003000 {
 109 +       compatible = "mediatek,mt8173-pericfg", "syscon";
 110 +       reg = <0 0x10003000 0 0x1000>;
 111 +       #clock-cells = <1>;
 112 +       #reset-cells = <1>;
 113 +};
 114 --- /dev/null
 115 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 116 @@ -0,0 +1,23 @@
 117 +Mediatek topckgen controller
 118 +============================
 119 +
 120 +The Mediatek topckgen controller provides various clocks to the system.
 121 +
 122 +Required Properties:
 123 +
 124 +- compatible: Should be:
 125 +       - "mediatek,mt8135-topckgen"
 126 +       - "mediatek,mt8173-topckgen"
 127 +- #clock-cells: Must be 1
 128 +
 129 +The topckgen controller uses the common clk binding from
 130 +Documentation/devicetree/bindings/clock/clock-bindings.txt
 131 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 132 +
 133 +Example:
 134 +
 135 +topckgen: topckgen@10000000 {
 136 +       compatible = "mediatek,mt8173-topckgen";
 137 +       reg = <0 0x10000000 0 0x1000>;
 138 +       #clock-cells = <1>;
 139 +};