target/linux/mpc83xx/patches-3.10/202-ata-add-pata_rbppc_cf-driver.patch

   1 --- a/drivers/ata/Kconfig
   2 +++ b/drivers/ata/Kconfig
   3 @@ -938,5 +938,12 @@ config PATA_LEGACY
   4
   5           If unsure, say N.
   6
   7 +config PATA_RB_PPC
   8 +       tristate "MikroTik RB600 PATA support"
   9 +       depends on RB_PPC
  10 +       help
  11 +         This option enables support for PATA devices on MikroTik RouterBOARD
  12 +         600 series boards.
  13 +
  14  endif # ATA_SFF
  15  endif # ATA
  16 --- a/drivers/ata/Makefile
  17 +++ b/drivers/ata/Makefile
  18 @@ -92,6 +92,7 @@ obj-$(CONFIG_PATA_PALMLD)     += pata_palmld
  19  obj-$(CONFIG_PATA_PLATFORM)    += pata_platform.o
  20  obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
  21  obj-$(CONFIG_PATA_RB532)       += pata_rb532_cf.o
  22 +obj-$(CONFIG_PATA_RB_PPC)      += pata_rbppc_cf.o
  23  obj-$(CONFIG_PATA_RZ1000)      += pata_rz1000.o
  24  obj-$(CONFIG_PATA_SAMSUNG_CF)  += pata_samsung_cf.o
  25
  26 --- /dev/null
  27 +++ b/drivers/ata/pata_rbppc_cf.c
  28 @@ -0,0 +1,699 @@
  29 +/*
  30 + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
  31 + * Copyright (C) Mikrotik 2007
  32 + *
  33 + * This program is free software; you can redistribute it and/or modify it
  34 + * under the terms of the GNU General Public License as published by the
  35 + * Free Software Foundation; either version 2 of the License, or (at your
  36 + * option) any later version.
  37 + */
  38 +
  39 +#include <linux/kernel.h>
  40 +#include <linux/module.h>
  41 +#include <linux/init.h>
  42 +#include <scsi/scsi_host.h>
  43 +#include <linux/libata.h>
  44 +#include <linux/of_platform.h>
  45 +#include <linux/ata_platform.h>
  46 +#include <linux/slab.h>
  47 +
  48 +#define DEBUG_UPM      0
  49 +
  50 +#define DRV_NAME       "pata_rbppc_cf"
  51 +#define DRV_VERSION    "0.0.2"
  52 +
  53 +#define DEV2SEL_OFFSET 0x00100000
  54 +
  55 +#define IMMR_LBCFG_OFFSET      0x00005000
  56 +#define IMMR_LBCFG_SIZE                0x00001000
  57 +
  58 +#define LOCAL_BUS_MCMR         0x00000078
  59 +#define   MxMR_OP_MASK                 0x30000000
  60 +#define   MxMR_OP_NORMAL               0x00000000
  61 +#define   MxMR_OP_WRITE                        0x10000000
  62 +#define   MxMR_OP_READ                 0x20000000
  63 +#define   MxMR_OP_RUN                  0x30000000
  64 +#define   MxMR_LUPWAIT_LOW             0x08000000
  65 +#define   MxMR_LUPWAIT_HIGH            0x00000000
  66 +#define   MxMR_LUPWAIT_ENABLE          0x00040000
  67 +#define   MxMR_RLF_MASK                        0x0003c000
  68 +#define   MxMR_RLF_SHIFT                       14
  69 +#define   MxMR_WLF_MASK                        0x00003c00
  70 +#define   MxMR_WLF_SHIFT                       10
  71 +#define   MxMR_MAD_MASK                        0x0000003f
  72 +#define LOCAL_BUS_MDR          0x00000088
  73 +#define LOCAL_BUS_LCRR         0x000000D4
  74 +#define   LCRR_CLKDIV_MASK             0x0000000f
  75 +
  76 +#define LOOP_SIZE      4
  77 +
  78 +#define UPM_READ_SINGLE_OFFSET 0x00
  79 +#define UPM_WRITE_SINGLE_OFFSET        0x18
  80 +#define UPM_DATA_SIZE  0x40
  81 +
  82 +#define LBT_CPUIN_MIN          0
  83 +#define LBT_CPUOUT_MIN         1
  84 +#define LBT_CPUOUT_MAX         2
  85 +#define LBT_EXTDEL_MIN         3
  86 +#define LBT_EXTDEL_MAX         4
  87 +#define LBT_SIZE               5
  88 +
  89 +/* UPM machine configuration bits */
  90 +#define N_BASE 0x00f00000
  91 +#define N_CS   0xf0000000
  92 +#define N_CS_H1        0xc0000000
  93 +#define N_CS_H2        0x30000000
  94 +#define N_WE   0x0f000000
  95 +#define N_WE_H1        0x0c000000
  96 +#define N_WE_H2        0x03000000
  97 +#define N_OE   0x00030000
  98 +#define N_OE_H1        0x00020000
  99 +#define N_OE_H2        0x00010000
 100 +#define WAEN   0x00001000
 101 +#define REDO_2 0x00000100
 102 +#define REDO_3 0x00000200
 103 +#define REDO_4 0x00000300
 104 +#define LOOP   0x00000080
 105 +#define NA     0x00000008
 106 +#define UTA    0x00000004
 107 +#define LAST   0x00000001
 108 +
 109 +#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
 110 +#define REDO_MAX_MULT  4
 111 +
 112 +#define READ_BASE      (N_BASE | N_WE)
 113 +#define WRITE_BASE     (N_BASE | N_OE)
 114 +#define EMPTY          (N_BASE | N_CS | N_OE | N_WE | LAST)
 115 +
 116 +#define EOF_UPM_SETTINGS       0
 117 +#define ANOTHER_TIMING         1
 118 +
 119 +#define OA_CPUIN_MIN           0x01
 120 +#define OA_CPUOUT_MAX          0x02
 121 +#define OD_CPUOUT_MIN          0x04
 122 +#define OA_CPUOUT_DELTA                0x06
 123 +#define OA_EXTDEL_MAX          0x08
 124 +#define OD_EXTDEL_MIN          0x10
 125 +#define OA_EXTDEL_DELTA                0x18
 126 +#define O_MIN_CYCLE_TIME       0x20
 127 +#define O_MINUS_PREV           0x40
 128 +#define O_HALF_CYCLE           0x80
 129 +
 130 +extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
 131 +extern void localbus_unmap(void __iomem *addr);
 132 +
 133 +struct rbppc_cf_info {
 134 +       unsigned lbcfg_addr;
 135 +       unsigned clk_time_ps;
 136 +       int cur_mode;
 137 +       u32 lb_timings[LBT_SIZE];
 138 +};
 139 +static struct rbppc_cf_info *rbinfo = NULL;
 140 +
 141 +struct upm_setting {
 142 +       unsigned value;
 143 +       unsigned ns[7];
 144 +       unsigned clk_minus;
 145 +       unsigned group_size;
 146 +       unsigned options;
 147 +};
 148 +
 149 +static const struct upm_setting cfUpmReadSingle[] = {
 150 +       { READ_BASE | N_OE,
 151 +         /* t1 - ADDR setup time */
 152 +               {  70,  50,  30,  30,  25,  15,  10 }, 0, 0, (OA_CPUOUT_DELTA |
 153 +                                                             OA_EXTDEL_MAX) },
 154 +       { READ_BASE | N_OE_H1,
 155 +               {   0,   0,   0,   0,   0,   0,   0 }, 0, 0, O_HALF_CYCLE },
 156 +       { READ_BASE,
 157 +         /* t2 - OE0 time */
 158 +               { 290, 290, 290,  80,  70,  65,  55 }, 0, 2, (OA_CPUOUT_MAX |
 159 +                                                             OA_CPUIN_MIN) },
 160 +       { READ_BASE | WAEN,
 161 +               {   1,   1,   1,   1,   1,   0,   0 }, 0, 0, 0 },
 162 +       { READ_BASE | UTA,
 163 +               {   1,   1,   1,   1,   1,   1,   1 }, 0, 0, 0 },
 164 +       { READ_BASE | N_OE,
 165 +         /* t9 - ADDR hold time */
 166 +               {  20,  15,  10,  10,  10,  10,  10 }, 0, 0, (OA_CPUOUT_DELTA |
 167 +                                                             OD_EXTDEL_MIN) },
 168 +       { READ_BASE | N_OE | N_CS_H2,
 169 +               {   0,   0,   0,   0,   0,   0,   0 }, 0, 0, O_HALF_CYCLE },
 170 +       { READ_BASE | N_OE | N_CS,
 171 +         /* t6Z -IORD data tristate */
 172 +               {  30,  30,  30,  30,  30,  20,  20 }, 1, 1, O_MINUS_PREV },
 173 +       { ANOTHER_TIMING,
 174 +         /* t2i -IORD recovery time */
 175 +               {   0,   0,   0,  70,  25,  25,  20 }, 2, 0, 0 },
 176 +       { ANOTHER_TIMING,
 177 +         /* CS 0 -> 1 MAX */
 178 +               {   0,   0,   0,   0,   0,   0,   0 }, 1, 0, (OA_CPUOUT_DELTA |
 179 +                                                             OA_EXTDEL_MAX) },
 180 +       { READ_BASE | N_OE | N_CS | LAST,
 181 +               {   1,   1,   1,   1,   1,   1,   1 }, 0, 0, 0 },
 182 +       { EOF_UPM_SETTINGS,
 183 +         /* min total cycle time - includes turnaround and ALE cycle */
 184 +               { 600, 383, 240, 180, 120, 100,  80 }, 2, 0, O_MIN_CYCLE_TIME },
 185 +};
 186 +
 187 +static const struct upm_setting cfUpmWriteSingle[] = {
 188 +       { WRITE_BASE | N_WE,
 189 +         /* t1 - ADDR setup time */
 190 +               {  70,  50,  30,  30,  25,  15,  10 }, 0, 0, (OA_CPUOUT_DELTA |
 191 +                                                             OA_EXTDEL_MAX) },
 192 +       { WRITE_BASE | N_WE_H1,
 193 +               {   0,   0,   0,   0,   0,   0,   0 }, 0, 0, O_HALF_CYCLE },
 194 +       { WRITE_BASE,
 195 +         /* t2 - WE0 time */
 196 +               { 290, 290, 290,  80,  70,  65,  55 }, 0, 1, OA_CPUOUT_DELTA },
 197 +       { WRITE_BASE | WAEN,
 198 +               {   1,   1,   1,   1,   1,   0,   0 }, 0, 0, 0 },
 199 +       { WRITE_BASE | N_WE,
 200 +         /* t9 - ADDR hold time */
 201 +               {  20,  15,  10,  10,  10,  10,  10 }, 0, 0, (OA_CPUOUT_DELTA |
 202 +                                                             OD_EXTDEL_MIN) },
 203 +       { WRITE_BASE | N_WE | N_CS_H2,
 204 +               {   0,   0,   0,   0,   0,   0,   0 }, 0, 0, O_HALF_CYCLE },
 205 +       { WRITE_BASE | N_WE | N_CS,
 206 +         /* t4 - DATA hold time */
 207 +               {  30,  20,  15,  10,  10,  10,  10 }, 0, 1, O_MINUS_PREV },
 208 +       { ANOTHER_TIMING,
 209 +         /* t2i -IOWR recovery time */
 210 +               {   0,   0,   0,  70,  25,  25,  20 }, 1, 0, 0 },
 211 +       { ANOTHER_TIMING,
 212 +         /* CS 0 -> 1 MAX */
 213 +               {   0,   0,   0,   0,   0,   0,   0 }, 0, 0, (OA_CPUOUT_DELTA |
 214 +                                                             OA_EXTDEL_MAX) },
 215 +       { WRITE_BASE | N_WE | N_CS | UTA | LAST,
 216 +               {   1,   1,   1,   1,   1,   1,   1 }, 0, 0, 0 },
 217 +       /* min total cycle time - includes ALE cycle */
 218 +       { EOF_UPM_SETTINGS,
 219 +               { 600, 383, 240, 180, 120, 100,  80 }, 1, 0, O_MIN_CYCLE_TIME },
 220 +};
 221 +
 222 +static u8 rbppc_cf_check_status(struct ata_port *ap) {
 223 +       u8 val = ioread8(ap->ioaddr.status_addr);
 224 +       if (val == 0xF9)
 225 +               val = 0x7F;
 226 +       return val;
 227 +}
 228 +
 229 +static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
 230 +       u8 val = ioread8(ap->ioaddr.altstatus_addr);
 231 +       if (val == 0xF9)
 232 +               val = 0x7F;
 233 +       return val;
 234 +}
 235 +
 236 +static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
 237 +static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
 238 +
 239 +static int ps2clk(int ps, unsigned clk_time_ps) {
 240 +       int psMaxOver;
 241 +       if (ps <= 0) return 0;
 242 +
 243 +       /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
 244 +       psMaxOver = ps * 2 / 100;
 245 +       if (4 * psMaxOver > clk_time_ps) {
 246 +               psMaxOver = clk_time_ps / 4;
 247 +       }
 248 +       return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
 249 +}
 250 +
 251 +static int upm_gen_ps_table(const struct upm_setting *upm,
 252 +                           int mode, struct rbppc_cf_info *info,
 253 +                           int *psFinal) {
 254 +       int uidx;
 255 +       int lastUpmValIdx = 0;
 256 +       int group_start_idx = -1;
 257 +       int group_left_num = -1;
 258 +       int clk_time_ps = info->clk_time_ps;
 259 +
 260 +       for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
 261 +               const struct upm_setting *us = upm + uidx;
 262 +               unsigned opt = us->options;
 263 +               int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
 264 +
 265 +               if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
 266 +               if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
 267 +               if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
 268 +               if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
 269 +               if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
 270 +
 271 +               if (us->value == ANOTHER_TIMING) {
 272 +                       /* use longest timing from alternatives */
 273 +                       if (psFinal[lastUpmValIdx] < ps) {
 274 +                               psFinal[lastUpmValIdx] = ps;
 275 +                       }
 276 +                       ps = 0;
 277 +               }
 278 +               else {
 279 +                       if (us->group_size) {
 280 +                               group_start_idx = uidx;
 281 +                               group_left_num = us->group_size;
 282 +                       }
 283 +                       else if (group_left_num > 0) {
 284 +                               /* group time is divided on all group members */
 285 +                               int clk = ps2clk(ps, clk_time_ps);
 286 +                               psFinal[group_start_idx] -= clk * clk_time_ps;
 287 +                               --group_left_num;
 288 +                       }
 289 +                       if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
 290 +                               int clk = ps2clk(psFinal[lastUpmValIdx],
 291 +                                                clk_time_ps);
 292 +                               ps -= clk * clk_time_ps;
 293 +                       }
 294 +                       lastUpmValIdx = uidx;
 295 +               }
 296 +               psFinal[uidx] = ps;
 297 +       }
 298 +       return uidx;
 299 +}
 300 +
 301 +static int free_half(int ps, int clk, int clk_time_ps) {
 302 +    if (clk < 2) return 0;
 303 +    return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
 304 +}
 305 +
 306 +static void upm_gen_clk_table(const struct upm_setting *upm,
 307 +                             int mode, int clk_time_ps,
 308 +                             int max_uidx, const int *psFinal, int *clkFinal) {
 309 +       int clk_cycle_time;
 310 +       int clk_total;
 311 +       int uidx;
 312 +
 313 +       /* convert picoseconds to clocks */
 314 +       clk_total = 0;
 315 +       for (uidx = 0; uidx < max_uidx; ++uidx) {
 316 +               int clk = ps2clk(psFinal[uidx], clk_time_ps);
 317 +               clkFinal[uidx] = clk;
 318 +               clk_total += clk;
 319 +       }
 320 +
 321 +       /* check possibility of half cycle usage */
 322 +       for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
 323 +               if ((upm[uidx].options & O_HALF_CYCLE) &&
 324 +                   free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
 325 +                             clk_time_ps) &&
 326 +                   free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
 327 +                             clk_time_ps)) {
 328 +                       ++clkFinal[uidx];
 329 +                       --clkFinal[uidx - 1];
 330 +                       --clkFinal[uidx + 1];
 331 +               }
 332 +       }
 333 +
 334 +       if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
 335 +
 336 +       /* check cycle time, adjust timings if needed */
 337 +       clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
 338 +                         upm[max_uidx].clk_minus);
 339 +       uidx = 0;
 340 +       while (clk_total < clk_cycle_time) {
 341 +               /* extend all timings in round-robin to match cycle time */
 342 +               if (clkFinal[uidx]) {
 343 +#if DEBUG_UPM
 344 +                       printk(KERN_INFO "extending %u by 1 clk\n", uidx);
 345 +#endif
 346 +                       ++clkFinal[uidx];
 347 +                       ++clk_total;
 348 +               }
 349 +               ++uidx;
 350 +               if (uidx == max_uidx) uidx = 0;
 351 +       }
 352 +}
 353 +
 354 +static void add_data_val(unsigned val, int *clkLeft, int maxClk,
 355 +                       unsigned *data, int *dataIdx) {
 356 +       if (*clkLeft == 0) return;
 357 +
 358 +       if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
 359 +               int times;
 360 +               int times1;
 361 +               int times2;
 362 +
 363 +               times = *clkLeft / LOOP_SIZE;
 364 +               if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
 365 +               times1 = times / 2;
 366 +               times2 = times - times1;
 367 +
 368 +               val |= LOOP;
 369 +               data[*dataIdx] = val | REDO_VAL(times1);
 370 +               ++(*dataIdx);
 371 +               data[*dataIdx] = val | REDO_VAL(times2);
 372 +               ++(*dataIdx);
 373 +
 374 +               *clkLeft -= times * LOOP_SIZE;
 375 +               return;
 376 +       }
 377 +
 378 +       if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
 379 +       if (*clkLeft < maxClk) maxClk = *clkLeft;
 380 +
 381 +       *clkLeft -= maxClk;
 382 +       val |= REDO_VAL(maxClk);
 383 +
 384 +       data[*dataIdx] = val;
 385 +       ++(*dataIdx);
 386 +}
 387 +
 388 +static int upm_gen_final_data(const struct upm_setting *upm,
 389 +                              int max_uidx, int *clkFinal, unsigned *data) {
 390 +       int dataIdx;
 391 +       int uidx;
 392 +
 393 +       dataIdx = 0;
 394 +       for (uidx = 0; uidx < max_uidx; ++uidx) {
 395 +               int clk = clkFinal[uidx];
 396 +               while (clk > 0) {
 397 +                       add_data_val(upm[uidx].value, &clk, 0,
 398 +                                    data, &dataIdx);
 399 +               }
 400 +       }
 401 +       return dataIdx;
 402 +}
 403 +
 404 +static int conv_upm_table(const struct upm_setting *upm,
 405 +                         int mode, struct rbppc_cf_info *info,
 406 +                         unsigned *data) {
 407 +#if DEBUG_UPM
 408 +       int uidx;
 409 +#endif
 410 +       int psFinal[32];
 411 +       int clkFinal[32];
 412 +       int max_uidx;
 413 +       int data_len;
 414 +
 415 +       max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
 416 +
 417 +       upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
 418 +                         psFinal, clkFinal);
 419 +
 420 +#if DEBUG_UPM
 421 +       /* dump out debug info */
 422 +       for (uidx = 0; uidx < max_uidx; ++uidx) {
 423 +               if (clkFinal[uidx]) {
 424 +                       printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
 425 +                               uidx, upm[uidx].value,
 426 +                               clkFinal[uidx], psFinal[uidx]);
 427 +               }
 428 +       }
 429 +#endif
 430 +
 431 +       data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
 432 +
 433 +#if DEBUG_UPM
 434 +       for (uidx = 0; uidx < data_len; ++uidx) {
 435 +               printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
 436 +                      uidx, data[uidx]);
 437 +       }
 438 +#endif
 439 +       return 0;
 440 +}
 441 +
 442 +static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
 443 +       int i;
 444 +
 445 +       for (i = 0; i < UPM_DATA_SIZE; ++i) {
 446 +               data[i] = EMPTY;
 447 +       }
 448 +
 449 +       if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
 450 +               return -1;
 451 +       }
 452 +       if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
 453 +               return -1;
 454 +       }
 455 +       return 0;
 456 +}
 457 +
 458 +static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
 459 +       unsigned i;
 460 +       unsigned mxmr;
 461 +
 462 +       mxmr = in_be32(lbcfg_mxmr);
 463 +       mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
 464 +       mxmr |= (MxMR_OP_WRITE | offset);
 465 +       out_be32(lbcfg_mxmr, mxmr);
 466 +       in_be32(lbcfg_mxmr); /* flush MxMR write */
 467 +
 468 +       for (i = 0; i < len; ++i) {
 469 +               int to;
 470 +               unsigned data = upmData[i + offset];
 471 +               out_be32(lbcfg_mdr, data);
 472 +               in_be32(lbcfg_mdr); /* flush MDR write */
 473 +
 474 +               iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
 475 +
 476 +               /* wait for dummy write to complete */
 477 +               for (to = 10000; to >= 0; --to) {
 478 +                       mxmr = in_be32(lbcfg_mxmr);
 479 +                       if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
 480 +                               break;
 481 +                       }
 482 +                       if (to == 0) {
 483 +                               printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
 484 +                       }
 485 +               }
 486 +       }
 487 +       mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
 488 +       mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
 489 +       out_be32(lbcfg_mxmr, mxmr);
 490 +}
 491 +
 492 +static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
 493 +       struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
 494 +       void *lbcfgBase;
 495 +       unsigned upmData[UPM_DATA_SIZE];
 496 +
 497 +       if (gen_upm_data(mode, info, upmData)) {
 498 +               return -1;
 499 +       }
 500 +
 501 +       lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
 502 +
 503 +       rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
 504 +       iounmap(lbcfgBase);
 505 +       return 0;
 506 +}
 507 +
 508 +static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
 509 +{
 510 +       struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
 511 +       int mode = adev->pio_mode - XFER_PIO_0;
 512 +
 513 +       DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
 514 +       if (mode < 0) mode = 0;
 515 +       if (mode > 6) mode = 6;
 516 +
 517 +       if (info->cur_mode < 0 || info->cur_mode > mode) {
 518 +               if (rbppc_cf_update_piomode(ap, mode) == 0) {
 519 +                       printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
 520 +                       info->cur_mode = mode;
 521 +               }
 522 +       }
 523 +}
 524 +
 525 +static struct scsi_host_template rbppc_cf_sht = {
 526 +       ATA_BASE_SHT(DRV_NAME),
 527 +};
 528 +
 529 +static struct ata_port_operations rbppc_cf_port_ops = {
 530 +       .inherits               = &ata_bmdma_port_ops,
 531 +
 532 +       .sff_check_status       = rbppc_cf_check_status,
 533 +       .sff_check_altstatus    = rbppc_cf_check_altstatus,
 534 +
 535 +       .set_piomode            = rbppc_cf_set_piomode,
 536 +
 537 +       .port_start             = rbppc_cf_dummy_ret0,
 538 +
 539 +       .sff_irq_clear          = rbppc_cf_dummy_noret,
 540 +};
 541 +
 542 +static int rbppc_cf_init_info(struct platform_device *pdev, struct rbppc_cf_info *info) {
 543 +       struct device_node *np;
 544 +       struct resource res;
 545 +       const u32 *u32ptr;
 546 +       void *lbcfgBase;
 547 +       void *lbcfg_lcrr;
 548 +       unsigned lbc_clk_khz;
 549 +       unsigned lbc_extra_divider = 1;
 550 +       unsigned ccb_freq_hz;
 551 +       unsigned lb_div;
 552 +
 553 +       u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
 554 +       if (u32ptr && *u32ptr) {
 555 +               lbc_extra_divider = *u32ptr;
 556 +#if DEBUG_UPM
 557 +               printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
 558 +                      lbc_extra_divider);
 559 +#endif
 560 +       }
 561 +
 562 +       np = of_find_node_by_type(NULL, "serial");
 563 +       if (!np) {
 564 +               printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
 565 +               return -1;
 566 +       }
 567 +       u32ptr = of_get_property(np, "clock-frequency", NULL);
 568 +       if (u32ptr == 0 || *u32ptr == 0) {
 569 +               printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
 570 +               of_node_put(np);
 571 +               return -1;
 572 +       }
 573 +       ccb_freq_hz = *u32ptr;
 574 +       of_node_put(np);
 575 +
 576 +       np = of_find_node_by_type(NULL, "soc");
 577 +       if (!np) {
 578 +               printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
 579 +               return -1;
 580 +       }
 581 +       if (of_address_to_resource(np, 0, &res)) {
 582 +               printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
 583 +               of_node_put(np);
 584 +               return -1;
 585 +       }
 586 +       info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
 587 +       of_node_put(np);
 588 +
 589 +       lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
 590 +       lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
 591 +       lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
 592 +       iounmap(lbcfgBase);
 593 +
 594 +       lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
 595 +       info->clk_time_ps = 1000000000 / lbc_clk_khz;
 596 +       printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
 597 +              lbc_clk_khz, info->clk_time_ps);
 598 +
 599 +       u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
 600 +       if (u32ptr) {
 601 +               memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
 602 +#if DEBUG_UPM
 603 +               printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
 604 +                      u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
 605 +#endif
 606 +       }
 607 +       info->cur_mode = -1;
 608 +       return 0;
 609 +}
 610 +
 611 +static int rbppc_cf_probe(struct platform_device *pdev)
 612 +{
 613 +       struct ata_host *host;
 614 +       struct ata_port *ap;
 615 +       struct rbppc_cf_info *info = NULL;
 616 +       struct resource res;
 617 +       void *baddr;
 618 +       const u32 *u32ptr;
 619 +       int irq_level = 0;
 620 +       int err = -ENOMEM;
 621 +
 622 +       printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
 623 +
 624 +       if (rbinfo == NULL) {
 625 +               info = kmalloc(sizeof(*info), GFP_KERNEL);
 626 +               if (info == NULL) {
 627 +                       printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
 628 +                       goto err_info;
 629 +               }
 630 +               memset(info, 0, sizeof(*info));
 631 +
 632 +               if (rbppc_cf_init_info(pdev, info)) {
 633 +                       goto err_info;
 634 +               }
 635 +               rbinfo = info;
 636 +       }
 637 +
 638 +       u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
 639 +       if (u32ptr) {
 640 +               irq_level = *u32ptr;
 641 +               printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
 642 +       }
 643 +
 644 +       if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
 645 +           printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
 646 +           goto err_info;
 647 +       }
 648 +
 649 +       host = ata_host_alloc(&pdev->dev, 1);
 650 +       if (!host)
 651 +           goto err_info;
 652 +
 653 +       baddr = localbus_map(res.start, res.end - res.start + 1);
 654 +       host->iomap = baddr;
 655 +       host->private_data = rbinfo;
 656 +
 657 +       ap = host->ports[0];
 658 +       ap->ops = &rbppc_cf_port_ops;
 659 +       ap->pio_mask = 0x7F;    /* PIO modes 0-6 */
 660 +       ap->mwdma_mask = 0;
 661 +
 662 +       ap->ioaddr.cmd_addr = baddr;
 663 +       ata_sff_std_ports(&ap->ioaddr);
 664 +       ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
 665 +       ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
 666 +       ap->ioaddr.bmdma_addr = 0;
 667 +
 668 +       err = ata_host_activate(
 669 +               host,
 670 +               irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
 671 +               irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
 672 +               &rbppc_cf_sht);
 673 +       if (!err) return 0;
 674 +
 675 +       localbus_unmap(baddr);
 676 +err_info:
 677 +       if (info) {
 678 +               kfree(info);
 679 +               rbinfo = NULL;
 680 +       }
 681 +       return err;
 682 +}
 683 +
 684 +static int rbppc_cf_remove(struct platform_device *pdev)
 685 +{
 686 +       struct device *dev = &pdev->dev;
 687 +       struct ata_host *host = dev_get_drvdata(dev);
 688 +
 689 +       if (host == NULL) return -1;
 690 +
 691 +       ata_host_detach(host);
 692 +       return 0;
 693 +}
 694 +
 695 +static struct of_device_id rbppc_cf_ids[] = {
 696 +       { .name = "cf", },
 697 +       { },
 698 +};
 699 +
 700 +static struct platform_driver rbppc_cf_driver = {
 701 +       .probe = rbppc_cf_probe,
 702 +       .remove = rbppc_cf_remove,
 703 +       .driver = {
 704 +               .name = "rbppc-cf",
 705 +               .owner = THIS_MODULE,
 706 +               .of_match_table = rbppc_cf_ids,
 707 +       },
 708 +};
 709 +
 710 +static int __init rbppc_init(void)
 711 +{
 712 +       return platform_driver_register(&rbppc_cf_driver);
 713 +}
 714 +
 715 +static void __exit rbppc_exit(void)
 716 +{
 717 +       platform_driver_unregister(&rbppc_cf_driver);
 718 +}
 719 +
 720 +MODULE_AUTHOR("Mikrotikls SIA");
 721 +MODULE_AUTHOR("Noah Fontes");
 722 +MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
 723 +MODULE_LICENSE("GPL");
 724 +MODULE_VERSION(DRV_VERSION);
 725 +
 726 +module_init(rbppc_init);
 727 +module_exit(rbppc_exit);