target/linux/mvebu/patches-4.14/527-PCI-aardvark-allow-to-specify-link-capability.patch

   1 From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
   2 From: Tomasz Maciej Nowak <tmn505@gmail.com>
   3 Date: Thu, 14 Jun 2018 14:24:40 +0200
   4 Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
   5
   6 Use DT of_pci_get_max_link_speed() facility to allow specifying link
   7 capability. If none or unspecified value is given it falls back to gen2,
   8 which is default for Armada 3700 SoC.
   9
  10 Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
  11 ---
  12  drivers/pci/host/pci-aardvark.c | 11 +++++++++--
  13  1 file changed, 9 insertions(+), 2 deletions(-)
  14
  15 --- a/drivers/pci/host/pci-aardvark.c
  16 +++ b/drivers/pci/host/pci-aardvark.c
  17 @@ -272,6 +272,8 @@ static void advk_pcie_set_ob_win(struct
  18
  19  static void advk_pcie_setup_hw(struct advk_pcie *pcie)
  20  {
  21 +       struct device *dev = &pcie->pdev->dev;
  22 +       struct device_node *node = dev->of_node;
  23         u32 reg;
  24         int i;
  25
  26 @@ -311,10 +313,15 @@ static void advk_pcie_setup_hw(struct ad
  27                 PCIE_CORE_CTRL2_TD_ENABLE;
  28         advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  29
  30 -       /* Set GEN2 */
  31 +       /* Set GEN */
  32         reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  33         reg &= ~PCIE_GEN_SEL_MSK;
  34 -       reg |= SPEED_GEN_2;
  35 +       if (of_pci_get_max_link_speed(node) == 1)
  36 +               reg |= SPEED_GEN_1;
  37 +       else if (of_pci_get_max_link_speed(node) == 3)
  38 +               reg |= SPEED_GEN_3;
  39 +       else
  40 +               reg |= SPEED_GEN_2;
  41         advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  42
  43         /* Set lane X1 */