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kernel: update kernel 4.9 to 4.9.17
[openwrt/staging/chunkeey.git] / target / linux / pistachio / patches-4.9 / 001-MIPS-DTS-Add-base-device-tree-for-Pistachio-SoC.patch
1 From 8efda11baddf344cbfab01dc016a8fef9bb64641 Mon Sep 17 00:00:00 2001
2 From: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
3 Date: Fri, 14 Oct 2016 11:25:54 +0530
4 Subject: MIPS: DTS: Add base device tree for Pistachio SoC
5
6 Add support for the base Device Tree for Imagination Technologies'
7 Pistachio SoC.
8
9 This commit supports the following peripherals:
10
11 * Clocks
12 * Pinctrl and GPIO
13 * UART
14 * SPI
15 * I2C
16 * PWM
17 * ADC
18 * Watchdog
19 * Ethernet
20 * MMC
21 * DMA engine
22 * Crypto
23 * I2S
24 * SPDIF
25 * Internal DAC
26 * Timer
27 * USB
28 * IR
29 * Interrupt Controller
30
31 Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
32 Acked-by: James Hartley <james.hartley@imgtec.com>
33 Cc: Rob Herring <robh+dt@kernel.org>
34 Cc: Mark Rutland <mark.rutland@arm.com>
35 Cc: linux-mips@linux-mips.org
36 Cc: devicetree@vger.kernel.org
37 Cc: linux-kernel@vger.kernel.org
38 Patchwork: https://patchwork.linux-mips.org/patch/14393/
39 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
40 ---
41 MAINTAINERS | 2 +-
42 arch/mips/boot/dts/img/pistachio.dtsi | 924 ++++++++++++++++++++++++++++++++++
43 2 files changed, 925 insertions(+), 1 deletion(-)
44 create mode 100644 arch/mips/boot/dts/img/pistachio.dtsi
45
46 --- a/MAINTAINERS
47 +++ b/MAINTAINERS
48 @@ -9569,7 +9569,7 @@ L: linux-mips@linux-mips.org
49 S: Maintained
50 F: arch/mips/pistachio/
51 F: arch/mips/include/asm/mach-pistachio/
52 -F: arch/mips/boot/dts/pistachio/
53 +F: arch/mips/boot/dts/img/pistachio*
54 F: arch/mips/configs/pistachio*_defconfig
55
56 PKTCDVD DRIVER
57 --- /dev/null
58 +++ b/arch/mips/boot/dts/img/pistachio.dtsi
59 @@ -0,0 +1,924 @@
60 +/*
61 + * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
62 + * Copyright (C) 2015 Google, Inc.
63 + *
64 + * This program is free software; you can redistribute it and/or modify
65 + * it under the terms of the GNU General Public License version 2 as
66 + * published by the Free Software Foundation.
67 + */
68 +
69 +#include <dt-bindings/clock/pistachio-clk.h>
70 +#include <dt-bindings/gpio/gpio.h>
71 +#include <dt-bindings/interrupt-controller/irq.h>
72 +#include <dt-bindings/interrupt-controller/mips-gic.h>
73 +#include <dt-bindings/reset/pistachio-resets.h>
74 +
75 +/ {
76 + compatible = "img,pistachio";
77 +
78 + #address-cells = <1>;
79 + #size-cells = <1>;
80 +
81 + interrupt-parent = <&gic>;
82 +
83 + cpus {
84 + #address-cells = <1>;
85 + #size-cells = <0>;
86 +
87 + cpu0: cpu@0 {
88 + device_type = "cpu";
89 + compatible = "mti,interaptiv";
90 + reg = <0>;
91 + clocks = <&clk_core CLK_MIPS_PLL>;
92 + clock-names = "cpu";
93 + clock-latency = <1000>;
94 + operating-points = <
95 + /* kHz uV(dummy) */
96 + 546000 1150000
97 + 520000 1100000
98 + 494000 1000000
99 + 468000 950000
100 + 442000 900000
101 + 416000 800000
102 + >;
103 + };
104 + };
105 +
106 + i2c0: i2c@18100000 {
107 + compatible = "img,scb-i2c";
108 + reg = <0x18100000 0x200>;
109 + interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
110 + clocks = <&clk_periph PERIPH_CLK_I2C0>,
111 + <&cr_periph SYS_CLK_I2C0>;
112 + clock-names = "scb", "sys";
113 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
114 + <&clk_periph PERIPH_CLK_I2C0_DIV>;
115 + assigned-clock-rates = <100000000>, <33333334>;
116 + status = "disabled";
117 + pinctrl-names = "default";
118 + pinctrl-0 = <&i2c0_pins>;
119 +
120 + #address-cells = <1>;
121 + #size-cells = <0>;
122 + };
123 +
124 + i2c1: i2c@18100200 {
125 + compatible = "img,scb-i2c";
126 + reg = <0x18100200 0x200>;
127 + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
128 + clocks = <&clk_periph PERIPH_CLK_I2C1>,
129 + <&cr_periph SYS_CLK_I2C1>;
130 + clock-names = "scb", "sys";
131 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
132 + <&clk_periph PERIPH_CLK_I2C1_DIV>;
133 + assigned-clock-rates = <100000000>, <33333334>;
134 + status = "disabled";
135 + pinctrl-names = "default";
136 + pinctrl-0 = <&i2c1_pins>;
137 +
138 + #address-cells = <1>;
139 + #size-cells = <0>;
140 + };
141 +
142 + i2c2: i2c@18100400 {
143 + compatible = "img,scb-i2c";
144 + reg = <0x18100400 0x200>;
145 + interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
146 + clocks = <&clk_periph PERIPH_CLK_I2C2>,
147 + <&cr_periph SYS_CLK_I2C2>;
148 + clock-names = "scb", "sys";
149 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
150 + <&clk_periph PERIPH_CLK_I2C2_DIV>;
151 + assigned-clock-rates = <100000000>, <33333334>;
152 + status = "disabled";
153 + pinctrl-names = "default";
154 + pinctrl-0 = <&i2c2_pins>;
155 +
156 + #address-cells = <1>;
157 + #size-cells = <0>;
158 + };
159 +
160 + i2c3: i2c@18100600 {
161 + compatible = "img,scb-i2c";
162 + reg = <0x18100600 0x200>;
163 + interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
164 + clocks = <&clk_periph PERIPH_CLK_I2C3>,
165 + <&cr_periph SYS_CLK_I2C3>;
166 + clock-names = "scb", "sys";
167 + assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
168 + <&clk_periph PERIPH_CLK_I2C3_DIV>;
169 + assigned-clock-rates = <100000000>, <33333334>;
170 + status = "disabled";
171 + pinctrl-names = "default";
172 + pinctrl-0 = <&i2c3_pins>;
173 +
174 + #address-cells = <1>;
175 + #size-cells = <0>;
176 + };
177 +
178 + i2s_in: i2s-in@18100800 {
179 + compatible = "img,i2s-in";
180 + reg = <0x18100800 0x200>;
181 + interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
182 + dmas = <&mdc 30 0xffffffff 0>;
183 + dma-names = "rx";
184 + clocks = <&cr_periph SYS_CLK_I2S_IN>;
185 + clock-names = "sys";
186 + img,i2s-channels = <6>;
187 + pinctrl-names = "default";
188 + pinctrl-0 = <&i2s_in_pins>;
189 + status = "disabled";
190 +
191 + #sound-dai-cells = <0>;
192 + };
193 +
194 + i2s_out: i2s-out@18100a00 {
195 + compatible = "img,i2s-out";
196 + reg = <0x18100a00 0x200>;
197 + interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
198 + dmas = <&mdc 23 0xffffffff 0>;
199 + dma-names = "tx";
200 + clocks = <&cr_periph SYS_CLK_I2S_OUT>,
201 + <&clk_core CLK_I2S>;
202 + clock-names = "sys", "ref";
203 + assigned-clocks = <&clk_core CLK_I2S_DIV>;
204 + assigned-clock-rates = <12288000>;
205 + img,i2s-channels = <6>;
206 + pinctrl-names = "default";
207 + pinctrl-0 = <&i2s_out_pins>;
208 + status = "disabled";
209 + resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
210 + reset-names = "rst";
211 + #sound-dai-cells = <0>;
212 + };
213 +
214 + parallel_out: parallel-audio-out@18100c00 {
215 + compatible = "img,parallel-out";
216 + reg = <0x18100c00 0x100>;
217 + interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
218 + dmas = <&mdc 16 0xffffffff 0>;
219 + dma-names = "tx";
220 + clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
221 + <&clk_core CLK_AUDIO_DAC>;
222 + clock-names = "sys", "ref";
223 + assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
224 + assigned-clock-rates = <12288000>;
225 + status = "disabled";
226 + resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
227 + reset-names = "rst";
228 + #sound-dai-cells = <0>;
229 + };
230 +
231 + spdif_out: spdif-out@18100d00 {
232 + compatible = "img,spdif-out";
233 + reg = <0x18100d00 0x100>;
234 + interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
235 + dmas = <&mdc 14 0xffffffff 0>;
236 + dma-names = "tx";
237 + clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
238 + <&clk_core CLK_SPDIF>;
239 + clock-names = "sys", "ref";
240 + assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
241 + assigned-clock-rates = <12288000>;
242 + pinctrl-names = "default";
243 + pinctrl-0 = <&spdif_out_pin>;
244 + status = "disabled";
245 + resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
246 + reset-names = "rst";
247 + #sound-dai-cells = <0>;
248 + };
249 +
250 + spdif_in: spdif-in@18100e00 {
251 + compatible = "img,spdif-in";
252 + reg = <0x18100e00 0x100>;
253 + interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
254 + dmas = <&mdc 15 0xffffffff 0>;
255 + dma-names = "rx";
256 + clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
257 + clock-names = "sys";
258 + pinctrl-names = "default";
259 + pinctrl-0 = <&spdif_in_pin>;
260 + status = "disabled";
261 +
262 + #sound-dai-cells = <0>;
263 + };
264 +
265 + internal_dac: internal-dac {
266 + compatible = "img,pistachio-internal-dac";
267 + img,cr-top = <&cr_top>;
268 + img,voltage-select = <1>;
269 +
270 + #sound-dai-cells = <0>;
271 + };
272 +
273 + spfi0: spi@18100f00 {
274 + compatible = "img,spfi";
275 + reg = <0x18100f00 0x100>;
276 + interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
277 + clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
278 + clock-names = "sys", "spfi";
279 + dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
280 + dma-names = "rx", "tx";
281 + spfi-max-frequency = <50000000>;
282 + status = "disabled";
283 +
284 + #address-cells = <1>;
285 + #size-cells = <0>;
286 + };
287 +
288 + spfi1: spi@18101000 {
289 + compatible = "img,spfi";
290 + reg = <0x18101000 0x100>;
291 + interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
292 + clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
293 + clock-names = "sys", "spfi";
294 + dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
295 + dma-names = "rx", "tx";
296 + img,supports-quad-mode;
297 + spfi-max-frequency = <50000000>;
298 + status = "disabled";
299 +
300 + #address-cells = <1>;
301 + #size-cells = <0>;
302 + };
303 +
304 + pwm: pwm@18101300 {
305 + compatible = "img,pistachio-pwm";
306 + reg = <0x18101300 0x100>;
307 + clocks = <&clk_periph PERIPH_CLK_PWM>,
308 + <&cr_periph SYS_CLK_PWM>;
309 + clock-names = "pwm", "sys";
310 + img,cr-periph = <&cr_periph>;
311 + #pwm-cells = <2>;
312 + status = "disabled";
313 + };
314 +
315 + uart0: uart@18101400 {
316 + compatible = "snps,dw-apb-uart";
317 + reg = <0x18101400 0x100>;
318 + interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
319 + clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
320 + clock-names = "baudclk", "apb_pclk";
321 + assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
322 + <&clk_core CLK_UART0_DIV>;
323 + reg-shift = <2>;
324 + reg-io-width = <4>;
325 + pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
326 + pinctrl-names = "default";
327 + status = "disabled";
328 + };
329 +
330 + uart1: uart@18101500 {
331 + compatible = "snps,dw-apb-uart";
332 + reg = <0x18101500 0x100>;
333 + interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
334 + clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
335 + clock-names = "baudclk", "apb_pclk";
336 + assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
337 + <&clk_core CLK_UART1_DIV>;
338 + assigned-clock-rates = <114278400>, <1843200>;
339 + reg-shift = <2>;
340 + reg-io-width = <4>;
341 + pinctrl-0 = <&uart1_pins>;
342 + pinctrl-names = "default";
343 + status = "disabled";
344 + };
345 +
346 + adc: adc@18101600 {
347 + compatible = "cosmic,10001-adc";
348 + reg = <0x18101600 0x24>;
349 + adc-reserved-channels = <0x30>;
350 + clocks = <&clk_core CLK_AUX_ADC>;
351 + clock-names = "adc";
352 + assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
353 + <&clk_core CLK_AUX_ADC_DIV>;
354 + assigned-clock-rates = <100000000>, <1000000>;
355 + status = "disabled";
356 +
357 + #io-channel-cells = <1>;
358 + };
359 +
360 + pinctrl: pinctrl@18101c00 {
361 + compatible = "img,pistachio-system-pinctrl";
362 + reg = <0x18101c00 0x400>;
363 +
364 + gpio0: gpio0 {
365 + interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
366 +
367 + gpio-controller;
368 + #gpio-cells = <2>;
369 + gpio-ranges = <&pinctrl 0 0 16>;
370 +
371 + interrupt-controller;
372 + #interrupt-cells = <2>;
373 + };
374 +
375 + gpio1: gpio1 {
376 + interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
377 +
378 + gpio-controller;
379 + #gpio-cells = <2>;
380 + gpio-ranges = <&pinctrl 0 16 16>;
381 +
382 + interrupt-controller;
383 + #interrupt-cells = <2>;
384 + };
385 +
386 + gpio2: gpio2 {
387 + interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
388 +
389 + gpio-controller;
390 + #gpio-cells = <2>;
391 + gpio-ranges = <&pinctrl 0 32 16>;
392 +
393 + interrupt-controller;
394 + #interrupt-cells = <2>;
395 + };
396 +
397 + gpio3: gpio3 {
398 + interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
399 +
400 + gpio-controller;
401 + #gpio-cells = <2>;
402 + gpio-ranges = <&pinctrl 0 48 16>;
403 +
404 + interrupt-controller;
405 + #interrupt-cells = <2>;
406 + };
407 +
408 + gpio4: gpio4 {
409 + interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
410 +
411 + gpio-controller;
412 + #gpio-cells = <2>;
413 + gpio-ranges = <&pinctrl 0 64 16>;
414 +
415 + interrupt-controller;
416 + #interrupt-cells = <2>;
417 + };
418 +
419 + gpio5: gpio5 {
420 + interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
421 +
422 + gpio-controller;
423 + #gpio-cells = <2>;
424 + gpio-ranges = <&pinctrl 0 80 10>;
425 +
426 + interrupt-controller;
427 + #interrupt-cells = <2>;
428 + };
429 +
430 + i2c0_pins: i2c0-pins {
431 + pin_i2c0: i2c0 {
432 + pins = "mfio28", "mfio29";
433 + function = "i2c0";
434 + drive-strength = <4>;
435 + };
436 + };
437 +
438 + i2c1_pins: i2c1-pins {
439 + pin_i2c1: i2c1 {
440 + pins = "mfio30", "mfio31";
441 + function = "i2c1";
442 + drive-strength = <4>;
443 + };
444 + };
445 +
446 + i2c2_pins: i2c2-pins {
447 + pin_i2c2: i2c2 {
448 + pins = "mfio32", "mfio33";
449 + function = "i2c2";
450 + drive-strength = <4>;
451 + };
452 + };
453 +
454 + i2c3_pins: i2c3-pins {
455 + pin_i2c3: i2c3 {
456 + pins = "mfio34", "mfio35";
457 + function = "i2c3";
458 + drive-strength = <4>;
459 + };
460 + };
461 +
462 + spim0_pins: spim0-pins {
463 + pin_spim0: spim0 {
464 + pins = "mfio9", "mfio10";
465 + function = "spim0";
466 + drive-strength = <4>;
467 + };
468 + spim0_clk: spim0-clk {
469 + pins = "mfio8";
470 + function = "spim0";
471 + drive-strength = <4>;
472 + };
473 + };
474 +
475 + spim0_cs0_alt_pin: spim0-cs0-alt-pin {
476 + spim0-cs0 {
477 + pins = "mfio2";
478 + drive-strength = <2>;
479 + };
480 + };
481 +
482 + spim0_cs1_pin: spim0-cs1-pin {
483 + spim0-cs1 {
484 + pins = "mfio1";
485 + drive-strength = <2>;
486 + };
487 + };
488 +
489 + spim0_cs2_pin: spim0-cs2-pin {
490 + spim0-cs2 {
491 + pins = "mfio55";
492 + drive-strength = <2>;
493 + };
494 + };
495 +
496 + spim0_cs2_alt_pin: spim0-cs2-alt-pin {
497 + spim0-cs2 {
498 + pins = "mfio28";
499 + drive-strength = <2>;
500 + };
501 + };
502 +
503 + spim0_cs3_pin: spim0-cs3-pin {
504 + spim0-cs3 {
505 + pins = "mfio56";
506 + drive-strength = <2>;
507 + };
508 + };
509 +
510 + spim0_cs3_alt_pin: spim0-cs3-alt-pin {
511 + spim0-cs3 {
512 + pins = "mfio29";
513 + drive-strength = <2>;
514 + };
515 + };
516 +
517 + spim0_cs4_pin: spim0-cs4-pin {
518 + spim0-cs4 {
519 + pins = "mfio57";
520 + drive-strength = <2>;
521 + };
522 + };
523 +
524 + spim0_cs4_alt_pin: spim0-cs4-alt-pin {
525 + spim0-cs4 {
526 + pins = "mfio30";
527 + drive-strength = <2>;
528 + };
529 + };
530 +
531 + spim1_pins: spim1-pins {
532 + spim1 {
533 + pins = "mfio3", "mfio4", "mfio5";
534 + function = "spim1";
535 + drive-strength = <2>;
536 + };
537 + };
538 +
539 + spim1_quad_pins: spim1-quad-pins {
540 + spim1-quad {
541 + pins = "mfio6", "mfio7";
542 + function = "spim1";
543 + drive-strength = <2>;
544 + };
545 + };
546 +
547 + spim1_cs0_pin: spim1-cs0-pins {
548 + spim1-cs0 {
549 + pins = "mfio0";
550 + function = "spim1";
551 + drive-strength = <2>;
552 + };
553 + };
554 +
555 + spim1_cs1_pin: spim1-cs1-pin {
556 + spim1-cs1 {
557 + pins = "mfio1";
558 + function = "spim1";
559 + drive-strength = <2>;
560 + };
561 + };
562 +
563 + spim1_cs1_alt_pin: spim1-cs1-alt-pin {
564 + spim1-cs1 {
565 + pins = "mfio58";
566 + function = "spim1";
567 + drive-strength = <2>;
568 + };
569 + };
570 +
571 + spim1_cs2_pin: spim1-cs2-pin {
572 + spim1-cs2 {
573 + pins = "mfio2";
574 + function = "spim1";
575 + drive-strength = <2>;
576 + };
577 + };
578 +
579 + spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
580 + spim1-cs2 {
581 + pins = "mfio31";
582 + function = "spim1";
583 + drive-strength = <2>;
584 + };
585 + };
586 +
587 + spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
588 + spim1-cs2 {
589 + pins = "mfio55";
590 + function = "spim1";
591 + drive-strength = <2>;
592 + };
593 + };
594 +
595 + spim1_cs3_pin: spim1-cs3-pin {
596 + spim1-cs3 {
597 + pins = "mfio56";
598 + function = "spim1";
599 + drive-strength = <2>;
600 + };
601 + };
602 +
603 + spim1_cs4_pin: spim1-cs4-pin {
604 + spim1-cs4 {
605 + pins = "mfio57";
606 + function = "spim1";
607 + drive-strength = <2>;
608 + };
609 + };
610 +
611 + uart0_pins: uart0-pins {
612 + uart0 {
613 + pins = "mfio55", "mfio56";
614 + function = "uart0";
615 + drive-strength = <2>;
616 + };
617 + };
618 +
619 + uart0_rts_cts_pins: uart0-rts-cts-pins {
620 + uart0-rts-cts {
621 + pins = "mfio57", "mfio58";
622 + function = "uart0";
623 + drive-strength = <2>;
624 + };
625 + };
626 +
627 + uart1_pins: uart1-pins {
628 + uart1 {
629 + pins = "mfio59", "mfio60";
630 + function = "uart1";
631 + drive-strength = <2>;
632 + };
633 + };
634 +
635 + uart1_rts_cts_pins: uart1-rts-cts-pins {
636 + uart1-rts-cts {
637 + pins = "mfio1", "mfio2";
638 + function = "uart1";
639 + drive-strength = <2>;
640 + };
641 + };
642 +
643 + enet_pins: enet-pins {
644 + pin_enet: enet {
645 + pins = "mfio63", "mfio64", "mfio65", "mfio66",
646 + "mfio67", "mfio68", "mfio69", "mfio70";
647 + function = "eth";
648 + slew-rate = <1>;
649 + drive-strength = <4>;
650 + };
651 + pin_enet_phy_clk: enet-phy-clk {
652 + pins = "mfio71";
653 + function = "eth";
654 + slew-rate = <1>;
655 + drive-strength = <8>;
656 + };
657 + };
658 +
659 + sdhost_pins: sdhost-pins {
660 + pin_sdhost_clk: sdhost-clk {
661 + pins = "mfio15";
662 + function = "sdhost";
663 + slew-rate = <1>;
664 + drive-strength = <4>;
665 + };
666 + pin_sdhost_cmd: sdhost-cmd {
667 + pins = "mfio16";
668 + function = "sdhost";
669 + slew-rate = <1>;
670 + drive-strength = <4>;
671 + };
672 + pin_sdhost_data: sdhost-data {
673 + pins = "mfio17", "mfio18", "mfio19", "mfio20",
674 + "mfio21", "mfio22", "mfio23", "mfio24";
675 + function = "sdhost";
676 + slew-rate = <1>;
677 + drive-strength = <4>;
678 + };
679 + pin_sdhost_power_select: sdhost-power-select {
680 + pins = "mfio25";
681 + function = "sdhost";
682 + slew-rate = <1>;
683 + drive-strength = <2>;
684 + };
685 + pin_sdhost_card_detect: sdhost-card-detect {
686 + pins = "mfio26";
687 + function = "sdhost";
688 + drive-strength = <2>;
689 + };
690 + pin_sdhost_write_protect: sdhost-write-protect {
691 + pins = "mfio27";
692 + function = "sdhost";
693 + drive-strength = <2>;
694 + };
695 + };
696 +
697 + ir_pin: ir-pin {
698 + ir-data {
699 + pins = "mfio72";
700 + function = "ir";
701 + drive-strength = <2>;
702 + };
703 + };
704 +
705 + pwmpdm0_pin: pwmpdm0-pin {
706 + pwmpdm0 {
707 + pins = "mfio73";
708 + function = "pwmpdm";
709 + drive-strength = <2>;
710 + };
711 + };
712 +
713 + pwmpdm1_pin: pwmpdm1-pin {
714 + pwmpdm1 {
715 + pins = "mfio74";
716 + function = "pwmpdm";
717 + drive-strength = <2>;
718 + };
719 + };
720 +
721 + pwmpdm2_pin: pwmpdm2-pin {
722 + pwmpdm2 {
723 + pins = "mfio75";
724 + function = "pwmpdm";
725 + drive-strength = <2>;
726 + };
727 + };
728 +
729 + pwmpdm3_pin: pwmpdm3-pin {
730 + pwmpdm3 {
731 + pins = "mfio76";
732 + function = "pwmpdm";
733 + drive-strength = <2>;
734 + };
735 + };
736 +
737 + dac_clk_pin: dac-clk-pin {
738 + pin_dac_clk: dac-clk {
739 + pins = "mfio45";
740 + function = "i2s_dac_clk";
741 + drive-strength = <4>;
742 + };
743 + };
744 +
745 + i2s_mclk_pin: i2s-mclk-pin {
746 + pin_i2s_mclk: i2s-mclk {
747 + pins = "mfio36";
748 + function = "i2s_out";
749 + drive-strength = <4>;
750 + };
751 + };
752 +
753 + spdif_out_pin: spdif-out-pin {
754 + spdif-out {
755 + pins = "mfio61";
756 + function = "spdif_out";
757 + slew-rate = <1>;
758 + drive-strength = <2>;
759 + };
760 + };
761 +
762 + spdif_in_pin: spdif-in-pin {
763 + spdif-in {
764 + pins = "mfio62";
765 + function = "spdif_in";
766 + drive-strength = <2>;
767 + };
768 + };
769 +
770 + i2s_out_pins: i2s-out-pins {
771 + pins_i2s_out_clk: i2s-out-clk {
772 + pins = "mfio37", "mfio38";
773 + function = "i2s_out";
774 + drive-strength = <4>;
775 + };
776 + pins_i2s_out: i2s-out {
777 + pins = "mfio39", "mfio40",
778 + "mfio41", "mfio42",
779 + "mfio43", "mfio44";
780 + function = "i2s_out";
781 + drive-strength = <2>;
782 + };
783 + };
784 +
785 + i2s_in_pins: i2s-in-pins {
786 + i2s-in {
787 + pins = "mfio47", "mfio48", "mfio49",
788 + "mfio50", "mfio51", "mfio52",
789 + "mfio53", "mfio54";
790 + function = "i2s_in";
791 + drive-strength = <2>;
792 + };
793 + };
794 + };
795 +
796 + timer: timer@18102000 {
797 + compatible = "img,pistachio-gptimer";
798 + reg = <0x18102000 0x100>;
799 + interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
800 + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
801 + <&cr_periph SYS_CLK_TIMER>;
802 + clock-names = "fast", "sys";
803 + img,cr-periph = <&cr_periph>;
804 + };
805 +
806 + wdt: watchdog@18102100 {
807 + compatible = "img,pdc-wdt";
808 + reg = <0x18102100 0x100>;
809 + interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
810 + clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
811 + clock-names = "wdt", "sys";
812 + assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
813 + <&clk_periph PERIPH_CLK_WD_DIV>;
814 + assigned-clock-rates = <4000000>, <32768>;
815 + };
816 +
817 + ir: ir@18102200 {
818 + compatible = "img,ir-rev1";
819 + reg = <0x18102200 0x100>;
820 + interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
821 + clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
822 + clock-names = "core", "sys";
823 + assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
824 + <&clk_periph PERIPH_CLK_IR_DIV>;
825 + assigned-clock-rates = <4000000>, <32768>;
826 + pinctrl-0 = <&ir_pin>;
827 + pinctrl-names = "default";
828 + status = "disabled";
829 + };
830 +
831 + usb: usb@18120000 {
832 + compatible = "snps,dwc2";
833 + reg = <0x18120000 0x1c000>;
834 + interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
835 + phys = <&usb_phy>;
836 + phy-names = "usb2-phy";
837 + g-tx-fifo-size = <256 256 256 256>;
838 + status = "disabled";
839 + };
840 +
841 + enet: ethernet@18140000 {
842 + compatible = "snps,dwmac";
843 + reg = <0x18140000 0x2000>;
844 + interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
845 + interrupt-names = "macirq";
846 + clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
847 + clock-names = "stmmaceth", "pclk";
848 + assigned-clocks = <&clk_core CLK_ENET_MUX>,
849 + <&clk_core CLK_ENET_DIV>;
850 + assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
851 + assigned-clock-rates = <0>, <50000000>;
852 + pinctrl-0 = <&enet_pins>;
853 + pinctrl-names = "default";
854 + phy-mode = "rmii";
855 + status = "disabled";
856 + };
857 +
858 + sdhost: mmc@18142000 {
859 + compatible = "img,pistachio-dw-mshc";
860 + reg = <0x18142000 0x400>;
861 + interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
862 + clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
863 + clock-names = "ciu", "biu";
864 + pinctrl-0 = <&sdhost_pins>;
865 + pinctrl-names = "default";
866 + fifo-depth = <0x20>;
867 + num-slots = <1>;
868 + clock-frequency = <50000000>;
869 + bus-width = <8>;
870 + cap-mmc-highspeed;
871 + cap-sd-highspeed;
872 + status = "disabled";
873 + };
874 +
875 + sram: sram@1b000000 {
876 + compatible = "mmio-sram";
877 + reg = <0x1b000000 0x10000>;
878 + };
879 +
880 + mdc: dma-controller@18143000 {
881 + compatible = "img,pistachio-mdc-dma";
882 + reg = <0x18143000 0x1000>;
883 + interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
884 + <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
885 + <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
886 + <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
887 + <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
888 + <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
889 + <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
890 + <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
891 + <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
892 + <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
893 + <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
894 + <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
895 + clocks = <&cr_periph SYS_CLK_MDC>;
896 + clock-names = "sys";
897 +
898 + img,max-burst-multiplier = <16>;
899 + img,cr-periph = <&cr_periph>;
900 +
901 + #dma-cells = <3>;
902 + };
903 +
904 + clk_core: clk@18144000 {
905 + compatible = "img,pistachio-clk", "syscon";
906 + clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
907 + <&cr_top EXT_CLK_ENET_IN>;
908 + clock-names = "xtal", "audio_refclk_ext_gate",
909 + "ext_enet_in_gate";
910 + reg = <0x18144000 0x800>;
911 + #clock-cells = <1>;
912 + };
913 +
914 + clk_periph: clk@18144800 {
915 + compatible = "img,pistachio-clk-periph";
916 + reg = <0x18144800 0x1000>;
917 + clocks = <&clk_core CLK_PERIPH_SYS>;
918 + clock-names = "periph_sys_core";
919 + #clock-cells = <1>;
920 + };
921 +
922 + cr_periph: clk@18148000 {
923 + compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
924 + reg = <0x18148000 0x1000>;
925 + clocks = <&clk_periph PERIPH_CLK_SYS>;
926 + clock-names = "sys";
927 + #clock-cells = <1>;
928 +
929 + pistachio_reset: reset-controller {
930 + compatible = "img,pistachio-reset";
931 + #reset-cells = <1>;
932 + };
933 + };
934 +
935 + cr_top: clk@18149000 {
936 + compatible = "img,pistachio-cr-top", "syscon";
937 + reg = <0x18149000 0x200>;
938 + #clock-cells = <1>;
939 + };
940 +
941 + hash: hash@18149600 {
942 + compatible = "img,hash-accelerator";
943 + reg = <0x18149600 0x100>, <0x18101100 0x4>;
944 + interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
945 + dmas = <&mdc 8 0xffffffff 0>;
946 + dma-names = "tx";
947 + clocks = <&cr_periph SYS_CLK_HASH>,
948 + <&clk_periph PERIPH_CLK_ROM>;
949 + clock-names = "sys", "hash";
950 + };
951 +
952 + gic: interrupt-controller@1bdc0000 {
953 + compatible = "mti,gic";
954 + reg = <0x1bdc0000 0x20000>;
955 +
956 + interrupt-controller;
957 + #interrupt-cells = <3>;
958 +
959 + timer {
960 + compatible = "mti,gic-timer";
961 + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
962 + clocks = <&clk_core CLK_MIPS>;
963 + };
964 + };
965 +
966 + usb_phy: usb-phy {
967 + compatible = "img,pistachio-usb-phy";
968 + clocks = <&clk_core CLK_USB_PHY>;
969 + clock-names = "usb_phy";
970 + assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
971 + assigned-clock-rates = <50000000>;
972 + img,refclk = <0x2>;
973 + img,cr-top = <&cr_top>;
974 + #phy-cells = <0>;
975 + };
976 +
977 + xtal: xtal {
978 + compatible = "fixed-clock";
979 + #clock-cells = <0>;
980 + clock-frequency = <52000000>;
981 + clock-output-names = "xtal";
982 + };
983 +};
Staging tree of Christian Lamparter