target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/init.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_address.h>
  33 #include <linux/switch.h>
  34
  35 #include <asm/mach-ralink/ralink_regs.h>
  36
  37 #include "ralink_soc_eth.h"
  38
  39 #include <linux/ioport.h>
  40 #include <linux/switch.h>
  41 #include <linux/mii.h>
  42
  43 #include <ralink_regs.h>
  44 #include <asm/mach-ralink/mt7620.h>
  45
  46 #include "ralink_soc_eth.h"
  47 #include "gsw_mt7620a.h"
  48 #include "mt7530.h"
  49 #include "mdio.h"
  50
  51 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  52
  53 #ifdef CONFIG_SOC_MT7621
  54 #define MT7620A_GSW_REG_PIAC    0x0004
  55 #else
  56 #define MT7620A_GSW_REG_PIAC    0x7004
  57 #endif
  58
  59 #define GSW_NUM_VLANS           16
  60 #define GSW_NUM_VIDS            4096
  61 #define GSW_NUM_PORTS           7
  62 #define GSW_PORT6               6
  63
  64 #define GSW_MDIO_ACCESS         BIT(31)
  65 #define GSW_MDIO_READ           BIT(19)
  66 #define GSW_MDIO_WRITE          BIT(18)
  67 #define GSW_MDIO_START          BIT(16)
  68 #define GSW_MDIO_ADDR_SHIFT     20
  69 #define GSW_MDIO_REG_SHIFT      25
  70
  71 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  72 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  73 #define GSW_REG_SMACCR0         0x3fE4
  74 #define GSW_REG_SMACCR1         0x3fE8
  75 #define GSW_REG_CKGCR           0x3ff0
  76
  77 #define GSW_REG_IMR             0x7008
  78 #define GSW_REG_ISR             0x700c
  79 #define GSW_REG_GPC1            0x7014
  80
  81 #define SYSC_REG_CHIP_REV_ID    0x0c
  82 #define SYSC_REG_CFG1           0x14
  83 #define SYSC_REG_RESET_CTRL     0x34
  84 #define RST_CTRL_MCM            BIT(2)
  85 #define SYSC_PAD_RGMII2_MDIO    0x58
  86 #define SYSC_GPIO_MODE          0x60
  87
  88 #define PORT_IRQ_ST_CHG         0x7f
  89
  90
  91 #ifdef CONFIG_SOC_MT7621
  92 #define ESW_PHY_POLLING         0x0000
  93 #else
  94 #define ESW_PHY_POLLING         0x7000
  95 #endif
  96
  97 #define PMCR_IPG                BIT(18)
  98 #define PMCR_MAC_MODE           BIT(16)
  99 #define PMCR_FORCE              BIT(15)
 100 #define PMCR_TX_EN              BIT(14)
 101 #define PMCR_RX_EN              BIT(13)
 102 #define PMCR_BACKOFF            BIT(9)
 103 #define PMCR_BACKPRES           BIT(8)
 104 #define PMCR_RX_FC              BIT(5)
 105 #define PMCR_TX_FC              BIT(4)
 106 #define PMCR_SPEED(_x)          (_x << 2)
 107 #define PMCR_DUPLEX             BIT(1)
 108 #define PMCR_LINK               BIT(0)
 109
 110 #define PHY_AN_EN               BIT(31)
 111 #define PHY_PRE_EN              BIT(30)
 112 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
 113
 114 enum {
 115         /* Global attributes. */
 116         GSW_ATTR_ENABLE_VLAN,
 117         /* Port attributes. */
 118         GSW_ATTR_PORT_UNTAG,
 119 };
 120
 121 enum {
 122         PORT4_EPHY = 0,
 123         PORT4_EXT,
 124 };
 125
 126 struct mt7620_gsw {
 127         struct device           *dev;
 128         void __iomem            *base;
 129         int                     irq;
 130         int                     port4;
 131         long unsigned int       autopoll;
 132 };
 133
 134 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
 135 {
 136         iowrite32(val, gsw->base + reg);
 137 }
 138
 139 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
 140 {
 141         return ioread32(gsw->base + reg);
 142 }
 143
 144 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
 145 {
 146         unsigned long t_start = jiffies;
 147
 148         while (1) {
 149                 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
 150                         return 0;
 151                 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
 152                         break;
 153                 }
 154         }
 155
 156         printk(KERN_ERR "mdio: MDIO timeout\n");
 157         return -1;
 158 }
 159
 160 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
 161                                 u32 write_data)
 162 {
 163         if (mt7620_mii_busy_wait(gsw))
 164                 return -1;
 165
 166         write_data &= 0xffff;
 167
 168         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
 169                 (phy_register << GSW_MDIO_REG_SHIFT) |
 170                 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
 171                 MT7620A_GSW_REG_PIAC);
 172
 173         if (mt7620_mii_busy_wait(gsw))
 174                 return -1;
 175
 176         return 0;
 177 }
 178
 179 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
 180 {
 181         u32 d;
 182
 183         if (mt7620_mii_busy_wait(gsw))
 184                 return 0xffff;
 185
 186         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
 187                 (phy_reg << GSW_MDIO_REG_SHIFT) |
 188                 (phy_addr << GSW_MDIO_ADDR_SHIFT),
 189                 MT7620A_GSW_REG_PIAC);
 190
 191         if (mt7620_mii_busy_wait(gsw))
 192                 return 0xffff;
 193
 194         d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
 195
 196         return d;
 197 }
 198
 199 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 200 {
 201         struct fe_priv *priv = bus->priv;
 202         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 203
 204         return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
 205 }
 206
 207 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 208 {
 209         struct fe_priv *priv = bus->priv;
 210         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 211
 212         return _mt7620_mii_read(gsw, phy_addr, phy_reg);
 213 }
 214
 215 static void
 216 mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
 217 {
 218         _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 219         _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
 220         _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
 221 }
 222
 223 static u32
 224 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
 225 {
 226         u16 high, low;
 227
 228         _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 229         low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
 230         high = _mt7620_mii_read(gsw, 0x1f, 0x10);
 231
 232         return (high << 16) | (low & 0xffff);
 233 }
 234
 235 static unsigned char *fe_speed_str(int speed)
 236 {
 237         switch (speed) {
 238         case 2:
 239         case SPEED_1000:
 240                 return "1000";
 241         case 1:
 242         case SPEED_100:
 243                 return "100";
 244         case 0:
 245         case SPEED_10:
 246                 return "10";
 247         }
 248
 249         return "? ";
 250 }
 251
 252 int mt7620a_has_carrier(struct fe_priv *priv)
 253 {
 254         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 255         int i;
 256
 257         for (i = 0; i < GSW_PORT6; i++)
 258                 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
 259                         return 1;
 260         return 0;
 261 }
 262
 263 static void mt7620a_handle_carrier(struct fe_priv *priv)
 264 {
 265         if (!priv->phy)
 266                 return;
 267
 268         if (mt7620a_has_carrier(priv))
 269                 netif_carrier_on(priv->netdev);
 270         else
 271                 netif_carrier_off(priv->netdev);
 272 }
 273
 274 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
 275 {
 276         if (priv->link[port])
 277                 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 278                         port, fe_speed_str(priv->phy->speed[port]),
 279                         (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
 280         else
 281                 netdev_info(priv->netdev, "port %d link down\n", port);
 282         mt7620a_handle_carrier(priv);
 283 }
 284
 285 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
 286 {
 287         struct fe_priv *priv = (struct fe_priv *) _priv;
 288         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 289         u32 status;
 290         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
 291
 292         status = gsw_r32(gsw, GSW_REG_ISR);
 293         if (status & PORT_IRQ_ST_CHG)
 294                 for (i = 0; i <= max; i++) {
 295                         u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
 296                         int link = status & 0x1;
 297
 298                         if (link != priv->link[i]) {
 299                                 if (link)
 300                                         netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 301                                                         i, fe_speed_str((status >> 2) & 3),
 302                                                         (status & 0x2) ? "Full" : "Half");
 303                                 else
 304                                         netdev_info(priv->netdev, "port %d link down\n", i);
 305                         }
 306
 307                         priv->link[i] = link;
 308                 }
 309         mt7620a_handle_carrier(priv);
 310
 311         gsw_w32(gsw, status, GSW_REG_ISR);
 312
 313         return IRQ_HANDLED;
 314 }
 315
 316 static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
 317 {
 318         struct fe_priv *priv = (struct fe_priv *) _priv;
 319         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 320         u32 reg, i;
 321
 322         reg = mt7530_mdio_r32(gsw, 0x700c);
 323
 324         for (i = 0; i < 5; i++)
 325                 if (reg & BIT(i)) {
 326                         unsigned int link = mt7530_mdio_r32(gsw, 0x3008 + (i * 0x100)) & 0x1;
 327
 328                         if (link != priv->link[i]) {
 329                                 priv->link[i] = link;
 330                                 if (link)
 331                                         netdev_info(priv->netdev, "port %d link up\n", i);
 332                                 else
 333                                         netdev_info(priv->netdev, "port %d link down\n", i);
 334                         }
 335                 }
 336
 337         mt7620a_handle_carrier(priv);
 338         mt7530_mdio_w32(gsw, 0x700c, 0x1f);
 339
 340         return IRQ_HANDLED;
 341 }
 342
 343 static int mt7620_is_bga(void)
 344 {
 345         u32 bga = rt_sysc_r32(0x0c);
 346
 347         return (bga >> 16) & 1;
 348 }
 349
 350 static void gsw_auto_poll(struct mt7620_gsw *gsw)
 351 {
 352         int phy;
 353         int lsb = -1, msb = 0;
 354
 355         for_each_set_bit(phy, &gsw->autopoll, 32) {
 356                 if (lsb < 0)
 357                         lsb = phy;
 358                 msb = phy;
 359         }
 360
 361         if (lsb == msb)
 362                 lsb--;
 363
 364         gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
 365 }
 366
 367 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 368 {
 369         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 370         const __be32 *_id = of_get_property(np, "reg", NULL);
 371         int phy_mode, size, id;
 372         int shift = 12;
 373         u32 val, mask = 0;
 374         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 375
 376         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 377                 if (_id)
 378                         pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
 379                 else
 380                         pr_err("%s: invalid port id\n", np->name);
 381                 return;
 382         }
 383
 384         id = be32_to_cpu(*_id);
 385
 386         if (id == 4)
 387                 shift = 14;
 388
 389         priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
 390         if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 391                 pr_err("%s: invalid fixed link property\n", np->name);
 392                 priv->phy->phy_fixed[id] = NULL;
 393                 return;
 394         }
 395
 396         phy_mode = of_get_phy_mode(np);
 397         switch (phy_mode) {
 398         case PHY_INTERFACE_MODE_RGMII:
 399                 mask = 0;
 400                 break;
 401         case PHY_INTERFACE_MODE_MII:
 402                 mask = 1;
 403                 break;
 404         case PHY_INTERFACE_MODE_RMII:
 405                 mask = 2;
 406                 break;
 407         default:
 408                 dev_err(priv->device, "port %d - invalid phy mode\n", id);
 409                 return;
 410         }
 411
 412         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 413         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 414                 return;
 415
 416         val = rt_sysc_r32(SYSC_REG_CFG1);
 417         val &= ~(3 << shift);
 418         val |= mask << shift;
 419         rt_sysc_w32(val, SYSC_REG_CFG1);
 420
 421         if (priv->phy->phy_fixed[id]) {
 422                 const __be32 *link = priv->phy->phy_fixed[id];
 423                 int tx_fc, rx_fc;
 424                 u32 val = 0;
 425
 426                 priv->phy->speed[id] = be32_to_cpup(link++);
 427                 tx_fc = be32_to_cpup(link++);
 428                 rx_fc = be32_to_cpup(link++);
 429                 priv->phy->duplex[id] = be32_to_cpup(link++);
 430                 priv->link[id] = 1;
 431
 432                 switch (priv->phy->speed[id]) {
 433                 case SPEED_10:
 434                         val = 0;
 435                         break;
 436                 case SPEED_100:
 437                         val = 1;
 438                         break;
 439                 case SPEED_1000:
 440                         val = 2;
 441                         break;
 442                 default:
 443                         dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
 444                         priv->phy->phy_fixed[id] = 0;
 445                         return;
 446                 }
 447                 val = PMCR_SPEED(val);
 448                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 449                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 450                 if (tx_fc)
 451                         val |= PMCR_TX_FC;
 452                 if (rx_fc)
 453                         val |= PMCR_RX_FC;
 454                 if (priv->phy->duplex[id])
 455                         val |= PMCR_DUPLEX;
 456                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 457                 dev_info(priv->device, "using fixed link parameters\n");
 458                 return;
 459         }
 460
 461         if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
 462                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 463                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 464
 465                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 466                 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
 467                 gsw->autopoll |= BIT(id);
 468                 gsw_auto_poll(gsw);
 469                 return;
 470         }
 471 }
 472
 473 static void gsw_hw_init_mt7620(struct mt7620_gsw *gsw, struct device_node *np)
 474 {
 475         u32 is_BGA = mt7620_is_bga();
 476
 477         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
 478         gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 479
 480         if (of_property_read_bool(np, "mediatek,mt7530")) {
 481                 u32 val;
 482
 483                 /* turn off ephy and set phy base addr to 12 */
 484                 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24) | (0xc << 16), GSW_REG_GPC1);
 485
 486                 /* set MT7530 central align */
 487                 val = mt7530_mdio_r32(gsw, 0x7830);
 488                 val &= ~1;
 489                 val |= 1<<1;
 490                 mt7530_mdio_w32(gsw, 0x7830, val);
 491
 492                 val = mt7530_mdio_r32(gsw, 0x7a40);
 493                 val &= ~(1<<30);
 494                 mt7530_mdio_w32(gsw, 0x7a40, val);
 495
 496                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 497         } else {
 498                 /* EPHY1 fixup - only run if the ephy is enabled */
 499
 500                 /*correct  PHY  setting L3.0 BGA*/
 501                 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
 502
 503                 _mt7620_mii_write(gsw, 1, 17, 0x7444);
 504                 if (is_BGA)
 505                         _mt7620_mii_write(gsw, 1, 19, 0x0114);
 506                 else
 507                         _mt7620_mii_write(gsw, 1, 19, 0x0117);
 508
 509                 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
 510                 _mt7620_mii_write(gsw, 1, 25, 0x6212);
 511                 _mt7620_mii_write(gsw, 1, 26, 0x0777);
 512                 _mt7620_mii_write(gsw, 1, 29, 0x4000);
 513                 _mt7620_mii_write(gsw, 1, 28, 0xc077);
 514                 _mt7620_mii_write(gsw, 1, 24, 0x0000);
 515
 516                 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
 517                 _mt7620_mii_write(gsw, 1, 17, 0x4838);
 518
 519                 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
 520                 if (is_BGA) {
 521                         _mt7620_mii_write(gsw, 1, 21, 0x0515);
 522                         _mt7620_mii_write(gsw, 1, 22, 0x0053);
 523                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 524                         _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
 525                         _mt7620_mii_write(gsw, 1, 25, 0x0fad);
 526                         _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
 527                 } else {
 528                         _mt7620_mii_write(gsw, 1, 21, 0x0517);
 529                         _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
 530                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 531                         _mt7620_mii_write(gsw, 1, 24, 0x0aab);
 532                         _mt7620_mii_write(gsw, 1, 25, 0x00ae);
 533                         _mt7620_mii_write(gsw, 1, 26, 0x0fff);
 534                 }
 535                 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
 536                 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
 537         }
 538
 539         _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
 540         _mt7620_mii_write(gsw, 0, 30, 0xa000);
 541         _mt7620_mii_write(gsw, 1, 30, 0xa000);
 542         _mt7620_mii_write(gsw, 2, 30, 0xa000);
 543         _mt7620_mii_write(gsw, 3, 30, 0xa000);
 544
 545         _mt7620_mii_write(gsw, 0, 4, 0x05e1);
 546         _mt7620_mii_write(gsw, 1, 4, 0x05e1);
 547         _mt7620_mii_write(gsw, 2, 4, 0x05e1);
 548         _mt7620_mii_write(gsw, 3, 4, 0x05e1);
 549
 550         _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
 551         _mt7620_mii_write(gsw, 0, 16, 0x1111);
 552         _mt7620_mii_write(gsw, 1, 16, 0x1010);
 553         _mt7620_mii_write(gsw, 2, 16, 0x1515);
 554         _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
 555
 556         /* CPU Port6 Force Link 1G, FC ON */
 557         gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 558         /* Set Port6 CPU Port */
 559         gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
 560
 561         /* setup port 4 */
 562         if (gsw->port4 == PORT4_EPHY) {
 563                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 564                 val |= 3 << 14;
 565                 rt_sysc_w32(val, SYSC_REG_CFG1);
 566                 _mt7620_mii_write(gsw, 4, 30, 0xa000);
 567                 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
 568                 _mt7620_mii_write(gsw, 4, 16, 0x1313);
 569                 pr_info("gsw: setting port4 to ephy mode\n");
 570         }
 571 }
 572
 573 static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
 574 {
 575         u32     i;
 576         u32     val;
 577
 578         /* Hardware reset Switch */
 579         val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 580         rt_sysc_w32(val | RST_CTRL_MCM, SYSC_REG_RESET_CTRL);
 581         udelay(1000);
 582         rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 583         udelay(10000);
 584
 585         /* reduce RGMII2 PAD driving strength */
 586         rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
 587
 588         /* gpio mux - RGMII1=Normal mode */
 589         rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
 590
 591         //GMAC1= RGMII mode
 592         rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
 593
 594         /* enable MDIO to control MT7530 */
 595         rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
 596
 597         /* turn off all PHYs */
 598         for (i = 0; i <= 4; i++) {
 599                 val = _mt7620_mii_read(gsw, i, 0x0);
 600                 val |= (0x1 << 11);
 601                 _mt7620_mii_write(gsw, i, 0x0, val);
 602         }
 603
 604         /* reset the switch */
 605         mt7530_mdio_w32(gsw, 0x7000, 0x3);
 606         udelay(10);
 607
 608         if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
 609                 /* (GE1, Force 1000M/FD, FC ON) */
 610                 gsw_w32(gsw, 0x2005e30b, 0x100);
 611                 mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
 612         } else {
 613                 /* (GE1, Force 1000M/FD, FC ON) */
 614                 gsw_w32(gsw, 0x2005e33b, 0x100);
 615                 mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
 616         }
 617
 618         /* (GE2, Link down) */
 619         gsw_w32(gsw, 0x8000, 0x200);
 620
 621         //val = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable
 622         val = mt7530_mdio_r32(gsw, 0x7804);
 623         val &= ~(1<<8); //Enable Port 6
 624         val |= (1<<6); //Disable Port 5
 625         val |= (1<<13); //Port 5 as GMAC, no Internal PHY
 626
 627         val |= (1<<16);//change HW-TRAP
 628         printk("change HW-TRAP to 0x%x\n", val);
 629         mt7530_mdio_w32(gsw, 0x7804, val);
 630
 631         val = rt_sysc_r32(0x10);
 632         val = (val >> 6) & 0x7;
 633         if (val >= 6) {
 634                 /* 25Mhz Xtal - do nothing */
 635         } else if(val >=3) {
 636                 /* 40Mhz */
 637
 638                 /* disable MT7530 core clock */
 639                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 640                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 641                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 642                 _mt7620_mii_write(gsw, 0, 14, 0x0);
 643
 644                 /* disable MT7530 PLL */
 645                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 646                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 647                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 648                 _mt7620_mii_write(gsw, 0, 14, 0x2020);
 649
 650                 /* for MT7530 core clock = 500Mhz */
 651                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 652                 _mt7620_mii_write(gsw, 0, 14, 0x40e);
 653                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 654                 _mt7620_mii_write(gsw, 0, 14, 0x119);
 655
 656                 /* enable MT7530 PLL */
 657                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 658                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 659                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 660                 _mt7620_mii_write(gsw, 0, 14, 0x2820);
 661
 662                 udelay(20);
 663
 664                 /* enable MT7530 core clock */
 665                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 666                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 667                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 668         } else {
 669                 /* 20Mhz Xtal - TODO */
 670         }
 671
 672         /* RGMII */
 673         _mt7620_mii_write(gsw, 0, 14, 0x1);
 674
 675         /* set MT7530 central align */
 676         val = mt7530_mdio_r32(gsw, 0x7830);
 677         val &= ~1;
 678         val |= 1<<1;
 679         mt7530_mdio_w32(gsw, 0x7830, val);
 680
 681         val = mt7530_mdio_r32(gsw, 0x7a40);
 682         val &= ~(1<<30);
 683         mt7530_mdio_w32(gsw, 0x7a40, val);
 684
 685         mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 686         mt7530_mdio_w32(gsw, 0x7b00, 0x102);  //delay setting for 10/1000M
 687         mt7530_mdio_w32(gsw, 0x7b04, 0x14);  //delay setting for 10/1000M
 688
 689         /*Tx Driving*/
 690         mt7530_mdio_w32(gsw, 0x7a54, 0x44);  //lower driving
 691         mt7530_mdio_w32(gsw, 0x7a5c, 0x44);  //lower driving
 692         mt7530_mdio_w32(gsw, 0x7a64, 0x44);  //lower driving
 693         mt7530_mdio_w32(gsw, 0x7a6c, 0x44);  //lower driving
 694         mt7530_mdio_w32(gsw, 0x7a74, 0x44);  //lower driving
 695         mt7530_mdio_w32(gsw, 0x7a7c, 0x44);  //lower driving
 696
 697         //LANWANPartition();
 698
 699         /* turn on all PHYs */
 700         for (i = 0; i <= 4; i++) {
 701                 val = _mt7620_mii_read(gsw, i, 0);
 702                 val &= ~BIT(11);
 703                 _mt7620_mii_write(gsw, i, 0, val);
 704         }
 705
 706         /* enable irq */
 707         val = mt7530_mdio_r32(gsw, 0x7808);
 708         val |= 3 << 16;
 709         mt7530_mdio_w32(gsw, 0x7808, val);
 710 }
 711
 712 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 713 {
 714         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 715         unsigned long flags;
 716
 717         spin_lock_irqsave(&priv->page_lock, flags);
 718         gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 719         gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 720                 GSW_REG_SMACCR0);
 721         spin_unlock_irqrestore(&priv->page_lock, flags);
 722 }
 723
 724 static struct of_device_id gsw_match[] = {
 725         { .compatible = "ralink,mt7620a-gsw" },
 726         {}
 727 };
 728
 729 int mt7620_gsw_config(struct fe_priv *priv)
 730 {
 731         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 732
 733         /* is the mt7530 internal or external */
 734         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
 735                 mt7530_probe(priv->device, gsw->base, NULL, 0);
 736                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 737         } else {
 738                 mt7530_probe(priv->device, gsw->base, NULL, 1);
 739         }
 740
 741         return 0;
 742 }
 743
 744 int mt7621_gsw_config(struct fe_priv *priv)
 745 {
 746         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
 747                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 748
 749         return 0;
 750 }
 751
 752 int mt7620_gsw_probe(struct fe_priv *priv)
 753 {
 754         struct mt7620_gsw *gsw;
 755         struct device_node *np;
 756         const char *port4 = NULL;
 757
 758         np = of_find_matching_node(NULL, gsw_match);
 759         if (!np) {
 760                 dev_err(priv->device, "no gsw node found\n");
 761                 return -EINVAL;
 762         }
 763         np = of_node_get(np);
 764
 765         gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
 766         if (!gsw) {
 767                 dev_err(priv->device, "no gsw memory for private data\n");
 768                 return -ENOMEM;
 769         }
 770
 771         gsw->base = of_iomap(np, 0);
 772         if (!gsw->base) {
 773                 dev_err(priv->device, "gsw ioremap failed\n");
 774                 return -ENOMEM;
 775         }
 776
 777         gsw->dev = priv->device;
 778         priv->soc->swpriv = gsw;
 779
 780         of_property_read_string(np, "ralink,port4", &port4);
 781         if (port4 && !strcmp(port4, "ephy"))
 782                 gsw->port4 = PORT4_EPHY;
 783         else if (port4 && !strcmp(port4, "gmac"))
 784                 gsw->port4 = PORT4_EXT;
 785         else
 786                 gsw->port4 = PORT4_EPHY;
 787
 788         if (IS_ENABLED(CONFIG_SOC_MT7620))
 789                 gsw_hw_init_mt7620(gsw, np);
 790         else
 791                 gsw_hw_init_mt7621(gsw, np);
 792
 793         gsw->irq = irq_of_parse_and_map(np, 0);
 794         if (gsw->irq) {
 795                 if (IS_ENABLED(CONFIG_SOC_MT7620)) {
 796                         request_irq(gsw->irq, gsw_interrupt_mt7620, 0, "gsw", priv);
 797                         gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 798                 } else {
 799                         request_irq(gsw->irq, gsw_interrupt_mt7621, 0, "gsw", priv);
 800                         mt7530_mdio_w32(gsw, 0x7008, 0x1f);
 801                 }
 802         }
 803
 804         return 0;
 805 }