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ramips: add xmit_more support
[openwrt/staging/chunkeey.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
48 (NETIF_MSG_DRV | \
49 NETIF_MSG_PROBE | \
50 NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | \
53 NETIF_MSG_IFUP | \
54 NETIF_MSG_RX_ERR | \
55 NETIF_MSG_TX_ERR)
56
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (priv->rx_ring_size - 1))
61
62 #define SYSC_REG_RSTCTRL 0x34
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base = 0;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_reset(u32 reset_bits)
117 {
118 u32 t;
119
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
121 t |= reset_bits;
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
123 udelay(10);
124
125 t &= ~reset_bits;
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
127 udelay(10);
128 }
129
130 static inline void fe_int_disable(u32 mask)
131 {
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
134 /* flush write */
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
136 }
137
138 static inline void fe_int_enable(u32 mask)
139 {
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
142 /* flush write */
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
144 }
145
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
153 FE_GDMA1_MAC_ADRL);
154 spin_unlock_irqrestore(&priv->page_lock, flags);
155 }
156
157 static int fe_set_mac_address(struct net_device *dev, void *p)
158 {
159 int ret = eth_mac_addr(dev, p);
160
161 if (!ret) {
162 struct fe_priv *priv = netdev_priv(dev);
163
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
166 else
167 fe_hw_set_macaddr(priv, p);
168 }
169
170 return ret;
171 }
172
173 static inline int fe_max_frag_size(int mtu)
174 {
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
177 }
178
179 static inline int fe_max_buf_size(int frag_size)
180 {
181 return frag_size - NET_SKB_PAD - NET_IP_ALIGN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
183 }
184
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
186 {
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
191 }
192
193 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
194 {
195 dma_txd->txd1 = txd->txd1;
196 dma_txd->txd3 = txd->txd3;
197 dma_txd->txd4 = txd->txd4;
198 /* clean dma done flag last */
199 dma_txd->txd2 = txd->txd2;
200 }
201
202 static void fe_clean_rx(struct fe_priv *priv)
203 {
204 int i;
205
206 if (priv->rx_data) {
207 for (i = 0; i < priv->rx_ring_size; i++)
208 if (priv->rx_data[i]) {
209 if (priv->rx_dma && priv->rx_dma[i].rxd1)
210 dma_unmap_single(&priv->netdev->dev,
211 priv->rx_dma[i].rxd1,
212 priv->rx_buf_size,
213 DMA_FROM_DEVICE);
214 put_page(virt_to_head_page(priv->rx_data[i]));
215 }
216
217 kfree(priv->rx_data);
218 priv->rx_data = NULL;
219 }
220
221 if (priv->rx_dma) {
222 dma_free_coherent(&priv->netdev->dev,
223 priv->rx_ring_size * sizeof(*priv->rx_dma),
224 priv->rx_dma,
225 priv->rx_phys);
226 priv->rx_dma = NULL;
227 }
228 }
229
230 static int fe_alloc_rx(struct fe_priv *priv)
231 {
232 struct net_device *netdev = priv->netdev;
233 int i, pad;
234
235 priv->rx_data = kcalloc(priv->rx_ring_size, sizeof(*priv->rx_data),
236 GFP_KERNEL);
237 if (!priv->rx_data)
238 goto no_rx_mem;
239
240 for (i = 0; i < priv->rx_ring_size; i++) {
241 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
242 if (!priv->rx_data[i])
243 goto no_rx_mem;
244 }
245
246 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
247 priv->rx_ring_size * sizeof(*priv->rx_dma),
248 &priv->rx_phys,
249 GFP_ATOMIC | __GFP_ZERO);
250 if (!priv->rx_dma)
251 goto no_rx_mem;
252
253 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
254 pad = 0;
255 else
256 pad = NET_IP_ALIGN;
257 for (i = 0; i < priv->rx_ring_size; i++) {
258 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
259 priv->rx_data[i] + NET_SKB_PAD + pad,
260 priv->rx_buf_size,
261 DMA_FROM_DEVICE);
262 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
263 goto no_rx_mem;
264 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
265
266 if (priv->flags & FE_FLAG_RX_SG_DMA)
267 priv->rx_dma[i].rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
268 else
269 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
270 }
271 wmb();
272
273 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
274 fe_reg_w32(priv->rx_ring_size, FE_REG_RX_MAX_CNT0);
275 fe_reg_w32((priv->rx_ring_size - 1), FE_REG_RX_CALC_IDX0);
276 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
277
278 return 0;
279
280 no_rx_mem:
281 return -ENOMEM;
282 }
283
284 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
285 {
286 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
287 dma_unmap_single(dev,
288 dma_unmap_addr(tx_buf, dma_addr0),
289 dma_unmap_len(tx_buf, dma_len0),
290 DMA_TO_DEVICE);
291 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
292 dma_unmap_page(dev,
293 dma_unmap_addr(tx_buf, dma_addr0),
294 dma_unmap_len(tx_buf, dma_len0),
295 DMA_TO_DEVICE);
296 }
297 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
298 dma_unmap_page(dev,
299 dma_unmap_addr(tx_buf, dma_addr1),
300 dma_unmap_len(tx_buf, dma_len1),
301 DMA_TO_DEVICE);
302
303 tx_buf->flags = 0;
304 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
305 dev_kfree_skb_any(tx_buf->skb);
306 }
307 tx_buf->skb = NULL;
308 }
309
310 static void fe_clean_tx(struct fe_priv *priv)
311 {
312 int i;
313 struct device *dev = &priv->netdev->dev;
314 struct fe_tx_ring *ring = &priv->tx_ring;
315
316 if (ring->tx_buf) {
317 for (i = 0; i < ring->tx_ring_size; i++)
318 fe_txd_unmap(dev, &ring->tx_buf[i]);
319 kfree(ring->tx_buf);
320 ring->tx_buf = NULL;
321 }
322
323 if (ring->tx_dma) {
324 dma_free_coherent(dev,
325 ring->tx_ring_size * sizeof(*ring->tx_dma),
326 ring->tx_dma,
327 ring->tx_phys);
328 ring->tx_dma = NULL;
329 }
330
331 netdev_reset_queue(priv->netdev);
332 }
333
334 static int fe_alloc_tx(struct fe_priv *priv)
335 {
336 int i;
337 struct fe_tx_ring *ring = &priv->tx_ring;
338
339 ring->tx_free_idx = 0;
340 ring->tx_next_idx = 0;
341 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
342
343 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
344 GFP_KERNEL);
345 if (!ring->tx_buf)
346 goto no_tx_mem;
347
348 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
349 ring->tx_ring_size * sizeof(*ring->tx_dma),
350 &ring->tx_phys,
351 GFP_ATOMIC | __GFP_ZERO);
352 if (!ring->tx_dma)
353 goto no_tx_mem;
354
355 for (i = 0; i < ring->tx_ring_size; i++) {
356 if (priv->soc->tx_dma) {
357 priv->soc->tx_dma(&ring->tx_dma[i]);
358 }
359 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
360 }
361 wmb();
362
363 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
364 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
365 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
366 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
367
368 return 0;
369
370 no_tx_mem:
371 return -ENOMEM;
372 }
373
374 static int fe_init_dma(struct fe_priv *priv)
375 {
376 int err;
377
378 err = fe_alloc_tx(priv);
379 if (err)
380 return err;
381
382 err = fe_alloc_rx(priv);
383 if (err)
384 return err;
385
386 return 0;
387 }
388
389 static void fe_free_dma(struct fe_priv *priv)
390 {
391 fe_clean_tx(priv);
392 fe_clean_rx(priv);
393 }
394
395 void fe_stats_update(struct fe_priv *priv)
396 {
397 struct fe_hw_stats *hwstats = priv->hw_stats;
398 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
399 u64 stats;
400
401 u64_stats_update_begin(&hwstats->syncp);
402
403 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
404 hwstats->rx_bytes += fe_r32(base);
405 stats = fe_r32(base + 0x04);
406 if (stats)
407 hwstats->rx_bytes += (stats << 32);
408 hwstats->rx_packets += fe_r32(base + 0x08);
409 hwstats->rx_overflow += fe_r32(base + 0x10);
410 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
411 hwstats->rx_short_errors += fe_r32(base + 0x18);
412 hwstats->rx_long_errors += fe_r32(base + 0x1c);
413 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
414 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
415 hwstats->tx_skip += fe_r32(base + 0x28);
416 hwstats->tx_collisions += fe_r32(base + 0x2c);
417 hwstats->tx_bytes += fe_r32(base + 0x30);
418 stats = fe_r32(base + 0x34);
419 if (stats)
420 hwstats->tx_bytes += (stats << 32);
421 hwstats->tx_packets += fe_r32(base + 0x38);
422 } else {
423 hwstats->tx_bytes += fe_r32(base);
424 hwstats->tx_packets += fe_r32(base + 0x04);
425 hwstats->tx_skip += fe_r32(base + 0x08);
426 hwstats->tx_collisions += fe_r32(base + 0x0c);
427 hwstats->rx_bytes += fe_r32(base + 0x20);
428 hwstats->rx_packets += fe_r32(base + 0x24);
429 hwstats->rx_overflow += fe_r32(base + 0x28);
430 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
431 hwstats->rx_short_errors += fe_r32(base + 0x30);
432 hwstats->rx_long_errors += fe_r32(base + 0x34);
433 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
434 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
435 }
436
437 u64_stats_update_end(&hwstats->syncp);
438 }
439
440 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
441 struct rtnl_link_stats64 *storage)
442 {
443 struct fe_priv *priv = netdev_priv(dev);
444 struct fe_hw_stats *hwstats = priv->hw_stats;
445 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
446 unsigned int start;
447
448 if (!base) {
449 netdev_stats_to_stats64(storage, &dev->stats);
450 return storage;
451 }
452
453 if (netif_running(dev) && netif_device_present(dev)) {
454 if (spin_trylock(&hwstats->stats_lock)) {
455 fe_stats_update(priv);
456 spin_unlock(&hwstats->stats_lock);
457 }
458 }
459
460 do {
461 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
462 storage->rx_packets = hwstats->rx_packets;
463 storage->tx_packets = hwstats->tx_packets;
464 storage->rx_bytes = hwstats->rx_bytes;
465 storage->tx_bytes = hwstats->tx_bytes;
466 storage->collisions = hwstats->tx_collisions;
467 storage->rx_length_errors = hwstats->rx_short_errors +
468 hwstats->rx_long_errors;
469 storage->rx_over_errors = hwstats->rx_overflow;
470 storage->rx_crc_errors = hwstats->rx_fcs_errors;
471 storage->rx_errors = hwstats->rx_checksum_errors;
472 storage->tx_aborted_errors = hwstats->tx_skip;
473 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
474
475 storage->tx_errors = priv->netdev->stats.tx_errors;
476 storage->rx_dropped = priv->netdev->stats.rx_dropped;
477 storage->tx_dropped = priv->netdev->stats.tx_dropped;
478
479 return storage;
480 }
481
482 static int fe_vlan_rx_add_vid(struct net_device *dev,
483 __be16 proto, u16 vid)
484 {
485 struct fe_priv *priv = netdev_priv(dev);
486 u32 idx = (vid & 0xf);
487 u32 vlan_cfg;
488
489 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
490 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
491 return 0;
492
493 if (test_bit(idx, &priv->vlan_map)) {
494 netdev_warn(dev, "disable tx vlan offload\n");
495 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
496 netdev_update_features(dev);
497 } else {
498 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
499 ((idx >> 1) << 2));
500 if (idx & 0x1) {
501 vlan_cfg &= 0xffff;
502 vlan_cfg |= (vid << 16);
503 } else {
504 vlan_cfg &= 0xffff0000;
505 vlan_cfg |= vid;
506 }
507 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
508 ((idx >> 1) << 2));
509 set_bit(idx, &priv->vlan_map);
510 }
511
512 return 0;
513 }
514
515 static int fe_vlan_rx_kill_vid(struct net_device *dev,
516 __be16 proto, u16 vid)
517 {
518 struct fe_priv *priv = netdev_priv(dev);
519 u32 idx = (vid & 0xf);
520
521 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
522 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
523 return 0;
524
525 clear_bit(idx, &priv->vlan_map);
526
527 return 0;
528 }
529
530 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
531 {
532 barrier();
533 return (u32)(ring->tx_ring_size -
534 ((ring->tx_next_idx - ring->tx_free_idx) &
535 (ring->tx_ring_size - 1)));
536 }
537
538 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
539 int tx_num, struct fe_tx_ring *ring)
540 {
541 struct fe_priv *priv = netdev_priv(dev);
542 struct skb_frag_struct *frag;
543 struct fe_tx_dma txd, *ptxd;
544 struct fe_tx_buf *tx_buf;
545 dma_addr_t mapped_addr;
546 unsigned int nr_frags;
547 u32 def_txd4;
548 int i, j, k, frag_size, frag_map_size, offset;
549
550 tx_buf = &ring->tx_buf[ring->tx_next_idx];
551 memset(tx_buf, 0, sizeof(*tx_buf));
552 memset(&txd, 0, sizeof(txd));
553 nr_frags = skb_shinfo(skb)->nr_frags;
554
555 /* init tx descriptor */
556 if (priv->soc->tx_dma)
557 priv->soc->tx_dma(&txd);
558 else
559 txd.txd4 = TX_DMA_DESP4_DEF;
560 def_txd4 = txd.txd4;
561
562 /* TX Checksum offload */
563 if (skb->ip_summed == CHECKSUM_PARTIAL)
564 txd.txd4 |= TX_DMA_CHKSUM;
565
566 /* VLAN header offload */
567 if (vlan_tx_tag_present(skb)) {
568 if (IS_ENABLED(CONFIG_SOC_MT7621))
569 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
570 else
571 txd.txd4 |= TX_DMA_INS_VLAN |
572 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
573 (vlan_tx_tag_get(skb) & 0xF);
574 }
575
576 /* TSO: fill MSS info in tcp checksum field */
577 if (skb_is_gso(skb)) {
578 if (skb_cow_head(skb, 0)) {
579 netif_warn(priv, tx_err, dev,
580 "GSO expand head fail.\n");
581 goto err_out;
582 }
583 if (skb_shinfo(skb)->gso_type &
584 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
585 txd.txd4 |= TX_DMA_TSO;
586 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
587 }
588 }
589
590 mapped_addr = dma_map_single(&dev->dev, skb->data,
591 skb_headlen(skb), DMA_TO_DEVICE);
592 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
593 goto err_out;
594 txd.txd1 = mapped_addr;
595 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
596
597 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
598 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
599 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
600
601 /* TX SG offload */
602 j = ring->tx_next_idx;
603 k = 0;
604 for (i = 0; i < nr_frags; i++) {
605 offset = 0;
606 frag = &skb_shinfo(skb)->frags[i];
607 frag_size = skb_frag_size(frag);
608
609 while (frag_size > 0) {
610 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
611 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
612 frag_map_size, DMA_TO_DEVICE);
613 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
614 goto err_dma;
615
616 if (k & 0x1) {
617 j = NEXT_TX_DESP_IDX(j);
618 txd.txd1 = mapped_addr;
619 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
620 txd.txd4 = def_txd4;
621
622 tx_buf = &ring->tx_buf[j];
623 memset(tx_buf, 0, sizeof(*tx_buf));
624
625 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
626 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
627 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
628 } else {
629 txd.txd3 = mapped_addr;
630 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
631
632 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
633 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
634 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
635 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
636
637 if (!((i == (nr_frags -1)) &&
638 (frag_map_size == frag_size))) {
639 fe_set_txd(&txd, &ring->tx_dma[j]);
640 memset(&txd, 0, sizeof(txd));
641 }
642 }
643 frag_size -= frag_map_size;
644 offset += frag_map_size;
645 k++;
646 }
647 }
648
649 /* set last segment */
650 if (k & 0x1)
651 txd.txd2 |= TX_DMA_LS1;
652 else
653 txd.txd2 |= TX_DMA_LS0;
654 fe_set_txd(&txd, &ring->tx_dma[j]);
655
656 /* store skb to cleanup */
657 tx_buf->skb = skb;
658
659 netdev_sent_queue(dev, skb->len);
660 skb_tx_timestamp(skb);
661
662 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
663 wmb();
664 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
665 netif_stop_queue(dev);
666 smp_mb();
667 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
668 netif_wake_queue(dev);
669 }
670
671 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
672 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
673
674 return 0;
675
676 err_dma:
677 j = ring->tx_next_idx;
678 for (i = 0; i < tx_num; i++) {
679 ptxd = &ring->tx_dma[j];
680 tx_buf = &ring->tx_buf[j];
681
682 /* unmap dma */
683 fe_txd_unmap(&dev->dev, tx_buf);
684
685 ptxd->txd2 = TX_DMA_DESP2_DEF;
686 j = NEXT_TX_DESP_IDX(j);
687 }
688 wmb();
689
690 err_out:
691 return -1;
692 }
693
694 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
695 unsigned int len;
696 int ret;
697
698 ret = 0;
699 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
700 if ((priv->flags & FE_FLAG_PADDING_64B) &&
701 !(priv->flags & FE_FLAG_PADDING_BUG))
702 return ret;
703
704 if (vlan_tx_tag_present(skb))
705 len = ETH_ZLEN;
706 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
707 len = VLAN_ETH_ZLEN;
708 else if(!(priv->flags & FE_FLAG_PADDING_64B))
709 len = ETH_ZLEN;
710 else
711 return ret;
712
713 if (skb->len < len) {
714 if ((ret = skb_pad(skb, len - skb->len)) < 0)
715 return ret;
716 skb->len = len;
717 skb_set_tail_pointer(skb, len);
718 }
719 }
720
721 return ret;
722 }
723
724 static inline int fe_cal_txd_req(struct sk_buff *skb)
725 {
726 int i, nfrags;
727 struct skb_frag_struct *frag;
728
729 nfrags = 1;
730 if (skb_is_gso(skb)) {
731 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
732 frag = &skb_shinfo(skb)->frags[i];
733 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
734 }
735 } else {
736 nfrags += skb_shinfo(skb)->nr_frags;
737 }
738
739 return DIV_ROUND_UP(nfrags, 2);
740 }
741
742 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
743 {
744 struct fe_priv *priv = netdev_priv(dev);
745 struct fe_tx_ring *ring = &priv->tx_ring;
746 struct net_device_stats *stats = &dev->stats;
747 int tx_num;
748 int len = skb->len;
749
750 if (fe_skb_padto(skb, priv)) {
751 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
752 return NETDEV_TX_OK;
753 }
754
755 tx_num = fe_cal_txd_req(skb);
756 if (unlikely(fe_empty_txd(ring) <= tx_num))
757 {
758 netif_stop_queue(dev);
759 netif_err(priv, tx_queued,dev,
760 "Tx Ring full when queue awake!\n");
761 return NETDEV_TX_BUSY;
762 }
763
764 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
765 stats->tx_dropped++;
766 } else {
767 stats->tx_packets++;
768 stats->tx_bytes += len;
769 }
770
771 return NETDEV_TX_OK;
772 }
773
774 static inline void fe_rx_vlan(struct sk_buff *skb)
775 {
776 struct ethhdr *ehdr;
777 u16 vlanid;
778
779 if (!__vlan_get_tag(skb, &vlanid)) {
780 /* pop the vlan tag */
781 ehdr = (struct ethhdr *)skb->data;
782 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
783 skb_pull(skb, VLAN_HLEN);
784 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
785 }
786 }
787
788 static int fe_poll_rx(struct napi_struct *napi, int budget,
789 struct fe_priv *priv, u32 rx_intr)
790 {
791 struct net_device *netdev = priv->netdev;
792 struct net_device_stats *stats = &netdev->stats;
793 struct fe_soc_data *soc = priv->soc;
794 u32 checksum_bit;
795 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
796 struct sk_buff *skb;
797 u8 *data, *new_data;
798 struct fe_rx_dma *rxd, trxd;
799 int done = 0, pad;
800 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
801
802 if (netdev->features & NETIF_F_RXCSUM)
803 checksum_bit = soc->checksum_bit;
804 else
805 checksum_bit = 0;
806
807 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
808 pad = 0;
809 else
810 pad = NET_IP_ALIGN;
811
812 while (done < budget) {
813 unsigned int pktlen;
814 dma_addr_t dma_addr;
815 idx = NEXT_RX_DESP_IDX(idx);
816 rxd = &priv->rx_dma[idx];
817 data = priv->rx_data[idx];
818
819 fe_get_rxd(&trxd, rxd);
820 if (!(trxd.rxd2 & RX_DMA_DONE))
821 break;
822
823 /* alloc new buffer */
824 new_data = netdev_alloc_frag(priv->frag_size);
825 if (unlikely(!new_data)) {
826 stats->rx_dropped++;
827 goto release_desc;
828 }
829 dma_addr = dma_map_single(&netdev->dev,
830 new_data + NET_SKB_PAD + pad,
831 priv->rx_buf_size,
832 DMA_FROM_DEVICE);
833 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
834 put_page(virt_to_head_page(new_data));
835 goto release_desc;
836 }
837
838 /* receive data */
839 skb = build_skb(data, priv->frag_size);
840 if (unlikely(!skb)) {
841 put_page(virt_to_head_page(new_data));
842 goto release_desc;
843 }
844 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
845
846 dma_unmap_single(&netdev->dev, trxd.rxd1,
847 priv->rx_buf_size, DMA_FROM_DEVICE);
848 pktlen = RX_DMA_PLEN0(trxd.rxd2);
849 skb->dev = netdev;
850 skb_put(skb, pktlen);
851 if (trxd.rxd4 & checksum_bit) {
852 skb->ip_summed = CHECKSUM_UNNECESSARY;
853 } else {
854 skb_checksum_none_assert(skb);
855 }
856 if (rx_vlan)
857 fe_rx_vlan(skb);
858 skb->protocol = eth_type_trans(skb, netdev);
859
860 stats->rx_packets++;
861 stats->rx_bytes += pktlen;
862
863 napi_gro_receive(napi, skb);
864
865 priv->rx_data[idx] = new_data;
866 rxd->rxd1 = (unsigned int) dma_addr;
867
868 release_desc:
869 if (priv->flags & FE_FLAG_RX_SG_DMA)
870 rxd->rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
871 else
872 rxd->rxd2 = RX_DMA_LSO;
873
874 wmb();
875 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
876 done++;
877 }
878
879 if (done < budget)
880 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
881
882 return done;
883 }
884
885 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
886 int *tx_again)
887 {
888 struct net_device *netdev = priv->netdev;
889 struct device *dev = &netdev->dev;
890 unsigned int bytes_compl = 0;
891 struct sk_buff *skb;
892 struct fe_tx_buf *tx_buf;
893 int done = 0;
894 u32 idx, hwidx;
895 struct fe_tx_ring *ring = &priv->tx_ring;
896
897 idx = ring->tx_free_idx;
898 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
899
900 while ((idx != hwidx) && budget) {
901 tx_buf = &ring->tx_buf[idx];
902 skb = tx_buf->skb;
903
904 if (!skb)
905 break;
906
907 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
908 bytes_compl += skb->len;
909 done++;
910 budget--;
911 }
912 fe_txd_unmap(dev, tx_buf);
913 idx = NEXT_TX_DESP_IDX(idx);
914 }
915 ring->tx_free_idx = idx;
916
917 if (idx == hwidx) {
918 /* read hw index again make sure no new tx packet */
919 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
920 if (idx == hwidx)
921 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
922 else
923 *tx_again = 1;
924 } else
925 *tx_again = 1;
926
927 if (done) {
928 netdev_completed_queue(netdev, done, bytes_compl);
929 smp_mb();
930 if (unlikely(netif_queue_stopped(netdev) &&
931 (fe_empty_txd(ring) > ring->tx_thresh)))
932 netif_wake_queue(netdev);
933 }
934
935 return done;
936 }
937
938 static int fe_poll(struct napi_struct *napi, int budget)
939 {
940 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
941 struct fe_hw_stats *hwstat = priv->hw_stats;
942 int tx_done, rx_done, tx_again;
943 u32 status, fe_status, status_reg, mask;
944 u32 tx_intr, rx_intr, status_intr;
945
946 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
947 tx_intr = priv->soc->tx_int;
948 rx_intr = priv->soc->rx_int;
949 status_intr = priv->soc->status_int;
950 tx_done = rx_done = tx_again = 0;
951
952 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
953 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
954 status_reg = FE_REG_FE_INT_STATUS2;
955 } else
956 status_reg = FE_REG_FE_INT_STATUS;
957
958 if (status & tx_intr)
959 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
960
961 if (status & rx_intr)
962 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
963
964 if (unlikely(fe_status & status_intr)) {
965 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
966 fe_stats_update(priv);
967 spin_unlock(&hwstat->stats_lock);
968 }
969 fe_reg_w32(status_intr, status_reg);
970 }
971
972 if (unlikely(netif_msg_intr(priv))) {
973 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
974 netdev_info(priv->netdev,
975 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
976 tx_done, rx_done, status, mask);
977 }
978
979 if (!tx_again && (rx_done < budget)) {
980 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
981 if (status & (tx_intr | rx_intr ))
982 goto poll_again;
983
984 napi_complete(napi);
985 fe_int_enable(tx_intr | rx_intr);
986 }
987
988 poll_again:
989 return rx_done;
990 }
991
992 static void fe_tx_timeout(struct net_device *dev)
993 {
994 struct fe_priv *priv = netdev_priv(dev);
995 struct fe_tx_ring *ring = &priv->tx_ring;
996
997 priv->netdev->stats.tx_errors++;
998 netif_err(priv, tx_err, dev,
999 "transmit timed out\n");
1000 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1001 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1002 netif_info(priv, drv, dev, "tx_ring=%d, " \
1003 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1004 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1005 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1006 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1007 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1008 ring->tx_free_idx,
1009 ring->tx_next_idx
1010 );
1011 netif_info(priv, drv, dev, "rx_ring=%d, " \
1012 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1013 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1014 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1015 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1016 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1017 );
1018
1019 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1020 schedule_work(&priv->pending_work);
1021 }
1022
1023 static irqreturn_t fe_handle_irq(int irq, void *dev)
1024 {
1025 struct fe_priv *priv = netdev_priv(dev);
1026 u32 status, int_mask;
1027
1028 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1029
1030 if (unlikely(!status))
1031 return IRQ_NONE;
1032
1033 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1034 if (likely(status & int_mask)) {
1035 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1036 fe_int_disable(int_mask);
1037 __napi_schedule(&priv->rx_napi);
1038 }
1039 } else {
1040 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1041 }
1042
1043 return IRQ_HANDLED;
1044 }
1045
1046 #ifdef CONFIG_NET_POLL_CONTROLLER
1047 static void fe_poll_controller(struct net_device *dev)
1048 {
1049 struct fe_priv *priv = netdev_priv(dev);
1050 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1051
1052 fe_int_disable(int_mask);
1053 fe_handle_irq(dev->irq, dev);
1054 fe_int_enable(int_mask);
1055 }
1056 #endif
1057
1058 int fe_set_clock_cycle(struct fe_priv *priv)
1059 {
1060 unsigned long sysclk = priv->sysclk;
1061
1062 if (!sysclk) {
1063 return -EINVAL;
1064 }
1065
1066 sysclk /= FE_US_CYC_CNT_DIVISOR;
1067 sysclk <<= FE_US_CYC_CNT_SHIFT;
1068
1069 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1070 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1071 sysclk,
1072 FE_FE_GLO_CFG);
1073 return 0;
1074 }
1075
1076 void fe_fwd_config(struct fe_priv *priv)
1077 {
1078 u32 fwd_cfg;
1079
1080 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1081
1082 /* disable jumbo frame */
1083 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1084 fwd_cfg &= ~FE_GDM1_JMB_EN;
1085
1086 /* set unicast/multicast/broadcast frame to cpu */
1087 fwd_cfg &= ~0xffff;
1088
1089 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1090 }
1091
1092 static void fe_rxcsum_config(bool enable)
1093 {
1094 if (enable)
1095 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1096 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1097 FE_GDMA1_FWD_CFG);
1098 else
1099 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1100 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1101 FE_GDMA1_FWD_CFG);
1102 }
1103
1104 static void fe_txcsum_config(bool enable)
1105 {
1106 if (enable)
1107 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1108 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1109 FE_CDMA_CSG_CFG);
1110 else
1111 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1112 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1113 FE_CDMA_CSG_CFG);
1114 }
1115
1116 void fe_csum_config(struct fe_priv *priv)
1117 {
1118 struct net_device *dev = priv_netdev(priv);
1119
1120 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1121 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1122 }
1123
1124 static int fe_hw_init(struct net_device *dev)
1125 {
1126 struct fe_priv *priv = netdev_priv(dev);
1127 int i, err;
1128
1129 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1130 dev_name(priv->device), dev);
1131 if (err)
1132 return err;
1133
1134 if (priv->soc->set_mac)
1135 priv->soc->set_mac(priv, dev->dev_addr);
1136 else
1137 fe_hw_set_macaddr(priv, dev->dev_addr);
1138
1139 /* disable delay interrupt */
1140 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1141
1142 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1143
1144 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1145 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1146 for (i = 0; i < 16; i += 2)
1147 fe_w32(((i + 1) << 16) + i,
1148 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1149 (i * 2));
1150
1151 BUG_ON(!priv->soc->fwd_config);
1152 if (priv->soc->fwd_config(priv))
1153 netdev_err(dev, "unable to get clock\n");
1154
1155 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1156 fe_reg_w32(1, FE_REG_FE_RST_GL);
1157 fe_reg_w32(0, FE_REG_FE_RST_GL);
1158 }
1159
1160 return 0;
1161 }
1162
1163 static int fe_open(struct net_device *dev)
1164 {
1165 struct fe_priv *priv = netdev_priv(dev);
1166 unsigned long flags;
1167 u32 val;
1168 int err;
1169
1170 err = fe_init_dma(priv);
1171 if (err)
1172 goto err_out;
1173
1174 spin_lock_irqsave(&priv->page_lock, flags);
1175
1176 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1177 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1178 val |= FE_RX_2B_OFFSET;
1179 val |= priv->soc->pdma_glo_cfg;
1180 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1181
1182 spin_unlock_irqrestore(&priv->page_lock, flags);
1183
1184 if (priv->phy)
1185 priv->phy->start(priv);
1186
1187 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1188 netif_carrier_on(dev);
1189
1190 napi_enable(&priv->rx_napi);
1191 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1192 netif_start_queue(dev);
1193
1194 return 0;
1195
1196 err_out:
1197 fe_free_dma(priv);
1198 return err;
1199 }
1200
1201 static int fe_stop(struct net_device *dev)
1202 {
1203 struct fe_priv *priv = netdev_priv(dev);
1204 unsigned long flags;
1205 int i;
1206
1207 netif_tx_disable(dev);
1208 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1209 napi_disable(&priv->rx_napi);
1210
1211 if (priv->phy)
1212 priv->phy->stop(priv);
1213
1214 spin_lock_irqsave(&priv->page_lock, flags);
1215
1216 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1217 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1218 FE_REG_PDMA_GLO_CFG);
1219 spin_unlock_irqrestore(&priv->page_lock, flags);
1220
1221 /* wait dma stop */
1222 for (i = 0; i < 10; i++) {
1223 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1224 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1225 msleep(10);
1226 continue;
1227 }
1228 break;
1229 }
1230
1231 fe_free_dma(priv);
1232
1233 return 0;
1234 }
1235
1236 static int __init fe_init(struct net_device *dev)
1237 {
1238 struct fe_priv *priv = netdev_priv(dev);
1239 struct device_node *port;
1240 int err;
1241
1242 BUG_ON(!priv->soc->reset_fe);
1243 priv->soc->reset_fe();
1244
1245 if (priv->soc->switch_init)
1246 priv->soc->switch_init(priv);
1247
1248 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1249 /*If the mac address is invalid, use random mac address */
1250 if (!is_valid_ether_addr(dev->dev_addr)) {
1251 random_ether_addr(dev->dev_addr);
1252 dev_err(priv->device, "generated random MAC address %pM\n",
1253 dev->dev_addr);
1254 }
1255
1256 err = fe_mdio_init(priv);
1257 if (err)
1258 return err;
1259
1260 if (priv->soc->port_init)
1261 for_each_child_of_node(priv->device->of_node, port)
1262 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1263 priv->soc->port_init(priv, port);
1264
1265 if (priv->phy) {
1266 err = priv->phy->connect(priv);
1267 if (err)
1268 goto err_phy_disconnect;
1269 }
1270
1271 err = fe_hw_init(dev);
1272 if (err)
1273 goto err_phy_disconnect;
1274
1275 if (priv->soc->switch_config)
1276 priv->soc->switch_config(priv);
1277
1278 return 0;
1279
1280 err_phy_disconnect:
1281 if (priv->phy)
1282 priv->phy->disconnect(priv);
1283 fe_mdio_cleanup(priv);
1284
1285 return err;
1286 }
1287
1288 static void fe_uninit(struct net_device *dev)
1289 {
1290 struct fe_priv *priv = netdev_priv(dev);
1291
1292 if (priv->phy)
1293 priv->phy->disconnect(priv);
1294 fe_mdio_cleanup(priv);
1295
1296 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1297 free_irq(dev->irq, dev);
1298 }
1299
1300 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1301 {
1302 struct fe_priv *priv = netdev_priv(dev);
1303
1304 if (!priv->phy_dev)
1305 return -ENODEV;
1306
1307 switch (cmd) {
1308 case SIOCETHTOOL:
1309 return phy_ethtool_ioctl(priv->phy_dev,
1310 (void *) ifr->ifr_data);
1311 case SIOCGMIIPHY:
1312 case SIOCGMIIREG:
1313 case SIOCSMIIREG:
1314 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1315 default:
1316 break;
1317 }
1318
1319 return -EOPNOTSUPP;
1320 }
1321
1322 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1323 {
1324 struct fe_priv *priv = netdev_priv(dev);
1325 int frag_size, old_mtu;
1326 u32 fwd_cfg;
1327
1328 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1329 return eth_change_mtu(dev, new_mtu);
1330
1331 frag_size = fe_max_frag_size(new_mtu);
1332 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1333 return -EINVAL;
1334
1335 old_mtu = dev->mtu;
1336 dev->mtu = new_mtu;
1337
1338 /* return early if the buffer sizes will not change */
1339 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1340 return 0;
1341 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1342 return 0;
1343
1344 if (new_mtu <= ETH_DATA_LEN)
1345 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1346 else
1347 priv->frag_size = PAGE_SIZE;
1348 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1349
1350 if (!netif_running(dev))
1351 return 0;
1352
1353 fe_stop(dev);
1354 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1355 if (new_mtu <= ETH_DATA_LEN)
1356 fwd_cfg &= ~FE_GDM1_JMB_EN;
1357 else {
1358 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1359 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1360 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1361 }
1362 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1363
1364 return fe_open(dev);
1365 }
1366
1367 static const struct net_device_ops fe_netdev_ops = {
1368 .ndo_init = fe_init,
1369 .ndo_uninit = fe_uninit,
1370 .ndo_open = fe_open,
1371 .ndo_stop = fe_stop,
1372 .ndo_start_xmit = fe_start_xmit,
1373 .ndo_set_mac_address = fe_set_mac_address,
1374 .ndo_validate_addr = eth_validate_addr,
1375 .ndo_do_ioctl = fe_do_ioctl,
1376 .ndo_change_mtu = fe_change_mtu,
1377 .ndo_tx_timeout = fe_tx_timeout,
1378 .ndo_get_stats64 = fe_get_stats64,
1379 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1380 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1381 #ifdef CONFIG_NET_POLL_CONTROLLER
1382 .ndo_poll_controller = fe_poll_controller,
1383 #endif
1384 };
1385
1386 static void fe_reset_pending(struct fe_priv *priv)
1387 {
1388 struct net_device *dev = priv->netdev;
1389 int err;
1390
1391 rtnl_lock();
1392 fe_stop(dev);
1393
1394 err = fe_open(dev);
1395 if (err)
1396 goto error;
1397 rtnl_unlock();
1398
1399 return;
1400 error:
1401 netif_alert(priv, ifup, dev,
1402 "Driver up/down cycle failed, closing device.\n");
1403 dev_close(dev);
1404 rtnl_unlock();
1405 }
1406
1407 static const struct fe_work_t fe_work[] = {
1408 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1409 };
1410
1411 static void fe_pending_work(struct work_struct *work)
1412 {
1413 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1414 int i;
1415 bool pending;
1416
1417 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1418 pending = test_and_clear_bit(fe_work[i].bitnr,
1419 priv->pending_flags);
1420 if (pending)
1421 fe_work[i].action(priv);
1422 }
1423 }
1424
1425 static int fe_probe(struct platform_device *pdev)
1426 {
1427 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1428 const struct of_device_id *match;
1429 struct fe_soc_data *soc;
1430 struct net_device *netdev;
1431 struct fe_priv *priv;
1432 struct clk *sysclk;
1433 int err, napi_weight;
1434
1435 device_reset(&pdev->dev);
1436
1437 match = of_match_device(of_fe_match, &pdev->dev);
1438 soc = (struct fe_soc_data *) match->data;
1439
1440 if (soc->reg_table)
1441 fe_reg_table = soc->reg_table;
1442 else
1443 soc->reg_table = fe_reg_table;
1444
1445 fe_base = devm_ioremap_resource(&pdev->dev, res);
1446 if (!fe_base) {
1447 err = -EADDRNOTAVAIL;
1448 goto err_out;
1449 }
1450
1451 netdev = alloc_etherdev(sizeof(*priv));
1452 if (!netdev) {
1453 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1454 err = -ENOMEM;
1455 goto err_iounmap;
1456 }
1457
1458 SET_NETDEV_DEV(netdev, &pdev->dev);
1459 netdev->netdev_ops = &fe_netdev_ops;
1460 netdev->base_addr = (unsigned long) fe_base;
1461
1462 netdev->irq = platform_get_irq(pdev, 0);
1463 if (netdev->irq < 0) {
1464 dev_err(&pdev->dev, "no IRQ resource found\n");
1465 err = -ENXIO;
1466 goto err_free_dev;
1467 }
1468
1469 if (soc->init_data)
1470 soc->init_data(soc, netdev);
1471 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1472 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1473 netdev->vlan_features = netdev->hw_features &
1474 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1475 netdev->features |= netdev->hw_features;
1476
1477 /* fake rx vlan filter func. to support tx vlan offload func */
1478 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1479 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1480
1481 priv = netdev_priv(netdev);
1482 spin_lock_init(&priv->page_lock);
1483 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1484 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1485 if (!priv->hw_stats) {
1486 err = -ENOMEM;
1487 goto err_free_dev;
1488 }
1489 spin_lock_init(&priv->hw_stats->stats_lock);
1490 }
1491
1492 sysclk = devm_clk_get(&pdev->dev, NULL);
1493 if (!IS_ERR(sysclk))
1494 priv->sysclk = clk_get_rate(sysclk);
1495
1496 priv->netdev = netdev;
1497 priv->device = &pdev->dev;
1498 priv->soc = soc;
1499 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1500 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1501 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1502 priv->tx_ring.tx_ring_size = priv->rx_ring_size = NUM_DMA_DESC;
1503 INIT_WORK(&priv->pending_work, fe_pending_work);
1504
1505 napi_weight = 32;
1506 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1507 napi_weight *= 4;
1508 priv->tx_ring.tx_ring_size *= 4;
1509 priv->rx_ring_size *= 4;
1510 }
1511 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1512 fe_set_ethtool_ops(netdev);
1513
1514 err = register_netdev(netdev);
1515 if (err) {
1516 dev_err(&pdev->dev, "error bringing up device\n");
1517 goto err_free_dev;
1518 }
1519
1520 platform_set_drvdata(pdev, netdev);
1521
1522 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1523 netdev->base_addr, netdev->irq);
1524
1525 return 0;
1526
1527 err_free_dev:
1528 free_netdev(netdev);
1529 err_iounmap:
1530 devm_iounmap(&pdev->dev, fe_base);
1531 err_out:
1532 return err;
1533 }
1534
1535 static int fe_remove(struct platform_device *pdev)
1536 {
1537 struct net_device *dev = platform_get_drvdata(pdev);
1538 struct fe_priv *priv = netdev_priv(dev);
1539
1540 netif_napi_del(&priv->rx_napi);
1541 if (priv->hw_stats)
1542 kfree(priv->hw_stats);
1543
1544 cancel_work_sync(&priv->pending_work);
1545
1546 unregister_netdev(dev);
1547 free_netdev(dev);
1548 platform_set_drvdata(pdev, NULL);
1549
1550 return 0;
1551 }
1552
1553 static struct platform_driver fe_driver = {
1554 .probe = fe_probe,
1555 .remove = fe_remove,
1556 .driver = {
1557 .name = "ralink_soc_eth",
1558 .owner = THIS_MODULE,
1559 .of_match_table = of_fe_match,
1560 },
1561 };
1562
1563 static int __init init_rtfe(void)
1564 {
1565 int ret;
1566
1567 ret = rtesw_init();
1568 if (ret)
1569 return ret;
1570
1571 ret = platform_driver_register(&fe_driver);
1572 if (ret)
1573 rtesw_exit();
1574
1575 return ret;
1576 }
1577
1578 static void __exit exit_rtfe(void)
1579 {
1580 platform_driver_unregister(&fe_driver);
1581 rtesw_exit();
1582 }
1583
1584 module_init(init_rtfe);
1585 module_exit(exit_rtfe);
1586
1587 MODULE_LICENSE("GPL");
1588 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1589 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1590 MODULE_VERSION(FE_DRV_VERSION);
Staging tree of Christian Lamparter