target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch

   1 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
   2 index 3865dfb9ed08..424359d3cbb1 100644
   3 --- a/drivers/pwm/Kconfig
   4 +++ b/drivers/pwm/Kconfig
   5 @@ -262,6 +262,15 @@ config PWM_STI
   6           To compile this driver as a module, choose M here: the module
   7           will be called pwm-sti.
   8
   9 +config PWM_SUN4I
  10 +       tristate "Allwinner sun4i PWM support"
  11 +       depends on ARCH_SUNXI || COMPILE_TEST
  12 +       help
  13 +         Generic PWM framework driver for Allwinner sun4i and sun7i SoCs.
  14 +
  15 +         To compile this driver as a module, choose M here: the module
  16 +         will be called pwm-sun4i.
  17 +
  18  config PWM_TEGRA
  19         tristate "NVIDIA Tegra PWM support"
  20         depends on ARCH_TEGRA
  21 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
  22 index c458606c3755..d607804deea1 100644
  23 --- a/drivers/pwm/Makefile
  24 +++ b/drivers/pwm/Makefile
  25 @@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_ROCKCHIP)    += pwm-rockchip.o
  26  obj-$(CONFIG_PWM_SAMSUNG)      += pwm-samsung.o
  27  obj-$(CONFIG_PWM_SPEAR)                += pwm-spear.o
  28  obj-$(CONFIG_PWM_STI)          += pwm-sti.o
  29 +obj-$(CONFIG_PWM_SUN4I)                += pwm-sun4i.o
  30  obj-$(CONFIG_PWM_TEGRA)                += pwm-tegra.o
  31  obj-$(CONFIG_PWM_TIECAP)       += pwm-tiecap.o
  32  obj-$(CONFIG_PWM_TIEHRPWM)     += pwm-tiehrpwm.o
  33 diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
  34 new file mode 100644
  35 index 000000000000..918f8ee79b51
  36 --- /dev/null
  37 +++ b/drivers/pwm/pwm-sun4i.c
  38 @@ -0,0 +1,371 @@
  39 +/*
  40 + * Driver for Allwinner sun4i Pulse Width Modulation Controller
  41 + *
  42 + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
  43 + *
  44 + * Licensed under GPLv2.
  45 + */
  46 +
  47 +#include <linux/bitops.h>
  48 +#include <linux/clk.h>
  49 +#include <linux/err.h>
  50 +#include <linux/io.h>
  51 +#include <linux/module.h>
  52 +#include <linux/mutex.h>
  53 +#include <linux/of.h>
  54 +#include <linux/of_device.h>
  55 +#include <linux/platform_device.h>
  56 +#include <linux/pwm.h>
  57 +#include <linux/slab.h>
  58 +#include <linux/time.h>
  59 +
  60 +#define PWM_CTRL_REG           0x0
  61 +
  62 +#define PWM_CH_PRD_BASE                0x4
  63 +#define PWM_CH_PRD_OFFSET      0x4
  64 +#define PWM_CH_PRD(ch)         (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  65 +
  66 +#define PWMCH_OFFSET           15
  67 +#define PWM_PRESCAL_MASK       GENMASK(3, 0)
  68 +#define PWM_PRESCAL_OFF                0
  69 +#define PWM_EN                 BIT(4)
  70 +#define PWM_ACT_STATE          BIT(5)
  71 +#define PWM_CLK_GATING         BIT(6)
  72 +#define PWM_MODE               BIT(7)
  73 +#define PWM_PULSE              BIT(8)
  74 +#define PWM_BYPASS             BIT(9)
  75 +
  76 +#define PWM_RDY_BASE           28
  77 +#define PWM_RDY_OFFSET         1
  78 +#define PWM_RDY(ch)            BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  79 +
  80 +#define PWM_PRD(prd)           (((prd) - 1) << 16)
  81 +#define PWM_PRD_MASK           GENMASK(15, 0)
  82 +
  83 +#define PWM_DTY_MASK           GENMASK(15, 0)
  84 +
  85 +#define BIT_CH(bit, chan)      ((bit) << ((chan) * PWMCH_OFFSET))
  86 +
  87 +static const u32 prescaler_table[] = {
  88 +       120,
  89 +       180,
  90 +       240,
  91 +       360,
  92 +       480,
  93 +       0,
  94 +       0,
  95 +       0,
  96 +       12000,
  97 +       24000,
  98 +       36000,
  99 +       48000,
 100 +       72000,
 101 +       0,
 102 +       0,
 103 +       0, /* Actually 1 but tested separately */
 104 +};
 105 +
 106 +struct sun4i_pwm_data {
 107 +       bool has_prescaler_bypass;
 108 +       bool has_rdy;
 109 +};
 110 +
 111 +struct sun4i_pwm_chip {
 112 +       struct pwm_chip chip;
 113 +       struct clk *clk;
 114 +       void __iomem *base;
 115 +       struct mutex ctrl_lock;
 116 +       const struct sun4i_pwm_data *data;
 117 +};
 118 +
 119 +static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
 120 +{
 121 +       return container_of(chip, struct sun4i_pwm_chip, chip);
 122 +}
 123 +
 124 +static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
 125 +                                 unsigned long offset)
 126 +{
 127 +       return readl(chip->base + offset);
 128 +}
 129 +
 130 +static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
 131 +                                   u32 val, unsigned long offset)
 132 +{
 133 +       writel(val, chip->base + offset);
 134 +}
 135 +
 136 +static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 137 +                           int duty_ns, int period_ns)
 138 +{
 139 +       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 140 +       u32 clk_rate, prd, dty, val, clk_gate;
 141 +       u64 div = 0;
 142 +       unsigned int prescaler = 0;
 143 +       int err;
 144 +
 145 +       clk_rate = clk_get_rate(sun4i_pwm->clk);
 146 +
 147 +       if (sun4i_pwm->data->has_prescaler_bypass) {
 148 +               /* First, test without any prescaler when available */
 149 +               prescaler = PWM_PRESCAL_MASK;
 150 +               /*
 151 +                * When not using any prescaler, the clock period in nanoseconds
 152 +                * is not an integer so round it half up instead of
 153 +                * truncating to get less surprising values.
 154 +                */
 155 +               div = clk_rate * (u64)period_ns + NSEC_PER_SEC/2;
 156 +               do_div(div, NSEC_PER_SEC);
 157 +               if (div - 1 > PWM_PRD_MASK)
 158 +                       prescaler = 0;
 159 +       }
 160 +
 161 +       if (prescaler == 0) {
 162 +               /* Go up from the first divider */
 163 +               for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
 164 +                       if (!prescaler_table[prescaler])
 165 +                               continue;
 166 +                       div = clk_rate / prescaler_table[prescaler];
 167 +                       div = div * (u64)period_ns;
 168 +                       do_div(div, NSEC_PER_SEC);
 169 +                       if (div - 1 <= PWM_PRD_MASK)
 170 +                               break;
 171 +               }
 172 +
 173 +               if (div - 1 > PWM_PRD_MASK) {
 174 +                       dev_err(chip->dev, "period exceeds the maximum value\n");
 175 +                       return -EINVAL;
 176 +               }
 177 +       }
 178 +
 179 +       prd = div;
 180 +       div *= duty_ns;
 181 +       do_div(div, period_ns);
 182 +       dty = div;
 183 +
 184 +       err = clk_prepare_enable(sun4i_pwm->clk);
 185 +       if (err) {
 186 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 187 +               return err;
 188 +       }
 189 +
 190 +       mutex_lock(&sun4i_pwm->ctrl_lock);
 191 +       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 192 +
 193 +       if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
 194 +               mutex_unlock(&sun4i_pwm->ctrl_lock);
 195 +               clk_disable_unprepare(sun4i_pwm->clk);
 196 +               return -EBUSY;
 197 +       }
 198 +
 199 +       clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 200 +       if (clk_gate) {
 201 +               val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 202 +               sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 203 +       }
 204 +
 205 +       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 206 +       val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 207 +       val |= BIT_CH(prescaler, pwm->hwpwm);
 208 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 209 +
 210 +       val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
 211 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 212 +
 213 +       if (clk_gate) {
 214 +               val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 215 +               val |= clk_gate;
 216 +               sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 217 +       }
 218 +
 219 +       mutex_unlock(&sun4i_pwm->ctrl_lock);
 220 +       clk_disable_unprepare(sun4i_pwm->clk);
 221 +
 222 +       return 0;
 223 +}
 224 +
 225 +static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 226 +                                 enum pwm_polarity polarity)
 227 +{
 228 +       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 229 +       u32 val;
 230 +       int ret;
 231 +
 232 +       ret = clk_prepare_enable(sun4i_pwm->clk);
 233 +       if (ret) {
 234 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 235 +               return ret;
 236 +       }
 237 +
 238 +       mutex_lock(&sun4i_pwm->ctrl_lock);
 239 +       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 240 +
 241 +       if (polarity != PWM_POLARITY_NORMAL)
 242 +               val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 243 +       else
 244 +               val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 245 +
 246 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 247 +
 248 +       mutex_unlock(&sun4i_pwm->ctrl_lock);
 249 +       clk_disable_unprepare(sun4i_pwm->clk);
 250 +
 251 +       return 0;
 252 +}
 253 +
 254 +static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 255 +{
 256 +       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 257 +       u32 val;
 258 +       int ret;
 259 +
 260 +       ret = clk_prepare_enable(sun4i_pwm->clk);
 261 +       if (ret) {
 262 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 263 +               return ret;
 264 +       }
 265 +
 266 +       mutex_lock(&sun4i_pwm->ctrl_lock);
 267 +       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 268 +       val |= BIT_CH(PWM_EN, pwm->hwpwm);
 269 +       val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 270 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 271 +       mutex_unlock(&sun4i_pwm->ctrl_lock);
 272 +
 273 +       return 0;
 274 +}
 275 +
 276 +static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 277 +{
 278 +       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 279 +       u32 val;
 280 +
 281 +       mutex_lock(&sun4i_pwm->ctrl_lock);
 282 +       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 283 +       val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 284 +       val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 285 +       sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
 286 +       mutex_unlock(&sun4i_pwm->ctrl_lock);
 287 +
 288 +       clk_disable_unprepare(sun4i_pwm->clk);
 289 +}
 290 +
 291 +static const struct pwm_ops sun4i_pwm_ops = {
 292 +       .config = sun4i_pwm_config,
 293 +       .set_polarity = sun4i_pwm_set_polarity,
 294 +       .enable = sun4i_pwm_enable,
 295 +       .disable = sun4i_pwm_disable,
 296 +       .owner = THIS_MODULE,
 297 +};
 298 +
 299 +static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
 300 +       .has_prescaler_bypass = false,
 301 +       .has_rdy = false,
 302 +};
 303 +
 304 +static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
 305 +       .has_prescaler_bypass = true,
 306 +       .has_rdy = true,
 307 +};
 308 +
 309 +static const struct of_device_id sun4i_pwm_dt_ids[] = {
 310 +       {
 311 +               .compatible = "allwinner,sun4i-a10-pwm",
 312 +               .data = &sun4i_pwm_data_a10,
 313 +       }, {
 314 +               .compatible = "allwinner,sun7i-a20-pwm",
 315 +               .data = &sun4i_pwm_data_a20,
 316 +       }, {
 317 +               /* sentinel */
 318 +       },
 319 +};
 320 +MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
 321 +
 322 +static int sun4i_pwm_probe(struct platform_device *pdev)
 323 +{
 324 +       struct sun4i_pwm_chip *pwm;
 325 +       struct resource *res;
 326 +       u32 val;
 327 +       int i, ret;
 328 +       const struct of_device_id *match;
 329 +
 330 +       match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
 331 +
 332 +       pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 333 +       if (!pwm)
 334 +               return -ENOMEM;
 335 +
 336 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 337 +       pwm->base = devm_ioremap_resource(&pdev->dev, res);
 338 +       if (IS_ERR(pwm->base))
 339 +               return PTR_ERR(pwm->base);
 340 +
 341 +       pwm->clk = devm_clk_get(&pdev->dev, NULL);
 342 +       if (IS_ERR(pwm->clk))
 343 +               return PTR_ERR(pwm->clk);
 344 +
 345 +       pwm->chip.dev = &pdev->dev;
 346 +       pwm->chip.ops = &sun4i_pwm_ops;
 347 +       pwm->chip.base = -1;
 348 +       pwm->chip.npwm = 2;
 349 +       pwm->chip.can_sleep = true;
 350 +       pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 351 +       pwm->chip.of_pwm_n_cells = 3;
 352 +       pwm->data = match->data;
 353 +
 354 +       mutex_init(&pwm->ctrl_lock);
 355 +
 356 +       ret = pwmchip_add(&pwm->chip);
 357 +       if (ret < 0) {
 358 +               dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 359 +               goto error;
 360 +       }
 361 +
 362 +       platform_set_drvdata(pdev, pwm);
 363 +
 364 +       ret = clk_prepare_enable(pwm->clk);
 365 +       if (ret) {
 366 +               dev_err(&pdev->dev, "failed to enable PWM clock\n");
 367 +               goto clk_error;
 368 +       }
 369 +
 370 +       val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
 371 +       for (i = 0; i < pwm->chip.npwm; i++) {
 372 +               if (!(val & BIT_CH(PWM_ACT_STATE, i)))
 373 +                       pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
 374 +       }
 375 +       clk_disable_unprepare(pwm->clk);
 376 +
 377 +       return 0;
 378 +
 379 +clk_error:
 380 +       pwmchip_remove(&pwm->chip);
 381 +
 382 +error:
 383 +       mutex_destroy(&pwm->ctrl_lock);
 384 +       return ret;
 385 +}
 386 +
 387 +static int sun4i_pwm_remove(struct platform_device *pdev)
 388 +{
 389 +       struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
 390 +
 391 +       mutex_destroy(&pwm->ctrl_lock);
 392 +
 393 +       return pwmchip_remove(&pwm->chip);
 394 +}
 395 +
 396 +static struct platform_driver sun4i_pwm_driver = {
 397 +       .driver = {
 398 +               .name = "sun4i-pwm",
 399 +               .of_match_table = sun4i_pwm_dt_ids,
 400 +       },
 401 +       .probe = sun4i_pwm_probe,
 402 +       .remove = sun4i_pwm_remove,
 403 +};
 404 +module_platform_driver(sun4i_pwm_driver);
 405 +
 406 +MODULE_ALIAS("platform:sun4i-pwm");
 407 +MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
 408 +MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
 409 +MODULE_LICENSE("GPL v2");