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kernel: update 3.10 to 3.10.3
[openwrt/staging/chunkeey.git] / target / linux / xburst / patches-3.10 / 015-MIPS-jz4740-Remove-custom-DMA-API.patch
1 From 7b91fca454e66ac1bc1fe5b68de0bf55f799bd41 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Thu, 30 May 2013 18:25:05 +0200
4 Subject: [PATCH 15/16] MIPS: jz4740: Remove custom DMA API
5
6 Now that all users of the custom jz4740 DMA API have been converted to use
7 the dmaengine API instead we can remove the custom API and move all the code
8 talking to the hardware to the dmaengine driver.
9
10 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
11 Acked-by: Ralf Baechle <ralf@linux-mips.org>
12 Signed-off-by: Vinod Koul <vinod.koul@intel.com>
13 ---
14 arch/mips/include/asm/mach-jz4740/dma.h | 56 ------
15 arch/mips/jz4740/Makefile | 2 +-
16 arch/mips/jz4740/dma.c | 307 -------------------------------
17 drivers/dma/dma-jz4740.c | 258 ++++++++++++++++++++++----
18 4 files changed, 222 insertions(+), 401 deletions(-)
19 delete mode 100644 arch/mips/jz4740/dma.c
20
21 --- a/arch/mips/include/asm/mach-jz4740/dma.h
22 +++ b/arch/mips/include/asm/mach-jz4740/dma.h
23 @@ -16,8 +16,6 @@
24 #ifndef __ASM_MACH_JZ4740_DMA_H__
25 #define __ASM_MACH_JZ4740_DMA_H__
26
27 -struct jz4740_dma_chan;
28 -
29 enum jz4740_dma_request_type {
30 JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
31 JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
32 @@ -33,58 +31,4 @@ enum jz4740_dma_request_type {
33 JZ4740_DMA_TYPE_SLCD = 30,
34 };
35
36 -enum jz4740_dma_width {
37 - JZ4740_DMA_WIDTH_32BIT = 0,
38 - JZ4740_DMA_WIDTH_8BIT = 1,
39 - JZ4740_DMA_WIDTH_16BIT = 2,
40 -};
41 -
42 -enum jz4740_dma_transfer_size {
43 - JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
44 - JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
45 - JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
46 - JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
47 - JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
48 -};
49 -
50 -enum jz4740_dma_flags {
51 - JZ4740_DMA_SRC_AUTOINC = 0x2,
52 - JZ4740_DMA_DST_AUTOINC = 0x1,
53 -};
54 -
55 -enum jz4740_dma_mode {
56 - JZ4740_DMA_MODE_SINGLE = 0,
57 - JZ4740_DMA_MODE_BLOCK = 1,
58 -};
59 -
60 -struct jz4740_dma_config {
61 - enum jz4740_dma_width src_width;
62 - enum jz4740_dma_width dst_width;
63 - enum jz4740_dma_transfer_size transfer_size;
64 - enum jz4740_dma_request_type request_type;
65 - enum jz4740_dma_flags flags;
66 - enum jz4740_dma_mode mode;
67 -};
68 -
69 -typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
70 -
71 -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
72 -void jz4740_dma_free(struct jz4740_dma_chan *dma);
73 -
74 -void jz4740_dma_configure(struct jz4740_dma_chan *dma,
75 - const struct jz4740_dma_config *config);
76 -
77 -
78 -void jz4740_dma_enable(struct jz4740_dma_chan *dma);
79 -void jz4740_dma_disable(struct jz4740_dma_chan *dma);
80 -
81 -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
82 -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
83 -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
84 -
85 -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
86 -
87 -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
88 - jz4740_dma_complete_callback_t cb);
89 -
90 #endif /* __ASM_JZ4740_DMA_H__ */
91 --- a/arch/mips/jz4740/Makefile
92 +++ b/arch/mips/jz4740/Makefile
93 @@ -4,7 +4,7 @@
94
95 # Object file lists.
96
97 -obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
98 +obj-y += prom.o irq.o time.o reset.o setup.o \
99 gpio.o clock.o platform.o timer.o serial.o
100
101 obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
102 --- a/arch/mips/jz4740/dma.c
103 +++ /dev/null
104 @@ -1,307 +0,0 @@
105 -/*
106 - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
107 - * JZ4740 SoC DMA support
108 - *
109 - * This program is free software; you can redistribute it and/or modify it
110 - * under the terms of the GNU General Public License as published by the
111 - * Free Software Foundation; either version 2 of the License, or (at your
112 - * option) any later version.
113 - *
114 - * You should have received a copy of the GNU General Public License along
115 - * with this program; if not, write to the Free Software Foundation, Inc.,
116 - * 675 Mass Ave, Cambridge, MA 02139, USA.
117 - *
118 - */
119 -
120 -#include <linux/kernel.h>
121 -#include <linux/module.h>
122 -#include <linux/spinlock.h>
123 -#include <linux/clk.h>
124 -#include <linux/interrupt.h>
125 -
126 -#include <linux/dma-mapping.h>
127 -#include <asm/mach-jz4740/dma.h>
128 -#include <asm/mach-jz4740/base.h>
129 -
130 -#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
131 -#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
132 -#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
133 -#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
134 -#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
135 -#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
136 -#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
137 -
138 -#define JZ_REG_DMA_CTRL 0x300
139 -#define JZ_REG_DMA_IRQ 0x304
140 -#define JZ_REG_DMA_DOORBELL 0x308
141 -#define JZ_REG_DMA_DOORBELL_SET 0x30C
142 -
143 -#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
144 -#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
145 -#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
146 -#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
147 -#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
148 -#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
149 -#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
150 -
151 -#define JZ_DMA_CMD_SRC_INC BIT(23)
152 -#define JZ_DMA_CMD_DST_INC BIT(22)
153 -#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
154 -#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
155 -#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
156 -#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
157 -#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
158 -#define JZ_DMA_CMD_DESC_VALID BIT(4)
159 -#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
160 -#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
161 -#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
162 -#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
163 -
164 -#define JZ_DMA_CMD_FLAGS_OFFSET 22
165 -#define JZ_DMA_CMD_RDIL_OFFSET 16
166 -#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
167 -#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
168 -#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
169 -#define JZ_DMA_CMD_MODE_OFFSET 7
170 -
171 -#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
172 -#define JZ_DMA_CTRL_HALT BIT(3)
173 -#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
174 -#define JZ_DMA_CTRL_ENABLE BIT(0)
175 -
176 -
177 -static void __iomem *jz4740_dma_base;
178 -static spinlock_t jz4740_dma_lock;
179 -
180 -static inline uint32_t jz4740_dma_read(size_t reg)
181 -{
182 - return readl(jz4740_dma_base + reg);
183 -}
184 -
185 -static inline void jz4740_dma_write(size_t reg, uint32_t val)
186 -{
187 - writel(val, jz4740_dma_base + reg);
188 -}
189 -
190 -static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
191 -{
192 - uint32_t val2;
193 - val2 = jz4740_dma_read(reg);
194 - val2 &= ~mask;
195 - val2 |= val;
196 - jz4740_dma_write(reg, val2);
197 -}
198 -
199 -struct jz4740_dma_chan {
200 - unsigned int id;
201 - void *dev;
202 - const char *name;
203 -
204 - enum jz4740_dma_flags flags;
205 - uint32_t transfer_shift;
206 -
207 - jz4740_dma_complete_callback_t complete_cb;
208 -
209 - unsigned used:1;
210 -};
211 -
212 -#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
213 -
214 -struct jz4740_dma_chan jz4740_dma_channels[] = {
215 - JZ4740_DMA_CHANNEL(0),
216 - JZ4740_DMA_CHANNEL(1),
217 - JZ4740_DMA_CHANNEL(2),
218 - JZ4740_DMA_CHANNEL(3),
219 - JZ4740_DMA_CHANNEL(4),
220 - JZ4740_DMA_CHANNEL(5),
221 -};
222 -
223 -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
224 -{
225 - unsigned int i;
226 - struct jz4740_dma_chan *dma = NULL;
227 -
228 - spin_lock(&jz4740_dma_lock);
229 -
230 - for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
231 - if (!jz4740_dma_channels[i].used) {
232 - dma = &jz4740_dma_channels[i];
233 - dma->used = 1;
234 - break;
235 - }
236 - }
237 -
238 - spin_unlock(&jz4740_dma_lock);
239 -
240 - if (!dma)
241 - return NULL;
242 -
243 - dma->dev = dev;
244 - dma->name = name;
245 -
246 - return dma;
247 -}
248 -EXPORT_SYMBOL_GPL(jz4740_dma_request);
249 -
250 -void jz4740_dma_configure(struct jz4740_dma_chan *dma,
251 - const struct jz4740_dma_config *config)
252 -{
253 - uint32_t cmd;
254 -
255 - switch (config->transfer_size) {
256 - case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
257 - dma->transfer_shift = 1;
258 - break;
259 - case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
260 - dma->transfer_shift = 2;
261 - break;
262 - case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
263 - dma->transfer_shift = 4;
264 - break;
265 - case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
266 - dma->transfer_shift = 5;
267 - break;
268 - default:
269 - dma->transfer_shift = 0;
270 - break;
271 - }
272 -
273 - cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
274 - cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
275 - cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
276 - cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
277 - cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
278 - cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
279 -
280 - jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
281 - jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
282 - jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
283 -}
284 -EXPORT_SYMBOL_GPL(jz4740_dma_configure);
285 -
286 -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
287 -{
288 - jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
289 -}
290 -EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
291 -
292 -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
293 -{
294 - jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
295 -}
296 -EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
297 -
298 -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
299 -{
300 - count >>= dma->transfer_shift;
301 - jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
302 -}
303 -EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
304 -
305 -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
306 - jz4740_dma_complete_callback_t cb)
307 -{
308 - dma->complete_cb = cb;
309 -}
310 -EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
311 -
312 -void jz4740_dma_free(struct jz4740_dma_chan *dma)
313 -{
314 - dma->dev = NULL;
315 - dma->complete_cb = NULL;
316 - dma->used = 0;
317 -}
318 -EXPORT_SYMBOL_GPL(jz4740_dma_free);
319 -
320 -void jz4740_dma_enable(struct jz4740_dma_chan *dma)
321 -{
322 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
323 - JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
324 - JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
325 - JZ_DMA_STATUS_CTRL_ENABLE);
326 -
327 - jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
328 - JZ_DMA_CTRL_ENABLE,
329 - JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
330 -}
331 -EXPORT_SYMBOL_GPL(jz4740_dma_enable);
332 -
333 -void jz4740_dma_disable(struct jz4740_dma_chan *dma)
334 -{
335 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
336 - JZ_DMA_STATUS_CTRL_ENABLE);
337 -}
338 -EXPORT_SYMBOL_GPL(jz4740_dma_disable);
339 -
340 -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
341 -{
342 - uint32_t residue;
343 - residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
344 - return residue << dma->transfer_shift;
345 -}
346 -EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
347 -
348 -static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
349 -{
350 - (void) jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
351 -
352 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
353 - JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
354 -
355 - if (dma->complete_cb)
356 - dma->complete_cb(dma, 0, dma->dev);
357 -}
358 -
359 -static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
360 -{
361 - uint32_t irq_status;
362 - unsigned int i;
363 -
364 - irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
365 -
366 - for (i = 0; i < 6; ++i) {
367 - if (irq_status & (1 << i))
368 - jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
369 - }
370 -
371 - return IRQ_HANDLED;
372 -}
373 -
374 -static int jz4740_dma_init(void)
375 -{
376 - struct clk *clk;
377 - unsigned int ret;
378 -
379 - jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
380 -
381 - if (!jz4740_dma_base)
382 - return -EBUSY;
383 -
384 - spin_lock_init(&jz4740_dma_lock);
385 -
386 - clk = clk_get(NULL, "dma");
387 - if (IS_ERR(clk)) {
388 - ret = PTR_ERR(clk);
389 - printk(KERN_ERR "JZ4740 DMA: Failed to request clock: %d\n",
390 - ret);
391 - goto err_iounmap;
392 - }
393 -
394 - ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
395 - if (ret) {
396 - printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
397 - goto err_clkput;
398 - }
399 -
400 - clk_enable(clk);
401 -
402 - return 0;
403 -
404 -err_clkput:
405 - clk_put(clk);
406 -
407 -err_iounmap:
408 - iounmap(jz4740_dma_base);
409 - return ret;
410 -}
411 -arch_initcall(jz4740_dma_init);
412 --- a/drivers/dma/dma-jz4740.c
413 +++ b/drivers/dma/dma-jz4740.c
414 @@ -22,6 +22,8 @@
415 #include <linux/platform_device.h>
416 #include <linux/slab.h>
417 #include <linux/spinlock.h>
418 +#include <linux/irq.h>
419 +#include <linux/clk.h>
420
421 #include <asm/mach-jz4740/dma.h>
422
423 @@ -29,6 +31,76 @@
424
425 #define JZ_DMA_NR_CHANS 6
426
427 +#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
428 +#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
429 +#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
430 +#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
431 +#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
432 +#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
433 +#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
434 +
435 +#define JZ_REG_DMA_CTRL 0x300
436 +#define JZ_REG_DMA_IRQ 0x304
437 +#define JZ_REG_DMA_DOORBELL 0x308
438 +#define JZ_REG_DMA_DOORBELL_SET 0x30C
439 +
440 +#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
441 +#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
442 +#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
443 +#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
444 +#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
445 +#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
446 +#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
447 +
448 +#define JZ_DMA_CMD_SRC_INC BIT(23)
449 +#define JZ_DMA_CMD_DST_INC BIT(22)
450 +#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
451 +#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
452 +#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
453 +#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
454 +#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
455 +#define JZ_DMA_CMD_DESC_VALID BIT(4)
456 +#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
457 +#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
458 +#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
459 +#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
460 +
461 +#define JZ_DMA_CMD_FLAGS_OFFSET 22
462 +#define JZ_DMA_CMD_RDIL_OFFSET 16
463 +#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
464 +#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
465 +#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
466 +#define JZ_DMA_CMD_MODE_OFFSET 7
467 +
468 +#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
469 +#define JZ_DMA_CTRL_HALT BIT(3)
470 +#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
471 +#define JZ_DMA_CTRL_ENABLE BIT(0)
472 +
473 +enum jz4740_dma_width {
474 + JZ4740_DMA_WIDTH_32BIT = 0,
475 + JZ4740_DMA_WIDTH_8BIT = 1,
476 + JZ4740_DMA_WIDTH_16BIT = 2,
477 +};
478 +
479 +enum jz4740_dma_transfer_size {
480 + JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
481 + JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
482 + JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
483 + JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
484 + JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
485 +};
486 +
487 +enum jz4740_dma_flags {
488 + JZ4740_DMA_SRC_AUTOINC = 0x2,
489 + JZ4740_DMA_DST_AUTOINC = 0x1,
490 +};
491 +
492 +enum jz4740_dma_mode {
493 + JZ4740_DMA_MODE_SINGLE = 0,
494 + JZ4740_DMA_MODE_BLOCK = 1,
495 +};
496 +
497 struct jz4740_dma_sg {
498 dma_addr_t addr;
499 unsigned int len;
500 @@ -46,9 +118,10 @@ struct jz4740_dma_desc {
501
502 struct jz4740_dmaengine_chan {
503 struct virt_dma_chan vchan;
504 - struct jz4740_dma_chan *jz_chan;
505 + unsigned int id;
506
507 dma_addr_t fifo_addr;
508 + unsigned int transfer_shift;
509
510 struct jz4740_dma_desc *desc;
511 unsigned int next_sg;
512 @@ -56,10 +129,19 @@ struct jz4740_dmaengine_chan {
513
514 struct jz4740_dma_dev {
515 struct dma_device ddev;
516 + void __iomem *base;
517 + struct clk *clk;
518
519 struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
520 };
521
522 +static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
523 + struct jz4740_dmaengine_chan *chan)
524 +{
525 + return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
526 + ddev);
527 +}
528 +
529 static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
530 {
531 return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
532 @@ -70,6 +152,29 @@ static struct jz4740_dma_desc *to_jz4740
533 return container_of(vdesc, struct jz4740_dma_desc, vdesc);
534 }
535
536 +static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
537 + unsigned int reg)
538 +{
539 + return readl(dmadev->base + reg);
540 +}
541 +
542 +static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
543 + unsigned reg, uint32_t val)
544 +{
545 + writel(val, dmadev->base + reg);
546 +}
547 +
548 +static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
549 + unsigned int reg, uint32_t val, uint32_t mask)
550 +{
551 + uint32_t tmp;
552 +
553 + tmp = jz4740_dma_read(dmadev, reg);
554 + tmp &= ~mask;
555 + tmp |= val;
556 + jz4740_dma_write(dmadev, reg, tmp);
557 +}
558 +
559 static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
560 {
561 return kzalloc(sizeof(struct jz4740_dma_desc) +
562 @@ -108,30 +213,60 @@ static int jz4740_dma_slave_config(struc
563 const struct dma_slave_config *config)
564 {
565 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
566 - struct jz4740_dma_config jzcfg;
567 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
568 + enum jz4740_dma_width src_width;
569 + enum jz4740_dma_width dst_width;
570 + enum jz4740_dma_transfer_size transfer_size;
571 + enum jz4740_dma_flags flags;
572 + uint32_t cmd;
573
574 switch (config->direction) {
575 case DMA_MEM_TO_DEV:
576 - jzcfg.flags = JZ4740_DMA_SRC_AUTOINC;
577 - jzcfg.transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
578 + flags = JZ4740_DMA_SRC_AUTOINC;
579 + transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
580 chan->fifo_addr = config->dst_addr;
581 break;
582 case DMA_DEV_TO_MEM:
583 - jzcfg.flags = JZ4740_DMA_DST_AUTOINC;
584 - jzcfg.transfer_size = jz4740_dma_maxburst(config->src_maxburst);
585 + flags = JZ4740_DMA_DST_AUTOINC;
586 + transfer_size = jz4740_dma_maxburst(config->src_maxburst);
587 chan->fifo_addr = config->src_addr;
588 break;
589 default:
590 return -EINVAL;
591 }
592
593 + src_width = jz4740_dma_width(config->src_addr_width);
594 + dst_width = jz4740_dma_width(config->dst_addr_width);
595
596 - jzcfg.src_width = jz4740_dma_width(config->src_addr_width);
597 - jzcfg.dst_width = jz4740_dma_width(config->dst_addr_width);
598 - jzcfg.mode = JZ4740_DMA_MODE_SINGLE;
599 - jzcfg.request_type = config->slave_id;
600 + switch (transfer_size) {
601 + case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
602 + chan->transfer_shift = 1;
603 + break;
604 + case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
605 + chan->transfer_shift = 2;
606 + break;
607 + case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
608 + chan->transfer_shift = 4;
609 + break;
610 + case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
611 + chan->transfer_shift = 5;
612 + break;
613 + default:
614 + chan->transfer_shift = 0;
615 + break;
616 + }
617
618 - jz4740_dma_configure(chan->jz_chan, &jzcfg);
619 + cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
620 + cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
621 + cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
622 + cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
623 + cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
624 + cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
625 +
626 + jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
627 + jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
628 + jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
629 + config->slave_id);
630
631 return 0;
632 }
633 @@ -139,11 +274,13 @@ static int jz4740_dma_slave_config(struc
634 static int jz4740_dma_terminate_all(struct dma_chan *c)
635 {
636 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
637 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
638 unsigned long flags;
639 LIST_HEAD(head);
640
641 spin_lock_irqsave(&chan->vchan.lock, flags);
642 - jz4740_dma_disable(chan->jz_chan);
643 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
644 + JZ_DMA_STATUS_CTRL_ENABLE);
645 chan->desc = NULL;
646 vchan_get_all_descriptors(&chan->vchan, &head);
647 spin_unlock_irqrestore(&chan->vchan.lock, flags);
648 @@ -170,11 +307,13 @@ static int jz4740_dma_control(struct dma
649
650 static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
651 {
652 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
653 dma_addr_t src_addr, dst_addr;
654 struct virt_dma_desc *vdesc;
655 struct jz4740_dma_sg *sg;
656
657 - jz4740_dma_disable(chan->jz_chan);
658 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
659 + JZ_DMA_STATUS_CTRL_ENABLE);
660
661 if (!chan->desc) {
662 vdesc = vchan_next_desc(&chan->vchan);
663 @@ -196,22 +335,27 @@ static int jz4740_dma_start_transfer(str
664 src_addr = chan->fifo_addr;
665 dst_addr = sg->addr;
666 }
667 - jz4740_dma_set_src_addr(chan->jz_chan, src_addr);
668 - jz4740_dma_set_dst_addr(chan->jz_chan, dst_addr);
669 - jz4740_dma_set_transfer_count(chan->jz_chan, sg->len);
670 + jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
671 + jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
672 + jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
673 + sg->len >> chan->transfer_shift);
674
675 chan->next_sg++;
676
677 - jz4740_dma_enable(chan->jz_chan);
678 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
679 + JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
680 + JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
681 + JZ_DMA_STATUS_CTRL_ENABLE);
682 +
683 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
684 + JZ_DMA_CTRL_ENABLE,
685 + JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
686
687 return 0;
688 }
689
690 -static void jz4740_dma_complete_cb(struct jz4740_dma_chan *jz_chan, int error,
691 - void *devid)
692 +static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
693 {
694 - struct jz4740_dmaengine_chan *chan = devid;
695 -
696 spin_lock(&chan->vchan.lock);
697 if (chan->desc) {
698 if (chan->desc && chan->desc->cyclic) {
699 @@ -227,6 +371,28 @@ static void jz4740_dma_complete_cb(struc
700 spin_unlock(&chan->vchan.lock);
701 }
702
703 +static irqreturn_t jz4740_dma_irq(int irq, void *devid)
704 +{
705 + struct jz4740_dma_dev *dmadev = devid;
706 + uint32_t irq_status;
707 + unsigned int i;
708 +
709 + irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
710 +
711 + for (i = 0; i < 6; ++i) {
712 + if (irq_status & (1 << i)) {
713 + jz4740_dma_write_mask(dmadev,
714 + JZ_REG_DMA_STATUS_CTRL(i), 0,
715 + JZ_DMA_STATUS_CTRL_ENABLE |
716 + JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
717 +
718 + jz4740_dma_chan_irq(&dmadev->chan[i]);
719 + }
720 + }
721 +
722 + return IRQ_HANDLED;
723 +}
724 +
725 static void jz4740_dma_issue_pending(struct dma_chan *c)
726 {
727 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
728 @@ -298,7 +464,8 @@ static struct dma_async_tx_descriptor *j
729 static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
730 struct jz4740_dma_desc *desc, unsigned int next_sg)
731 {
732 - size_t residue = 0;
733 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
734 + unsigned int residue, count;
735 unsigned int i;
736
737 residue = 0;
738 @@ -306,8 +473,11 @@ static size_t jz4740_dma_desc_residue(st
739 for (i = next_sg; i < desc->num_sgs; i++)
740 residue += desc->sg[i].len;
741
742 - if (next_sg != 0)
743 - residue += jz4740_dma_get_residue(chan->jz_chan);
744 + if (next_sg != 0) {
745 + count = jz4740_dma_read(dmadev,
746 + JZ_REG_DMA_TRANSFER_COUNT(chan->id));
747 + residue += count << chan->transfer_shift;
748 + }
749
750 return residue;
751 }
752 @@ -342,24 +512,12 @@ static enum dma_status jz4740_dma_tx_sta
753
754 static int jz4740_dma_alloc_chan_resources(struct dma_chan *c)
755 {
756 - struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
757 -
758 - chan->jz_chan = jz4740_dma_request(chan, NULL);
759 - if (!chan->jz_chan)
760 - return -EBUSY;
761 -
762 - jz4740_dma_set_complete_cb(chan->jz_chan, jz4740_dma_complete_cb);
763 -
764 return 0;
765 }
766
767 static void jz4740_dma_free_chan_resources(struct dma_chan *c)
768 {
769 - struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
770 -
771 - vchan_free_chan_resources(&chan->vchan);
772 - jz4740_dma_free(chan->jz_chan);
773 - chan->jz_chan = NULL;
774 + vchan_free_chan_resources(to_virt_chan(c));
775 }
776
777 static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
778 @@ -373,7 +531,9 @@ static int jz4740_dma_probe(struct platf
779 struct jz4740_dma_dev *dmadev;
780 struct dma_device *dd;
781 unsigned int i;
782 + struct resource *res;
783 int ret;
784 + int irq;
785
786 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
787 if (!dmadev)
788 @@ -381,6 +541,17 @@ static int jz4740_dma_probe(struct platf
789
790 dd = &dmadev->ddev;
791
792 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
793 + dmadev->base = devm_ioremap_resource(&pdev->dev, res);
794 + if (IS_ERR(dmadev->base))
795 + return PTR_ERR(dmadev->base);
796 +
797 + dmadev->clk = clk_get(&pdev->dev, "dma");
798 + if (IS_ERR(dmadev->clk))
799 + return PTR_ERR(dmadev->clk);
800 +
801 + clk_prepare_enable(dmadev->clk);
802 +
803 dma_cap_set(DMA_SLAVE, dd->cap_mask);
804 dma_cap_set(DMA_CYCLIC, dd->cap_mask);
805 dd->device_alloc_chan_resources = jz4740_dma_alloc_chan_resources;
806 @@ -396,6 +567,7 @@ static int jz4740_dma_probe(struct platf
807
808 for (i = 0; i < dd->chancnt; i++) {
809 chan = &dmadev->chan[i];
810 + chan->id = i;
811 chan->vchan.desc_free = jz4740_dma_desc_free;
812 vchan_init(&chan->vchan, dd);
813 }
814 @@ -404,16 +576,28 @@ static int jz4740_dma_probe(struct platf
815 if (ret)
816 return ret;
817
818 + irq = platform_get_irq(pdev, 0);
819 + ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
820 + if (ret)
821 + goto err_unregister;
822 +
823 platform_set_drvdata(pdev, dmadev);
824
825 return 0;
826 +
827 +err_unregister:
828 + dma_async_device_unregister(dd);
829 + return ret;
830 }
831
832 static int jz4740_dma_remove(struct platform_device *pdev)
833 {
834 struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
835 + int irq = platform_get_irq(pdev, 0);
836
837 + free_irq(irq, dmadev);
838 dma_async_device_unregister(&dmadev->ddev);
839 + clk_disable_unprepare(dmadev->clk);
840
841 return 0;
842 }
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