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[openwrt/staging/chunkeey.git] / target / linux / xburst / patches-3.10 / 015-MIPS-jz4740-Remove-custom-DMA-API.patch
1 From 7b91fca454e66ac1bc1fe5b68de0bf55f799bd41 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Thu, 30 May 2013 18:25:05 +0200
4 Subject: [PATCH 15/16] MIPS: jz4740: Remove custom DMA API
5
6 Now that all users of the custom jz4740 DMA API have been converted to use
7 the dmaengine API instead we can remove the custom API and move all the code
8 talking to the hardware to the dmaengine driver.
9
10 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
11 Acked-by: Ralf Baechle <ralf@linux-mips.org>
12 Signed-off-by: Vinod Koul <vinod.koul@intel.com>
13 ---
14 arch/mips/include/asm/mach-jz4740/dma.h | 56 ------
15 arch/mips/jz4740/Makefile | 2 +-
16 arch/mips/jz4740/dma.c | 307 -------------------------------
17 drivers/dma/dma-jz4740.c | 258 ++++++++++++++++++++++----
18 4 files changed, 222 insertions(+), 401 deletions(-)
19 delete mode 100644 arch/mips/jz4740/dma.c
20
21 diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
22 index 98b4e7c..509cd58 100644
23 --- a/arch/mips/include/asm/mach-jz4740/dma.h
24 +++ b/arch/mips/include/asm/mach-jz4740/dma.h
25 @@ -16,8 +16,6 @@
26 #ifndef __ASM_MACH_JZ4740_DMA_H__
27 #define __ASM_MACH_JZ4740_DMA_H__
28
29 -struct jz4740_dma_chan;
30 -
31 enum jz4740_dma_request_type {
32 JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
33 JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
34 @@ -33,58 +31,4 @@ enum jz4740_dma_request_type {
35 JZ4740_DMA_TYPE_SLCD = 30,
36 };
37
38 -enum jz4740_dma_width {
39 - JZ4740_DMA_WIDTH_32BIT = 0,
40 - JZ4740_DMA_WIDTH_8BIT = 1,
41 - JZ4740_DMA_WIDTH_16BIT = 2,
42 -};
43 -
44 -enum jz4740_dma_transfer_size {
45 - JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
46 - JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
47 - JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
48 - JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
49 - JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
50 -};
51 -
52 -enum jz4740_dma_flags {
53 - JZ4740_DMA_SRC_AUTOINC = 0x2,
54 - JZ4740_DMA_DST_AUTOINC = 0x1,
55 -};
56 -
57 -enum jz4740_dma_mode {
58 - JZ4740_DMA_MODE_SINGLE = 0,
59 - JZ4740_DMA_MODE_BLOCK = 1,
60 -};
61 -
62 -struct jz4740_dma_config {
63 - enum jz4740_dma_width src_width;
64 - enum jz4740_dma_width dst_width;
65 - enum jz4740_dma_transfer_size transfer_size;
66 - enum jz4740_dma_request_type request_type;
67 - enum jz4740_dma_flags flags;
68 - enum jz4740_dma_mode mode;
69 -};
70 -
71 -typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
72 -
73 -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
74 -void jz4740_dma_free(struct jz4740_dma_chan *dma);
75 -
76 -void jz4740_dma_configure(struct jz4740_dma_chan *dma,
77 - const struct jz4740_dma_config *config);
78 -
79 -
80 -void jz4740_dma_enable(struct jz4740_dma_chan *dma);
81 -void jz4740_dma_disable(struct jz4740_dma_chan *dma);
82 -
83 -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
84 -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
85 -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
86 -
87 -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
88 -
89 -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
90 - jz4740_dma_complete_callback_t cb);
91 -
92 #endif /* __ASM_JZ4740_DMA_H__ */
93 diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
94 index 63bad0e..28e5535 100644
95 --- a/arch/mips/jz4740/Makefile
96 +++ b/arch/mips/jz4740/Makefile
97 @@ -4,7 +4,7 @@
98
99 # Object file lists.
100
101 -obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
102 +obj-y += prom.o irq.o time.o reset.o setup.o \
103 gpio.o clock.o platform.o timer.o serial.o
104
105 obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
106 diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
107 deleted file mode 100644
108 index fb5266c..0000000
109 --- a/arch/mips/jz4740/dma.c
110 +++ /dev/null
111 @@ -1,307 +0,0 @@
112 -/*
113 - * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
114 - * JZ4740 SoC DMA support
115 - *
116 - * This program is free software; you can redistribute it and/or modify it
117 - * under the terms of the GNU General Public License as published by the
118 - * Free Software Foundation; either version 2 of the License, or (at your
119 - * option) any later version.
120 - *
121 - * You should have received a copy of the GNU General Public License along
122 - * with this program; if not, write to the Free Software Foundation, Inc.,
123 - * 675 Mass Ave, Cambridge, MA 02139, USA.
124 - *
125 - */
126 -
127 -#include <linux/kernel.h>
128 -#include <linux/module.h>
129 -#include <linux/spinlock.h>
130 -#include <linux/clk.h>
131 -#include <linux/interrupt.h>
132 -
133 -#include <linux/dma-mapping.h>
134 -#include <asm/mach-jz4740/dma.h>
135 -#include <asm/mach-jz4740/base.h>
136 -
137 -#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
138 -#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
139 -#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
140 -#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
141 -#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
142 -#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
143 -#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
144 -
145 -#define JZ_REG_DMA_CTRL 0x300
146 -#define JZ_REG_DMA_IRQ 0x304
147 -#define JZ_REG_DMA_DOORBELL 0x308
148 -#define JZ_REG_DMA_DOORBELL_SET 0x30C
149 -
150 -#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
151 -#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
152 -#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
153 -#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
154 -#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
155 -#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
156 -#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
157 -
158 -#define JZ_DMA_CMD_SRC_INC BIT(23)
159 -#define JZ_DMA_CMD_DST_INC BIT(22)
160 -#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
161 -#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
162 -#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
163 -#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
164 -#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
165 -#define JZ_DMA_CMD_DESC_VALID BIT(4)
166 -#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
167 -#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
168 -#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
169 -#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
170 -
171 -#define JZ_DMA_CMD_FLAGS_OFFSET 22
172 -#define JZ_DMA_CMD_RDIL_OFFSET 16
173 -#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
174 -#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
175 -#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
176 -#define JZ_DMA_CMD_MODE_OFFSET 7
177 -
178 -#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
179 -#define JZ_DMA_CTRL_HALT BIT(3)
180 -#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
181 -#define JZ_DMA_CTRL_ENABLE BIT(0)
182 -
183 -
184 -static void __iomem *jz4740_dma_base;
185 -static spinlock_t jz4740_dma_lock;
186 -
187 -static inline uint32_t jz4740_dma_read(size_t reg)
188 -{
189 - return readl(jz4740_dma_base + reg);
190 -}
191 -
192 -static inline void jz4740_dma_write(size_t reg, uint32_t val)
193 -{
194 - writel(val, jz4740_dma_base + reg);
195 -}
196 -
197 -static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
198 -{
199 - uint32_t val2;
200 - val2 = jz4740_dma_read(reg);
201 - val2 &= ~mask;
202 - val2 |= val;
203 - jz4740_dma_write(reg, val2);
204 -}
205 -
206 -struct jz4740_dma_chan {
207 - unsigned int id;
208 - void *dev;
209 - const char *name;
210 -
211 - enum jz4740_dma_flags flags;
212 - uint32_t transfer_shift;
213 -
214 - jz4740_dma_complete_callback_t complete_cb;
215 -
216 - unsigned used:1;
217 -};
218 -
219 -#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
220 -
221 -struct jz4740_dma_chan jz4740_dma_channels[] = {
222 - JZ4740_DMA_CHANNEL(0),
223 - JZ4740_DMA_CHANNEL(1),
224 - JZ4740_DMA_CHANNEL(2),
225 - JZ4740_DMA_CHANNEL(3),
226 - JZ4740_DMA_CHANNEL(4),
227 - JZ4740_DMA_CHANNEL(5),
228 -};
229 -
230 -struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
231 -{
232 - unsigned int i;
233 - struct jz4740_dma_chan *dma = NULL;
234 -
235 - spin_lock(&jz4740_dma_lock);
236 -
237 - for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
238 - if (!jz4740_dma_channels[i].used) {
239 - dma = &jz4740_dma_channels[i];
240 - dma->used = 1;
241 - break;
242 - }
243 - }
244 -
245 - spin_unlock(&jz4740_dma_lock);
246 -
247 - if (!dma)
248 - return NULL;
249 -
250 - dma->dev = dev;
251 - dma->name = name;
252 -
253 - return dma;
254 -}
255 -EXPORT_SYMBOL_GPL(jz4740_dma_request);
256 -
257 -void jz4740_dma_configure(struct jz4740_dma_chan *dma,
258 - const struct jz4740_dma_config *config)
259 -{
260 - uint32_t cmd;
261 -
262 - switch (config->transfer_size) {
263 - case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
264 - dma->transfer_shift = 1;
265 - break;
266 - case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
267 - dma->transfer_shift = 2;
268 - break;
269 - case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
270 - dma->transfer_shift = 4;
271 - break;
272 - case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
273 - dma->transfer_shift = 5;
274 - break;
275 - default:
276 - dma->transfer_shift = 0;
277 - break;
278 - }
279 -
280 - cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
281 - cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
282 - cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
283 - cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
284 - cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
285 - cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
286 -
287 - jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
288 - jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
289 - jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
290 -}
291 -EXPORT_SYMBOL_GPL(jz4740_dma_configure);
292 -
293 -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
294 -{
295 - jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
296 -}
297 -EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
298 -
299 -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
300 -{
301 - jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
302 -}
303 -EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
304 -
305 -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
306 -{
307 - count >>= dma->transfer_shift;
308 - jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
309 -}
310 -EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
311 -
312 -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
313 - jz4740_dma_complete_callback_t cb)
314 -{
315 - dma->complete_cb = cb;
316 -}
317 -EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
318 -
319 -void jz4740_dma_free(struct jz4740_dma_chan *dma)
320 -{
321 - dma->dev = NULL;
322 - dma->complete_cb = NULL;
323 - dma->used = 0;
324 -}
325 -EXPORT_SYMBOL_GPL(jz4740_dma_free);
326 -
327 -void jz4740_dma_enable(struct jz4740_dma_chan *dma)
328 -{
329 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
330 - JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
331 - JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
332 - JZ_DMA_STATUS_CTRL_ENABLE);
333 -
334 - jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
335 - JZ_DMA_CTRL_ENABLE,
336 - JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
337 -}
338 -EXPORT_SYMBOL_GPL(jz4740_dma_enable);
339 -
340 -void jz4740_dma_disable(struct jz4740_dma_chan *dma)
341 -{
342 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
343 - JZ_DMA_STATUS_CTRL_ENABLE);
344 -}
345 -EXPORT_SYMBOL_GPL(jz4740_dma_disable);
346 -
347 -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
348 -{
349 - uint32_t residue;
350 - residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
351 - return residue << dma->transfer_shift;
352 -}
353 -EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
354 -
355 -static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
356 -{
357 - (void) jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
358 -
359 - jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
360 - JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
361 -
362 - if (dma->complete_cb)
363 - dma->complete_cb(dma, 0, dma->dev);
364 -}
365 -
366 -static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
367 -{
368 - uint32_t irq_status;
369 - unsigned int i;
370 -
371 - irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
372 -
373 - for (i = 0; i < 6; ++i) {
374 - if (irq_status & (1 << i))
375 - jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
376 - }
377 -
378 - return IRQ_HANDLED;
379 -}
380 -
381 -static int jz4740_dma_init(void)
382 -{
383 - struct clk *clk;
384 - unsigned int ret;
385 -
386 - jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
387 -
388 - if (!jz4740_dma_base)
389 - return -EBUSY;
390 -
391 - spin_lock_init(&jz4740_dma_lock);
392 -
393 - clk = clk_get(NULL, "dma");
394 - if (IS_ERR(clk)) {
395 - ret = PTR_ERR(clk);
396 - printk(KERN_ERR "JZ4740 DMA: Failed to request clock: %d\n",
397 - ret);
398 - goto err_iounmap;
399 - }
400 -
401 - ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
402 - if (ret) {
403 - printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
404 - goto err_clkput;
405 - }
406 -
407 - clk_enable(clk);
408 -
409 - return 0;
410 -
411 -err_clkput:
412 - clk_put(clk);
413 -
414 -err_iounmap:
415 - iounmap(jz4740_dma_base);
416 - return ret;
417 -}
418 -arch_initcall(jz4740_dma_init);
419 diff --git a/drivers/dma/dma-jz4740.c b/drivers/dma/dma-jz4740.c
420 index 3d42434..b0c0c82 100644
421 --- a/drivers/dma/dma-jz4740.c
422 +++ b/drivers/dma/dma-jz4740.c
423 @@ -22,6 +22,8 @@
424 #include <linux/platform_device.h>
425 #include <linux/slab.h>
426 #include <linux/spinlock.h>
427 +#include <linux/irq.h>
428 +#include <linux/clk.h>
429
430 #include <asm/mach-jz4740/dma.h>
431
432 @@ -29,6 +31,76 @@
433
434 #define JZ_DMA_NR_CHANS 6
435
436 +#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
437 +#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
438 +#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
439 +#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
440 +#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
441 +#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
442 +#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
443 +
444 +#define JZ_REG_DMA_CTRL 0x300
445 +#define JZ_REG_DMA_IRQ 0x304
446 +#define JZ_REG_DMA_DOORBELL 0x308
447 +#define JZ_REG_DMA_DOORBELL_SET 0x30C
448 +
449 +#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
450 +#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
451 +#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
452 +#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
453 +#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
454 +#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
455 +#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
456 +
457 +#define JZ_DMA_CMD_SRC_INC BIT(23)
458 +#define JZ_DMA_CMD_DST_INC BIT(22)
459 +#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
460 +#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
461 +#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
462 +#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
463 +#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
464 +#define JZ_DMA_CMD_DESC_VALID BIT(4)
465 +#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
466 +#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
467 +#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
468 +#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
469 +
470 +#define JZ_DMA_CMD_FLAGS_OFFSET 22
471 +#define JZ_DMA_CMD_RDIL_OFFSET 16
472 +#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
473 +#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
474 +#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
475 +#define JZ_DMA_CMD_MODE_OFFSET 7
476 +
477 +#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
478 +#define JZ_DMA_CTRL_HALT BIT(3)
479 +#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
480 +#define JZ_DMA_CTRL_ENABLE BIT(0)
481 +
482 +enum jz4740_dma_width {
483 + JZ4740_DMA_WIDTH_32BIT = 0,
484 + JZ4740_DMA_WIDTH_8BIT = 1,
485 + JZ4740_DMA_WIDTH_16BIT = 2,
486 +};
487 +
488 +enum jz4740_dma_transfer_size {
489 + JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
490 + JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
491 + JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
492 + JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
493 + JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
494 +};
495 +
496 +enum jz4740_dma_flags {
497 + JZ4740_DMA_SRC_AUTOINC = 0x2,
498 + JZ4740_DMA_DST_AUTOINC = 0x1,
499 +};
500 +
501 +enum jz4740_dma_mode {
502 + JZ4740_DMA_MODE_SINGLE = 0,
503 + JZ4740_DMA_MODE_BLOCK = 1,
504 +};
505 +
506 struct jz4740_dma_sg {
507 dma_addr_t addr;
508 unsigned int len;
509 @@ -46,9 +118,10 @@ struct jz4740_dma_desc {
510
511 struct jz4740_dmaengine_chan {
512 struct virt_dma_chan vchan;
513 - struct jz4740_dma_chan *jz_chan;
514 + unsigned int id;
515
516 dma_addr_t fifo_addr;
517 + unsigned int transfer_shift;
518
519 struct jz4740_dma_desc *desc;
520 unsigned int next_sg;
521 @@ -56,10 +129,19 @@ struct jz4740_dmaengine_chan {
522
523 struct jz4740_dma_dev {
524 struct dma_device ddev;
525 + void __iomem *base;
526 + struct clk *clk;
527
528 struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
529 };
530
531 +static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
532 + struct jz4740_dmaengine_chan *chan)
533 +{
534 + return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
535 + ddev);
536 +}
537 +
538 static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
539 {
540 return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
541 @@ -70,6 +152,29 @@ static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
542 return container_of(vdesc, struct jz4740_dma_desc, vdesc);
543 }
544
545 +static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
546 + unsigned int reg)
547 +{
548 + return readl(dmadev->base + reg);
549 +}
550 +
551 +static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
552 + unsigned reg, uint32_t val)
553 +{
554 + writel(val, dmadev->base + reg);
555 +}
556 +
557 +static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
558 + unsigned int reg, uint32_t val, uint32_t mask)
559 +{
560 + uint32_t tmp;
561 +
562 + tmp = jz4740_dma_read(dmadev, reg);
563 + tmp &= ~mask;
564 + tmp |= val;
565 + jz4740_dma_write(dmadev, reg, tmp);
566 +}
567 +
568 static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
569 {
570 return kzalloc(sizeof(struct jz4740_dma_desc) +
571 @@ -108,30 +213,60 @@ static int jz4740_dma_slave_config(struct dma_chan *c,
572 const struct dma_slave_config *config)
573 {
574 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
575 - struct jz4740_dma_config jzcfg;
576 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
577 + enum jz4740_dma_width src_width;
578 + enum jz4740_dma_width dst_width;
579 + enum jz4740_dma_transfer_size transfer_size;
580 + enum jz4740_dma_flags flags;
581 + uint32_t cmd;
582
583 switch (config->direction) {
584 case DMA_MEM_TO_DEV:
585 - jzcfg.flags = JZ4740_DMA_SRC_AUTOINC;
586 - jzcfg.transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
587 + flags = JZ4740_DMA_SRC_AUTOINC;
588 + transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
589 chan->fifo_addr = config->dst_addr;
590 break;
591 case DMA_DEV_TO_MEM:
592 - jzcfg.flags = JZ4740_DMA_DST_AUTOINC;
593 - jzcfg.transfer_size = jz4740_dma_maxburst(config->src_maxburst);
594 + flags = JZ4740_DMA_DST_AUTOINC;
595 + transfer_size = jz4740_dma_maxburst(config->src_maxburst);
596 chan->fifo_addr = config->src_addr;
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 + src_width = jz4740_dma_width(config->src_addr_width);
603 + dst_width = jz4740_dma_width(config->dst_addr_width);
604 +
605 + switch (transfer_size) {
606 + case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
607 + chan->transfer_shift = 1;
608 + break;
609 + case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
610 + chan->transfer_shift = 2;
611 + break;
612 + case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
613 + chan->transfer_shift = 4;
614 + break;
615 + case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
616 + chan->transfer_shift = 5;
617 + break;
618 + default:
619 + chan->transfer_shift = 0;
620 + break;
621 + }
622
623 - jzcfg.src_width = jz4740_dma_width(config->src_addr_width);
624 - jzcfg.dst_width = jz4740_dma_width(config->dst_addr_width);
625 - jzcfg.mode = JZ4740_DMA_MODE_SINGLE;
626 - jzcfg.request_type = config->slave_id;
627 + cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
628 + cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
629 + cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
630 + cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
631 + cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
632 + cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
633
634 - jz4740_dma_configure(chan->jz_chan, &jzcfg);
635 + jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
636 + jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
637 + jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
638 + config->slave_id);
639
640 return 0;
641 }
642 @@ -139,11 +274,13 @@ static int jz4740_dma_slave_config(struct dma_chan *c,
643 static int jz4740_dma_terminate_all(struct dma_chan *c)
644 {
645 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
646 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
647 unsigned long flags;
648 LIST_HEAD(head);
649
650 spin_lock_irqsave(&chan->vchan.lock, flags);
651 - jz4740_dma_disable(chan->jz_chan);
652 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
653 + JZ_DMA_STATUS_CTRL_ENABLE);
654 chan->desc = NULL;
655 vchan_get_all_descriptors(&chan->vchan, &head);
656 spin_unlock_irqrestore(&chan->vchan.lock, flags);
657 @@ -170,11 +307,13 @@ static int jz4740_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
658
659 static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
660 {
661 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
662 dma_addr_t src_addr, dst_addr;
663 struct virt_dma_desc *vdesc;
664 struct jz4740_dma_sg *sg;
665
666 - jz4740_dma_disable(chan->jz_chan);
667 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
668 + JZ_DMA_STATUS_CTRL_ENABLE);
669
670 if (!chan->desc) {
671 vdesc = vchan_next_desc(&chan->vchan);
672 @@ -196,22 +335,27 @@ static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
673 src_addr = chan->fifo_addr;
674 dst_addr = sg->addr;
675 }
676 - jz4740_dma_set_src_addr(chan->jz_chan, src_addr);
677 - jz4740_dma_set_dst_addr(chan->jz_chan, dst_addr);
678 - jz4740_dma_set_transfer_count(chan->jz_chan, sg->len);
679 + jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
680 + jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
681 + jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
682 + sg->len >> chan->transfer_shift);
683
684 chan->next_sg++;
685
686 - jz4740_dma_enable(chan->jz_chan);
687 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
688 + JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
689 + JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
690 + JZ_DMA_STATUS_CTRL_ENABLE);
691 +
692 + jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
693 + JZ_DMA_CTRL_ENABLE,
694 + JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
695
696 return 0;
697 }
698
699 -static void jz4740_dma_complete_cb(struct jz4740_dma_chan *jz_chan, int error,
700 - void *devid)
701 +static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
702 {
703 - struct jz4740_dmaengine_chan *chan = devid;
704 -
705 spin_lock(&chan->vchan.lock);
706 if (chan->desc) {
707 if (chan->desc && chan->desc->cyclic) {
708 @@ -227,6 +371,28 @@ static void jz4740_dma_complete_cb(struct jz4740_dma_chan *jz_chan, int error,
709 spin_unlock(&chan->vchan.lock);
710 }
711
712 +static irqreturn_t jz4740_dma_irq(int irq, void *devid)
713 +{
714 + struct jz4740_dma_dev *dmadev = devid;
715 + uint32_t irq_status;
716 + unsigned int i;
717 +
718 + irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
719 +
720 + for (i = 0; i < 6; ++i) {
721 + if (irq_status & (1 << i)) {
722 + jz4740_dma_write_mask(dmadev,
723 + JZ_REG_DMA_STATUS_CTRL(i), 0,
724 + JZ_DMA_STATUS_CTRL_ENABLE |
725 + JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
726 +
727 + jz4740_dma_chan_irq(&dmadev->chan[i]);
728 + }
729 + }
730 +
731 + return IRQ_HANDLED;
732 +}
733 +
734 static void jz4740_dma_issue_pending(struct dma_chan *c)
735 {
736 struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
737 @@ -298,7 +464,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
738 static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
739 struct jz4740_dma_desc *desc, unsigned int next_sg)
740 {
741 - size_t residue = 0;
742 + struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
743 + unsigned int residue, count;
744 unsigned int i;
745
746 residue = 0;
747 @@ -306,8 +473,11 @@ static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
748 for (i = next_sg; i < desc->num_sgs; i++)
749 residue += desc->sg[i].len;
750
751 - if (next_sg != 0)
752 - residue += jz4740_dma_get_residue(chan->jz_chan);
753 + if (next_sg != 0) {
754 + count = jz4740_dma_read(dmadev,
755 + JZ_REG_DMA_TRANSFER_COUNT(chan->id));
756 + residue += count << chan->transfer_shift;
757 + }
758
759 return residue;
760 }
761 @@ -342,24 +512,12 @@ static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
762
763 static int jz4740_dma_alloc_chan_resources(struct dma_chan *c)
764 {
765 - struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
766 -
767 - chan->jz_chan = jz4740_dma_request(chan, NULL);
768 - if (!chan->jz_chan)
769 - return -EBUSY;
770 -
771 - jz4740_dma_set_complete_cb(chan->jz_chan, jz4740_dma_complete_cb);
772 -
773 return 0;
774 }
775
776 static void jz4740_dma_free_chan_resources(struct dma_chan *c)
777 {
778 - struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
779 -
780 - vchan_free_chan_resources(&chan->vchan);
781 - jz4740_dma_free(chan->jz_chan);
782 - chan->jz_chan = NULL;
783 + vchan_free_chan_resources(to_virt_chan(c));
784 }
785
786 static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
787 @@ -373,7 +531,9 @@ static int jz4740_dma_probe(struct platform_device *pdev)
788 struct jz4740_dma_dev *dmadev;
789 struct dma_device *dd;
790 unsigned int i;
791 + struct resource *res;
792 int ret;
793 + int irq;
794
795 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
796 if (!dmadev)
797 @@ -381,6 +541,17 @@ static int jz4740_dma_probe(struct platform_device *pdev)
798
799 dd = &dmadev->ddev;
800
801 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
802 + dmadev->base = devm_ioremap_resource(&pdev->dev, res);
803 + if (IS_ERR(dmadev->base))
804 + return PTR_ERR(dmadev->base);
805 +
806 + dmadev->clk = clk_get(&pdev->dev, "dma");
807 + if (IS_ERR(dmadev->clk))
808 + return PTR_ERR(dmadev->clk);
809 +
810 + clk_prepare_enable(dmadev->clk);
811 +
812 dma_cap_set(DMA_SLAVE, dd->cap_mask);
813 dma_cap_set(DMA_CYCLIC, dd->cap_mask);
814 dd->device_alloc_chan_resources = jz4740_dma_alloc_chan_resources;
815 @@ -396,6 +567,7 @@ static int jz4740_dma_probe(struct platform_device *pdev)
816
817 for (i = 0; i < dd->chancnt; i++) {
818 chan = &dmadev->chan[i];
819 + chan->id = i;
820 chan->vchan.desc_free = jz4740_dma_desc_free;
821 vchan_init(&chan->vchan, dd);
822 }
823 @@ -404,16 +576,28 @@ static int jz4740_dma_probe(struct platform_device *pdev)
824 if (ret)
825 return ret;
826
827 + irq = platform_get_irq(pdev, 0);
828 + ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
829 + if (ret)
830 + goto err_unregister;
831 +
832 platform_set_drvdata(pdev, dmadev);
833
834 return 0;
835 +
836 +err_unregister:
837 + dma_async_device_unregister(dd);
838 + return ret;
839 }
840
841 static int jz4740_dma_remove(struct platform_device *pdev)
842 {
843 struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
844 + int irq = platform_get_irq(pdev, 0);
845
846 + free_irq(irq, dmadev);
847 dma_async_device_unregister(&dmadev->ddev);
848 + clk_disable_unprepare(dmadev->clk);
849
850 return 0;
851 }
852 --
853 1.7.10.4
854
Staging tree of Christian Lamparter