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integrate the newer broadcom wl driver from us robotics
[openwrt/staging/dedeckeh.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -Naur linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-06 15:38:09.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-06 15:34:15.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -Naur linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-04-06 15:34:14.000000000 +0200
35 @@ -0,0 +1,15 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := nvram_linux.o setup.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -Naur linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
52 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-06 15:34:14.000000000 +0200
54 @@ -0,0 +1,234 @@
55 +/*
56 + * NVRAM variable manipulation (Linux kernel half)
57 + *
58 + * Copyright 2001-2003, Broadcom Corporation
59 + * All Rights Reserved.
60 + *
61 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
62 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
63 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
64 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
65 + *
66 + * $Id$
67 + */
68 +
69 +#include <linux/config.h>
70 +#include <linux/init.h>
71 +#include <linux/module.h>
72 +#include <linux/kernel.h>
73 +#include <linux/string.h>
74 +#include <asm/io.h>
75 +#include <asm/uaccess.h>
76 +
77 +#include <typedefs.h>
78 +#include <osl.h>
79 +#include <bcmendian.h>
80 +#include <bcmutils.h>
81 +
82 +#define NVRAM_SIZE (0x1ff0)
83 +static char _nvdata[NVRAM_SIZE] __initdata;
84 +static char _valuestr[256] __initdata;
85 +
86 +/*
87 + * TLV types. These codes are used in the "type-length-value"
88 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
89 + *
90 + * The layout of the flash/nvram is as follows:
91 + *
92 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
93 + *
94 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
95 + * The "length" field marks the length of the data section, not
96 + * including the type and length fields.
97 + *
98 + * Environment variables are stored as follows:
99 + *
100 + * <type_env> <length> <flags> <name> = <value>
101 + *
102 + * If bit 0 (low bit) is set, the length is an 8-bit value.
103 + * If bit 0 (low bit) is clear, the length is a 16-bit value
104 + *
105 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
106 + * indicates the size of the length field.
107 + *
108 + * Flags are from the constants below:
109 + *
110 + */
111 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
112 +#define ENV_LENGTH_8BITS 0x01
113 +
114 +#define ENV_TYPE_USER 0x80
115 +
116 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
117 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
118 +
119 +/*
120 + * The actual TLV types we support
121 + */
122 +
123 +#define ENV_TLV_TYPE_END 0x00
124 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
125 +
126 +/*
127 + * Environment variable flags
128 + */
129 +
130 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
131 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
132 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
133 +
134 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
135 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
136 +
137 +
138 +/* *********************************************************************
139 + * _nvram_read(buffer,offset,length)
140 + *
141 + * Read data from the NVRAM device
142 + *
143 + * Input parameters:
144 + * buffer - destination buffer
145 + * offset - offset of data to read
146 + * length - number of bytes to read
147 + *
148 + * Return value:
149 + * number of bytes read, or <0 if error occured
150 + ********************************************************************* */
151 +static int
152 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
153 +{
154 + int i;
155 + if (offset > NVRAM_SIZE)
156 + return -1;
157 +
158 + for ( i = 0; i < length; i++) {
159 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
160 + }
161 + return length;
162 +}
163 +
164 +
165 +static char*
166 +_strnchr(const char *dest,int c,size_t cnt)
167 +{
168 + while (*dest && (cnt > 0)) {
169 + if (*dest == c) return (char *) dest;
170 + dest++;
171 + cnt--;
172 + }
173 + return NULL;
174 +}
175 +
176 +
177 +
178 +/*
179 + * Core support API: Externally visible.
180 + */
181 +
182 +/*
183 + * Get the value of an NVRAM variable
184 + * @param name name of variable to get
185 + * @return value of variable or NULL if undefined
186 + */
187 +
188 +char*
189 +cfe_env_get(unsigned char *nv_buf, char* name)
190 +{
191 + int size;
192 + unsigned char *buffer;
193 + unsigned char *ptr;
194 + unsigned char *envval;
195 + unsigned int reclen;
196 + unsigned int rectype;
197 + int offset;
198 + int flg;
199 +
200 + size = NVRAM_SIZE;
201 + buffer = &_nvdata[0];
202 +
203 + ptr = buffer;
204 + offset = 0;
205 +
206 + /* Read the record type and length */
207 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
208 + goto error;
209 + }
210 +
211 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
212 +
213 + /* Adjust pointer for TLV type */
214 + rectype = *(ptr);
215 + offset++;
216 + size--;
217 +
218 + /*
219 + * Read the length. It can be either 1 or 2 bytes
220 + * depending on the code
221 + */
222 + if (rectype & ENV_LENGTH_8BITS) {
223 + /* Read the record type and length - 8 bits */
224 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
225 + goto error;
226 + }
227 + reclen = *(ptr);
228 + size--;
229 + offset++;
230 + }
231 + else {
232 + /* Read the record type and length - 16 bits, MSB first */
233 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
234 + goto error;
235 + }
236 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
237 + size -= 2;
238 + offset += 2;
239 + }
240 +
241 + if (reclen > size)
242 + break; /* should not happen, bad NVRAM */
243 +
244 + switch (rectype) {
245 + case ENV_TLV_TYPE_ENV:
246 + /* Read the TLV data */
247 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
248 + goto error;
249 + flg = *ptr++;
250 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
251 + if (envval) {
252 + *envval++ = '\0';
253 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
254 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
255 +#if 0
256 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
257 +#endif
258 + if(!strcmp(ptr, name)){
259 + return _valuestr;
260 + }
261 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
262 + return _valuestr;
263 + }
264 + break;
265 +
266 + default:
267 + /* Unknown TLV type, skip it. */
268 + break;
269 + }
270 +
271 + /*
272 + * Advance to next TLV
273 + */
274 +
275 + size -= (int)reclen;
276 + offset += reclen;
277 +
278 + /* Read the next record type */
279 + ptr = buffer;
280 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
281 + goto error;
282 + }
283 +
284 +error:
285 + return NULL;
286 +
287 +}
288 +
289 diff -Naur linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
290 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
291 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-06 15:34:14.000000000 +0200
292 @@ -0,0 +1,33 @@
293 +#
294 +# Makefile for Broadcom BCM947XX boards
295 +#
296 +# Copyright 2001-2003, Broadcom Corporation
297 +# All Rights Reserved.
298 +#
299 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
300 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
301 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
302 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
303 +#
304 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
305 +#
306 +
307 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
308 +SYSTEM ?= $(TOPDIR)/vmlinux
309 +
310 +all: vmlinuz
311 +
312 +# Don't build dependencies, this may die if $(CC) isn't gcc
313 +dep:
314 +
315 +# Create a gzipped version named vmlinuz for compatibility
316 +vmlinuz: piggy
317 + gzip -c9 $< > $@
318 +
319 +piggy: $(SYSTEM)
320 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
321 +
322 +mrproper: clean
323 +
324 +clean:
325 + rm -f vmlinuz piggy
326 diff -Naur linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
327 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
328 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-06 15:34:14.000000000 +0200
329 @@ -0,0 +1,15 @@
330 +#
331 +# Makefile for the BCM947xx specific kernel interface routines
332 +# under Linux.
333 +#
334 +
335 +.S.s:
336 + $(CPP) $(AFLAGS) $< -o $*.s
337 +.S.o:
338 + $(CC) $(AFLAGS) -c $< -o $*.o
339 +
340 +O_TARGET := brcm.o
341 +
342 +obj-y := int-handler.o irq.o
343 +
344 +include $(TOPDIR)/Rules.make
345 diff -Naur linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
346 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
347 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-06 15:34:14.000000000 +0200
348 @@ -0,0 +1,51 @@
349 +/*
350 + * Generic interrupt handler for Broadcom MIPS boards
351 + *
352 + * Copyright 2004, Broadcom Corporation
353 + * All Rights Reserved.
354 + *
355 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
356 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
357 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
358 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
359 + *
360 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
361 + */
362 +
363 +#include <linux/config.h>
364 +
365 +#include <asm/asm.h>
366 +#include <asm/mipsregs.h>
367 +#include <asm/regdef.h>
368 +#include <asm/stackframe.h>
369 +
370 +/*
371 + * MIPS IRQ Source
372 + * -------- ------
373 + * 0 Software (ignored)
374 + * 1 Software (ignored)
375 + * 2 Combined hardware interrupt (hw0)
376 + * 3 Hardware
377 + * 4 Hardware
378 + * 5 Hardware
379 + * 6 Hardware
380 + * 7 R4k timer
381 + */
382 +
383 + .text
384 + .set noreorder
385 + .set noat
386 + .align 5
387 + NESTED(brcmIRQ, PT_SIZE, sp)
388 + SAVE_ALL
389 + CLI
390 + .set at
391 + .set noreorder
392 +
393 + jal brcm_irq_dispatch
394 + move a0, sp
395 +
396 + j ret_from_irq
397 + nop
398 +
399 + END(brcmIRQ)
400 diff -Naur linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
401 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
402 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-06 15:34:14.000000000 +0200
403 @@ -0,0 +1,130 @@
404 +/*
405 + * Generic interrupt control functions for Broadcom MIPS boards
406 + *
407 + * Copyright 2004, Broadcom Corporation
408 + * All Rights Reserved.
409 + *
410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
414 + *
415 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
416 + */
417 +
418 +#include <linux/config.h>
419 +#include <linux/init.h>
420 +#include <linux/kernel.h>
421 +#include <linux/types.h>
422 +#include <linux/interrupt.h>
423 +#include <linux/irq.h>
424 +
425 +#include <asm/irq.h>
426 +#include <asm/mipsregs.h>
427 +#include <asm/gdb-stub.h>
428 +
429 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
430 +
431 +extern asmlinkage void brcmIRQ(void);
432 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
433 +
434 +void
435 +brcm_irq_dispatch(struct pt_regs *regs)
436 +{
437 + u32 cause;
438 +
439 + cause = read_c0_cause() &
440 + read_c0_status() &
441 + CAUSEF_IP;
442 +
443 +#ifdef CONFIG_KERNPROF
444 + change_c0_status(cause | 1, 1);
445 +#else
446 + clear_c0_status(cause);
447 +#endif
448 +
449 + if (cause & CAUSEF_IP7)
450 + do_IRQ(7, regs);
451 + if (cause & CAUSEF_IP2)
452 + do_IRQ(2, regs);
453 + if (cause & CAUSEF_IP3)
454 + do_IRQ(3, regs);
455 + if (cause & CAUSEF_IP4)
456 + do_IRQ(4, regs);
457 + if (cause & CAUSEF_IP5)
458 + do_IRQ(5, regs);
459 + if (cause & CAUSEF_IP6)
460 + do_IRQ(6, regs);
461 +}
462 +
463 +static void
464 +enable_brcm_irq(unsigned int irq)
465 +{
466 + if (irq < 8)
467 + set_c0_status(1 << (irq + 8));
468 + else
469 + set_c0_status(IE_IRQ0);
470 +}
471 +
472 +static void
473 +disable_brcm_irq(unsigned int irq)
474 +{
475 + if (irq < 8)
476 + clear_c0_status(1 << (irq + 8));
477 + else
478 + clear_c0_status(IE_IRQ0);
479 +}
480 +
481 +static void
482 +ack_brcm_irq(unsigned int irq)
483 +{
484 + /* Already done in brcm_irq_dispatch */
485 +}
486 +
487 +static unsigned int
488 +startup_brcm_irq(unsigned int irq)
489 +{
490 + enable_brcm_irq(irq);
491 +
492 + return 0; /* never anything pending */
493 +}
494 +
495 +static void
496 +end_brcm_irq(unsigned int irq)
497 +{
498 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
499 + enable_brcm_irq(irq);
500 +}
501 +
502 +static struct hw_interrupt_type brcm_irq_type = {
503 + typename: "MIPS",
504 + startup: startup_brcm_irq,
505 + shutdown: disable_brcm_irq,
506 + enable: enable_brcm_irq,
507 + disable: disable_brcm_irq,
508 + ack: ack_brcm_irq,
509 + end: end_brcm_irq,
510 + NULL
511 +};
512 +
513 +void __init
514 +init_IRQ(void)
515 +{
516 + int i;
517 +
518 + for (i = 0; i < NR_IRQS; i++) {
519 + irq_desc[i].status = IRQ_DISABLED;
520 + irq_desc[i].action = 0;
521 + irq_desc[i].depth = 1;
522 + irq_desc[i].handler = &brcm_irq_type;
523 + }
524 +
525 + set_except_vector(0, brcmIRQ);
526 + change_c0_status(ST0_IM, ALLINTS);
527 +
528 +#ifdef CONFIG_REMOTE_DEBUG
529 + printk("Breaking into debugger...\n");
530 + set_debug_traps();
531 + breakpoint();
532 +#endif
533 +}
534 diff -Naur linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
535 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
536 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-06 15:34:14.000000000 +0200
537 @@ -0,0 +1,158 @@
538 +/*
539 + * GPIO char driver
540 + *
541 + * Copyright 2005, Broadcom Corporation
542 + * All Rights Reserved.
543 + *
544 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
545 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
546 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
547 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
548 + *
549 + * $Id$
550 + */
551 +
552 +#include <linux/module.h>
553 +#include <linux/init.h>
554 +#include <linux/fs.h>
555 +#include <linux/miscdevice.h>
556 +#include <asm/uaccess.h>
557 +
558 +#include <typedefs.h>
559 +#include <bcmutils.h>
560 +#include <sbutils.h>
561 +#include <bcmdevs.h>
562 +
563 +static sb_t *gpio_sbh;
564 +static int gpio_major;
565 +static devfs_handle_t gpio_dir;
566 +static struct {
567 + char *name;
568 + devfs_handle_t handle;
569 +} gpio_file[] = {
570 + { "in", NULL },
571 + { "out", NULL },
572 + { "outen", NULL },
573 + { "control", NULL }
574 +};
575 +
576 +static int
577 +gpio_open(struct inode *inode, struct file * file)
578 +{
579 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
580 + return -ENODEV;
581 +
582 + MOD_INC_USE_COUNT;
583 + return 0;
584 +}
585 +
586 +static int
587 +gpio_release(struct inode *inode, struct file * file)
588 +{
589 + MOD_DEC_USE_COUNT;
590 + return 0;
591 +}
592 +
593 +static ssize_t
594 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
595 +{
596 + u32 val;
597 +
598 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
599 + case 0:
600 + val = sb_gpioin(gpio_sbh);
601 + break;
602 + case 1:
603 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
604 + break;
605 + case 2:
606 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
607 + break;
608 + case 3:
609 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
610 + break;
611 + default:
612 + return -ENODEV;
613 + }
614 +
615 + if (put_user(val, (u32 *) buf))
616 + return -EFAULT;
617 +
618 + return sizeof(val);
619 +}
620 +
621 +static ssize_t
622 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
623 +{
624 + u32 val;
625 +
626 + if (get_user(val, (u32 *) buf))
627 + return -EFAULT;
628 +
629 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
630 + case 0:
631 + return -EACCES;
632 + case 1:
633 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
634 + break;
635 + case 2:
636 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
637 + break;
638 + case 3:
639 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
640 + break;
641 + default:
642 + return -ENODEV;
643 + }
644 +
645 + return sizeof(val);
646 +}
647 +
648 +static struct file_operations gpio_fops = {
649 + owner: THIS_MODULE,
650 + open: gpio_open,
651 + release: gpio_release,
652 + read: gpio_read,
653 + write: gpio_write,
654 +};
655 +
656 +static int __init
657 +gpio_init(void)
658 +{
659 + int i;
660 +
661 + if (!(gpio_sbh = sb_kattach()))
662 + return -ENODEV;
663 +
664 + sb_gpiosetcore(gpio_sbh);
665 +
666 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
667 + return gpio_major;
668 +
669 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
670 +
671 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
672 + gpio_file[i].handle = devfs_register(gpio_dir,
673 + gpio_file[i].name,
674 + DEVFS_FL_DEFAULT, gpio_major, i,
675 + S_IFCHR | S_IRUGO | S_IWUGO,
676 + &gpio_fops, NULL);
677 + }
678 +
679 + return 0;
680 +}
681 +
682 +static void __exit
683 +gpio_exit(void)
684 +{
685 + int i;
686 +
687 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
688 + devfs_unregister(gpio_file[i].handle);
689 + devfs_unregister(gpio_dir);
690 + devfs_unregister_chrdev(gpio_major, "gpio");
691 + sb_detach(gpio_sbh);
692 +}
693 +
694 +module_init(gpio_init);
695 +module_exit(gpio_exit);
696 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
697 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
698 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-06 15:34:14.000000000 +0200
699 @@ -0,0 +1,391 @@
700 +/*
701 + * Broadcom device-specific manifest constants.
702 + *
703 + * Copyright 2005, Broadcom Corporation
704 + * All Rights Reserved.
705 + *
706 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
707 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
708 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
709 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
710 + * $Id$
711 + */
712 +
713 +#ifndef _BCMDEVS_H
714 +#define _BCMDEVS_H
715 +
716 +
717 +/* Known PCI vendor Id's */
718 +#define VENDOR_EPIGRAM 0xfeda
719 +#define VENDOR_BROADCOM 0x14e4
720 +#define VENDOR_3COM 0x10b7
721 +#define VENDOR_NETGEAR 0x1385
722 +#define VENDOR_DIAMOND 0x1092
723 +#define VENDOR_DELL 0x1028
724 +#define VENDOR_HP 0x0e11
725 +#define VENDOR_APPLE 0x106b
726 +
727 +/* PCI Device Id's */
728 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
729 +#define BCM4211_DEVICE_ID 0x4211
730 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
731 +#define BCM4231_DEVICE_ID 0x4231
732 +
733 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
734 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
735 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
736 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
737 +
738 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
739 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
740 +
741 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
742 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
743 +
744 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
745 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
746 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
747 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
748 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
749 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
750 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
751 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
752 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
753 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
754 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
755 +
756 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
757 +
758 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
759 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
760 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
761 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
762 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
763 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
764 +
765 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
766 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
767 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
768 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
769 +
770 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
771 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
772 +
773 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
774 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
775 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
776 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
777 +
778 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
779 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
780 +#define BCM4306_D11G_ID2 0x4325
781 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
782 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
783 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
784 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
785 +
786 +#define BCM4309_PKG_ID 1 /* 4309 package id */
787 +
788 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
789 +#define BCM4303_PKG_ID 2 /* 4303 package id */
790 +
791 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
792 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
793 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
794 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
795 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
796 +
797 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
798 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
799 +
800 +
801 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
802 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
803 +
804 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
805 +
806 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
807 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
808 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
809 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
810 +
811 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
812 +
813 +/* Address map */
814 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
815 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
816 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
817 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
818 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
819 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
820 +
821 +/* Core register space */
822 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
823 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
824 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
825 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
826 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
827 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
828 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
829 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
830 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
831 +
832 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
833 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
834 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
835 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
836 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
837 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
838 +
839 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
840 +
841 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
842 +
843 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
844 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
845 +
846 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
847 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
848 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
849 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
850 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
851 +
852 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
853 +
854 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
855 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
856 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
857 +
858 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
859 +
860 +/* PCMCIA vendor Id's */
861 +
862 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
863 +
864 +/* SDIO vendor Id's */
865 +#define VENDOR_BROADCOM_SDIO 0x00BF
866 +
867 +
868 +/* boardflags */
869 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
870 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
871 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
872 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
873 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
874 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
875 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
876 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
877 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
878 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
879 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
880 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
881 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
882 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
883 +
884 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
885 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
886 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
887 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
888 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
889 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
890 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
891 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
892 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
893 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
894 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
895 +
896 +/* Bus types */
897 +#define SB_BUS 0 /* Silicon Backplane */
898 +#define PCI_BUS 1 /* PCI target */
899 +#define PCMCIA_BUS 2 /* PCMCIA target */
900 +#define SDIO_BUS 3 /* SDIO target */
901 +#define JTAG_BUS 4 /* JTAG */
902 +
903 +/* Allows optimization for single-bus support */
904 +#ifdef BCMBUSTYPE
905 +#define BUSTYPE(bus) (BCMBUSTYPE)
906 +#else
907 +#define BUSTYPE(bus) (bus)
908 +#endif
909 +
910 +/* power control defines */
911 +#define PLL_DELAY 150 /* us pll on delay */
912 +#define FREF_DELAY 200 /* us fref change delay */
913 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
914 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
915 +
916 +/* Reference Board Types */
917 +
918 +#define BU4710_BOARD 0x0400
919 +#define VSIM4710_BOARD 0x0401
920 +#define QT4710_BOARD 0x0402
921 +
922 +#define BU4610_BOARD 0x0403
923 +#define VSIM4610_BOARD 0x0404
924 +
925 +#define BU4307_BOARD 0x0405
926 +#define BCM94301CB_BOARD 0x0406
927 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
928 +#define BCM94301MP_BOARD 0x0407
929 +#define BCM94307MP_BOARD 0x0408
930 +#define BCMAP4307_BOARD 0x0409
931 +
932 +#define BU4309_BOARD 0x040a
933 +#define BCM94309CB_BOARD 0x040b
934 +#define BCM94309MP_BOARD 0x040c
935 +#define BCM4309AP_BOARD 0x040d
936 +
937 +#define BCM94302MP_BOARD 0x040e
938 +
939 +#define VSIM4310_BOARD 0x040f
940 +#define BU4711_BOARD 0x0410
941 +#define BCM94310U_BOARD 0x0411
942 +#define BCM94310AP_BOARD 0x0412
943 +#define BCM94310MP_BOARD 0x0414
944 +
945 +#define BU4306_BOARD 0x0416
946 +#define BCM94306CB_BOARD 0x0417
947 +#define BCM94306MP_BOARD 0x0418
948 +
949 +#define BCM94710D_BOARD 0x041a
950 +#define BCM94710R1_BOARD 0x041b
951 +#define BCM94710R4_BOARD 0x041c
952 +#define BCM94710AP_BOARD 0x041d
953 +
954 +
955 +#define BU2050_BOARD 0x041f
956 +
957 +
958 +#define BCM94309G_BOARD 0x0421
959 +
960 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
961 +
962 +#define BU4704_BOARD 0x0423
963 +#define BU4702_BOARD 0x0424
964 +
965 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
966 +
967 +#define BU4317_BOARD 0x0426
968 +
969 +
970 +#define BCM94702MN_BOARD 0x0428
971 +
972 +/* BCM4702 1U CompactPCI Board */
973 +#define BCM94702CPCI_BOARD 0x0429
974 +
975 +/* BCM4702 with BCM95380 VLAN Router */
976 +#define BCM95380RR_BOARD 0x042a
977 +
978 +/* cb4306 with SiGe PA */
979 +#define BCM94306CBSG_BOARD 0x042b
980 +
981 +/* mp4301 with 2050 radio */
982 +#define BCM94301MPL_BOARD 0x042c
983 +
984 +/* cb4306 with SiGe PA */
985 +#define PCSG94306_BOARD 0x042d
986 +
987 +/* bu4704 with sdram */
988 +#define BU4704SD_BOARD 0x042e
989 +
990 +/* Dual 11a/11g Router */
991 +#define BCM94704AGR_BOARD 0x042f
992 +
993 +/* 11a-only minipci */
994 +#define BCM94308MP_BOARD 0x0430
995 +
996 +
997 +
998 +/* BCM94317 boards */
999 +#define BCM94317CB_BOARD 0x0440
1000 +#define BCM94317MP_BOARD 0x0441
1001 +#define BCM94317PCMCIA_BOARD 0x0442
1002 +#define BCM94317SDIO_BOARD 0x0443
1003 +
1004 +#define BU4712_BOARD 0x0444
1005 +#define BU4712SD_BOARD 0x045d
1006 +#define BU4712L_BOARD 0x045f
1007 +
1008 +/* BCM4712 boards */
1009 +#define BCM94712AP_BOARD 0x0445
1010 +#define BCM94712P_BOARD 0x0446
1011 +
1012 +/* BCM4318 boards */
1013 +#define BU4318_BOARD 0x0447
1014 +#define CB4318_BOARD 0x0448
1015 +#define MPG4318_BOARD 0x0449
1016 +#define MP4318_BOARD 0x044a
1017 +#define SD4318_BOARD 0x044b
1018 +
1019 +/* BCM63XX boards */
1020 +#define BCM96338_BOARD 0x6338
1021 +#define BCM96345_BOARD 0x6345
1022 +#define BCM96348_BOARD 0x6348
1023 +
1024 +/* Another mp4306 with SiGe */
1025 +#define BCM94306P_BOARD 0x044c
1026 +
1027 +/* CF-like 4317 modules */
1028 +#define BCM94317CF_BOARD 0x044d
1029 +
1030 +/* mp4303 */
1031 +#define BCM94303MP_BOARD 0x044e
1032 +
1033 +/* mpsgh4306 */
1034 +#define BCM94306MPSGH_BOARD 0x044f
1035 +
1036 +/* BRCM 4306 w/ Front End Modules */
1037 +#define BCM94306MPM 0x0450
1038 +#define BCM94306MPL 0x0453
1039 +
1040 +/* 4712agr */
1041 +#define BCM94712AGR_BOARD 0x0451
1042 +
1043 +/* The real CF 4317 board */
1044 +#define CFI4317_BOARD 0x0452
1045 +
1046 +/* pcmcia 4303 */
1047 +#define PC4303_BOARD 0x0454
1048 +
1049 +/* 5350K */
1050 +#define BCM95350K_BOARD 0x0455
1051 +
1052 +/* 5350R */
1053 +#define BCM95350R_BOARD 0x0456
1054 +
1055 +/* 4306mplna */
1056 +#define BCM94306MPLNA_BOARD 0x0457
1057 +
1058 +/* 4320 boards */
1059 +#define BU4320_BOARD 0x0458
1060 +#define BU4320S_BOARD 0x0459
1061 +#define BCM94320PH_BOARD 0x045a
1062 +
1063 +/* 4306mph */
1064 +#define BCM94306MPH_BOARD 0x045b
1065 +
1066 +/* 4306pciv */
1067 +#define BCM94306PCIV_BOARD 0x045c
1068 +
1069 +#define BU4712SD_BOARD 0x045d
1070 +
1071 +#define BCM94320PFLSH_BOARD 0x045e
1072 +
1073 +#define BU4712L_BOARD 0x045f
1074 +#define BCM94712LGR_BOARD 0x0460
1075 +#define BCM94320R_BOARD 0x0461
1076 +
1077 +#define BU5352_BOARD 0x0462
1078 +
1079 +#define BCM94318MPGH_BOARD 0x0463
1080 +
1081 +
1082 +#define BCM95352GR_BOARD 0x0467
1083 +
1084 +/* bcm95351agr */
1085 +#define BCM95351AGR_BOARD 0x0470
1086 +
1087 +/* # of GPIO pins */
1088 +#define GPIO_NUMPINS 16
1089 +
1090 +#endif /* _BCMDEVS_H */
1091 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
1092 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
1093 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-06 15:34:14.000000000 +0200
1094 @@ -0,0 +1,152 @@
1095 +/*
1096 + * local version of endian.h - byte order defines
1097 + *
1098 + * Copyright 2005, Broadcom Corporation
1099 + * All Rights Reserved.
1100 + *
1101 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1102 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1103 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1104 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1105 + *
1106 + * $Id$
1107 +*/
1108 +
1109 +#ifndef _BCMENDIAN_H_
1110 +#define _BCMENDIAN_H_
1111 +
1112 +#include <typedefs.h>
1113 +
1114 +/* Byte swap a 16 bit value */
1115 +#define BCMSWAP16(val) \
1116 + ((uint16)( \
1117 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
1118 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
1119 +
1120 +/* Byte swap a 32 bit value */
1121 +#define BCMSWAP32(val) \
1122 + ((uint32)( \
1123 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
1124 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
1125 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
1126 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1127 +
1128 +/* 2 Byte swap a 32 bit value */
1129 +#define BCMSWAP32BY16(val) \
1130 + ((uint32)( \
1131 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1132 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1133 +
1134 +
1135 +static INLINE uint16
1136 +bcmswap16(uint16 val)
1137 +{
1138 + return BCMSWAP16(val);
1139 +}
1140 +
1141 +static INLINE uint32
1142 +bcmswap32(uint32 val)
1143 +{
1144 + return BCMSWAP32(val);
1145 +}
1146 +
1147 +static INLINE uint32
1148 +bcmswap32by16(uint32 val)
1149 +{
1150 + return BCMSWAP32BY16(val);
1151 +}
1152 +
1153 +/* buf - start of buffer of shorts to swap */
1154 +/* len - byte length of buffer */
1155 +static INLINE void
1156 +bcmswap16_buf(uint16 *buf, uint len)
1157 +{
1158 + len = len/2;
1159 +
1160 + while(len--){
1161 + *buf = bcmswap16(*buf);
1162 + buf++;
1163 + }
1164 +}
1165 +
1166 +#ifndef hton16
1167 +#ifndef IL_BIGENDIAN
1168 +#define HTON16(i) BCMSWAP16(i)
1169 +#define hton16(i) bcmswap16(i)
1170 +#define hton32(i) bcmswap32(i)
1171 +#define ntoh16(i) bcmswap16(i)
1172 +#define ntoh32(i) bcmswap32(i)
1173 +#define ltoh16(i) (i)
1174 +#define ltoh32(i) (i)
1175 +#define htol16(i) (i)
1176 +#define htol32(i) (i)
1177 +#else
1178 +#define HTON16(i) (i)
1179 +#define hton16(i) (i)
1180 +#define hton32(i) (i)
1181 +#define ntoh16(i) (i)
1182 +#define ntoh32(i) (i)
1183 +#define ltoh16(i) bcmswap16(i)
1184 +#define ltoh32(i) bcmswap32(i)
1185 +#define htol16(i) bcmswap16(i)
1186 +#define htol32(i) bcmswap32(i)
1187 +#endif
1188 +#endif
1189 +
1190 +#ifndef IL_BIGENDIAN
1191 +#define ltoh16_buf(buf, i)
1192 +#define htol16_buf(buf, i)
1193 +#else
1194 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1195 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1196 +#endif
1197 +
1198 +/*
1199 +* load 16-bit value from unaligned little endian byte array.
1200 +*/
1201 +static INLINE uint16
1202 +ltoh16_ua(uint8 *bytes)
1203 +{
1204 + return (bytes[1]<<8)+bytes[0];
1205 +}
1206 +
1207 +/*
1208 +* load 32-bit value from unaligned little endian byte array.
1209 +*/
1210 +static INLINE uint32
1211 +ltoh32_ua(uint8 *bytes)
1212 +{
1213 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1214 +}
1215 +
1216 +/*
1217 +* load 16-bit value from unaligned big(network) endian byte array.
1218 +*/
1219 +static INLINE uint16
1220 +ntoh16_ua(uint8 *bytes)
1221 +{
1222 + return (bytes[0]<<8)+bytes[1];
1223 +}
1224 +
1225 +/*
1226 +* load 32-bit value from unaligned big(network) endian byte array.
1227 +*/
1228 +static INLINE uint32
1229 +ntoh32_ua(uint8 *bytes)
1230 +{
1231 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1232 +}
1233 +
1234 +#define ltoh_ua(ptr) ( \
1235 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1236 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1237 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1238 +)
1239 +
1240 +#define ntoh_ua(ptr) ( \
1241 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1242 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1243 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1244 +)
1245 +
1246 +#endif /* _BCMENDIAN_H_ */
1247 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1248 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1249 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-04-06 15:34:14.000000000 +0200
1250 @@ -0,0 +1,141 @@
1251 +/*
1252 + * NVRAM variable manipulation
1253 + *
1254 + * Copyright 2005, Broadcom Corporation
1255 + * All Rights Reserved.
1256 + *
1257 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1258 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1259 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1260 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1261 + *
1262 + * $Id$
1263 + */
1264 +
1265 +#ifndef _bcmnvram_h_
1266 +#define _bcmnvram_h_
1267 +
1268 +#ifndef _LANGUAGE_ASSEMBLY
1269 +
1270 +#include <typedefs.h>
1271 +
1272 +struct nvram_header {
1273 + uint32 magic;
1274 + uint32 len;
1275 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1276 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1277 + uint32 config_ncdl; /* ncdl values for memc */
1278 +};
1279 +
1280 +struct nvram_tuple {
1281 + char *name;
1282 + char *value;
1283 + struct nvram_tuple *next;
1284 +};
1285 +
1286 +/*
1287 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1288 + * platforms.
1289 + */
1290 +extern int BCMINIT(nvram_init)(void *sbh);
1291 +
1292 +/*
1293 + * Disable NVRAM access. May be unnecessary or undefined on certain
1294 + * platforms.
1295 + */
1296 +extern void BCMINIT(nvram_exit)(void *sbh);
1297 +
1298 +/*
1299 + * Get the value of an NVRAM variable. The pointer returned may be
1300 + * invalid after a set.
1301 + * @param name name of variable to get
1302 + * @return value of variable or NULL if undefined
1303 + */
1304 +extern char * BCMINIT(nvram_get)(const char *name);
1305 +
1306 +/*
1307 + * Read the reset GPIO value from the nvram and set the GPIO
1308 + * as input
1309 + */
1310 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1311 +
1312 +/*
1313 + * Get the value of an NVRAM variable.
1314 + * @param name name of variable to get
1315 + * @return value of variable or NUL if undefined
1316 + */
1317 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1318 +
1319 +/*
1320 + * Match an NVRAM variable.
1321 + * @param name name of variable to match
1322 + * @param match value to compare against value of variable
1323 + * @return TRUE if variable is defined and its value is string equal
1324 + * to match or FALSE otherwise
1325 + */
1326 +static INLINE int
1327 +nvram_match(char *name, char *match) {
1328 + const char *value = BCMINIT(nvram_get)(name);
1329 + return (value && !strcmp(value, match));
1330 +}
1331 +
1332 +/*
1333 + * Inversely match an NVRAM variable.
1334 + * @param name name of variable to match
1335 + * @param match value to compare against value of variable
1336 + * @return TRUE if variable is defined and its value is not string
1337 + * equal to invmatch or FALSE otherwise
1338 + */
1339 +static INLINE int
1340 +nvram_invmatch(char *name, char *invmatch) {
1341 + const char *value = BCMINIT(nvram_get)(name);
1342 + return (value && strcmp(value, invmatch));
1343 +}
1344 +
1345 +/*
1346 + * Set the value of an NVRAM variable. The name and value strings are
1347 + * copied into private storage. Pointers to previously set values
1348 + * may become invalid. The new value may be immediately
1349 + * retrieved but will not be permanently stored until a commit.
1350 + * @param name name of variable to set
1351 + * @param value value of variable
1352 + * @return 0 on success and errno on failure
1353 + */
1354 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1355 +
1356 +/*
1357 + * Unset an NVRAM variable. Pointers to previously set values
1358 + * remain valid until a set.
1359 + * @param name name of variable to unset
1360 + * @return 0 on success and errno on failure
1361 + * NOTE: use nvram_commit to commit this change to flash.
1362 + */
1363 +extern int BCMINIT(nvram_unset)(const char *name);
1364 +
1365 +/*
1366 + * Commit NVRAM variables to permanent storage. All pointers to values
1367 + * may be invalid after a commit.
1368 + * NVRAM values are undefined after a commit.
1369 + * @return 0 on success and errno on failure
1370 + */
1371 +extern int BCMINIT(nvram_commit)(void);
1372 +
1373 +/*
1374 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1375 + * @param buf buffer to store variables
1376 + * @param count size of buffer in bytes
1377 + * @return 0 on success and errno on failure
1378 + */
1379 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1380 +
1381 +#endif /* _LANGUAGE_ASSEMBLY */
1382 +
1383 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1384 +#define NVRAM_VERSION 1
1385 +#define NVRAM_HEADER_SIZE 20
1386 +#define NVRAM_SPACE 0x8000
1387 +
1388 +#define NVRAM_MAX_VALUE_LEN 255
1389 +#define NVRAM_MAX_PARAM_LEN 64
1390 +
1391 +#endif /* _bcmnvram_h_ */
1392 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1393 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1394 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-04-06 15:34:14.000000000 +0200
1395 @@ -0,0 +1,23 @@
1396 +/*
1397 + * Misc useful routines to access NIC local SROM/OTP .
1398 + *
1399 + * Copyright 2005, Broadcom Corporation
1400 + * All Rights Reserved.
1401 + *
1402 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1403 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1404 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1405 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1406 + *
1407 + * $Id$
1408 + */
1409 +
1410 +#ifndef _bcmsrom_h_
1411 +#define _bcmsrom_h_
1412 +
1413 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1414 +
1415 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1416 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1417 +
1418 +#endif /* _bcmsrom_h_ */
1419 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1420 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1421 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-04-06 17:07:30.000000000 +0200
1422 @@ -0,0 +1,287 @@
1423 +/*
1424 + * Misc useful os-independent macros and functions.
1425 + *
1426 + * Copyright 2005, Broadcom Corporation
1427 + * All Rights Reserved.
1428 + *
1429 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1430 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1431 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1432 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1433 + * $Id$
1434 + */
1435 +
1436 +#ifndef _bcmutils_h_
1437 +#define _bcmutils_h_
1438 +
1439 +/*** driver-only section ***/
1440 +#ifdef BCMDRIVER
1441 +#include <osl.h>
1442 +
1443 +#define _BCM_U 0x01 /* upper */
1444 +#define _BCM_L 0x02 /* lower */
1445 +#define _BCM_D 0x04 /* digit */
1446 +#define _BCM_C 0x08 /* cntrl */
1447 +#define _BCM_P 0x10 /* punct */
1448 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1449 +#define _BCM_X 0x40 /* hex digit */
1450 +#define _BCM_SP 0x80 /* hard space (0x20) */
1451 +
1452 +#define GPIO_PIN_NOTDEFINED 0x20
1453 +
1454 +extern unsigned char bcm_ctype[];
1455 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1456 +
1457 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1458 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1459 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1460 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1461 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1462 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1463 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1464 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1465 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1466 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1467 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1468 +
1469 +/*
1470 + * Spin at most 'us' microseconds while 'exp' is true.
1471 + * Caller should explicitly test 'exp' when this completes
1472 + * and take appropriate error action if 'exp' is still true.
1473 + */
1474 +#define SPINWAIT(exp, us) { \
1475 + uint countdown = (us) + 9; \
1476 + while ((exp) && (countdown >= 10)) {\
1477 + OSL_DELAY(10); \
1478 + countdown -= 10; \
1479 + } \
1480 +}
1481 +
1482 +/* string */
1483 +extern uint bcm_atoi(char *s);
1484 +extern uchar bcm_toupper(uchar c);
1485 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1486 +extern char *bcmstrstr(char *haystack, char *needle);
1487 +extern char *bcmstrcat(char *dest, const char *src);
1488 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1489 +/* ethernet address */
1490 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1491 +extern int bcm_ether_atoe(char *p, char *ea);
1492 +/* delay */
1493 +extern void bcm_mdelay(uint ms);
1494 +/* variable access */
1495 +extern char *getvar(char *vars, char *name);
1496 +extern int getintvar(char *vars, char *name);
1497 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1498 +#define bcmlog(fmt, a1, a2)
1499 +#define bcmdumplog(buf, size) *buf = '\0'
1500 +#define bcmdumplogent(buf, idx) -1
1501 +
1502 +#endif /* #ifdef BCMDRIVER */
1503 +
1504 +/*** driver/apps-shared section ***/
1505 +
1506 +#define BCME_STRLEN 64
1507 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1508 +
1509 +
1510 +/*
1511 + * error codes could be added but the defined ones shouldn't be changed/deleted
1512 + * these error codes are exposed to the user code
1513 + * when ever a new error code is added to this list
1514 + * please update errorstring table with the related error string and
1515 + * update osl files with os specific errorcode map
1516 +*/
1517 +
1518 +#define BCME_ERROR -1 /* Error generic */
1519 +#define BCME_BADARG -2 /* Bad Argument */
1520 +#define BCME_BADOPTION -3 /* Bad option */
1521 +#define BCME_NOTUP -4 /* Not up */
1522 +#define BCME_NOTDOWN -5 /* Not down */
1523 +#define BCME_NOTAP -6 /* Not AP */
1524 +#define BCME_NOTSTA -7 /* Not STA */
1525 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1526 +#define BCME_RADIOOFF -9 /* Radio Off */
1527 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1528 +#define BCME_NOCLK -11 /* No Clock*/
1529 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1530 +#define BCME_BADBAND -13 /* BAD Band */
1531 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1532 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1533 +#define BCME_BUSY -16 /* Busy*/
1534 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1535 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1536 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1537 +#define BCME_BADCHAN -20 /* BAD Channel */
1538 +#define BCME_BADADDR -21 /* BAD Address*/
1539 +#define BCME_NORESOURCE -22 /* No resources*/
1540 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1541 +#define BCME_BADLEN -24 /* Bad Length*/
1542 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1543 +#define BCME_EPERM -26 /* Not Permitted */
1544 +#define BCME_NOMEM -27 /* No Memory */
1545 +#define BCME_ASSOCIATED -28 /* Associated */
1546 +#define BCME_RANGE -29 /* Range Error*/
1547 +#define BCME_NOTFOUND -30 /* Not found */
1548 +#define BCME_LAST BCME_NOTFOUND
1549 +
1550 +#ifndef ABS
1551 +#define ABS(a) (((a)<0)?-(a):(a))
1552 +#endif
1553 +
1554 +#ifndef MIN
1555 +#define MIN(a, b) (((a)<(b))?(a):(b))
1556 +#endif
1557 +
1558 +#ifndef MAX
1559 +#define MAX(a, b) (((a)>(b))?(a):(b))
1560 +#endif
1561 +
1562 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1563 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1564 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1565 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1566 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1567 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1568 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1569 +
1570 +/* bit map related macros */
1571 +#ifndef setbit
1572 +#define NBBY 8 /* 8 bits per byte */
1573 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1574 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1575 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1576 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1577 +#endif
1578 +
1579 +#define NBITS(type) (sizeof(type) * 8)
1580 +#define NBITVAL(bits) (1 << (bits))
1581 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1582 +
1583 +/* crc defines */
1584 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1585 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1586 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1587 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1588 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1589 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1590 +
1591 +/* bcm_format_flags() bit description structure */
1592 +typedef struct bcm_bit_desc {
1593 + uint32 bit;
1594 + char* name;
1595 +} bcm_bit_desc_t;
1596 +
1597 +/* tag_ID/length/value_buffer tuple */
1598 +typedef struct bcm_tlv {
1599 + uint8 id;
1600 + uint8 len;
1601 + uint8 data[1];
1602 +} bcm_tlv_t;
1603 +
1604 +/* Check that bcm_tlv_t fits into the given buflen */
1605 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1606 +
1607 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1608 +#define ETHER_ADDR_STR_LEN 18
1609 +
1610 +/* unaligned load and store macros */
1611 +#ifdef IL_BIGENDIAN
1612 +static INLINE uint32
1613 +load32_ua(uint8 *a)
1614 +{
1615 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1616 +}
1617 +
1618 +static INLINE void
1619 +store32_ua(uint8 *a, uint32 v)
1620 +{
1621 + a[0] = (v >> 24) & 0xff;
1622 + a[1] = (v >> 16) & 0xff;
1623 + a[2] = (v >> 8) & 0xff;
1624 + a[3] = v & 0xff;
1625 +}
1626 +
1627 +static INLINE uint16
1628 +load16_ua(uint8 *a)
1629 +{
1630 + return ((a[0] << 8) | a[1]);
1631 +}
1632 +
1633 +static INLINE void
1634 +store16_ua(uint8 *a, uint16 v)
1635 +{
1636 + a[0] = (v >> 8) & 0xff;
1637 + a[1] = v & 0xff;
1638 +}
1639 +
1640 +#else
1641 +
1642 +static INLINE uint32
1643 +load32_ua(uint8 *a)
1644 +{
1645 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1646 +}
1647 +
1648 +static INLINE void
1649 +store32_ua(uint8 *a, uint32 v)
1650 +{
1651 + a[3] = (v >> 24) & 0xff;
1652 + a[2] = (v >> 16) & 0xff;
1653 + a[1] = (v >> 8) & 0xff;
1654 + a[0] = v & 0xff;
1655 +}
1656 +
1657 +static INLINE uint16
1658 +load16_ua(uint8 *a)
1659 +{
1660 + return ((a[1] << 8) | a[0]);
1661 +}
1662 +
1663 +static INLINE void
1664 +store16_ua(uint8 *a, uint16 v)
1665 +{
1666 + a[1] = (v >> 8) & 0xff;
1667 + a[0] = v & 0xff;
1668 +}
1669 +
1670 +#endif
1671 +
1672 +/* externs */
1673 +/* crc */
1674 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1675 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1676 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1677 +/* format/print */
1678 +/* IE parsing */
1679 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1680 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1681 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1682 +
1683 +/* bcmerror*/
1684 +extern const char *bcmerrorstr(int bcmerror);
1685 +
1686 +/* multi-bool data type: set of bools, mbool is true if any is set */
1687 +typedef uint32 mbool;
1688 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1689 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1690 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1691 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1692 +
1693 +/* power conversion */
1694 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
1695 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
1696 +
1697 +/* generic datastruct to help dump routines */
1698 +struct fielddesc {
1699 + char *nameandfmt;
1700 + uint32 offset;
1701 + uint32 len;
1702 +};
1703 +
1704 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
1705 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
1706 +
1707 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
1708 +
1709 +#endif /* _bcmutils_h_ */
1710 diff -Naur linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
1711 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
1712 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-04-06 15:34:14.000000000 +0200
1713 @@ -0,0 +1,16 @@
1714 +/*
1715 + * Alternate include file for HND sbmips.h since CFE also ships with
1716 + * a sbmips.h.
1717 + *
1718 + * Copyright 2005, Broadcom Corporation
1719 + * All Rights Reserved.
1720 + *
1721 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1722 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1723 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1724 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1725 + *
1726 + * $Id$
1727 + */
1728 +
1729 +#include "sbmips.h"
1730 diff -Naur linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
1731 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
1732 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2006-04-06 15:34:14.000000000 +0200
1733 @@ -0,0 +1,371 @@
1734 +/*
1735 + * Linux OS Independent Layer
1736 + *
1737 + * Copyright 2005, Broadcom Corporation
1738 + * All Rights Reserved.
1739 + *
1740 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1741 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1742 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1743 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1744 + *
1745 + * $Id$
1746 + */
1747 +
1748 +#ifndef _linux_osl_h_
1749 +#define _linux_osl_h_
1750 +
1751 +#include <typedefs.h>
1752 +
1753 +/* use current 2.4.x calling conventions */
1754 +#include <linuxver.h>
1755 +
1756 +/* assert and panic */
1757 +#ifdef __GNUC__
1758 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
1759 +#if GCC_VERSION > 30100
1760 +#define ASSERT(exp) do {} while (0)
1761 +#else
1762 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
1763 +#define ASSERT(exp)
1764 +#endif
1765 +#endif
1766 +
1767 +/* microsecond delay */
1768 +#define OSL_DELAY(usec) osl_delay(usec)
1769 +extern void osl_delay(uint usec);
1770 +
1771 +/* PCMCIA attribute space access macros */
1772 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
1773 +struct pcmcia_dev {
1774 + dev_link_t link; /* PCMCIA device pointer */
1775 + dev_node_t node; /* PCMCIA node structure */
1776 + void *base; /* Mapped attribute memory window */
1777 + size_t size; /* Size of window */
1778 + void *drv; /* Driver data */
1779 +};
1780 +#endif
1781 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
1782 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
1783 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
1784 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
1785 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
1786 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
1787 +
1788 +/* PCI configuration space access macros */
1789 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
1790 + osl_pci_read_config((osh), (offset), (size))
1791 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
1792 + osl_pci_write_config((osh), (offset), (size), (val))
1793 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
1794 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
1795 +
1796 +/* PCI device bus # and slot # */
1797 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
1798 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
1799 +extern uint osl_pci_bus(osl_t *osh);
1800 +extern uint osl_pci_slot(osl_t *osh);
1801 +
1802 +/* OSL initialization */
1803 +extern osl_t *osl_attach(void *pdev);
1804 +extern void osl_detach(osl_t *osh);
1805 +
1806 +/* host/bus architecture-specific byte swap */
1807 +#define BUS_SWAP32(v) (v)
1808 +
1809 +/* general purpose memory allocation */
1810 +
1811 +#if defined(BCMDBG_MEM)
1812 +
1813 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
1814 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
1815 +#define MALLOCED(osh) osl_malloced((osh))
1816 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
1817 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
1818 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
1819 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
1820 +
1821 +#else
1822 +
1823 +#define MALLOC(osh, size) osl_malloc((osh), (size))
1824 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
1825 +#define MALLOCED(osh) osl_malloced((osh))
1826 +
1827 +#endif /* BCMDBG_MEM */
1828 +
1829 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
1830 +
1831 +extern void *osl_malloc(osl_t *osh, uint size);
1832 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
1833 +extern uint osl_malloced(osl_t *osh);
1834 +extern uint osl_malloc_failed(osl_t *osh);
1835 +
1836 +/* allocate/free shared (dma-able) consistent memory */
1837 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
1838 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
1839 + osl_dma_alloc_consistent((osh), (size), (pap))
1840 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
1841 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
1842 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
1843 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
1844 +
1845 +/* map/unmap direction */
1846 +#define DMA_TX 1
1847 +#define DMA_RX 2
1848 +
1849 +/* map/unmap shared (dma-able) memory */
1850 +#define DMA_MAP(osh, va, size, direction, p) \
1851 + osl_dma_map((osh), (va), (size), (direction))
1852 +#define DMA_UNMAP(osh, pa, size, direction, p) \
1853 + osl_dma_unmap((osh), (pa), (size), (direction))
1854 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
1855 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
1856 +
1857 +/* register access macros */
1858 +#if defined(BCMJTAG)
1859 +#include <bcmjtag.h>
1860 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
1861 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
1862 +#endif
1863 +
1864 +/*
1865 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
1866 + * Macros expand to calls to functions defined in linux_osl.c .
1867 + */
1868 +#ifndef BINOSL
1869 +
1870 +/* string library, kernel mode */
1871 +#define printf(fmt, args...) printk(fmt, ## args)
1872 +#include <linux/kernel.h>
1873 +#include <linux/string.h>
1874 +
1875 +/* register access macros */
1876 +#if !defined(BCMJTAG)
1877 +#ifndef IL_BIGENDIAN
1878 +#define R_REG(r) ( \
1879 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
1880 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
1881 + readl((volatile uint32*)(r)) \
1882 +)
1883 +#define W_REG(r, v) do { \
1884 + switch (sizeof(*(r))) { \
1885 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
1886 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
1887 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1888 + } \
1889 +} while (0)
1890 +#else /* IL_BIGENDIAN */
1891 +#define R_REG(r) ({ \
1892 + __typeof(*(r)) __osl_v; \
1893 + switch (sizeof(*(r))) { \
1894 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
1895 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
1896 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
1897 + } \
1898 + __osl_v; \
1899 +})
1900 +#define W_REG(r, v) do { \
1901 + switch (sizeof(*(r))) { \
1902 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
1903 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
1904 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1905 + } \
1906 +} while (0)
1907 +#endif
1908 +#endif
1909 +
1910 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
1911 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
1912 +
1913 +/* bcopy, bcmp, and bzero */
1914 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
1915 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
1916 +#define bzero(b, len) memset((b), '\0', (len))
1917 +
1918 +/* uncached virtual address */
1919 +#ifdef mips
1920 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
1921 +#include <asm/addrspace.h>
1922 +#else
1923 +#define OSL_UNCACHED(va) (va)
1924 +#endif
1925 +
1926 +/* get processor cycle count */
1927 +#if defined(mips)
1928 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
1929 +#elif defined(__i386__)
1930 +#define OSL_GETCYCLES(x) rdtscl((x))
1931 +#else
1932 +#define OSL_GETCYCLES(x) ((x) = 0)
1933 +#endif
1934 +
1935 +/* dereference an address that may cause a bus exception */
1936 +#ifdef mips
1937 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
1938 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
1939 +#else
1940 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
1941 +#include <asm/paccess.h>
1942 +#endif
1943 +#else
1944 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
1945 +#endif
1946 +
1947 +/* map/unmap physical to virtual I/O */
1948 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
1949 +#define REG_UNMAP(va) iounmap((void *)(va))
1950 +
1951 +/* shared (dma-able) memory access macros */
1952 +#define R_SM(r) *(r)
1953 +#define W_SM(r, v) (*(r) = (v))
1954 +#define BZERO_SM(r, len) memset((r), '\0', (len))
1955 +
1956 +/* packet primitives */
1957 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
1958 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
1959 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
1960 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
1961 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
1962 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
1963 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
1964 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
1965 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
1966 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
1967 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
1968 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
1969 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
1970 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
1971 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
1972 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
1973 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
1974 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
1975 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
1976 +extern void osl_pktfree(void *skb);
1977 +
1978 +#else /* BINOSL */
1979 +
1980 +/* string library */
1981 +#ifndef LINUX_OSL
1982 +#undef printf
1983 +#define printf(fmt, args...) osl_printf((fmt), ## args)
1984 +#undef sprintf
1985 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
1986 +#undef strcmp
1987 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
1988 +#undef strncmp
1989 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
1990 +#undef strlen
1991 +#define strlen(s) osl_strlen((s))
1992 +#undef strcpy
1993 +#define strcpy(d, s) osl_strcpy((d), (s))
1994 +#undef strncpy
1995 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
1996 +#endif
1997 +extern int osl_printf(const char *format, ...);
1998 +extern int osl_sprintf(char *buf, const char *format, ...);
1999 +extern int osl_strcmp(const char *s1, const char *s2);
2000 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
2001 +extern int osl_strlen(const char *s);
2002 +extern char* osl_strcpy(char *d, const char *s);
2003 +extern char* osl_strncpy(char *d, const char *s, uint n);
2004 +
2005 +/* register access macros */
2006 +#if !defined(BCMJTAG)
2007 +#define R_REG(r) ( \
2008 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
2009 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
2010 + osl_readl((volatile uint32*)(r)) \
2011 +)
2012 +#define W_REG(r, v) do { \
2013 + switch (sizeof(*(r))) { \
2014 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
2015 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
2016 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
2017 + } \
2018 +} while (0)
2019 +#endif
2020 +
2021 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2022 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2023 +extern uint8 osl_readb(volatile uint8 *r);
2024 +extern uint16 osl_readw(volatile uint16 *r);
2025 +extern uint32 osl_readl(volatile uint32 *r);
2026 +extern void osl_writeb(uint8 v, volatile uint8 *r);
2027 +extern void osl_writew(uint16 v, volatile uint16 *r);
2028 +extern void osl_writel(uint32 v, volatile uint32 *r);
2029 +
2030 +/* bcopy, bcmp, and bzero */
2031 +extern void bcopy(const void *src, void *dst, int len);
2032 +extern int bcmp(const void *b1, const void *b2, int len);
2033 +extern void bzero(void *b, int len);
2034 +
2035 +/* uncached virtual address */
2036 +#define OSL_UNCACHED(va) osl_uncached((va))
2037 +extern void *osl_uncached(void *va);
2038 +
2039 +/* get processor cycle count */
2040 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
2041 +extern uint osl_getcycles(void);
2042 +
2043 +/* dereference an address that may target abort */
2044 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
2045 +extern int osl_busprobe(uint32 *val, uint32 addr);
2046 +
2047 +/* map/unmap physical to virtual */
2048 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
2049 +#define REG_UNMAP(va) osl_reg_unmap((va))
2050 +extern void *osl_reg_map(uint32 pa, uint size);
2051 +extern void osl_reg_unmap(void *va);
2052 +
2053 +/* shared (dma-able) memory access macros */
2054 +#define R_SM(r) *(r)
2055 +#define W_SM(r, v) (*(r) = (v))
2056 +#define BZERO_SM(r, len) bzero((r), (len))
2057 +
2058 +/* packet primitives */
2059 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
2060 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
2061 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
2062 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
2063 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
2064 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
2065 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
2066 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
2067 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
2068 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
2069 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
2070 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
2071 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
2072 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
2073 +#define PKTLINK(skb) osl_pktlink((skb))
2074 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
2075 +#define PKTPRIO(skb) osl_pktprio((skb))
2076 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
2077 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
2078 +extern void osl_pktfree(void *skb);
2079 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
2080 +extern uint osl_pktlen(osl_t *osh, void *skb);
2081 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
2082 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
2083 +extern void *osl_pktnext(osl_t *osh, void *skb);
2084 +extern void osl_pktsetnext(void *skb, void *x);
2085 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
2086 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
2087 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
2088 +extern void *osl_pktdup(osl_t *osh, void *skb);
2089 +extern void *osl_pktcookie(void *skb);
2090 +extern void osl_pktsetcookie(void *skb, void *x);
2091 +extern void *osl_pktlink(void *skb);
2092 +extern void osl_pktsetlink(void *skb, void *x);
2093 +extern uint osl_pktprio(void *skb);
2094 +extern void osl_pktsetprio(void *skb, uint x);
2095 +
2096 +#endif /* BINOSL */
2097 +
2098 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2099 +extern int osl_error(int bcmerror);
2100 +
2101 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2102 +#define PKTBUFSZ 2048
2103 +
2104 +#endif /* _linux_osl_h_ */
2105 diff -Naur linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
2106 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
2107 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-04-06 15:34:14.000000000 +0200
2108 @@ -0,0 +1,411 @@
2109 +/*
2110 + * Linux-specific abstractions to gain some independence from linux kernel versions.
2111 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
2112 + *
2113 + * Copyright 2005, Broadcom Corporation
2114 + * All Rights Reserved.
2115 + *
2116 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2117 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2118 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2119 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2120 + *
2121 + * $Id$
2122 + */
2123 +
2124 +#ifndef _linuxver_h_
2125 +#define _linuxver_h_
2126 +
2127 +#include <linux/config.h>
2128 +#include <linux/version.h>
2129 +
2130 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
2131 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
2132 +#ifdef __UNDEF_NO_VERSION__
2133 +#undef __NO_VERSION__
2134 +#else
2135 +#define __NO_VERSION__
2136 +#endif
2137 +#endif
2138 +
2139 +#if defined(MODULE) && defined(MODVERSIONS)
2140 +#include <linux/modversions.h>
2141 +#endif
2142 +
2143 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2144 +#include <linux/moduleparam.h>
2145 +#endif
2146 +
2147 +
2148 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2149 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
2150 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
2151 +#endif
2152 +
2153 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
2154 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
2155 +#include <linux/malloc.h>
2156 +#else
2157 +#include <linux/slab.h>
2158 +#endif
2159 +
2160 +#include <linux/types.h>
2161 +#include <linux/init.h>
2162 +#include <linux/mm.h>
2163 +#include <linux/string.h>
2164 +#include <linux/pci.h>
2165 +#include <linux/interrupt.h>
2166 +#include <linux/netdevice.h>
2167 +#include <asm/io.h>
2168 +
2169 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
2170 +#include <linux/workqueue.h>
2171 +#else
2172 +#include <linux/tqueue.h>
2173 +#ifndef work_struct
2174 +#define work_struct tq_struct
2175 +#endif
2176 +#ifndef INIT_WORK
2177 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
2178 +#endif
2179 +#ifndef schedule_work
2180 +#define schedule_work(_work) schedule_task((_work))
2181 +#endif
2182 +#ifndef flush_scheduled_work
2183 +#define flush_scheduled_work() flush_scheduled_tasks()
2184 +#endif
2185 +#endif
2186 +
2187 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2188 +/* Some distributions have their own 2.6.x compatibility layers */
2189 +#ifndef IRQ_NONE
2190 +typedef void irqreturn_t;
2191 +#define IRQ_NONE
2192 +#define IRQ_HANDLED
2193 +#define IRQ_RETVAL(x)
2194 +#endif
2195 +#else
2196 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
2197 +#endif
2198 +
2199 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2200 +
2201 +#include <pcmcia/version.h>
2202 +#include <pcmcia/cs_types.h>
2203 +#include <pcmcia/cs.h>
2204 +#include <pcmcia/cistpl.h>
2205 +#include <pcmcia/cisreg.h>
2206 +#include <pcmcia/ds.h>
2207 +
2208 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
2209 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
2210 + * does this, but it's not in 2.4 so we do our own for now. */
2211 +static inline void
2212 +cs_error(client_handle_t handle, int func, int ret)
2213 +{
2214 + error_info_t err = { func, ret };
2215 + CardServices(ReportError, handle, &err);
2216 +}
2217 +#endif
2218 +
2219 +#endif /* CONFIG_PCMCIA */
2220 +
2221 +#ifndef __exit
2222 +#define __exit
2223 +#endif
2224 +#ifndef __devexit
2225 +#define __devexit
2226 +#endif
2227 +#ifndef __devinit
2228 +#define __devinit __init
2229 +#endif
2230 +#ifndef __devinitdata
2231 +#define __devinitdata
2232 +#endif
2233 +#ifndef __devexit_p
2234 +#define __devexit_p(x) x
2235 +#endif
2236 +
2237 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
2238 +
2239 +#define pci_get_drvdata(dev) (dev)->sysdata
2240 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
2241 +
2242 +/*
2243 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
2244 + */
2245 +
2246 +struct pci_device_id {
2247 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
2248 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
2249 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
2250 + unsigned long driver_data; /* Data private to the driver */
2251 +};
2252 +
2253 +struct pci_driver {
2254 + struct list_head node;
2255 + char *name;
2256 + const struct pci_device_id *id_table; /* NULL if wants all devices */
2257 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
2258 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
2259 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
2260 + void (*resume)(struct pci_dev *dev); /* Device woken up */
2261 +};
2262 +
2263 +#define MODULE_DEVICE_TABLE(type, name)
2264 +#define PCI_ANY_ID (~0)
2265 +
2266 +/* compatpci.c */
2267 +#define pci_module_init pci_register_driver
2268 +extern int pci_register_driver(struct pci_driver *drv);
2269 +extern void pci_unregister_driver(struct pci_driver *drv);
2270 +
2271 +#endif /* PCI registration */
2272 +
2273 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
2274 +#ifdef MODULE
2275 +#define module_init(x) int init_module(void) { return x(); }
2276 +#define module_exit(x) void cleanup_module(void) { x(); }
2277 +#else
2278 +#define module_init(x) __initcall(x);
2279 +#define module_exit(x) __exitcall(x);
2280 +#endif
2281 +#endif
2282 +
2283 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
2284 +#define list_for_each(pos, head) \
2285 + for (pos = (head)->next; pos != (head); pos = pos->next)
2286 +#endif
2287 +
2288 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
2289 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
2290 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
2291 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
2292 +#endif
2293 +
2294 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
2295 +#define pci_enable_device(dev) do { } while (0)
2296 +#endif
2297 +
2298 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
2299 +#define net_device device
2300 +#endif
2301 +
2302 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
2303 +
2304 +/*
2305 + * DMA mapping
2306 + *
2307 + * See linux/Documentation/DMA-mapping.txt
2308 + */
2309 +
2310 +#ifndef PCI_DMA_TODEVICE
2311 +#define PCI_DMA_TODEVICE 1
2312 +#define PCI_DMA_FROMDEVICE 2
2313 +#endif
2314 +
2315 +typedef u32 dma_addr_t;
2316 +
2317 +/* Pure 2^n version of get_order */
2318 +static inline int get_order(unsigned long size)
2319 +{
2320 + int order;
2321 +
2322 + size = (size-1) >> (PAGE_SHIFT-1);
2323 + order = -1;
2324 + do {
2325 + size >>= 1;
2326 + order++;
2327 + } while (size);
2328 + return order;
2329 +}
2330 +
2331 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
2332 + dma_addr_t *dma_handle)
2333 +{
2334 + void *ret;
2335 + int gfp = GFP_ATOMIC | GFP_DMA;
2336 +
2337 + ret = (void *)__get_free_pages(gfp, get_order(size));
2338 +
2339 + if (ret != NULL) {
2340 + memset(ret, 0, size);
2341 + *dma_handle = virt_to_bus(ret);
2342 + }
2343 + return ret;
2344 +}
2345 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
2346 + void *vaddr, dma_addr_t dma_handle)
2347 +{
2348 + free_pages((unsigned long)vaddr, get_order(size));
2349 +}
2350 +#ifdef ILSIM
2351 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
2352 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
2353 +#else
2354 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
2355 +#define pci_unmap_single(cookie, address, size, dir)
2356 +#endif
2357 +
2358 +#endif /* DMA mapping */
2359 +
2360 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
2361 +
2362 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
2363 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
2364 +
2365 +/* pcmcia-cs provides its own netdevice compatibility layer */
2366 +#ifndef _COMPAT_NETDEVICE_H
2367 +
2368 +/*
2369 + * SoftNet
2370 + *
2371 + * For pre-softnet kernels we need to tell the upper layer not to
2372 + * re-enter start_xmit() while we are in there. However softnet
2373 + * guarantees not to enter while we are in there so there is no need
2374 + * to do the netif_stop_queue() dance unless the transmit queue really
2375 + * gets stuck. This should also improve performance according to tests
2376 + * done by Aman Singla.
2377 + */
2378 +
2379 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
2380 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
2381 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
2382 +
2383 +static inline void netif_start_queue(struct net_device *dev)
2384 +{
2385 + dev->tbusy = 0;
2386 + dev->interrupt = 0;
2387 + dev->start = 1;
2388 +}
2389 +
2390 +#define netif_queue_stopped(dev) (dev)->tbusy
2391 +#define netif_running(dev) (dev)->start
2392 +
2393 +#endif /* _COMPAT_NETDEVICE_H */
2394 +
2395 +#define netif_device_attach(dev) netif_start_queue(dev)
2396 +#define netif_device_detach(dev) netif_stop_queue(dev)
2397 +
2398 +/* 2.4.x renamed bottom halves to tasklets */
2399 +#define tasklet_struct tq_struct
2400 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
2401 +{
2402 + queue_task(tasklet, &tq_immediate);
2403 + mark_bh(IMMEDIATE_BH);
2404 +}
2405 +
2406 +static inline void tasklet_init(struct tasklet_struct *tasklet,
2407 + void (*func)(unsigned long),
2408 + unsigned long data)
2409 +{
2410 + tasklet->next = NULL;
2411 + tasklet->sync = 0;
2412 + tasklet->routine = (void (*)(void *))func;
2413 + tasklet->data = (void *)data;
2414 +}
2415 +#define tasklet_kill(tasklet) {do{} while(0);}
2416 +
2417 +/* 2.4.x introduced del_timer_sync() */
2418 +#define del_timer_sync(timer) del_timer(timer)
2419 +
2420 +#else
2421 +
2422 +#define netif_down(dev)
2423 +
2424 +#endif /* SoftNet */
2425 +
2426 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
2427 +
2428 +/*
2429 + * Emit code to initialise a tq_struct's routine and data pointers
2430 + */
2431 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
2432 + do { \
2433 + (_tq)->routine = _routine; \
2434 + (_tq)->data = _data; \
2435 + } while (0)
2436 +
2437 +/*
2438 + * Emit code to initialise all of a tq_struct
2439 + */
2440 +#define INIT_TQUEUE(_tq, _routine, _data) \
2441 + do { \
2442 + INIT_LIST_HEAD(&(_tq)->list); \
2443 + (_tq)->sync = 0; \
2444 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
2445 + } while (0)
2446 +
2447 +#endif
2448 +
2449 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
2450 +
2451 +/* Power management related routines */
2452 +
2453 +static inline int
2454 +pci_save_state(struct pci_dev *dev, u32 *buffer)
2455 +{
2456 + int i;
2457 + if (buffer) {
2458 + for (i = 0; i < 16; i++)
2459 + pci_read_config_dword(dev, i * 4,&buffer[i]);
2460 + }
2461 + return 0;
2462 +}
2463 +
2464 +static inline int
2465 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
2466 +{
2467 + int i;
2468 +
2469 + if (buffer) {
2470 + for (i = 0; i < 16; i++)
2471 + pci_write_config_dword(dev,i * 4, buffer[i]);
2472 + }
2473 + /*
2474 + * otherwise, write the context information we know from bootup.
2475 + * This works around a problem where warm-booting from Windows
2476 + * combined with a D3(hot)->D0 transition causes PCI config
2477 + * header data to be forgotten.
2478 + */
2479 + else {
2480 + for (i = 0; i < 6; i ++)
2481 + pci_write_config_dword(dev,
2482 + PCI_BASE_ADDRESS_0 + (i * 4),
2483 + pci_resource_start(dev, i));
2484 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2485 + }
2486 + return 0;
2487 +}
2488 +
2489 +#endif /* PCI power management */
2490 +
2491 +/* Old cp0 access macros deprecated in 2.4.19 */
2492 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
2493 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
2494 +#endif
2495 +
2496 +/* Module refcount handled internally in 2.6.x */
2497 +#ifndef SET_MODULE_OWNER
2498 +#define SET_MODULE_OWNER(dev) do {} while (0)
2499 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
2500 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
2501 +#else
2502 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
2503 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
2504 +#endif
2505 +
2506 +#ifndef SET_NETDEV_DEV
2507 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
2508 +#endif
2509 +
2510 +#ifndef HAVE_FREE_NETDEV
2511 +#define free_netdev(dev) kfree(dev)
2512 +#endif
2513 +
2514 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2515 +/* struct packet_type redefined in 2.6.x */
2516 +#define af_packet_priv data
2517 +#endif
2518 +
2519 +#endif /* _linuxver_h_ */
2520 diff -Naur linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
2521 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
2522 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-04-06 15:34:14.000000000 +0200
2523 @@ -0,0 +1,552 @@
2524 +/*
2525 + * HND Run Time Environment for standalone MIPS programs.
2526 + *
2527 + * Copyright 2005, Broadcom Corporation
2528 + * All Rights Reserved.
2529 + *
2530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2534 + *
2535 + * $Id$
2536 + */
2537 +
2538 +#ifndef _MISPINC_H
2539 +#define _MISPINC_H
2540 +
2541 +
2542 +/* MIPS defines */
2543 +
2544 +#ifdef _LANGUAGE_ASSEMBLY
2545 +
2546 +/*
2547 + * Symbolic register names for 32 bit ABI
2548 + */
2549 +#define zero $0 /* wired zero */
2550 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
2551 +#define v0 $2 /* return value */
2552 +#define v1 $3
2553 +#define a0 $4 /* argument registers */
2554 +#define a1 $5
2555 +#define a2 $6
2556 +#define a3 $7
2557 +#define t0 $8 /* caller saved */
2558 +#define t1 $9
2559 +#define t2 $10
2560 +#define t3 $11
2561 +#define t4 $12
2562 +#define t5 $13
2563 +#define t6 $14
2564 +#define t7 $15
2565 +#define s0 $16 /* callee saved */
2566 +#define s1 $17
2567 +#define s2 $18
2568 +#define s3 $19
2569 +#define s4 $20
2570 +#define s5 $21
2571 +#define s6 $22
2572 +#define s7 $23
2573 +#define t8 $24 /* caller saved */
2574 +#define t9 $25
2575 +#define jp $25 /* PIC jump register */
2576 +#define k0 $26 /* kernel scratch */
2577 +#define k1 $27
2578 +#define gp $28 /* global pointer */
2579 +#define sp $29 /* stack pointer */
2580 +#define fp $30 /* frame pointer */
2581 +#define s8 $30 /* same like fp! */
2582 +#define ra $31 /* return address */
2583 +
2584 +
2585 +/*
2586 + * CP0 Registers
2587 + */
2588 +
2589 +#define C0_INX $0
2590 +#define C0_RAND $1
2591 +#define C0_TLBLO0 $2
2592 +#define C0_TLBLO C0_TLBLO0
2593 +#define C0_TLBLO1 $3
2594 +#define C0_CTEXT $4
2595 +#define C0_PGMASK $5
2596 +#define C0_WIRED $6
2597 +#define C0_BADVADDR $8
2598 +#define C0_COUNT $9
2599 +#define C0_TLBHI $10
2600 +#define C0_COMPARE $11
2601 +#define C0_SR $12
2602 +#define C0_STATUS C0_SR
2603 +#define C0_CAUSE $13
2604 +#define C0_EPC $14
2605 +#define C0_PRID $15
2606 +#define C0_CONFIG $16
2607 +#define C0_LLADDR $17
2608 +#define C0_WATCHLO $18
2609 +#define C0_WATCHHI $19
2610 +#define C0_XCTEXT $20
2611 +#define C0_DIAGNOSTIC $22
2612 +#define C0_BROADCOM C0_DIAGNOSTIC
2613 +#define C0_PERFORMANCE $25
2614 +#define C0_ECC $26
2615 +#define C0_CACHEERR $27
2616 +#define C0_TAGLO $28
2617 +#define C0_TAGHI $29
2618 +#define C0_ERREPC $30
2619 +#define C0_DESAVE $31
2620 +
2621 +/*
2622 + * LEAF - declare leaf routine
2623 + */
2624 +#define LEAF(symbol) \
2625 + .globl symbol; \
2626 + .align 2; \
2627 + .type symbol,@function; \
2628 + .ent symbol,0; \
2629 +symbol: .frame sp,0,ra
2630 +
2631 +/*
2632 + * END - mark end of function
2633 + */
2634 +#define END(function) \
2635 + .end function; \
2636 + .size function,.-function
2637 +
2638 +#define _ULCAST_
2639 +
2640 +#else
2641 +
2642 +/*
2643 + * The following macros are especially useful for __asm__
2644 + * inline assembler.
2645 + */
2646 +#ifndef __STR
2647 +#define __STR(x) #x
2648 +#endif
2649 +#ifndef STR
2650 +#define STR(x) __STR(x)
2651 +#endif
2652 +
2653 +#define _ULCAST_ (unsigned long)
2654 +
2655 +
2656 +/*
2657 + * CP0 Registers
2658 + */
2659 +
2660 +#define C0_INX 0 /* CP0: TLB Index */
2661 +#define C0_RAND 1 /* CP0: TLB Random */
2662 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
2663 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
2664 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
2665 +#define C0_CTEXT 4 /* CP0: Context */
2666 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
2667 +#define C0_WIRED 6 /* CP0: TLB Wired */
2668 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
2669 +#define C0_COUNT 9 /* CP0: Count */
2670 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
2671 +#define C0_COMPARE 11 /* CP0: Compare */
2672 +#define C0_SR 12 /* CP0: Processor Status */
2673 +#define C0_STATUS C0_SR /* CP0: Processor Status */
2674 +#define C0_CAUSE 13 /* CP0: Exception Cause */
2675 +#define C0_EPC 14 /* CP0: Exception PC */
2676 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
2677 +#define C0_CONFIG 16 /* CP0: Config */
2678 +#define C0_LLADDR 17 /* CP0: LLAddr */
2679 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
2680 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
2681 +#define C0_XCTEXT 20 /* CP0: XContext */
2682 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
2683 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
2684 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
2685 +#define C0_ECC 26 /* CP0: ECC */
2686 +#define C0_CACHEERR 27 /* CP0: CacheErr */
2687 +#define C0_TAGLO 28 /* CP0: TagLo */
2688 +#define C0_TAGHI 29 /* CP0: TagHi */
2689 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
2690 +#define C0_DESAVE 31 /* CP0: DebugSave */
2691 +
2692 +#endif /* _LANGUAGE_ASSEMBLY */
2693 +
2694 +/*
2695 + * Memory segments (32bit kernel mode addresses)
2696 + */
2697 +#undef KUSEG
2698 +#undef KSEG0
2699 +#undef KSEG1
2700 +#undef KSEG2
2701 +#undef KSEG3
2702 +#define KUSEG 0x00000000
2703 +#define KSEG0 0x80000000
2704 +#define KSEG1 0xa0000000
2705 +#define KSEG2 0xc0000000
2706 +#define KSEG3 0xe0000000
2707 +#define PHYSADDR_MASK 0x1fffffff
2708 +
2709 +/*
2710 + * Map an address to a certain kernel segment
2711 + */
2712 +#undef PHYSADDR
2713 +#undef KSEG0ADDR
2714 +#undef KSEG1ADDR
2715 +#undef KSEG2ADDR
2716 +#undef KSEG3ADDR
2717 +
2718 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
2719 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
2720 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
2721 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
2722 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
2723 +
2724 +
2725 +#ifndef Index_Invalidate_I
2726 +/*
2727 + * Cache Operations
2728 + */
2729 +#define Index_Invalidate_I 0x00
2730 +#define Index_Writeback_Inv_D 0x01
2731 +#define Index_Invalidate_SI 0x02
2732 +#define Index_Writeback_Inv_SD 0x03
2733 +#define Index_Load_Tag_I 0x04
2734 +#define Index_Load_Tag_D 0x05
2735 +#define Index_Load_Tag_SI 0x06
2736 +#define Index_Load_Tag_SD 0x07
2737 +#define Index_Store_Tag_I 0x08
2738 +#define Index_Store_Tag_D 0x09
2739 +#define Index_Store_Tag_SI 0x0A
2740 +#define Index_Store_Tag_SD 0x0B
2741 +#define Create_Dirty_Excl_D 0x0d
2742 +#define Create_Dirty_Excl_SD 0x0f
2743 +#define Hit_Invalidate_I 0x10
2744 +#define Hit_Invalidate_D 0x11
2745 +#define Hit_Invalidate_SI 0x12
2746 +#define Hit_Invalidate_SD 0x13
2747 +#define Fill_I 0x14
2748 +#define Hit_Writeback_Inv_D 0x15
2749 + /* 0x16 is unused */
2750 +#define Hit_Writeback_Inv_SD 0x17
2751 +#define R5K_Page_Invalidate_S 0x17
2752 +#define Hit_Writeback_I 0x18
2753 +#define Hit_Writeback_D 0x19
2754 + /* 0x1a is unused */
2755 +#define Hit_Writeback_SD 0x1b
2756 + /* 0x1c is unused */
2757 + /* 0x1e is unused */
2758 +#define Hit_Set_Virtual_SI 0x1e
2759 +#define Hit_Set_Virtual_SD 0x1f
2760 +#endif
2761 +
2762 +
2763 +/*
2764 + * R4x00 interrupt enable / cause bits
2765 + */
2766 +#define IE_SW0 (_ULCAST_(1) << 8)
2767 +#define IE_SW1 (_ULCAST_(1) << 9)
2768 +#define IE_IRQ0 (_ULCAST_(1) << 10)
2769 +#define IE_IRQ1 (_ULCAST_(1) << 11)
2770 +#define IE_IRQ2 (_ULCAST_(1) << 12)
2771 +#define IE_IRQ3 (_ULCAST_(1) << 13)
2772 +#define IE_IRQ4 (_ULCAST_(1) << 14)
2773 +#define IE_IRQ5 (_ULCAST_(1) << 15)
2774 +
2775 +#ifndef ST0_UM
2776 +/*
2777 + * Bitfields in the mips32 cp0 status register
2778 + */
2779 +#define ST0_IE 0x00000001
2780 +#define ST0_EXL 0x00000002
2781 +#define ST0_ERL 0x00000004
2782 +#define ST0_UM 0x00000010
2783 +#define ST0_SWINT0 0x00000100
2784 +#define ST0_SWINT1 0x00000200
2785 +#define ST0_HWINT0 0x00000400
2786 +#define ST0_HWINT1 0x00000800
2787 +#define ST0_HWINT2 0x00001000
2788 +#define ST0_HWINT3 0x00002000
2789 +#define ST0_HWINT4 0x00004000
2790 +#define ST0_HWINT5 0x00008000
2791 +#define ST0_IM 0x0000ff00
2792 +#define ST0_NMI 0x00080000
2793 +#define ST0_SR 0x00100000
2794 +#define ST0_TS 0x00200000
2795 +#define ST0_BEV 0x00400000
2796 +#define ST0_RE 0x02000000
2797 +#define ST0_RP 0x08000000
2798 +#define ST0_CU 0xf0000000
2799 +#define ST0_CU0 0x10000000
2800 +#define ST0_CU1 0x20000000
2801 +#define ST0_CU2 0x40000000
2802 +#define ST0_CU3 0x80000000
2803 +#endif
2804 +
2805 +
2806 +/*
2807 + * Bitfields in the mips32 cp0 cause register
2808 + */
2809 +#define C_EXC 0x0000007c
2810 +#define C_EXC_SHIFT 2
2811 +#define C_INT 0x0000ff00
2812 +#define C_INT_SHIFT 8
2813 +#define C_SW0 (_ULCAST_(1) << 8)
2814 +#define C_SW1 (_ULCAST_(1) << 9)
2815 +#define C_IRQ0 (_ULCAST_(1) << 10)
2816 +#define C_IRQ1 (_ULCAST_(1) << 11)
2817 +#define C_IRQ2 (_ULCAST_(1) << 12)
2818 +#define C_IRQ3 (_ULCAST_(1) << 13)
2819 +#define C_IRQ4 (_ULCAST_(1) << 14)
2820 +#define C_IRQ5 (_ULCAST_(1) << 15)
2821 +#define C_WP 0x00400000
2822 +#define C_IV 0x00800000
2823 +#define C_CE 0x30000000
2824 +#define C_CE_SHIFT 28
2825 +#define C_BD 0x80000000
2826 +
2827 +/* Values in C_EXC */
2828 +#define EXC_INT 0
2829 +#define EXC_TLBM 1
2830 +#define EXC_TLBL 2
2831 +#define EXC_TLBS 3
2832 +#define EXC_AEL 4
2833 +#define EXC_AES 5
2834 +#define EXC_IBE 6
2835 +#define EXC_DBE 7
2836 +#define EXC_SYS 8
2837 +#define EXC_BPT 9
2838 +#define EXC_RI 10
2839 +#define EXC_CU 11
2840 +#define EXC_OV 12
2841 +#define EXC_TR 13
2842 +#define EXC_WATCH 23
2843 +#define EXC_MCHK 24
2844 +
2845 +
2846 +/*
2847 + * Bits in the cp0 config register.
2848 + */
2849 +#define CONF_CM_CACHABLE_NO_WA 0
2850 +#define CONF_CM_CACHABLE_WA 1
2851 +#define CONF_CM_UNCACHED 2
2852 +#define CONF_CM_CACHABLE_NONCOHERENT 3
2853 +#define CONF_CM_CACHABLE_CE 4
2854 +#define CONF_CM_CACHABLE_COW 5
2855 +#define CONF_CM_CACHABLE_CUW 6
2856 +#define CONF_CM_CACHABLE_ACCELERATED 7
2857 +#define CONF_CM_CMASK 7
2858 +#define CONF_CU (_ULCAST_(1) << 3)
2859 +#define CONF_DB (_ULCAST_(1) << 4)
2860 +#define CONF_IB (_ULCAST_(1) << 5)
2861 +#define CONF_SE (_ULCAST_(1) << 12)
2862 +#define CONF_SC (_ULCAST_(1) << 17)
2863 +#define CONF_AC (_ULCAST_(1) << 23)
2864 +#define CONF_HALT (_ULCAST_(1) << 25)
2865 +
2866 +
2867 +/*
2868 + * Bits in the cp0 config register select 1.
2869 + */
2870 +#define CONF1_FP 0x00000001 /* FPU present */
2871 +#define CONF1_EP 0x00000002 /* EJTAG present */
2872 +#define CONF1_CA 0x00000004 /* mips16 implemented */
2873 +#define CONF1_WR 0x00000008 /* Watch registers present */
2874 +#define CONF1_PC 0x00000010 /* Performance counters present */
2875 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
2876 +#define CONF1_DA_MASK 0x00000380
2877 +#define CONF1_DA_BASE 1
2878 +#define CONF1_DL_SHIFT 10 /* D$ line size */
2879 +#define CONF1_DL_MASK 0x00001c00
2880 +#define CONF1_DL_BASE 2
2881 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
2882 +#define CONF1_DS_MASK 0x0000e000
2883 +#define CONF1_DS_BASE 64
2884 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
2885 +#define CONF1_IA_MASK 0x00070000
2886 +#define CONF1_IA_BASE 1
2887 +#define CONF1_IL_SHIFT 19 /* I$ line size */
2888 +#define CONF1_IL_MASK 0x00380000
2889 +#define CONF1_IL_BASE 2
2890 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
2891 +#define CONF1_IS_MASK 0x01c00000
2892 +#define CONF1_IS_BASE 64
2893 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
2894 +#define CONF1_MS_SHIFT 25
2895 +
2896 +/* PRID register */
2897 +#define PRID_COPT_MASK 0xff000000
2898 +#define PRID_COMP_MASK 0x00ff0000
2899 +#define PRID_IMP_MASK 0x0000ff00
2900 +#define PRID_REV_MASK 0x000000ff
2901 +
2902 +#define PRID_COMP_LEGACY 0x000000
2903 +#define PRID_COMP_MIPS 0x010000
2904 +#define PRID_COMP_BROADCOM 0x020000
2905 +#define PRID_COMP_ALCHEMY 0x030000
2906 +#define PRID_COMP_SIBYTE 0x040000
2907 +#define PRID_IMP_BCM4710 0x4000
2908 +#define PRID_IMP_BCM3302 0x9000
2909 +#define PRID_IMP_BCM3303 0x9100
2910 +
2911 +#define PRID_IMP_UNKNOWN 0xff00
2912 +
2913 +#define BCM330X(id) \
2914 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
2915 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
2916 +
2917 +/* Bits in C0_BROADCOM */
2918 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
2919 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
2920 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
2921 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
2922 +
2923 +/* PreFetch Cache aka Read Ahead Cache */
2924 +
2925 +#define PFC_CR0 0xff400000 /* control reg 0 */
2926 +#define PFC_CR1 0xff400004 /* control reg 1 */
2927 +
2928 +/* PFC operations */
2929 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
2930 +#define PFC_D 0x00000002 /* Enable PFC use for data */
2931 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
2932 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
2933 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
2934 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
2935 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
2936 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
2937 +#define PFC_BRR 0x40000000 /* Bus error indication */
2938 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
2939 +
2940 +/* Handy defaults */
2941 +#define PFC_DISABLED 0
2942 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
2943 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
2944 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
2945 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
2946 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
2947 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
2948 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
2949 +
2950 +
2951 +/*
2952 + * These are the UART port assignments, expressed as offsets from the base
2953 + * register. These assignments should hold for any serial port based on
2954 + * a 8250, 16450, or 16550(A).
2955 + */
2956 +
2957 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
2958 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
2959 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
2960 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
2961 +#define UART_LCR 3 /* Out: Line Control Register */
2962 +#define UART_MCR 4 /* Out: Modem Control Register */
2963 +#define UART_LSR 5 /* In: Line Status Register */
2964 +#define UART_MSR 6 /* In: Modem Status Register */
2965 +#define UART_SCR 7 /* I/O: Scratch Register */
2966 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
2967 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
2968 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
2969 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
2970 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
2971 +
2972 +
2973 +#ifndef _LANGUAGE_ASSEMBLY
2974 +
2975 +/*
2976 + * Macros to access the system control coprocessor
2977 + */
2978 +
2979 +#define MFC0(source, sel) \
2980 +({ \
2981 + int __res; \
2982 + __asm__ __volatile__( \
2983 + ".set\tnoreorder\n\t" \
2984 + ".set\tnoat\n\t" \
2985 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
2986 + "move\t%0,$1\n\t" \
2987 + ".set\tat\n\t" \
2988 + ".set\treorder" \
2989 + :"=r" (__res) \
2990 + : \
2991 + :"$1"); \
2992 + __res; \
2993 +})
2994 +
2995 +#define MTC0(source, sel, value) \
2996 +do { \
2997 + __asm__ __volatile__( \
2998 + ".set\tnoreorder\n\t" \
2999 + ".set\tnoat\n\t" \
3000 + "move\t$1,%z0\n\t" \
3001 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
3002 + ".set\tat\n\t" \
3003 + ".set\treorder" \
3004 + : \
3005 + :"jr" (value) \
3006 + :"$1"); \
3007 +} while (0)
3008 +
3009 +#define get_c0_count() \
3010 +({ \
3011 + int __res; \
3012 + __asm__ __volatile__( \
3013 + ".set\tnoreorder\n\t" \
3014 + ".set\tnoat\n\t" \
3015 + "mfc0\t%0,$9\n\t" \
3016 + ".set\tat\n\t" \
3017 + ".set\treorder" \
3018 + :"=r" (__res)); \
3019 + __res; \
3020 +})
3021 +
3022 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
3023 +{
3024 + uint lsz, sets, ways;
3025 +
3026 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3027 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
3028 + lsz = CONF1_IL_BASE << lsz;
3029 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
3030 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
3031 + *size = lsz * sets * ways;
3032 + *lsize = lsz;
3033 +}
3034 +
3035 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
3036 +{
3037 + uint lsz, sets, ways;
3038 +
3039 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
3040 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
3041 + lsz = CONF1_DL_BASE << lsz;
3042 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
3043 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
3044 + *size = lsz * sets * ways;
3045 + *lsize = lsz;
3046 +}
3047 +
3048 +#define cache_op(base, op) \
3049 + __asm__ __volatile__(" \
3050 + .set noreorder; \
3051 + .set mips3; \
3052 + cache %1, (%0); \
3053 + .set mips0; \
3054 + .set reorder" \
3055 + : \
3056 + : "r" (base), \
3057 + "i" (op));
3058 +
3059 +#define cache_unroll4(base, delta, op) \
3060 + __asm__ __volatile__(" \
3061 + .set noreorder; \
3062 + .set mips3; \
3063 + cache %1,0(%0); \
3064 + cache %1,delta(%0); \
3065 + cache %1,(2 * delta)(%0); \
3066 + cache %1,(3 * delta)(%0); \
3067 + .set mips0; \
3068 + .set reorder" \
3069 + : \
3070 + : "r" (base), \
3071 + "i" (op));
3072 +
3073 +#endif /* !_LANGUAGE_ASSEMBLY */
3074 +
3075 +#endif /* _MISPINC_H */
3076 diff -Naur linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
3077 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
3078 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-04-06 15:34:14.000000000 +0200
3079 @@ -0,0 +1,42 @@
3080 +/*
3081 + * OS Abstraction Layer
3082 + *
3083 + * Copyright 2005, Broadcom Corporation
3084 + * All Rights Reserved.
3085 + *
3086 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3087 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3088 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3089 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3090 + * $Id$
3091 + */
3092 +
3093 +#ifndef _osl_h_
3094 +#define _osl_h_
3095 +
3096 +/* osl handle type forward declaration */
3097 +typedef struct os_handle osl_t;
3098 +
3099 +#if defined(linux)
3100 +#include <linux_osl.h>
3101 +#elif defined(NDIS)
3102 +#include <ndis_osl.h>
3103 +#elif defined(_CFE_)
3104 +#include <cfe_osl.h>
3105 +#elif defined(_HNDRTE_)
3106 +#include <hndrte_osl.h>
3107 +#elif defined(_MINOSL_)
3108 +#include <min_osl.h>
3109 +#elif PMON
3110 +#include <pmon_osl.h>
3111 +#elif defined(MACOSX)
3112 +#include <macosx_osl.h>
3113 +#else
3114 +#error "Unsupported OSL requested"
3115 +#endif
3116 +
3117 +/* handy */
3118 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
3119 +#define MAXPRIO 7 /* 0-7 */
3120 +
3121 +#endif /* _osl_h_ */
3122 diff -Naur linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
3123 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
3124 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-04-06 15:34:14.000000000 +0200
3125 @@ -0,0 +1,451 @@
3126 +/*
3127 + * pcicfg.h: PCI configuration constants and structures.
3128 + *
3129 + * Copyright 2005, Broadcom Corporation
3130 + * All Rights Reserved.
3131 + *
3132 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3133 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3134 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3135 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3136 + *
3137 + * $Id$
3138 + */
3139 +
3140 +#ifndef _h_pci_
3141 +#define _h_pci_
3142 +
3143 +/* The following inside ifndef's so we don't collide with NTDDK.H */
3144 +#ifndef PCI_MAX_BUS
3145 +#define PCI_MAX_BUS 0x100
3146 +#endif
3147 +#ifndef PCI_MAX_DEVICES
3148 +#define PCI_MAX_DEVICES 0x20
3149 +#endif
3150 +#ifndef PCI_MAX_FUNCTION
3151 +#define PCI_MAX_FUNCTION 0x8
3152 +#endif
3153 +
3154 +#ifndef PCI_INVALID_VENDORID
3155 +#define PCI_INVALID_VENDORID 0xffff
3156 +#endif
3157 +#ifndef PCI_INVALID_DEVICEID
3158 +#define PCI_INVALID_DEVICEID 0xffff
3159 +#endif
3160 +
3161 +
3162 +/* Convert between bus-slot-function-register and config addresses */
3163 +
3164 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
3165 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
3166 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
3167 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
3168 +
3169 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
3170 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
3171 +#define PCICFG_FUN_MASK 7 /* Function mask */
3172 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
3173 +
3174 +#define PCI_CONFIG_ADDR(b, s, f, o) \
3175 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
3176 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
3177 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
3178 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
3179 +
3180 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
3181 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
3182 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
3183 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
3184 +
3185 +/* PCIE Config space accessing MACROS*/
3186 +
3187 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
3188 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
3189 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
3190 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
3191 +
3192 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
3193 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
3194 +#define PCIECFG_FUN_MASK 7 /* Function mask */
3195 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
3196 +
3197 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
3198 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
3199 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
3200 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
3201 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
3202 +
3203 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
3204 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
3205 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
3206 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
3207 +
3208 +
3209 +/* The actual config space */
3210 +
3211 +#define PCI_BAR_MAX 6
3212 +
3213 +#define PCI_ROM_BAR 8
3214 +
3215 +#define PCR_RSVDA_MAX 2
3216 +
3217 +/* pci config status reg has a bit to indicate that capability ptr is present*/
3218 +
3219 +#define PCI_CAPPTR_PRESENT 0x0010
3220 +
3221 +typedef struct _pci_config_regs {
3222 + unsigned short vendor;
3223 + unsigned short device;
3224 + unsigned short command;
3225 + unsigned short status;
3226 + unsigned char rev_id;
3227 + unsigned char prog_if;
3228 + unsigned char sub_class;
3229 + unsigned char base_class;
3230 + unsigned char cache_line_size;
3231 + unsigned char latency_timer;
3232 + unsigned char header_type;
3233 + unsigned char bist;
3234 + unsigned long base[PCI_BAR_MAX];
3235 + unsigned long cardbus_cis;
3236 + unsigned short subsys_vendor;
3237 + unsigned short subsys_id;
3238 + unsigned long baserom;
3239 + unsigned long rsvd_a[PCR_RSVDA_MAX];
3240 + unsigned char int_line;
3241 + unsigned char int_pin;
3242 + unsigned char min_gnt;
3243 + unsigned char max_lat;
3244 + unsigned char dev_dep[192];
3245 +} pci_config_regs;
3246 +
3247 +#define SZPCR (sizeof (pci_config_regs))
3248 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
3249 +
3250 +/* A structure for the config registers is nice, but in most
3251 + * systems the config space is not memory mapped, so we need
3252 + * filed offsetts. :-(
3253 + */
3254 +#define PCI_CFG_VID 0
3255 +#define PCI_CFG_DID 2
3256 +#define PCI_CFG_CMD 4
3257 +#define PCI_CFG_STAT 6
3258 +#define PCI_CFG_REV 8
3259 +#define PCI_CFG_PROGIF 9
3260 +#define PCI_CFG_SUBCL 0xa
3261 +#define PCI_CFG_BASECL 0xb
3262 +#define PCI_CFG_CLSZ 0xc
3263 +#define PCI_CFG_LATTIM 0xd
3264 +#define PCI_CFG_HDR 0xe
3265 +#define PCI_CFG_BIST 0xf
3266 +#define PCI_CFG_BAR0 0x10
3267 +#define PCI_CFG_BAR1 0x14
3268 +#define PCI_CFG_BAR2 0x18
3269 +#define PCI_CFG_BAR3 0x1c
3270 +#define PCI_CFG_BAR4 0x20
3271 +#define PCI_CFG_BAR5 0x24
3272 +#define PCI_CFG_CIS 0x28
3273 +#define PCI_CFG_SVID 0x2c
3274 +#define PCI_CFG_SSID 0x2e
3275 +#define PCI_CFG_ROMBAR 0x30
3276 +#define PCI_CFG_CAPPTR 0x34
3277 +#define PCI_CFG_INT 0x3c
3278 +#define PCI_CFG_PIN 0x3d
3279 +#define PCI_CFG_MINGNT 0x3e
3280 +#define PCI_CFG_MAXLAT 0x3f
3281 +
3282 +/* Classes and subclasses */
3283 +
3284 +typedef enum {
3285 + PCI_CLASS_OLD = 0,
3286 + PCI_CLASS_DASDI,
3287 + PCI_CLASS_NET,
3288 + PCI_CLASS_DISPLAY,
3289 + PCI_CLASS_MMEDIA,
3290 + PCI_CLASS_MEMORY,
3291 + PCI_CLASS_BRIDGE,
3292 + PCI_CLASS_COMM,
3293 + PCI_CLASS_BASE,
3294 + PCI_CLASS_INPUT,
3295 + PCI_CLASS_DOCK,
3296 + PCI_CLASS_CPU,
3297 + PCI_CLASS_SERIAL,
3298 + PCI_CLASS_INTELLIGENT = 0xe,
3299 + PCI_CLASS_SATELLITE,
3300 + PCI_CLASS_CRYPT,
3301 + PCI_CLASS_DSP,
3302 + PCI_CLASS_MAX
3303 +} pci_classes;
3304 +
3305 +typedef enum {
3306 + PCI_DASDI_SCSI,
3307 + PCI_DASDI_IDE,
3308 + PCI_DASDI_FLOPPY,
3309 + PCI_DASDI_IPI,
3310 + PCI_DASDI_RAID,
3311 + PCI_DASDI_OTHER = 0x80
3312 +} pci_dasdi_subclasses;
3313 +
3314 +typedef enum {
3315 + PCI_NET_ETHER,
3316 + PCI_NET_TOKEN,
3317 + PCI_NET_FDDI,
3318 + PCI_NET_ATM,
3319 + PCI_NET_OTHER = 0x80
3320 +} pci_net_subclasses;
3321 +
3322 +typedef enum {
3323 + PCI_DISPLAY_VGA,
3324 + PCI_DISPLAY_XGA,
3325 + PCI_DISPLAY_3D,
3326 + PCI_DISPLAY_OTHER = 0x80
3327 +} pci_display_subclasses;
3328 +
3329 +typedef enum {
3330 + PCI_MMEDIA_VIDEO,
3331 + PCI_MMEDIA_AUDIO,
3332 + PCI_MMEDIA_PHONE,
3333 + PCI_MEDIA_OTHER = 0x80
3334 +} pci_mmedia_subclasses;
3335 +
3336 +typedef enum {
3337 + PCI_MEMORY_RAM,
3338 + PCI_MEMORY_FLASH,
3339 + PCI_MEMORY_OTHER = 0x80
3340 +} pci_memory_subclasses;
3341 +
3342 +typedef enum {
3343 + PCI_BRIDGE_HOST,
3344 + PCI_BRIDGE_ISA,
3345 + PCI_BRIDGE_EISA,
3346 + PCI_BRIDGE_MC,
3347 + PCI_BRIDGE_PCI,
3348 + PCI_BRIDGE_PCMCIA,
3349 + PCI_BRIDGE_NUBUS,
3350 + PCI_BRIDGE_CARDBUS,
3351 + PCI_BRIDGE_RACEWAY,
3352 + PCI_BRIDGE_OTHER = 0x80
3353 +} pci_bridge_subclasses;
3354 +
3355 +typedef enum {
3356 + PCI_COMM_UART,
3357 + PCI_COMM_PARALLEL,
3358 + PCI_COMM_MULTIUART,
3359 + PCI_COMM_MODEM,
3360 + PCI_COMM_OTHER = 0x80
3361 +} pci_comm_subclasses;
3362 +
3363 +typedef enum {
3364 + PCI_BASE_PIC,
3365 + PCI_BASE_DMA,
3366 + PCI_BASE_TIMER,
3367 + PCI_BASE_RTC,
3368 + PCI_BASE_PCI_HOTPLUG,
3369 + PCI_BASE_OTHER = 0x80
3370 +} pci_base_subclasses;
3371 +
3372 +typedef enum {
3373 + PCI_INPUT_KBD,
3374 + PCI_INPUT_PEN,
3375 + PCI_INPUT_MOUSE,
3376 + PCI_INPUT_SCANNER,
3377 + PCI_INPUT_GAMEPORT,
3378 + PCI_INPUT_OTHER = 0x80
3379 +} pci_input_subclasses;
3380 +
3381 +typedef enum {
3382 + PCI_DOCK_GENERIC,
3383 + PCI_DOCK_OTHER = 0x80
3384 +} pci_dock_subclasses;
3385 +
3386 +typedef enum {
3387 + PCI_CPU_386,
3388 + PCI_CPU_486,
3389 + PCI_CPU_PENTIUM,
3390 + PCI_CPU_ALPHA = 0x10,
3391 + PCI_CPU_POWERPC = 0x20,
3392 + PCI_CPU_MIPS = 0x30,
3393 + PCI_CPU_COPROC = 0x40,
3394 + PCI_CPU_OTHER = 0x80
3395 +} pci_cpu_subclasses;
3396 +
3397 +typedef enum {
3398 + PCI_SERIAL_IEEE1394,
3399 + PCI_SERIAL_ACCESS,
3400 + PCI_SERIAL_SSA,
3401 + PCI_SERIAL_USB,
3402 + PCI_SERIAL_FIBER,
3403 + PCI_SERIAL_SMBUS,
3404 + PCI_SERIAL_OTHER = 0x80
3405 +} pci_serial_subclasses;
3406 +
3407 +typedef enum {
3408 + PCI_INTELLIGENT_I2O,
3409 +} pci_intelligent_subclasses;
3410 +
3411 +typedef enum {
3412 + PCI_SATELLITE_TV,
3413 + PCI_SATELLITE_AUDIO,
3414 + PCI_SATELLITE_VOICE,
3415 + PCI_SATELLITE_DATA,
3416 + PCI_SATELLITE_OTHER = 0x80
3417 +} pci_satellite_subclasses;
3418 +
3419 +typedef enum {
3420 + PCI_CRYPT_NETWORK,
3421 + PCI_CRYPT_ENTERTAINMENT,
3422 + PCI_CRYPT_OTHER = 0x80
3423 +} pci_crypt_subclasses;
3424 +
3425 +typedef enum {
3426 + PCI_DSP_DPIO,
3427 + PCI_DSP_OTHER = 0x80
3428 +} pci_dsp_subclasses;
3429 +
3430 +/* Header types */
3431 +typedef enum {
3432 + PCI_HEADER_NORMAL,
3433 + PCI_HEADER_BRIDGE,
3434 + PCI_HEADER_CARDBUS
3435 +} pci_header_types;
3436 +
3437 +
3438 +/* Overlay for a PCI-to-PCI bridge */
3439 +
3440 +#define PPB_RSVDA_MAX 2
3441 +#define PPB_RSVDD_MAX 8
3442 +
3443 +typedef struct _ppb_config_regs {
3444 + unsigned short vendor;
3445 + unsigned short device;
3446 + unsigned short command;
3447 + unsigned short status;
3448 + unsigned char rev_id;
3449 + unsigned char prog_if;
3450 + unsigned char sub_class;
3451 + unsigned char base_class;
3452 + unsigned char cache_line_size;
3453 + unsigned char latency_timer;
3454 + unsigned char header_type;
3455 + unsigned char bist;
3456 + unsigned long rsvd_a[PPB_RSVDA_MAX];
3457 + unsigned char prim_bus;
3458 + unsigned char sec_bus;
3459 + unsigned char sub_bus;
3460 + unsigned char sec_lat;
3461 + unsigned char io_base;
3462 + unsigned char io_lim;
3463 + unsigned short sec_status;
3464 + unsigned short mem_base;
3465 + unsigned short mem_lim;
3466 + unsigned short pf_mem_base;
3467 + unsigned short pf_mem_lim;
3468 + unsigned long pf_mem_base_hi;
3469 + unsigned long pf_mem_lim_hi;
3470 + unsigned short io_base_hi;
3471 + unsigned short io_lim_hi;
3472 + unsigned short subsys_vendor;
3473 + unsigned short subsys_id;
3474 + unsigned long rsvd_b;
3475 + unsigned char rsvd_c;
3476 + unsigned char int_pin;
3477 + unsigned short bridge_ctrl;
3478 + unsigned char chip_ctrl;
3479 + unsigned char diag_ctrl;
3480 + unsigned short arb_ctrl;
3481 + unsigned long rsvd_d[PPB_RSVDD_MAX];
3482 + unsigned char dev_dep[192];
3483 +} ppb_config_regs;
3484 +
3485 +
3486 +/* PCI CAPABILITY DEFINES */
3487 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
3488 +#define PCI_CAP_MSICAP_ID 0x05
3489 +#define PCI_CAP_PCIECAP_ID 0x10
3490 +
3491 +/* Data structure to define the Message Signalled Interrupt facility
3492 + * Valid for PCI and PCIE configurations */
3493 +typedef struct _pciconfig_cap_msi {
3494 + unsigned char capID;
3495 + unsigned char nextptr;
3496 + unsigned short msgctrl;
3497 + unsigned int msgaddr;
3498 +} pciconfig_cap_msi;
3499 +
3500 +/* Data structure to define the Power managment facility
3501 + * Valid for PCI and PCIE configurations */
3502 +typedef struct _pciconfig_cap_pwrmgmt {
3503 + unsigned char capID;
3504 + unsigned char nextptr;
3505 + unsigned short pme_cap;
3506 + unsigned short pme_sts_ctrl;
3507 + unsigned char pme_bridge_ext;
3508 + unsigned char data;
3509 +} pciconfig_cap_pwrmgmt;
3510 +
3511 +/* Data structure to define the PCIE capability */
3512 +typedef struct _pciconfig_cap_pcie {
3513 + unsigned char capID;
3514 + unsigned char nextptr;
3515 + unsigned short pcie_cap;
3516 + unsigned int dev_cap;
3517 + unsigned short dev_ctrl;
3518 + unsigned short dev_status;
3519 + unsigned int link_cap;
3520 + unsigned short link_ctrl;
3521 + unsigned short link_status;
3522 +} pciconfig_cap_pcie;
3523 +
3524 +/* PCIE Enhanced CAPABILITY DEFINES */
3525 +#define PCIE_EXTCFG_OFFSET 0x100
3526 +#define PCIE_ADVERRREP_CAPID 0x0001
3527 +#define PCIE_VC_CAPID 0x0002
3528 +#define PCIE_DEVSNUM_CAPID 0x0003
3529 +#define PCIE_PWRBUDGET_CAPID 0x0004
3530 +
3531 +/* Header to define the PCIE specific capabilities in the extended config space */
3532 +typedef struct _pcie_enhanced_caphdr {
3533 + unsigned short capID;
3534 + unsigned short cap_ver : 4;
3535 + unsigned short next_ptr : 12;
3536 +} pcie_enhanced_caphdr;
3537 +
3538 +
3539 +/* Everything below is BRCM HND proprietary */
3540 +
3541 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
3542 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
3543 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
3544 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
3545 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
3546 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
3547 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
3548 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
3549 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
3550 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
3551 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
3552 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
3553 +
3554 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
3555 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
3556 +
3557 +/* PCI_INT_STATUS */
3558 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
3559 +
3560 +/* PCI_INT_MASK */
3561 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
3562 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
3563 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
3564 +
3565 +/* PCI_SPROM_CONTROL */
3566 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
3567 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
3568 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
3569 +
3570 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
3571 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
3572 +
3573 +/* PCI_CFG_CMD_STAT */
3574 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
3575 +
3576 +#endif
3577 diff -Naur linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
3578 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
3579 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-04-06 15:34:14.000000000 +0200
3580 @@ -0,0 +1,440 @@
3581 +/*
3582 + * SiliconBackplane Chipcommon core hardware definitions.
3583 + *
3584 + * The chipcommon core provides chip identification, SB control,
3585 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
3586 + * gpio interface, extbus, and support for serial and parallel flashes.
3587 + *
3588 + * $Id$
3589 + * Copyright 2005, Broadcom Corporation
3590 + * All Rights Reserved.
3591 + *
3592 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3593 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3594 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3595 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3596 + *
3597 + */
3598 +
3599 +#ifndef _SBCHIPC_H
3600 +#define _SBCHIPC_H
3601 +
3602 +
3603 +#ifndef _LANGUAGE_ASSEMBLY
3604 +
3605 +/* cpp contortions to concatenate w/arg prescan */
3606 +#ifndef PAD
3607 +#define _PADLINE(line) pad ## line
3608 +#define _XSTR(line) _PADLINE(line)
3609 +#define PAD _XSTR(__LINE__)
3610 +#endif /* PAD */
3611 +
3612 +typedef volatile struct {
3613 + uint32 chipid; /* 0x0 */
3614 + uint32 capabilities;
3615 + uint32 corecontrol; /* corerev >= 1 */
3616 + uint32 bist;
3617 +
3618 + /* OTP */
3619 + uint32 otpstatus; /* 0x10, corerev >= 10 */
3620 + uint32 otpcontrol;
3621 + uint32 otpprog;
3622 + uint32 PAD;
3623 +
3624 + /* Interrupt control */
3625 + uint32 intstatus; /* 0x20 */
3626 + uint32 intmask;
3627 + uint32 chipcontrol; /* 0x28, rev >= 11 */
3628 + uint32 chipstatus; /* 0x2c, rev >= 11 */
3629 +
3630 + /* Jtag Master */
3631 + uint32 jtagcmd; /* 0x30, rev >= 10 */
3632 + uint32 jtagir;
3633 + uint32 jtagdr;
3634 + uint32 jtagctrl;
3635 +
3636 + /* serial flash interface registers */
3637 + uint32 flashcontrol; /* 0x40 */
3638 + uint32 flashaddress;
3639 + uint32 flashdata;
3640 + uint32 PAD[1];
3641 +
3642 + /* Silicon backplane configuration broadcast control */
3643 + uint32 broadcastaddress; /* 0x50 */
3644 + uint32 broadcastdata;
3645 + uint32 PAD[2];
3646 +
3647 + /* gpio - cleared only by power-on-reset */
3648 + uint32 gpioin; /* 0x60 */
3649 + uint32 gpioout;
3650 + uint32 gpioouten;
3651 + uint32 gpiocontrol;
3652 + uint32 gpiointpolarity;
3653 + uint32 gpiointmask;
3654 + uint32 PAD[2];
3655 +
3656 + /* Watchdog timer */
3657 + uint32 watchdog; /* 0x80 */
3658 + uint32 PAD[1];
3659 +
3660 + /*GPIO based LED powersave registers corerev >= 16*/
3661 + uint32 gpiotimerval; /*0x88 */
3662 + uint32 gpiotimeroutmask;
3663 +
3664 + /* clock control */
3665 + uint32 clockcontrol_n; /* 0x90 */
3666 + uint32 clockcontrol_sb; /* aka m0 */
3667 + uint32 clockcontrol_pci; /* aka m1 */
3668 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
3669 + uint32 clockcontrol_mips; /* aka m3 */
3670 + uint32 clkdiv; /* corerev >= 3 */
3671 + uint32 PAD[2];
3672 +
3673 + /* pll delay registers (corerev >= 4) */
3674 + uint32 pll_on_delay; /* 0xb0 */
3675 + uint32 fref_sel_delay;
3676 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
3677 + uint32 PAD[1];
3678 +
3679 + /* Instaclock registers (corerev >= 10) */
3680 + uint32 system_clk_ctl; /* 0xc0 */
3681 + uint32 clkstatestretch;
3682 + uint32 PAD[14];
3683 +
3684 + /* ExtBus control registers (corerev >= 3) */
3685 + uint32 pcmcia_config; /* 0x100 */
3686 + uint32 pcmcia_memwait;
3687 + uint32 pcmcia_attrwait;
3688 + uint32 pcmcia_iowait;
3689 + uint32 ide_config;
3690 + uint32 ide_memwait;
3691 + uint32 ide_attrwait;
3692 + uint32 ide_iowait;
3693 + uint32 prog_config;
3694 + uint32 prog_waitcount;
3695 + uint32 flash_config;
3696 + uint32 flash_waitcount;
3697 + uint32 PAD[116];
3698 +
3699 + /* uarts */
3700 + uint8 uart0data; /* 0x300 */
3701 + uint8 uart0imr;
3702 + uint8 uart0fcr;
3703 + uint8 uart0lcr;
3704 + uint8 uart0mcr;
3705 + uint8 uart0lsr;
3706 + uint8 uart0msr;
3707 + uint8 uart0scratch;
3708 + uint8 PAD[248]; /* corerev >= 1 */
3709 +
3710 + uint8 uart1data; /* 0x400 */
3711 + uint8 uart1imr;
3712 + uint8 uart1fcr;
3713 + uint8 uart1lcr;
3714 + uint8 uart1mcr;
3715 + uint8 uart1lsr;
3716 + uint8 uart1msr;
3717 + uint8 uart1scratch;
3718 +} chipcregs_t;
3719 +
3720 +#endif /* _LANGUAGE_ASSEMBLY */
3721 +
3722 +#define CC_CHIPID 0
3723 +#define CC_CAPABILITIES 4
3724 +#define CC_JTAGCMD 0x30
3725 +#define CC_JTAGIR 0x34
3726 +#define CC_JTAGDR 0x38
3727 +#define CC_JTAGCTRL 0x3c
3728 +#define CC_WATCHDOG 0x80
3729 +#define CC_CLKC_N 0x90
3730 +#define CC_CLKC_M0 0x94
3731 +#define CC_CLKC_M1 0x98
3732 +#define CC_CLKC_M2 0x9c
3733 +#define CC_CLKC_M3 0xa0
3734 +#define CC_CLKDIV 0xa4
3735 +#define CC_SYS_CLK_CTL 0xc0
3736 +#define CC_OTP 0x800
3737 +
3738 +/* chipid */
3739 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
3740 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
3741 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
3742 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
3743 +#define CID_PKG_SHIFT 20 /* Package Option shift */
3744 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
3745 +#define CID_CC_SHIFT 24
3746 +
3747 +/* capabilities */
3748 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
3749 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
3750 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
3751 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
3752 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
3753 +#define CAP_EXTBUS 0x00000040 /* External bus present */
3754 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
3755 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
3756 +#define CAP_PWR_CTL 0x00040000 /* Power control */
3757 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
3758 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
3759 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
3760 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
3761 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
3762 +
3763 +/* PLL type */
3764 +#define PLL_NONE 0x00000000
3765 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
3766 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
3767 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
3768 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
3769 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
3770 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
3771 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
3772 +
3773 +/* corecontrol */
3774 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
3775 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3776 +
3777 +/* Fields in the otpstatus register */
3778 +#define OTPS_PROGFAIL 0x80000000
3779 +#define OTPS_PROTECT 0x00000007
3780 +#define OTPS_HW_PROTECT 0x00000001
3781 +#define OTPS_SW_PROTECT 0x00000002
3782 +#define OTPS_CID_PROTECT 0x00000004
3783 +
3784 +/* Fields in the otpcontrol register */
3785 +#define OTPC_RECWAIT 0xff000000
3786 +#define OTPC_PROGWAIT 0x00ffff00
3787 +#define OTPC_PRW_SHIFT 8
3788 +#define OTPC_MAXFAIL 0x00000038
3789 +#define OTPC_VSEL 0x00000006
3790 +#define OTPC_SELVL 0x00000001
3791 +
3792 +/* Fields in otpprog */
3793 +#define OTPP_COL_MASK 0x000000ff
3794 +#define OTPP_ROW_MASK 0x0000ff00
3795 +#define OTPP_ROW_SHIFT 8
3796 +#define OTPP_READERR 0x10000000
3797 +#define OTPP_VALUE 0x20000000
3798 +#define OTPP_VALUE_SHIFT 29
3799 +#define OTPP_READ 0x40000000
3800 +#define OTPP_START 0x80000000
3801 +#define OTPP_BUSY 0x80000000
3802 +
3803 +/* jtagcmd */
3804 +#define JCMD_START 0x80000000
3805 +#define JCMD_BUSY 0x80000000
3806 +#define JCMD_PAUSE 0x40000000
3807 +#define JCMD0_ACC_MASK 0x0000f000
3808 +#define JCMD0_ACC_IRDR 0x00000000
3809 +#define JCMD0_ACC_DR 0x00001000
3810 +#define JCMD0_ACC_IR 0x00002000
3811 +#define JCMD0_ACC_RESET 0x00003000
3812 +#define JCMD0_ACC_IRPDR 0x00004000
3813 +#define JCMD0_ACC_PDR 0x00005000
3814 +#define JCMD0_IRW_MASK 0x00000f00
3815 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
3816 +#define JCMD_ACC_IRDR 0x00000000
3817 +#define JCMD_ACC_DR 0x00010000
3818 +#define JCMD_ACC_IR 0x00020000
3819 +#define JCMD_ACC_RESET 0x00030000
3820 +#define JCMD_ACC_IRPDR 0x00040000
3821 +#define JCMD_ACC_PDR 0x00050000
3822 +#define JCMD_IRW_MASK 0x00001f00
3823 +#define JCMD_IRW_SHIFT 8
3824 +#define JCMD_DRW_MASK 0x0000003f
3825 +
3826 +/* jtagctrl */
3827 +#define JCTRL_FORCE_CLK 4 /* Force clock */
3828 +#define JCTRL_EXT_EN 2 /* Enable external targets */
3829 +#define JCTRL_EN 1 /* Enable Jtag master */
3830 +
3831 +/* Fields in clkdiv */
3832 +#define CLKD_SFLASH 0x0f000000
3833 +#define CLKD_SFLASH_SHIFT 24
3834 +#define CLKD_OTP 0x000f0000
3835 +#define CLKD_OTP_SHIFT 16
3836 +#define CLKD_JTAG 0x00000f00
3837 +#define CLKD_JTAG_SHIFT 8
3838 +#define CLKD_UART 0x000000ff
3839 +
3840 +/* intstatus/intmask */
3841 +#define CI_GPIO 0x00000001 /* gpio intr */
3842 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
3843 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
3844 +
3845 +/* slow_clk_ctl */
3846 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
3847 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
3848 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
3849 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
3850 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
3851 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
3852 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
3853 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
3854 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
3855 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
3856 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
3857 +#define SCC_CD_SHIFT 16
3858 +
3859 +/* system_clk_ctl */
3860 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
3861 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
3862 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
3863 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
3864 +#define SYCC_HR 0x00000010 /* Force HT */
3865 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
3866 +#define SYCC_CD_SHIFT 16
3867 +
3868 +/* gpiotimerval*/
3869 +#define GPIO_ONTIME_SHIFT 16
3870 +
3871 +/* clockcontrol_n */
3872 +#define CN_N1_MASK 0x3f /* n1 control */
3873 +#define CN_N2_MASK 0x3f00 /* n2 control */
3874 +#define CN_N2_SHIFT 8
3875 +#define CN_PLLC_MASK 0xf0000 /* pll control */
3876 +#define CN_PLLC_SHIFT 16
3877 +
3878 +/* clockcontrol_sb/pci/uart */
3879 +#define CC_M1_MASK 0x3f /* m1 control */
3880 +#define CC_M2_MASK 0x3f00 /* m2 control */
3881 +#define CC_M2_SHIFT 8
3882 +#define CC_M3_MASK 0x3f0000 /* m3 control */
3883 +#define CC_M3_SHIFT 16
3884 +#define CC_MC_MASK 0x1f000000 /* mux control */
3885 +#define CC_MC_SHIFT 24
3886 +
3887 +/* N3M Clock control magic field values */
3888 +#define CC_F6_2 0x02 /* A factor of 2 in */
3889 +#define CC_F6_3 0x03 /* 6-bit fields like */
3890 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
3891 +#define CC_F6_5 0x09
3892 +#define CC_F6_6 0x11
3893 +#define CC_F6_7 0x21
3894 +
3895 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
3896 +
3897 +#define CC_MC_BYPASS 0x08
3898 +#define CC_MC_M1 0x04
3899 +#define CC_MC_M1M2 0x02
3900 +#define CC_MC_M1M2M3 0x01
3901 +#define CC_MC_M1M3 0x11
3902 +
3903 +/* Type 2 Clock control magic field values */
3904 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
3905 +#define CC_T2M2_BIAS 3 /* m2 bias */
3906 +
3907 +#define CC_T2MC_M1BYP 1
3908 +#define CC_T2MC_M2BYP 2
3909 +#define CC_T2MC_M3BYP 4
3910 +
3911 +/* Type 6 Clock control magic field values */
3912 +#define CC_T6_MMASK 1 /* bits of interest in m */
3913 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
3914 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
3915 +#define SB2MIPS_T6(sb) (2 * (sb))
3916 +
3917 +/* Common clock base */
3918 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
3919 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
3920 +
3921 +/* Clock control values for 200Mhz in 5350 */
3922 +#define CLKC_5350_N 0x0311
3923 +#define CLKC_5350_M 0x04020009
3924 +
3925 +/* Flash types in the chipcommon capabilities register */
3926 +#define FLASH_NONE 0x000 /* No flash */
3927 +#define SFLASH_ST 0x100 /* ST serial flash */
3928 +#define SFLASH_AT 0x200 /* Atmel serial flash */
3929 +#define PFLASH 0x700 /* Parallel flash */
3930 +
3931 +/* Bits in the config registers */
3932 +#define CC_CFG_EN 0x0001 /* Enable */
3933 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
3934 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
3935 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
3936 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
3937 +#define CC_CFG_EM_IDE 0x000a /* IDE */
3938 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
3939 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
3940 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
3941 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
3942 +
3943 +/* Start/busy bit in flashcontrol */
3944 +#define SFLASH_START 0x80000000
3945 +#define SFLASH_BUSY SFLASH_START
3946 +
3947 +/* flashcontrol opcodes for ST flashes */
3948 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
3949 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
3950 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
3951 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
3952 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
3953 +#define SFLASH_ST_PP 0x0302 /* Page Program */
3954 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
3955 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
3956 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
3957 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
3958 +
3959 +/* Status register bits for ST flashes */
3960 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
3961 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
3962 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
3963 +#define SFLASH_ST_BP_SHIFT 2
3964 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
3965 +
3966 +/* flashcontrol opcodes for Atmel flashes */
3967 +#define SFLASH_AT_READ 0x07e8
3968 +#define SFLASH_AT_PAGE_READ 0x07d2
3969 +#define SFLASH_AT_BUF1_READ
3970 +#define SFLASH_AT_BUF2_READ
3971 +#define SFLASH_AT_STATUS 0x01d7
3972 +#define SFLASH_AT_BUF1_WRITE 0x0384
3973 +#define SFLASH_AT_BUF2_WRITE 0x0387
3974 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
3975 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
3976 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
3977 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
3978 +#define SFLASH_AT_PAGE_ERASE 0x0281
3979 +#define SFLASH_AT_BLOCK_ERASE 0x0250
3980 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
3981 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
3982 +#define SFLASH_AT_BUF1_LOAD 0x0253
3983 +#define SFLASH_AT_BUF2_LOAD 0x0255
3984 +#define SFLASH_AT_BUF1_COMPARE 0x0260
3985 +#define SFLASH_AT_BUF2_COMPARE 0x0261
3986 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
3987 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
3988 +
3989 +/* Status register bits for Atmel flashes */
3990 +#define SFLASH_AT_READY 0x80
3991 +#define SFLASH_AT_MISMATCH 0x40
3992 +#define SFLASH_AT_ID_MASK 0x38
3993 +#define SFLASH_AT_ID_SHIFT 3
3994 +
3995 +/* OTP regions */
3996 +#define OTP_HW_REGION OTPS_HW_PROTECT
3997 +#define OTP_SW_REGION OTPS_SW_PROTECT
3998 +#define OTP_CID_REGION OTPS_CID_PROTECT
3999 +
4000 +/* OTP regions (Byte offsets from otp size) */
4001 +#define OTP_SWLIM_OFF (-8)
4002 +#define OTP_CIDBASE_OFF 0
4003 +#define OTP_CIDLIM_OFF 8
4004 +
4005 +/* Predefined OTP words (Word offset from otp size) */
4006 +#define OTP_BOUNDARY_OFF (-4)
4007 +#define OTP_HWSIGN_OFF (-3)
4008 +#define OTP_SWSIGN_OFF (-2)
4009 +#define OTP_CIDSIGN_OFF (-1)
4010 +
4011 +#define OTP_CID_OFF 0
4012 +#define OTP_PKG_OFF 1
4013 +#define OTP_FID_OFF 2
4014 +#define OTP_RSV_OFF 3
4015 +#define OTP_LIM_OFF 4
4016 +
4017 +#define OTP_SIGNATURE 0x578a
4018 +#define OTP_MAGIC 0x4e56
4019 +
4020 +#endif /* _SBCHIPC_H */
4021 diff -Naur linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
4022 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
4023 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-04-06 15:34:14.000000000 +0200
4024 @@ -0,0 +1,342 @@
4025 +/*
4026 + * Broadcom SiliconBackplane hardware register definitions.
4027 + *
4028 + * Copyright 2005, Broadcom Corporation
4029 + * All Rights Reserved.
4030 + *
4031 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4032 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4033 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4034 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4035 + * $Id$
4036 + */
4037 +
4038 +#ifndef _SBCONFIG_H
4039 +#define _SBCONFIG_H
4040 +
4041 +/* cpp contortions to concatenate w/arg prescan */
4042 +#ifndef PAD
4043 +#define _PADLINE(line) pad ## line
4044 +#define _XSTR(line) _PADLINE(line)
4045 +#define PAD _XSTR(__LINE__)
4046 +#endif
4047 +
4048 +/*
4049 + * SiliconBackplane Address Map.
4050 + * All regions may not exist on all chips.
4051 + */
4052 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
4053 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
4054 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
4055 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
4056 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
4057 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
4058 +
4059 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
4060 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
4061 +
4062 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
4063 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
4064 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
4065 +
4066 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
4067 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
4068 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
4069 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
4070 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
4071 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
4072 +
4073 +
4074 +/* enumeration space related defs */
4075 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
4076 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
4077 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
4078 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
4079 +
4080 +/* mips address */
4081 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
4082 +
4083 +/*
4084 + * Sonics Configuration Space Registers.
4085 + */
4086 +#define SBIPSFLAG 0x08
4087 +#define SBTPSFLAG 0x18
4088 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
4089 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
4090 +#define SBADMATCH3 0x60
4091 +#define SBADMATCH2 0x68
4092 +#define SBADMATCH1 0x70
4093 +#define SBIMSTATE 0x90
4094 +#define SBINTVEC 0x94
4095 +#define SBTMSTATELOW 0x98
4096 +#define SBTMSTATEHIGH 0x9c
4097 +#define SBBWA0 0xa0
4098 +#define SBIMCONFIGLOW 0xa8
4099 +#define SBIMCONFIGHIGH 0xac
4100 +#define SBADMATCH0 0xb0
4101 +#define SBTMCONFIGLOW 0xb8
4102 +#define SBTMCONFIGHIGH 0xbc
4103 +#define SBBCONFIG 0xc0
4104 +#define SBBSTATE 0xc8
4105 +#define SBACTCNFG 0xd8
4106 +#define SBFLAGST 0xe8
4107 +#define SBIDLOW 0xf8
4108 +#define SBIDHIGH 0xfc
4109 +
4110 +#ifndef _LANGUAGE_ASSEMBLY
4111 +
4112 +typedef volatile struct _sbconfig {
4113 + uint32 PAD[2];
4114 + uint32 sbipsflag; /* initiator port ocp slave flag */
4115 + uint32 PAD[3];
4116 + uint32 sbtpsflag; /* target port ocp slave flag */
4117 + uint32 PAD[11];
4118 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
4119 + uint32 PAD;
4120 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
4121 + uint32 PAD[3];
4122 + uint32 sbadmatch3; /* address match3 */
4123 + uint32 PAD;
4124 + uint32 sbadmatch2; /* address match2 */
4125 + uint32 PAD;
4126 + uint32 sbadmatch1; /* address match1 */
4127 + uint32 PAD[7];
4128 + uint32 sbimstate; /* initiator agent state */
4129 + uint32 sbintvec; /* interrupt mask */
4130 + uint32 sbtmstatelow; /* target state */
4131 + uint32 sbtmstatehigh; /* target state */
4132 + uint32 sbbwa0; /* bandwidth allocation table0 */
4133 + uint32 PAD;
4134 + uint32 sbimconfiglow; /* initiator configuration */
4135 + uint32 sbimconfighigh; /* initiator configuration */
4136 + uint32 sbadmatch0; /* address match0 */
4137 + uint32 PAD;
4138 + uint32 sbtmconfiglow; /* target configuration */
4139 + uint32 sbtmconfighigh; /* target configuration */
4140 + uint32 sbbconfig; /* broadcast configuration */
4141 + uint32 PAD;
4142 + uint32 sbbstate; /* broadcast state */
4143 + uint32 PAD[3];
4144 + uint32 sbactcnfg; /* activate configuration */
4145 + uint32 PAD[3];
4146 + uint32 sbflagst; /* current sbflags */
4147 + uint32 PAD[3];
4148 + uint32 sbidlow; /* identification */
4149 + uint32 sbidhigh; /* identification */
4150 +} sbconfig_t;
4151 +
4152 +#endif /* _LANGUAGE_ASSEMBLY */
4153 +
4154 +/* sbipsflag */
4155 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
4156 +#define SBIPS_INT1_SHIFT 0
4157 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
4158 +#define SBIPS_INT2_SHIFT 8
4159 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
4160 +#define SBIPS_INT3_SHIFT 16
4161 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
4162 +#define SBIPS_INT4_SHIFT 24
4163 +
4164 +/* sbtpsflag */
4165 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
4166 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
4167 +
4168 +/* sbtmerrlog */
4169 +#define SBTMEL_CM 0x00000007 /* command */
4170 +#define SBTMEL_CI 0x0000ff00 /* connection id */
4171 +#define SBTMEL_EC 0x0f000000 /* error code */
4172 +#define SBTMEL_ME 0x80000000 /* multiple error */
4173 +
4174 +/* sbimstate */
4175 +#define SBIM_PC 0xf /* pipecount */
4176 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
4177 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
4178 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
4179 +#define SBIM_AP_TK 0x20 /* use token only */
4180 +#define SBIM_AP_RSV 0x30 /* reserved */
4181 +#define SBIM_IBE 0x20000 /* inbanderror */
4182 +#define SBIM_TO 0x40000 /* timeout */
4183 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
4184 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
4185 +
4186 +/* sbtmstatelow */
4187 +#define SBTML_RESET 0x1 /* reset */
4188 +#define SBTML_REJ_MASK 0x6 /* reject */
4189 +#define SBTML_REJ_SHIFT 1
4190 +#define SBTML_CLK 0x10000 /* clock enable */
4191 +#define SBTML_FGC 0x20000 /* force gated clocks on */
4192 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
4193 +#define SBTML_PE 0x40000000 /* pme enable */
4194 +#define SBTML_BE 0x80000000 /* bist enable */
4195 +
4196 +/* sbtmstatehigh */
4197 +#define SBTMH_SERR 0x1 /* serror */
4198 +#define SBTMH_INT 0x2 /* interrupt */
4199 +#define SBTMH_BUSY 0x4 /* busy */
4200 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
4201 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
4202 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
4203 +#define SBTMH_GCR 0x20000000 /* gated clock request */
4204 +#define SBTMH_BISTF 0x40000000 /* bist failed */
4205 +#define SBTMH_BISTD 0x80000000 /* bist done */
4206 +
4207 +
4208 +/* sbbwa0 */
4209 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
4210 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
4211 +#define SBBWA_TAB1_SHIFT 16
4212 +
4213 +/* sbimconfiglow */
4214 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
4215 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
4216 +#define SBIMCL_RTO_SHIFT 4
4217 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
4218 +#define SBIMCL_CID_SHIFT 16
4219 +
4220 +/* sbimconfighigh */
4221 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
4222 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
4223 +#define SBIMCH_TEM_SHIFT 4
4224 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
4225 +#define SBIMCH_BEM_SHIFT 6
4226 +
4227 +/* sbadmatch0 */
4228 +#define SBAM_TYPE_MASK 0x3 /* address type */
4229 +#define SBAM_AD64 0x4 /* reserved */
4230 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
4231 +#define SBAM_ADINT0_SHIFT 3
4232 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
4233 +#define SBAM_ADINT1_SHIFT 3
4234 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
4235 +#define SBAM_ADINT2_SHIFT 3
4236 +#define SBAM_ADEN 0x400 /* enable */
4237 +#define SBAM_ADNEG 0x800 /* negative decode */
4238 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
4239 +#define SBAM_BASE0_SHIFT 8
4240 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
4241 +#define SBAM_BASE1_SHIFT 12
4242 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
4243 +#define SBAM_BASE2_SHIFT 16
4244 +
4245 +/* sbtmconfiglow */
4246 +#define SBTMCL_CD_MASK 0xff /* clock divide */
4247 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
4248 +#define SBTMCL_CO_SHIFT 11
4249 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
4250 +#define SBTMCL_IF_SHIFT 18
4251 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
4252 +#define SBTMCL_IM_SHIFT 24
4253 +
4254 +/* sbtmconfighigh */
4255 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
4256 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
4257 +#define SBTMCH_RM_SHIFT 2
4258 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
4259 +#define SBTMCH_SM_SHIFT 4
4260 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
4261 +#define SBTMCH_EM_SHIFT 8
4262 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
4263 +#define SBTMCH_IM_SHIFT 10
4264 +
4265 +/* sbbconfig */
4266 +#define SBBC_LAT_MASK 0x3 /* sb latency */
4267 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
4268 +#define SBBC_MAX0_SHIFT 16
4269 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
4270 +#define SBBC_MAX1_SHIFT 20
4271 +
4272 +/* sbbstate */
4273 +#define SBBS_SRD 0x1 /* st reg disable */
4274 +#define SBBS_HRD 0x2 /* hold reg disable */
4275 +
4276 +/* sbidlow */
4277 +#define SBIDL_CS_MASK 0x3 /* config space */
4278 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
4279 +#define SBIDL_AR_SHIFT 3
4280 +#define SBIDL_SYNCH 0x40 /* sync */
4281 +#define SBIDL_INIT 0x80 /* initiator */
4282 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
4283 +#define SBIDL_MINLAT_SHIFT 8
4284 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
4285 +#define SBIDL_MAXLAT_SHIFT 12
4286 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
4287 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
4288 +#define SBIDL_CW_SHIFT 18
4289 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
4290 +#define SBIDL_TP_SHIFT 20
4291 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
4292 +#define SBIDL_IP_SHIFT 24
4293 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
4294 +#define SBIDL_RV_SHIFT 28
4295 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
4296 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
4297 +
4298 +/* sbidhigh */
4299 +#define SBIDH_RC_MASK 0x000f /* revision code */
4300 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
4301 +#define SBIDH_RCE_SHIFT 8
4302 +#define SBCOREREV(sbidh) \
4303 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
4304 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
4305 +#define SBIDH_CC_SHIFT 4
4306 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
4307 +#define SBIDH_VC_SHIFT 16
4308 +
4309 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
4310 +
4311 +/* vendor codes */
4312 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
4313 +
4314 +/* core codes */
4315 +#define SB_CC 0x800 /* chipcommon core */
4316 +#define SB_ILINE20 0x801 /* iline20 core */
4317 +#define SB_SDRAM 0x803 /* sdram core */
4318 +#define SB_PCI 0x804 /* pci core */
4319 +#define SB_MIPS 0x805 /* mips core */
4320 +#define SB_ENET 0x806 /* enet mac core */
4321 +#define SB_CODEC 0x807 /* v90 codec core */
4322 +#define SB_USB 0x808 /* usb 1.1 host/device core */
4323 +#define SB_ADSL 0x809 /* ADSL core */
4324 +#define SB_ILINE100 0x80a /* iline100 core */
4325 +#define SB_IPSEC 0x80b /* ipsec core */
4326 +#define SB_PCMCIA 0x80d /* pcmcia core */
4327 +#define SB_SOCRAM 0x80e /* internal memory core */
4328 +#define SB_MEMC 0x80f /* memc sdram core */
4329 +#define SB_EXTIF 0x811 /* external interface core */
4330 +#define SB_D11 0x812 /* 802.11 MAC core */
4331 +#define SB_MIPS33 0x816 /* mips3302 core */
4332 +#define SB_USB11H 0x817 /* usb 1.1 host core */
4333 +#define SB_USB11D 0x818 /* usb 1.1 device core */
4334 +#define SB_USB20H 0x819 /* usb 2.0 host core */
4335 +#define SB_USB20D 0x81a /* usb 2.0 device core */
4336 +#define SB_SDIOH 0x81b /* sdio host core */
4337 +#define SB_ROBO 0x81c /* roboswitch core */
4338 +#define SB_ATA100 0x81d /* parallel ATA core */
4339 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
4340 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
4341 +#define SB_PCIE 0x820 /* pci express core */
4342 +#define SB_SRAMC 0x822 /* SRAM controller core */
4343 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
4344 +
4345 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
4346 +
4347 +/* Not really related to Silicon Backplane, but a couple of software
4348 + * conventions for the use the flash space:
4349 + */
4350 +
4351 +/* Minumum amount of flash we support */
4352 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
4353 +
4354 +/* A boot/binary may have an embedded block that describes its size */
4355 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
4356 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
4357 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
4358 +#define BISZ_TXTST_IDX 1 /* 1: text start */
4359 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
4360 +#define BISZ_DATAST_IDX 3 /* 3: text start */
4361 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
4362 +#define BISZ_BSSST_IDX 5 /* 5: text start */
4363 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
4364 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
4365 +
4366 +#endif /* _SBCONFIG_H */
4367 diff -Naur linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
4368 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
4369 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-04-06 15:34:14.000000000 +0200
4370 @@ -0,0 +1,242 @@
4371 +/*
4372 + * Hardware-specific External Interface I/O core definitions
4373 + * for the BCM47xx family of SiliconBackplane-based chips.
4374 + *
4375 + * The External Interface core supports a total of three external chip selects
4376 + * supporting external interfaces. One of the external chip selects is
4377 + * used for Flash, one is used for PCMCIA, and the other may be
4378 + * programmed to support either a synchronous interface or an
4379 + * asynchronous interface. The asynchronous interface can be used to
4380 + * support external devices such as UARTs and the BCM2019 Bluetooth
4381 + * baseband processor.
4382 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
4383 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
4384 + *
4385 + * Copyright 2005, Broadcom Corporation
4386 + * All Rights Reserved.
4387 + *
4388 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4389 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4390 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4391 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4392 + * $Id$
4393 + */
4394 +
4395 +#ifndef _SBEXTIF_H
4396 +#define _SBEXTIF_H
4397 +
4398 +/* external interface address space */
4399 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
4400 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
4401 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
4402 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
4403 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
4404 +
4405 +/* cpp contortions to concatenate w/arg prescan */
4406 +#ifndef PAD
4407 +#define _PADLINE(line) pad ## line
4408 +#define _XSTR(line) _PADLINE(line)
4409 +#define PAD _XSTR(__LINE__)
4410 +#endif /* PAD */
4411 +
4412 +/*
4413 + * The multiple instances of output and output enable registers
4414 + * are present to allow driver software for multiple cores to control
4415 + * gpio outputs without needing to share a single register pair.
4416 + */
4417 +struct gpiouser {
4418 + uint32 out;
4419 + uint32 outen;
4420 +};
4421 +#define NGPIOUSER 5
4422 +
4423 +typedef volatile struct {
4424 + uint32 corecontrol;
4425 + uint32 extstatus;
4426 + uint32 PAD[2];
4427 +
4428 + /* pcmcia control registers */
4429 + uint32 pcmcia_config;
4430 + uint32 pcmcia_memwait;
4431 + uint32 pcmcia_attrwait;
4432 + uint32 pcmcia_iowait;
4433 +
4434 + /* programmable interface control registers */
4435 + uint32 prog_config;
4436 + uint32 prog_waitcount;
4437 +
4438 + /* flash control registers */
4439 + uint32 flash_config;
4440 + uint32 flash_waitcount;
4441 + uint32 PAD[4];
4442 +
4443 + uint32 watchdog;
4444 +
4445 + /* clock control */
4446 + uint32 clockcontrol_n;
4447 + uint32 clockcontrol_sb;
4448 + uint32 clockcontrol_pci;
4449 + uint32 clockcontrol_mii;
4450 + uint32 PAD[3];
4451 +
4452 + /* gpio */
4453 + uint32 gpioin;
4454 + struct gpiouser gpio[NGPIOUSER];
4455 + uint32 PAD;
4456 + uint32 ejtagouten;
4457 + uint32 gpiointpolarity;
4458 + uint32 gpiointmask;
4459 + uint32 PAD[153];
4460 +
4461 + uint8 uartdata;
4462 + uint8 PAD[3];
4463 + uint8 uartimer;
4464 + uint8 PAD[3];
4465 + uint8 uartfcr;
4466 + uint8 PAD[3];
4467 + uint8 uartlcr;
4468 + uint8 PAD[3];
4469 + uint8 uartmcr;
4470 + uint8 PAD[3];
4471 + uint8 uartlsr;
4472 + uint8 PAD[3];
4473 + uint8 uartmsr;
4474 + uint8 PAD[3];
4475 + uint8 uartscratch;
4476 + uint8 PAD[3];
4477 +} extifregs_t;
4478 +
4479 +/* corecontrol */
4480 +#define CC_UE (1 << 0) /* uart enable */
4481 +
4482 +/* extstatus */
4483 +#define ES_EM (1 << 0) /* endian mode (ro) */
4484 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
4485 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
4486 +
4487 +/* gpio bit mask */
4488 +#define GPIO_BIT0 (1 << 0)
4489 +#define GPIO_BIT1 (1 << 1)
4490 +#define GPIO_BIT2 (1 << 2)
4491 +#define GPIO_BIT3 (1 << 3)
4492 +#define GPIO_BIT4 (1 << 4)
4493 +#define GPIO_BIT5 (1 << 5)
4494 +#define GPIO_BIT6 (1 << 6)
4495 +#define GPIO_BIT7 (1 << 7)
4496 +
4497 +
4498 +/* pcmcia/prog/flash_config */
4499 +#define CF_EN (1 << 0) /* enable */
4500 +#define CF_EM_MASK 0xe /* mode */
4501 +#define CF_EM_SHIFT 1
4502 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
4503 +#define CF_EM_SYNC 0x2 /* synchronous mode */
4504 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
4505 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
4506 +#define CF_BS (1 << 5) /* byteswap */
4507 +#define CF_CD_MASK 0xc0 /* clock divider */
4508 +#define CF_CD_SHIFT 6
4509 +#define CF_CD_DIV2 0x0 /* backplane/2 */
4510 +#define CF_CD_DIV3 0x40 /* backplane/3 */
4511 +#define CF_CD_DIV4 0x80 /* backplane/4 */
4512 +#define CF_CE (1 << 8) /* clock enable */
4513 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
4514 +
4515 +/* pcmcia_memwait */
4516 +#define PM_W0_MASK 0x3f /* waitcount0 */
4517 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
4518 +#define PM_W1_SHIFT 8
4519 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
4520 +#define PM_W2_SHIFT 16
4521 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
4522 +#define PM_W3_SHIFT 24
4523 +
4524 +/* pcmcia_attrwait */
4525 +#define PA_W0_MASK 0x3f /* waitcount0 */
4526 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
4527 +#define PA_W1_SHIFT 8
4528 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
4529 +#define PA_W2_SHIFT 16
4530 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
4531 +#define PA_W3_SHIFT 24
4532 +
4533 +/* pcmcia_iowait */
4534 +#define PI_W0_MASK 0x3f /* waitcount0 */
4535 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
4536 +#define PI_W1_SHIFT 8
4537 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
4538 +#define PI_W2_SHIFT 16
4539 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
4540 +#define PI_W3_SHIFT 24
4541 +
4542 +/* prog_waitcount */
4543 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
4544 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
4545 +#define PW_W1_SHIFT 8
4546 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
4547 +#define PW_W2_SHIFT 16
4548 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
4549 +#define PW_W3_SHIFT 24
4550 +
4551 +#define PW_W0 0x0000000c
4552 +#define PW_W1 0x00000a00
4553 +#define PW_W2 0x00020000
4554 +#define PW_W3 0x01000000
4555 +
4556 +/* flash_waitcount */
4557 +#define FW_W0_MASK 0x1f /* waitcount0 */
4558 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
4559 +#define FW_W1_SHIFT 8
4560 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
4561 +#define FW_W2_SHIFT 16
4562 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
4563 +#define FW_W3_SHIFT 24
4564 +
4565 +/* watchdog */
4566 +#define WATCHDOG_CLOCK 48000000 /* Hz */
4567 +
4568 +/* clockcontrol_n */
4569 +#define CN_N1_MASK 0x3f /* n1 control */
4570 +#define CN_N2_MASK 0x3f00 /* n2 control */
4571 +#define CN_N2_SHIFT 8
4572 +
4573 +/* clockcontrol_sb/pci/mii */
4574 +#define CC_M1_MASK 0x3f /* m1 control */
4575 +#define CC_M2_MASK 0x3f00 /* m2 control */
4576 +#define CC_M2_SHIFT 8
4577 +#define CC_M3_MASK 0x3f0000 /* m3 control */
4578 +#define CC_M3_SHIFT 16
4579 +#define CC_MC_MASK 0x1f000000 /* mux control */
4580 +#define CC_MC_SHIFT 24
4581 +
4582 +/* Clock control default values */
4583 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
4584 +#define CC_DEF_100 0x04020011
4585 +#define CC_DEF_33 0x11030011
4586 +#define CC_DEF_25 0x11050011
4587 +
4588 +/* Clock control values for 125Mhz */
4589 +#define CC_125_N 0x0802
4590 +#define CC_125_M 0x04020009
4591 +#define CC_125_M25 0x11090009
4592 +#define CC_125_M33 0x11090005
4593 +
4594 +/* Clock control magic field values */
4595 +#define CC_F6_2 0x02 /* A factor of 2 in */
4596 +#define CC_F6_3 0x03 /* 6-bit fields like */
4597 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
4598 +#define CC_F6_5 0x09
4599 +#define CC_F6_6 0x11
4600 +#define CC_F6_7 0x21
4601 +
4602 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
4603 +
4604 +#define CC_MC_BYPASS 0x08
4605 +#define CC_MC_M1 0x04
4606 +#define CC_MC_M1M2 0x02
4607 +#define CC_MC_M1M2M3 0x01
4608 +#define CC_MC_M1M3 0x11
4609 +
4610 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
4611 +
4612 +#endif /* _SBEXTIF_H */
4613 diff -Naur linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
4614 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
4615 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-04-06 15:34:14.000000000 +0200
4616 @@ -0,0 +1,148 @@
4617 +/*
4618 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
4619 + *
4620 + * Copyright 2005, Broadcom Corporation
4621 + * All Rights Reserved.
4622 + *
4623 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4624 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4625 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4626 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4627 + *
4628 + * $Id$
4629 + */
4630 +
4631 +#ifndef _SBMEMC_H
4632 +#define _SBMEMC_H
4633 +
4634 +#ifdef _LANGUAGE_ASSEMBLY
4635 +
4636 +#define MEMC_CONTROL 0x00
4637 +#define MEMC_CONFIG 0x04
4638 +#define MEMC_REFRESH 0x08
4639 +#define MEMC_BISTSTAT 0x0c
4640 +#define MEMC_MODEBUF 0x10
4641 +#define MEMC_BKCLS 0x14
4642 +#define MEMC_PRIORINV 0x18
4643 +#define MEMC_DRAMTIM 0x1c
4644 +#define MEMC_INTSTAT 0x20
4645 +#define MEMC_INTMASK 0x24
4646 +#define MEMC_INTINFO 0x28
4647 +#define MEMC_NCDLCTL 0x30
4648 +#define MEMC_RDNCDLCOR 0x34
4649 +#define MEMC_WRNCDLCOR 0x38
4650 +#define MEMC_MISCDLYCTL 0x3c
4651 +#define MEMC_DQSGATENCDL 0x40
4652 +#define MEMC_SPARE 0x44
4653 +#define MEMC_TPADDR 0x48
4654 +#define MEMC_TPDATA 0x4c
4655 +#define MEMC_BARRIER 0x50
4656 +#define MEMC_CORE 0x54
4657 +
4658 +
4659 +#else
4660 +
4661 +/* Sonics side: MEMC core registers */
4662 +typedef volatile struct sbmemcregs {
4663 + uint32 control;
4664 + uint32 config;
4665 + uint32 refresh;
4666 + uint32 biststat;
4667 + uint32 modebuf;
4668 + uint32 bkcls;
4669 + uint32 priorinv;
4670 + uint32 dramtim;
4671 + uint32 intstat;
4672 + uint32 intmask;
4673 + uint32 intinfo;
4674 + uint32 reserved1;
4675 + uint32 ncdlctl;
4676 + uint32 rdncdlcor;
4677 + uint32 wrncdlcor;
4678 + uint32 miscdlyctl;
4679 + uint32 dqsgatencdl;
4680 + uint32 spare;
4681 + uint32 tpaddr;
4682 + uint32 tpdata;
4683 + uint32 barrier;
4684 + uint32 core;
4685 +} sbmemcregs_t;
4686 +
4687 +#endif
4688 +
4689 +/* MEMC Core Init values (OCP ID 0x80f) */
4690 +
4691 +/* For sdr: */
4692 +#define MEMC_SD_CONFIG_INIT 0x00048000
4693 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
4694 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
4695 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
4696 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
4697 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
4698 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
4699 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
4700 +#define MEMC_SD_CONTROL_INIT0 0x00000002
4701 +#define MEMC_SD_CONTROL_INIT1 0x00000008
4702 +#define MEMC_SD_CONTROL_INIT2 0x00000004
4703 +#define MEMC_SD_CONTROL_INIT3 0x00000010
4704 +#define MEMC_SD_CONTROL_INIT4 0x00000001
4705 +#define MEMC_SD_MODEBUF_INIT 0x00000000
4706 +#define MEMC_SD_REFRESH_INIT 0x0000840f
4707 +
4708 +
4709 +/* This is for SDRM8X8X4 */
4710 +#define MEMC_SDR_INIT 0x0008
4711 +#define MEMC_SDR_MODE 0x32
4712 +#define MEMC_SDR_NCDL 0x00020032
4713 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
4714 +
4715 +/* For ddr: */
4716 +#define MEMC_CONFIG_INIT 0x00048000
4717 +#define MEMC_DRAMTIM2_INIT 0x000754d8
4718 +#define MEMC_DRAMTIM25_INIT 0x000754d9
4719 +#define MEMC_RDNCDLCOR_INIT 0x00000000
4720 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
4721 +#define MEMC_WRNCDLCOR_INIT 0x49351200
4722 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
4723 +#define MEMC_DQSGATENCDL_INIT 0x00030000
4724 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
4725 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
4726 +#define MEMC_NCDLCTL_INIT 0x00002001
4727 +#define MEMC_CONTROL_INIT0 0x00000002
4728 +#define MEMC_CONTROL_INIT1 0x00000008
4729 +#define MEMC_MODEBUF_INIT0 0x00004000
4730 +#define MEMC_CONTROL_INIT2 0x00000010
4731 +#define MEMC_MODEBUF_INIT1 0x00000100
4732 +#define MEMC_CONTROL_INIT3 0x00000010
4733 +#define MEMC_CONTROL_INIT4 0x00000008
4734 +#define MEMC_REFRESH_INIT 0x0000840f
4735 +#define MEMC_CONTROL_INIT5 0x00000004
4736 +#define MEMC_MODEBUF_INIT2 0x00000000
4737 +#define MEMC_CONTROL_INIT6 0x00000010
4738 +#define MEMC_CONTROL_INIT7 0x00000001
4739 +
4740 +
4741 +/* This is for DDRM16X16X2 */
4742 +#define MEMC_DDR_INIT 0x0009
4743 +#define MEMC_DDR_MODE 0x62
4744 +#define MEMC_DDR_NCDL 0x0005050a
4745 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
4746 +
4747 +/* mask for sdr/ddr calibration registers */
4748 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
4749 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
4750 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
4751 +
4752 +/* masks for miscdlyctl registers */
4753 +#define MEMC_MISC_SM_MASK 0x30000000
4754 +#define MEMC_MISC_SM_SHIFT 28
4755 +#define MEMC_MISC_SD_MASK 0x0f000000
4756 +#define MEMC_MISC_SD_SHIFT 24
4757 +
4758 +/* hw threshhold for calculating wr/rd for sdr memc */
4759 +#define MEMC_CD_THRESHOLD 128
4760 +
4761 +/* Low bit of init register says if memc is ddr or sdr */
4762 +#define MEMC_CONFIG_DDR 0x00000001
4763 +
4764 +#endif /* _SBMEMC_H */
4765 diff -Naur linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
4766 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
4767 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2006-04-06 15:34:14.000000000 +0200
4768 @@ -0,0 +1,62 @@
4769 +/*
4770 + * Broadcom SiliconBackplane MIPS definitions
4771 + *
4772 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
4773 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
4774 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
4775 + * interface. The core revision is stored in the SB ID register in SB
4776 + * configuration space.
4777 + *
4778 + * Copyright 2005, Broadcom Corporation
4779 + * All Rights Reserved.
4780 + *
4781 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4782 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4783 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4784 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4785 + *
4786 + * $Id$
4787 + */
4788 +
4789 +#ifndef _SBMIPS_H
4790 +#define _SBMIPS_H
4791 +
4792 +#include <mipsinc.h>
4793 +
4794 +#ifndef _LANGUAGE_ASSEMBLY
4795 +
4796 +/* cpp contortions to concatenate w/arg prescan */
4797 +#ifndef PAD
4798 +#define _PADLINE(line) pad ## line
4799 +#define _XSTR(line) _PADLINE(line)
4800 +#define PAD _XSTR(__LINE__)
4801 +#endif /* PAD */
4802 +
4803 +typedef volatile struct {
4804 + uint32 corecontrol;
4805 + uint32 PAD[2];
4806 + uint32 biststatus;
4807 + uint32 PAD[4];
4808 + uint32 intstatus;
4809 + uint32 intmask;
4810 + uint32 timer;
4811 +} mipsregs_t;
4812 +
4813 +extern uint32 sb_flag(sb_t *sbh);
4814 +extern uint sb_irq(sb_t *sbh);
4815 +
4816 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
4817 +
4818 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
4819 +extern void sb_jtagm_disable(void *h);
4820 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
4821 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
4822 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
4823 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4824 +extern void BCMINIT(enable_pfc)(uint32 mode);
4825 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
4826 +
4827 +
4828 +#endif /* _LANGUAGE_ASSEMBLY */
4829 +
4830 +#endif /* _SBMIPS_H */
4831 diff -Naur linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
4832 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
4833 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-04-06 15:34:14.000000000 +0200
4834 @@ -0,0 +1,122 @@
4835 +/*
4836 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
4837 + *
4838 + * $Id$
4839 + * Copyright 2005, Broadcom Corporation
4840 + * All Rights Reserved.
4841 + *
4842 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4843 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4844 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4845 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4846 + */
4847 +
4848 +#ifndef _SBPCI_H
4849 +#define _SBPCI_H
4850 +
4851 +/* cpp contortions to concatenate w/arg prescan */
4852 +#ifndef PAD
4853 +#define _PADLINE(line) pad ## line
4854 +#define _XSTR(line) _PADLINE(line)
4855 +#define PAD _XSTR(__LINE__)
4856 +#endif
4857 +
4858 +/* Sonics side: PCI core and host control registers */
4859 +typedef struct sbpciregs {
4860 + uint32 control; /* PCI control */
4861 + uint32 PAD[3];
4862 + uint32 arbcontrol; /* PCI arbiter control */
4863 + uint32 PAD[3];
4864 + uint32 intstatus; /* Interrupt status */
4865 + uint32 intmask; /* Interrupt mask */
4866 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
4867 + uint32 PAD[9];
4868 + uint32 bcastaddr; /* Sonics broadcast address */
4869 + uint32 bcastdata; /* Sonics broadcast data */
4870 + uint32 PAD[2];
4871 + uint32 gpioin; /* ro: gpio input (>=rev2) */
4872 + uint32 gpioout; /* rw: gpio output (>=rev2) */
4873 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
4874 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
4875 + uint32 PAD[36];
4876 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
4877 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
4878 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
4879 + uint32 PAD[445];
4880 + uint16 sprom[36]; /* SPROM shadow Area */
4881 + uint32 PAD[46];
4882 +} sbpciregs_t;
4883 +
4884 +/* PCI control */
4885 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
4886 +#define PCI_RST 0x02 /* Value driven out to pin */
4887 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
4888 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
4889 +
4890 +/* PCI arbiter control */
4891 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
4892 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
4893 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
4894 +#define PCI_PARKID_SHIFT 1
4895 +#define PCI_PARKID_LAST 0 /* Last requestor */
4896 +#define PCI_PARKID_4710 1 /* 4710 */
4897 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
4898 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
4899 +
4900 +/* Interrupt status/mask */
4901 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
4902 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
4903 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
4904 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
4905 +#define PCI_PME 0x10 /* PCI PME# is asserted */
4906 +
4907 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
4908 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
4909 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
4910 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
4911 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
4912 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
4913 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
4914 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
4915 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
4916 +
4917 +/* Sonics broadcast address */
4918 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
4919 +
4920 +/* Sonics to PCI translation types */
4921 +#define SBTOPCI0_MASK 0xfc000000
4922 +#define SBTOPCI1_MASK 0xfc000000
4923 +#define SBTOPCI2_MASK 0xc0000000
4924 +#define SBTOPCI_MEM 0
4925 +#define SBTOPCI_IO 1
4926 +#define SBTOPCI_CFG0 2
4927 +#define SBTOPCI_CFG1 3
4928 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
4929 +#define SBTOPCI_BURST 0x8 /* burst enable */
4930 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
4931 +#define SBTOPCI_RC_READ 0x00 /* memory read */
4932 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
4933 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
4934 +
4935 +/* PCI core index in SROM shadow area */
4936 +#define SRSH_PI_OFFSET 0 /* first word */
4937 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
4938 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
4939 +
4940 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
4941 +#define cap_list rsvd_a[0]
4942 +#define bar0_window dev_dep[0x80 - 0x40]
4943 +#define bar1_window dev_dep[0x84 - 0x40]
4944 +#define sprom_control dev_dep[0x88 - 0x40]
4945 +
4946 +#ifndef _LANGUAGE_ASSEMBLY
4947 +
4948 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
4949 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
4950 +extern void sbpci_ban(uint16 core);
4951 +extern int sbpci_init(sb_t *sbh);
4952 +extern void sbpci_check(sb_t *sbh);
4953 +
4954 +#endif /* !_LANGUAGE_ASSEMBLY */
4955 +
4956 +#endif /* _SBPCI_H */
4957 diff -Naur linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
4958 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
4959 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-04-06 15:34:14.000000000 +0200
4960 @@ -0,0 +1,199 @@
4961 +/*
4962 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
4963 + *
4964 + * $Id:
4965 + * Copyright 2005, Broadcom Corporation
4966 + * All Rights Reserved.
4967 + *
4968 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4969 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4970 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4971 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4972 + */
4973 +
4974 +#ifndef _SBPCIE_H
4975 +#define _SBPCIE_H
4976 +
4977 +/* cpp contortions to concatenate w/arg prescan */
4978 +#ifndef PAD
4979 +#define _PADLINE(line) pad ## line
4980 +#define _XSTR(line) _PADLINE(line)
4981 +#define PAD _XSTR(__LINE__)
4982 +#endif
4983 +
4984 +/* PCIE Enumeration space offsets*/
4985 +#define PCIE_CORE_CONFIG_OFFSET 0x0
4986 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
4987 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
4988 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
4989 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
4990 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
4991 +#define PCIE_SBCONFIG_OFFSET 0xE00
4992 +
4993 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
4994 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
4995 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
4996 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
4997 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
4998 +
4999 +/* SB side: PCIE core and host control registers */
5000 +typedef struct sbpcieregs {
5001 +
5002 + uint32 PAD[3];
5003 + uint32 biststatus; /* bist Status: 0x00C*/
5004 + uint32 PAD[6];
5005 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
5006 + uint32 PAD[54];
5007 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
5008 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
5009 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
5010 + uint32 PAD[4];
5011 +
5012 + /* pcie core supports in direct access to config space */
5013 + uint32 configaddr; /* pcie config space access: Address field: 0x120*/
5014 + uint32 configdata; /* pcie config space access: Data field: 0x124*/
5015 +
5016 + /* mdio access to serdes */
5017 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
5018 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
5019 +
5020 + /* pcie protocol phy/dllp/tlp register access mechanism*/
5021 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
5022 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
5023 +
5024 + uint32 PAD[434];
5025 + uint16 sprom[36]; /* SPROM shadow Area */
5026 +} sbpcieregs_t;
5027 +
5028 +/* SB to PCIE translation masks */
5029 +#define SBTOPCIE0_MASK 0xfc000000
5030 +#define SBTOPCIE1_MASK 0xfc000000
5031 +#define SBTOPCIE2_MASK 0xc0000000
5032 +
5033 +/* Access type bits (0:1)*/
5034 +#define SBTOPCIE_MEM 0
5035 +#define SBTOPCIE_IO 1
5036 +#define SBTOPCIE_CFG0 2
5037 +#define SBTOPCIE_CFG1 3
5038 +
5039 +/*Prefetch enable bit 2*/
5040 +#define SBTOPCIE_PF 4
5041 +
5042 +/*Write Burst enable for memory write bit 3*/
5043 +#define SBTOPCIE_WR_BURST 8
5044 +
5045 +/* config access */
5046 +#define CONFIGADDR_FUNC_MASK 0x7000
5047 +#define CONFIGADDR_FUNC_SHF 12
5048 +#define CONFIGADDR_REG_MASK 0x0FFF
5049 +#define CONFIGADDR_REG_SHF 0
5050 +
5051 +/* PCIE protocol regs Indirect Address */
5052 +#define PCIEADDR_PROT_MASK 0x300
5053 +#define PCIEADDR_PROT_SHF 8
5054 +#define PCIEADDR_PL_TLP 0
5055 +#define PCIEADDR_PL_DLLP 1
5056 +#define PCIEADDR_PL_PLP 2
5057 +
5058 +/* PCIE protocol PHY diagnostic registers */
5059 +#define PCIE_PLP_MODEREG 0x200 /* Mode*/
5060 +#define PCIE_PLP_STATUSREG 0x204 /* Status*/
5061 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
5062 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
5063 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
5064 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
5065 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
5066 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
5067 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
5068 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
5069 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
5070 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
5071 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
5072 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
5073 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
5074 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
5075 +
5076 +/* PCIE protocol DLLP diagnostic registers */
5077 +#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
5078 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
5079 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
5080 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
5081 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
5082 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
5083 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
5084 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
5085 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
5086 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
5087 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
5088 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
5089 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
5090 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
5091 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
5092 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
5093 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
5094 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
5095 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
5096 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
5097 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
5098 +
5099 +/* PCIE protocol TLP diagnostic registers */
5100 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
5101 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
5102 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
5103 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
5104 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
5105 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
5106 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
5107 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
5108 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
5109 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
5110 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
5111 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
5112 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
5113 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
5114 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
5115 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
5116 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
5117 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
5118 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
5119 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
5120 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
5121 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
5122 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
5123 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
5124 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
5125 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
5126 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
5127 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
5128 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
5129 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
5130 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
5131 +
5132 +/* MDIO control */
5133 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
5134 +#define MDIOCTL_DIVISOR_VAL 0x2
5135 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
5136 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
5137 +
5138 +/* MDIO Data */
5139 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
5140 +#define MDIODATA_TA 0x00020000 /* Turnaround */
5141 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
5142 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
5143 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
5144 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
5145 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
5146 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
5147 +#define MDIODATA_START 0x40000000 /* start of Transaction */
5148 +
5149 +/* MDIO devices (SERDES modules) */
5150 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
5151 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
5152 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
5153 +
5154 +/* SERDES registers */
5155 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
5156 +#define SERDES_RX_CDR 6 /* CDR */
5157 +#define SERDES_RX_CDRBW 7 /* CDR BW */
5158 +
5159 +#endif /* _SBPCIE_H */
5160 diff -Naur linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
5161 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
5162 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-04-06 15:34:14.000000000 +0200
5163 @@ -0,0 +1,146 @@
5164 +/*
5165 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
5166 + *
5167 + * $Id$
5168 + * Copyright 2005, Broadcom Corporation
5169 + * All Rights Reserved.
5170 + *
5171 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5172 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5173 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5174 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5175 + */
5176 +
5177 +#ifndef _SBPCMCIA_H
5178 +#define _SBPCMCIA_H
5179 +
5180 +
5181 +/* All the addresses that are offsets in attribute space are divided
5182 + * by two to account for the fact that odd bytes are invalid in
5183 + * attribute space and our read/write routines make the space appear
5184 + * as if they didn't exist. Still we want to show the original numbers
5185 + * as documented in the hnd_pcmcia core manual.
5186 + */
5187 +
5188 +/* PCMCIA Function Configuration Registers */
5189 +#define PCMCIA_FCR (0x700 / 2)
5190 +
5191 +#define FCR0_OFF 0
5192 +#define FCR1_OFF (0x40 / 2)
5193 +#define FCR2_OFF (0x80 / 2)
5194 +#define FCR3_OFF (0xc0 / 2)
5195 +
5196 +#define PCMCIA_FCR0 (0x700 / 2)
5197 +#define PCMCIA_FCR1 (0x740 / 2)
5198 +#define PCMCIA_FCR2 (0x780 / 2)
5199 +#define PCMCIA_FCR3 (0x7c0 / 2)
5200 +
5201 +/* Standard PCMCIA FCR registers */
5202 +
5203 +#define PCMCIA_COR 0
5204 +
5205 +#define COR_RST 0x80
5206 +#define COR_LEV 0x40
5207 +#define COR_IRQEN 0x04
5208 +#define COR_BLREN 0x01
5209 +#define COR_FUNEN 0x01
5210 +
5211 +
5212 +#define PCICIA_FCSR (2 / 2)
5213 +#define PCICIA_PRR (4 / 2)
5214 +#define PCICIA_SCR (6 / 2)
5215 +#define PCICIA_ESR (8 / 2)
5216 +
5217 +
5218 +#define PCM_MEMOFF 0x0000
5219 +#define F0_MEMOFF 0x1000
5220 +#define F1_MEMOFF 0x2000
5221 +#define F2_MEMOFF 0x3000
5222 +#define F3_MEMOFF 0x4000
5223 +
5224 +/* Memory base in the function fcr's */
5225 +#define MEM_ADDR0 (0x728 / 2)
5226 +#define MEM_ADDR1 (0x72a / 2)
5227 +#define MEM_ADDR2 (0x72c / 2)
5228 +
5229 +/* PCMCIA base plus Srom access in fcr0: */
5230 +#define PCMCIA_ADDR0 (0x072e / 2)
5231 +#define PCMCIA_ADDR1 (0x0730 / 2)
5232 +#define PCMCIA_ADDR2 (0x0732 / 2)
5233 +
5234 +#define MEM_SEG (0x0734 / 2)
5235 +#define SROM_CS (0x0736 / 2)
5236 +#define SROM_DATAL (0x0738 / 2)
5237 +#define SROM_DATAH (0x073a / 2)
5238 +#define SROM_ADDRL (0x073c / 2)
5239 +#define SROM_ADDRH (0x073e / 2)
5240 +
5241 +/* Values for srom_cs: */
5242 +#define SROM_IDLE 0
5243 +#define SROM_WRITE 1
5244 +#define SROM_READ 2
5245 +#define SROM_WEN 4
5246 +#define SROM_WDS 7
5247 +#define SROM_DONE 8
5248 +
5249 +/* CIS stuff */
5250 +
5251 +/* The CIS stops where the FCRs start */
5252 +#define CIS_SIZE PCMCIA_FCR
5253 +
5254 +/* Standard tuples we know about */
5255 +
5256 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
5257 +#define CISTPL_FUNCE 0x22 /* Function extensions */
5258 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
5259 +
5260 +/* Function extensions for LANs */
5261 +
5262 +#define LAN_TECH 1 /* Technology type */
5263 +#define LAN_SPEED 2 /* Raw bit rate */
5264 +#define LAN_MEDIA 3 /* Transmission media */
5265 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
5266 +#define LAN_CONN 5 /* Connector standard */
5267 +
5268 +
5269 +/* CFTable */
5270 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
5271 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
5272 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
5273 +
5274 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
5275 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
5276 + */
5277 +
5278 +#define CISTPL_BRCM_HNBU 0x80
5279 +
5280 +/* Subtypes of BRCM_HNBU: */
5281 +
5282 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
5283 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
5284 + * device id and chiprev
5285 + */
5286 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
5287 +#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
5288 + * or 9 (sromrev > 1) bytes */
5289 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
5290 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
5291 +#define HNBU_AA 0x06 /* Antennas available */
5292 +#define HNBU_AG 0x07 /* Antenna gain */
5293 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
5294 +#define HNBU_LEDS 0x09 /* LED set */
5295 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
5296 + * in rev 2
5297 + */
5298 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
5299 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
5300 +
5301 +
5302 +/* sbtmstatelow */
5303 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
5304 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
5305 +
5306 +/* sbtmstatehigh */
5307 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
5308 +
5309 +#endif /* _SBPCMCIA_H */
5310 diff -Naur linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
5311 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
5312 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-04-06 15:34:14.000000000 +0200
5313 @@ -0,0 +1,75 @@
5314 +/*
5315 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
5316 + *
5317 + * Copyright 2005, Broadcom Corporation
5318 + * All Rights Reserved.
5319 + *
5320 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5321 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5322 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5323 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5324 + * $Id$
5325 + */
5326 +
5327 +#ifndef _SBSDRAM_H
5328 +#define _SBSDRAM_H
5329 +
5330 +#ifndef _LANGUAGE_ASSEMBLY
5331 +
5332 +/* Sonics side: SDRAM core registers */
5333 +typedef volatile struct sbsdramregs {
5334 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
5335 + uint32 config; /* Initializes external SDRAM mode register */
5336 + uint32 refresh; /* Controls external SDRAM refresh rate */
5337 + uint32 pad1;
5338 + uint32 pad2;
5339 +} sbsdramregs_t;
5340 +
5341 +#endif
5342 +
5343 +/* SDRAM initialization control (initcontrol) register bits */
5344 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
5345 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
5346 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
5347 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
5348 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
5349 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
5350 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
5351 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
5352 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
5353 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
5354 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
5355 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
5356 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
5357 +
5358 +/* SDRAM configuration (config) register bits */
5359 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
5360 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
5361 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
5362 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
5363 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
5364 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
5365 +
5366 +/* SDRAM refresh control (refresh) register bits */
5367 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
5368 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
5369 +
5370 +/* SDRAM Core default Init values (OCP ID 0x803) */
5371 +#define SDRAM_INIT MEM4MX16X2
5372 +#define SDRAM_CONFIG SDRAM_BURSTFULL
5373 +#define SDRAM_REFRESH SDRAM_REF(0x40)
5374 +
5375 +#define MEM1MX16 0x009 /* 2 MB */
5376 +#define MEM1MX16X2 0x409 /* 4 MB */
5377 +#define MEM2MX8X2 0x809 /* 4 MB */
5378 +#define MEM2MX8X4 0xc09 /* 8 MB */
5379 +#define MEM2MX32 0x439 /* 8 MB */
5380 +#define MEM4MX16 0x019 /* 8 MB */
5381 +#define MEM4MX16X2 0x419 /* 16 MB */
5382 +#define MEM8MX8X2 0x819 /* 16 MB */
5383 +#define MEM8MX16 0x829 /* 16 MB */
5384 +#define MEM4MX32 0x429 /* 16 MB */
5385 +#define MEM8MX8X4 0xc19 /* 32 MB */
5386 +#define MEM8MX16X2 0xc29 /* 32 MB */
5387 +
5388 +#endif /* _SBSDRAM_H */
5389 diff -Naur linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
5390 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
5391 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-04-06 15:34:14.000000000 +0200
5392 @@ -0,0 +1,37 @@
5393 +/*
5394 + * BCM47XX Sonics SiliconBackplane embedded ram core
5395 + *
5396 + * Copyright 2005, Broadcom Corporation
5397 + * All Rights Reserved.
5398 + *
5399 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5400 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5401 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5402 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5403 + *
5404 + * $Id$
5405 + */
5406 +
5407 +#ifndef _SBSOCRAM_H
5408 +#define _SBSOCRAM_H
5409 +
5410 +#define SOCRAM_MEMSIZE 0x00
5411 +#define SOCRAM_BISTSTAT 0x0c
5412 +
5413 +
5414 +#ifndef _LANGUAGE_ASSEMBLY
5415 +
5416 +/* Memcsocram core registers */
5417 +typedef volatile struct sbsocramregs {
5418 + uint32 memsize;
5419 + uint32 biststat;
5420 +} sbsocramregs_t;
5421 +
5422 +#endif
5423 +
5424 +/* Them memory size is 2 to the power of the following
5425 + * base added to the contents of the memsize register.
5426 + */
5427 +#define SOCRAM_MEMSIZE_BASESHIFT 16
5428 +
5429 +#endif /* _SBSOCRAM_H */
5430 diff -Naur linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
5431 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
5432 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-04-06 15:34:14.000000000 +0200
5433 @@ -0,0 +1,140 @@
5434 +/*
5435 + * Misc utility routines for accessing chip-specific features
5436 + * of Broadcom HNBU SiliconBackplane-based chips.
5437 + *
5438 + * Copyright 2005, Broadcom Corporation
5439 + * All Rights Reserved.
5440 + *
5441 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5442 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5443 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5444 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5445 + *
5446 + * $Id$
5447 + */
5448 +
5449 +#ifndef _sbutils_h_
5450 +#define _sbutils_h_
5451 +
5452 +/*
5453 + * Datastructure to export all chip specific common variables
5454 + * public (read-only) portion of sbutils handle returned by
5455 + * sb_attach()/sb_kattach()
5456 +*/
5457 +
5458 +struct sb_pub {
5459 +
5460 + uint bustype; /* SB_BUS, PCI_BUS */
5461 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
5462 + uint buscorerev; /* buscore rev */
5463 + uint buscoreidx; /* buscore index */
5464 + int ccrev; /* chip common core rev */
5465 + uint boardtype; /* board type */
5466 + uint boardvendor; /* board vendor */
5467 + uint chip; /* chip number */
5468 + uint chiprev; /* chip revision */
5469 + uint chippkg; /* chip package option */
5470 + uint sonicsrev; /* sonics backplane rev */
5471 +};
5472 +
5473 +typedef const struct sb_pub sb_t;
5474 +
5475 +/*
5476 + * Many of the routines below take an 'sbh' handle as their first arg.
5477 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
5478 + * At any one time, the sbh is logically focused on one particular sb core
5479 + * (the "current core").
5480 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
5481 + */
5482 +
5483 +/* exported externs */
5484 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
5485 +extern sb_t * BCMINIT(sb_kattach)(void);
5486 +extern void sb_detach(sb_t *sbh);
5487 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
5488 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
5489 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
5490 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
5491 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
5492 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
5493 +extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
5494 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
5495 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
5496 +extern uint sb_bus(sb_t *sbh);
5497 +extern uint sb_buscoretype(sb_t *sbh);
5498 +extern uint sb_buscorerev(sb_t *sbh);
5499 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
5500 +extern uint sb_coreid(sb_t *sbh);
5501 +extern uint sb_coreidx(sb_t *sbh);
5502 +extern uint sb_coreunit(sb_t *sbh);
5503 +extern uint sb_corevendor(sb_t *sbh);
5504 +extern uint sb_corerev(sb_t *sbh);
5505 +extern void *sb_osh(sb_t *sbh);
5506 +extern void *sb_coreregs(sb_t *sbh);
5507 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
5508 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
5509 +extern bool sb_iscoreup(sb_t *sbh);
5510 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
5511 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
5512 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
5513 +extern void sb_commit(sb_t *sbh);
5514 +extern uint32 sb_base(uint32 admatch);
5515 +extern uint32 sb_size(uint32 admatch);
5516 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
5517 +extern void sb_core_tofixup(sb_t *sbh);
5518 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
5519 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
5520 +extern uint32 sb_clock(sb_t *sbh);
5521 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
5522 +extern void sb_pcmcia_init(sb_t *sbh);
5523 +extern void sb_watchdog(sb_t *sbh, uint ticks);
5524 +extern void *sb_gpiosetcore(sb_t *sbh);
5525 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
5526 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
5527 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
5528 +extern uint32 sb_gpioin(sb_t *sbh);
5529 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
5530 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
5531 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
5532 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
5533 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
5534 +
5535 +extern void sb_clkctl_init(sb_t *sbh);
5536 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
5537 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
5538 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
5539 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
5540 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
5541 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
5542 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5543 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
5544 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
5545 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
5546 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
5547 +
5548 +
5549 +
5550 +/*
5551 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
5552 +* The returned path is NULL terminated and has trailing '/'.
5553 +* Return 0 on success, nonzero otherwise.
5554 +*/
5555 +extern int sb_devpath(sb_t *sbh, char *path, int size);
5556 +
5557 +/* clkctl xtal what flags */
5558 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
5559 +#define PLL 0x2 /* main chip pll */
5560 +
5561 +/* clkctl clk mode */
5562 +#define CLK_FAST 0 /* force fast (pll) clock */
5563 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
5564 +
5565 +
5566 +/* GPIO usage priorities */
5567 +#define GPIO_DRV_PRIORITY 0
5568 +#define GPIO_APP_PRIORITY 1
5569 +
5570 +/* device path */
5571 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
5572 +
5573 +#endif /* _sbutils_h_ */
5574 diff -Naur linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
5575 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
5576 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-04-06 15:34:14.000000000 +0200
5577 @@ -0,0 +1,36 @@
5578 +/*
5579 + * Broadcom SiliconBackplane chipcommon serial flash interface
5580 + *
5581 + * Copyright 2005, Broadcom Corporation
5582 + * All Rights Reserved.
5583 + *
5584 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5585 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5586 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5587 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5588 + *
5589 + * $Id$
5590 + */
5591 +
5592 +#ifndef _sflash_h_
5593 +#define _sflash_h_
5594 +
5595 +#include <typedefs.h>
5596 +#include <sbchipc.h>
5597 +
5598 +struct sflash {
5599 + uint blocksize; /* Block size */
5600 + uint numblocks; /* Number of blocks */
5601 + uint32 type; /* Type */
5602 + uint size; /* Total size in bytes */
5603 +};
5604 +
5605 +/* Utility functions */
5606 +extern int sflash_poll(chipcregs_t *cc, uint offset);
5607 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
5608 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
5609 +extern int sflash_erase(chipcregs_t *cc, uint offset);
5610 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
5611 +extern struct sflash * sflash_init(chipcregs_t *cc);
5612 +
5613 +#endif /* _sflash_h_ */
5614 diff -Naur linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
5615 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
5616 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-04-06 15:34:14.000000000 +0200
5617 @@ -0,0 +1,33 @@
5618 +/*
5619 + * TRX image file header format.
5620 + *
5621 + * Copyright 2005, Broadcom Corporation
5622 + * All Rights Reserved.
5623 + *
5624 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5625 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5626 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5627 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5628 + *
5629 + * $Id$
5630 + */
5631 +
5632 +#include <typedefs.h>
5633 +
5634 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
5635 +#define TRX_VERSION 1
5636 +#define TRX_MAX_LEN 0x3A0000
5637 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
5638 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
5639 +#define TRX_MAX_OFFSET 3
5640 +
5641 +struct trx_header {
5642 + uint32 magic; /* "HDR0" */
5643 + uint32 len; /* Length of file including header */
5644 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
5645 + uint32 flag_version; /* 0:15 flags, 16:31 version */
5646 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
5647 +};
5648 +
5649 +/* Compatibility */
5650 +typedef struct trx_header TRXHDR, *PTRXHDR;
5651 diff -Naur linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
5652 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
5653 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-04-06 15:34:14.000000000 +0200
5654 @@ -0,0 +1,326 @@
5655 +/*
5656 + * Copyright 2005, Broadcom Corporation
5657 + * All Rights Reserved.
5658 + *
5659 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5660 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5661 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5662 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5663 + * $Id$
5664 + */
5665 +
5666 +#ifndef _TYPEDEFS_H_
5667 +#define _TYPEDEFS_H_
5668 +
5669 +
5670 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
5671 + * typedef file "site_typedefs.h".
5672 + *
5673 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
5674 + * section of this file makes inferences about the compile environment
5675 + * based on defined symbols and possibly compiler pragmas.
5676 + *
5677 + * Following these two sections is the "Default Typedefs"
5678 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
5679 + * defined. This section has a default set of typedefs and a few
5680 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
5681 + */
5682 +
5683 +#ifdef SITE_TYPEDEFS
5684 +
5685 +/*******************************************************************************
5686 + * Site Specific Typedefs
5687 + *******************************************************************************/
5688 +
5689 +#include "site_typedefs.h"
5690 +
5691 +#else
5692 +
5693 +/*******************************************************************************
5694 + * Inferred Typedefs
5695 + *******************************************************************************/
5696 +
5697 +/* Infer the compile environment based on preprocessor symbols and pramas.
5698 + * Override type definitions as needed, and include configuration dependent
5699 + * header files to define types.
5700 + */
5701 +
5702 +#ifdef __cplusplus
5703 +
5704 +#define TYPEDEF_BOOL
5705 +#ifndef FALSE
5706 +#define FALSE false
5707 +#endif
5708 +#ifndef TRUE
5709 +#define TRUE true
5710 +#endif
5711 +
5712 +#else /* ! __cplusplus */
5713 +
5714 +#if defined(_WIN32)
5715 +
5716 +#define TYPEDEF_BOOL
5717 +typedef unsigned char bool; /* consistent w/BOOL */
5718 +
5719 +#endif /* _WIN32 */
5720 +
5721 +#endif /* ! __cplusplus */
5722 +
5723 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
5724 +#if defined(_WIN64)
5725 +#include <basetsd.h>
5726 +#define TYPEDEF_UINTPTR
5727 +typedef ULONG_PTR uintptr;
5728 +#endif
5729 +
5730 +#ifdef _HNDRTE_
5731 +typedef long unsigned int size_t;
5732 +#endif
5733 +
5734 +#ifdef _MSC_VER /* Microsoft C */
5735 +#define TYPEDEF_INT64
5736 +#define TYPEDEF_UINT64
5737 +typedef signed __int64 int64;
5738 +typedef unsigned __int64 uint64;
5739 +#endif
5740 +
5741 +#if defined(MACOSX) && defined(KERNEL)
5742 +#define TYPEDEF_BOOL
5743 +#endif
5744 +
5745 +
5746 +#if defined(linux)
5747 +#define TYPEDEF_UINT
5748 +#define TYPEDEF_USHORT
5749 +#define TYPEDEF_ULONG
5750 +#endif
5751 +
5752 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
5753 +#define TYPEDEF_UINT
5754 +#define TYPEDEF_USHORT
5755 +#endif
5756 +
5757 +
5758 +/* Do not support the (u)int64 types with strict ansi for GNU C */
5759 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
5760 +#define TYPEDEF_INT64
5761 +#define TYPEDEF_UINT64
5762 +#endif
5763 +
5764 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
5765 + * for singned or unsigned */
5766 +#if defined(__ICL)
5767 +
5768 +#define TYPEDEF_INT64
5769 +
5770 +#if defined(__STDC__)
5771 +#define TYPEDEF_UINT64
5772 +#endif
5773 +
5774 +#endif /* __ICL */
5775 +
5776 +
5777 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
5778 +
5779 +/* pick up ushort & uint from standard types.h */
5780 +#if defined(linux) && defined(__KERNEL__)
5781 +
5782 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
5783 +
5784 +#else
5785 +
5786 +#include <sys/types.h>
5787 +
5788 +#endif
5789 +
5790 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
5791 +
5792 +#if defined(MACOSX) && defined(KERNEL)
5793 +#include <IOKit/IOTypes.h>
5794 +#endif
5795 +
5796 +
5797 +/* use the default typedefs in the next section of this file */
5798 +#define USE_TYPEDEF_DEFAULTS
5799 +
5800 +#endif /* SITE_TYPEDEFS */
5801 +
5802 +
5803 +/*******************************************************************************
5804 + * Default Typedefs
5805 + *******************************************************************************/
5806 +
5807 +#ifdef USE_TYPEDEF_DEFAULTS
5808 +#undef USE_TYPEDEF_DEFAULTS
5809 +
5810 +#ifndef TYPEDEF_BOOL
5811 +typedef /*@abstract@*/ unsigned char bool;
5812 +#endif
5813 +
5814 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
5815 +
5816 +#ifndef TYPEDEF_UCHAR
5817 +typedef unsigned char uchar;
5818 +#endif
5819 +
5820 +#ifndef TYPEDEF_USHORT
5821 +typedef unsigned short ushort;
5822 +#endif
5823 +
5824 +#ifndef TYPEDEF_UINT
5825 +typedef unsigned int uint;
5826 +#endif
5827 +
5828 +#ifndef TYPEDEF_ULONG
5829 +typedef unsigned long ulong;
5830 +#endif
5831 +
5832 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
5833 +
5834 +#ifndef TYPEDEF_UINT8
5835 +typedef unsigned char uint8;
5836 +#endif
5837 +
5838 +#ifndef TYPEDEF_UINT16
5839 +typedef unsigned short uint16;
5840 +#endif
5841 +
5842 +#ifndef TYPEDEF_UINT32
5843 +typedef unsigned int uint32;
5844 +#endif
5845 +
5846 +#ifndef TYPEDEF_UINT64
5847 +typedef unsigned long long uint64;
5848 +#endif
5849 +
5850 +#ifndef TYPEDEF_UINTPTR
5851 +typedef unsigned int uintptr;
5852 +#endif
5853 +
5854 +#ifndef TYPEDEF_INT8
5855 +typedef signed char int8;
5856 +#endif
5857 +
5858 +#ifndef TYPEDEF_INT16
5859 +typedef signed short int16;
5860 +#endif
5861 +
5862 +#ifndef TYPEDEF_INT32
5863 +typedef signed int int32;
5864 +#endif
5865 +
5866 +#ifndef TYPEDEF_INT64
5867 +typedef signed long long int64;
5868 +#endif
5869 +
5870 +/*----------------------- define float32/64, float_t -----------------------*/
5871 +
5872 +#ifndef TYPEDEF_FLOAT32
5873 +typedef float float32;
5874 +#endif
5875 +
5876 +#ifndef TYPEDEF_FLOAT64
5877 +typedef double float64;
5878 +#endif
5879 +
5880 +/*
5881 + * abstracted floating point type allows for compile time selection of
5882 + * single or double precision arithmetic. Compiling with -DFLOAT32
5883 + * selects single precision; the default is double precision.
5884 + */
5885 +
5886 +#ifndef TYPEDEF_FLOAT_T
5887 +
5888 +#if defined(FLOAT32)
5889 +typedef float32 float_t;
5890 +#else /* default to double precision floating point */
5891 +typedef float64 float_t;
5892 +#endif
5893 +
5894 +#endif /* TYPEDEF_FLOAT_T */
5895 +
5896 +/*----------------------- define macro values -----------------------------*/
5897 +
5898 +#ifndef FALSE
5899 +#define FALSE 0
5900 +#endif
5901 +
5902 +#ifndef TRUE
5903 +#define TRUE 1
5904 +#endif
5905 +
5906 +#ifndef NULL
5907 +#define NULL 0
5908 +#endif
5909 +
5910 +#ifndef OFF
5911 +#define OFF 0
5912 +#endif
5913 +
5914 +#ifndef ON
5915 +#define ON 1
5916 +#endif
5917 +
5918 +#define AUTO (-1)
5919 +
5920 +/* Reclaiming text and data :
5921 + The following macros specify special linker sections that can be reclaimed
5922 + after a system is considered 'up'.
5923 + */
5924 +#if defined(__GNUC__) && defined(BCMRECLAIM)
5925 +extern bool bcmreclaimed;
5926 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
5927 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
5928 +#define BCMINIT(_id) _id##_ini
5929 +#else
5930 +#define BCMINITDATA(_data) _data
5931 +#define BCMINITFN(_fn) _fn
5932 +#define BCMINIT(_id) _id
5933 +#define bcmreclaimed 0
5934 +#endif
5935 +
5936 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
5937 +
5938 +#ifndef PTRSZ
5939 +#define PTRSZ sizeof (char*)
5940 +#endif
5941 +
5942 +#ifndef INLINE
5943 +
5944 +#ifdef _MSC_VER
5945 +
5946 +#define INLINE __inline
5947 +
5948 +#elif __GNUC__
5949 +
5950 +#define INLINE __inline__
5951 +
5952 +#else
5953 +
5954 +#define INLINE
5955 +
5956 +#endif /* _MSC_VER */
5957 +
5958 +#endif /* INLINE */
5959 +
5960 +#undef TYPEDEF_BOOL
5961 +#undef TYPEDEF_UCHAR
5962 +#undef TYPEDEF_USHORT
5963 +#undef TYPEDEF_UINT
5964 +#undef TYPEDEF_ULONG
5965 +#undef TYPEDEF_UINT8
5966 +#undef TYPEDEF_UINT16
5967 +#undef TYPEDEF_UINT32
5968 +#undef TYPEDEF_UINT64
5969 +#undef TYPEDEF_UINTPTR
5970 +#undef TYPEDEF_INT8
5971 +#undef TYPEDEF_INT16
5972 +#undef TYPEDEF_INT32
5973 +#undef TYPEDEF_INT64
5974 +#undef TYPEDEF_FLOAT32
5975 +#undef TYPEDEF_FLOAT64
5976 +#undef TYPEDEF_FLOAT_T
5977 +
5978 +#endif /* USE_TYPEDEF_DEFAULTS */
5979 +
5980 +#endif /* _TYPEDEFS_H_ */
5981 diff -Naur linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
5982 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
5983 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-04-06 15:34:14.000000000 +0200
5984 @@ -0,0 +1,320 @@
5985 +/*
5986 + * NVRAM variable manipulation (common)
5987 + *
5988 + * Copyright 2004, Broadcom Corporation
5989 + * All Rights Reserved.
5990 + *
5991 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5992 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5993 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5994 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5995 + *
5996 + */
5997 +
5998 +#include <typedefs.h>
5999 +#include <osl.h>
6000 +#include <bcmendian.h>
6001 +#include <bcmnvram.h>
6002 +#include <bcmutils.h>
6003 +#include <sbsdram.h>
6004 +
6005 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
6006 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
6007 +extern int BCMINIT(_nvram_read)(void *buf);
6008 +
6009 +char * BCMINIT(_nvram_get)(const char *name);
6010 +int BCMINIT(_nvram_set)(const char *name, const char *value);
6011 +int BCMINIT(_nvram_unset)(const char *name);
6012 +int BCMINIT(_nvram_getall)(char *buf, int count);
6013 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
6014 +int BCMINIT(_nvram_init)(void);
6015 +void BCMINIT(_nvram_exit)(void);
6016 +
6017 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
6018 +static struct nvram_tuple * nvram_dead;
6019 +
6020 +/* Free all tuples. Should be locked. */
6021 +static void
6022 +BCMINITFN(nvram_free)(void)
6023 +{
6024 + uint i;
6025 + struct nvram_tuple *t, *next;
6026 +
6027 + /* Free hash table */
6028 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
6029 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
6030 + next = t->next;
6031 + BCMINIT(_nvram_free)(t);
6032 + }
6033 + BCMINIT(nvram_hash)[i] = NULL;
6034 + }
6035 +
6036 + /* Free dead table */
6037 + for (t = nvram_dead; t; t = next) {
6038 + next = t->next;
6039 + BCMINIT(_nvram_free)(t);
6040 + }
6041 + nvram_dead = NULL;
6042 +
6043 + /* Indicate to per-port code that all tuples have been freed */
6044 + BCMINIT(_nvram_free)(NULL);
6045 +}
6046 +
6047 +/* String hash */
6048 +static INLINE uint
6049 +hash(const char *s)
6050 +{
6051 + uint hash = 0;
6052 +
6053 + while (*s)
6054 + hash = 31 * hash + *s++;
6055 +
6056 + return hash;
6057 +}
6058 +
6059 +/* (Re)initialize the hash table. Should be locked. */
6060 +static int
6061 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
6062 +{
6063 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
6064 +
6065 + /* (Re)initialize hash table */
6066 + BCMINIT(nvram_free)();
6067 +
6068 + /* Parse and set "name=value\0 ... \0\0" */
6069 + name = (char *) &header[1];
6070 + end = (char *) header + NVRAM_SPACE - 2;
6071 + end[0] = end[1] = '\0';
6072 + for (; *name; name = value + strlen(value) + 1) {
6073 + if (!(eq = strchr(name, '=')))
6074 + break;
6075 + *eq = '\0';
6076 + value = eq + 1;
6077 + BCMINIT(_nvram_set)(name, value);
6078 + *eq = '=';
6079 + }
6080 +
6081 + /* Set special SDRAM parameters */
6082 + if (!BCMINIT(_nvram_get)("sdram_init")) {
6083 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
6084 + BCMINIT(_nvram_set)("sdram_init", buf);
6085 + }
6086 + if (!BCMINIT(_nvram_get)("sdram_config")) {
6087 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
6088 + BCMINIT(_nvram_set)("sdram_config", buf);
6089 + }
6090 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
6091 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
6092 + BCMINIT(_nvram_set)("sdram_refresh", buf);
6093 + }
6094 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
6095 + sprintf(buf, "0x%08X", header->config_ncdl);
6096 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
6097 + }
6098 +
6099 + return 0;
6100 +}
6101 +
6102 +/* Get the value of an NVRAM variable. Should be locked. */
6103 +char *
6104 +BCMINITFN(_nvram_get)(const char *name)
6105 +{
6106 + uint i;
6107 + struct nvram_tuple *t;
6108 + char *value;
6109 +
6110 + if (!name)
6111 + return NULL;
6112 +
6113 + /* Hash the name */
6114 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
6115 +
6116 + /* Find the associated tuple in the hash table */
6117 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
6118 +
6119 + value = t ? t->value : NULL;
6120 +
6121 + return value;
6122 +}
6123 +
6124 +/* Get the value of an NVRAM variable. Should be locked. */
6125 +int
6126 +BCMINITFN(_nvram_set)(const char *name, const char *value)
6127 +{
6128 + uint i;
6129 + struct nvram_tuple *t, *u, **prev;
6130 +
6131 + /* Hash the name */
6132 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
6133 +
6134 + /* Find the associated tuple in the hash table */
6135 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
6136 +
6137 + /* (Re)allocate tuple */
6138 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
6139 + return -12; /* -ENOMEM */
6140 +
6141 + /* Value reallocated */
6142 + if (t && t == u)
6143 + return 0;
6144 +
6145 + /* Move old tuple to the dead table */
6146 + if (t) {
6147 + *prev = t->next;
6148 + t->next = nvram_dead;
6149 + nvram_dead = t;
6150 + }
6151 +
6152 + /* Add new tuple to the hash table */
6153 + u->next = BCMINIT(nvram_hash)[i];
6154 + BCMINIT(nvram_hash)[i] = u;
6155 +
6156 + return 0;
6157 +}
6158 +
6159 +/* Unset the value of an NVRAM variable. Should be locked. */
6160 +int
6161 +BCMINITFN(_nvram_unset)(const char *name)
6162 +{
6163 + uint i;
6164 + struct nvram_tuple *t, **prev;
6165 +
6166 + if (!name)
6167 + return 0;
6168 +
6169 + /* Hash the name */
6170 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
6171 +
6172 + /* Find the associated tuple in the hash table */
6173 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
6174 +
6175 + /* Move it to the dead table */
6176 + if (t) {
6177 + *prev = t->next;
6178 + t->next = nvram_dead;
6179 + nvram_dead = t;
6180 + }
6181 +
6182 + return 0;
6183 +}
6184 +
6185 +/* Get all NVRAM variables. Should be locked. */
6186 +int
6187 +BCMINITFN(_nvram_getall)(char *buf, int count)
6188 +{
6189 + uint i;
6190 + struct nvram_tuple *t;
6191 + int len = 0;
6192 +
6193 + bzero(buf, count);
6194 +
6195 + /* Write name=value\0 ... \0\0 */
6196 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
6197 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
6198 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
6199 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
6200 + else
6201 + break;
6202 + }
6203 + }
6204 +
6205 + return 0;
6206 +}
6207 +
6208 +/* Regenerate NVRAM. Should be locked. */
6209 +int
6210 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
6211 +{
6212 + char *init, *config, *refresh, *ncdl;
6213 + char *ptr, *end;
6214 + int i;
6215 + struct nvram_tuple *t;
6216 + struct nvram_header tmp;
6217 + uint8 crc;
6218 +
6219 + /* Regenerate header */
6220 + header->magic = NVRAM_MAGIC;
6221 + header->crc_ver_init = (NVRAM_VERSION << 8);
6222 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
6223 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
6224 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
6225 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
6226 + header->crc_ver_init |= SDRAM_INIT << 16;
6227 + header->config_refresh = SDRAM_CONFIG;
6228 + header->config_refresh |= SDRAM_REFRESH << 16;
6229 + header->config_ncdl = 0;
6230 + } else {
6231 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
6232 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
6233 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
6234 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
6235 + }
6236 +
6237 + /* Clear data area */
6238 + ptr = (char *) header + sizeof(struct nvram_header);
6239 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
6240 +
6241 + /* Leave space for a double NUL at the end */
6242 + end = (char *) header + NVRAM_SPACE - 2;
6243 +
6244 + /* Write out all tuples */
6245 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
6246 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
6247 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
6248 + break;
6249 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
6250 + }
6251 + }
6252 +
6253 + /* End with a double NUL */
6254 + ptr += 2;
6255 +
6256 + /* Set new length */
6257 + header->len = ROUNDUP(ptr - (char *) header, 4);
6258 +
6259 + /* Little-endian CRC8 over the last 11 bytes of the header */
6260 + tmp.crc_ver_init = htol32(header->crc_ver_init);
6261 + tmp.config_refresh = htol32(header->config_refresh);
6262 + tmp.config_ncdl = htol32(header->config_ncdl);
6263 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
6264 +
6265 + /* Continue CRC8 over data bytes */
6266 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
6267 +
6268 + /* Set new CRC8 */
6269 + header->crc_ver_init |= crc;
6270 +
6271 + /* Reinitialize hash table */
6272 + return BCMINIT(nvram_rehash)(header);
6273 +}
6274 +
6275 +/* Initialize hash table. Should be locked. */
6276 +int
6277 +BCMINITFN(_nvram_init)(void)
6278 +{
6279 + struct nvram_header *header;
6280 + int ret;
6281 + void *osh;
6282 +
6283 + /* get kernel osl handler */
6284 + osh = osl_attach(NULL);
6285 +
6286 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
6287 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
6288 + return -12; /* -ENOMEM */
6289 + }
6290 +
6291 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
6292 + header->magic == NVRAM_MAGIC)
6293 + BCMINIT(nvram_rehash)(header);
6294 +
6295 + MFREE(osh, header, NVRAM_SPACE);
6296 + return ret;
6297 +}
6298 +
6299 +/* Free hash table. Should be locked. */
6300 +void
6301 +BCMINITFN(_nvram_exit)(void)
6302 +{
6303 + BCMINIT(nvram_free)();
6304 +}
6305 diff -Naur linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
6306 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
6307 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-04-06 15:34:14.000000000 +0200
6308 @@ -0,0 +1,653 @@
6309 +/*
6310 + * NVRAM variable manipulation (Linux kernel half)
6311 + *
6312 + * Copyright 2005, Broadcom Corporation
6313 + * All Rights Reserved.
6314 + *
6315 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6316 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6317 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6318 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6319 + *
6320 + */
6321 +
6322 +#include <linux/config.h>
6323 +#include <linux/init.h>
6324 +#include <linux/module.h>
6325 +#include <linux/kernel.h>
6326 +#include <linux/string.h>
6327 +#include <linux/interrupt.h>
6328 +#include <linux/spinlock.h>
6329 +#include <linux/slab.h>
6330 +#include <linux/bootmem.h>
6331 +#include <linux/wrapper.h>
6332 +#include <linux/fs.h>
6333 +#include <linux/miscdevice.h>
6334 +#include <linux/mtd/mtd.h>
6335 +#include <asm/addrspace.h>
6336 +#include <asm/io.h>
6337 +#include <asm/uaccess.h>
6338 +
6339 +#include <typedefs.h>
6340 +#include <bcmendian.h>
6341 +#include <bcmnvram.h>
6342 +#include <bcmutils.h>
6343 +#include <sbconfig.h>
6344 +#include <sbchipc.h>
6345 +#include <sbutils.h>
6346 +#include <sbmips.h>
6347 +#include <sflash.h>
6348 +
6349 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
6350 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
6351 +
6352 +#ifdef MODULE
6353 +
6354 +#define early_nvram_get(name) nvram_get(name)
6355 +
6356 +#else /* !MODULE */
6357 +
6358 +/* Global SB handle */
6359 +extern void *bcm947xx_sbh;
6360 +extern spinlock_t bcm947xx_sbh_lock;
6361 +
6362 +static int cfe_env;
6363 +extern char *cfe_env_get(char *nv_buf, const char *name);
6364 +
6365 +/* Convenience */
6366 +#define sbh bcm947xx_sbh
6367 +#define sbh_lock bcm947xx_sbh_lock
6368 +#define KB * 1024
6369 +#define MB * 1024 * 1024
6370 +
6371 +/* Probe for NVRAM header */
6372 +static void __init
6373 +early_nvram_init(void)
6374 +{
6375 + struct nvram_header *header;
6376 + chipcregs_t *cc;
6377 + struct sflash *info = NULL;
6378 + int i;
6379 + uint32 base, off, lim;
6380 + u32 *src, *dst;
6381 +
6382 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
6383 + base = KSEG1ADDR(SB_FLASH2);
6384 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
6385 + case PFLASH:
6386 + lim = SB_FLASH2_SZ;
6387 + break;
6388 +
6389 + case SFLASH_ST:
6390 + case SFLASH_AT:
6391 + if ((info = sflash_init(cc)) == NULL)
6392 + return;
6393 + lim = info->size;
6394 + break;
6395 +
6396 + case FLASH_NONE:
6397 + default:
6398 + return;
6399 + }
6400 + } else {
6401 + /* extif assumed, Stop at 4 MB */
6402 + base = KSEG1ADDR(SB_FLASH1);
6403 + lim = SB_FLASH1_SZ;
6404 + }
6405 +
6406 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
6407 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
6408 + dst = (u32 *) nvram_buf;
6409 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
6410 + printk("early_nvram_init: WGT634U NVRAM found.\n");
6411 +
6412 + for (i = 0; i < 0x1ff0; i++) {
6413 + if (*src == 0xFFFFFFFF)
6414 + break;
6415 + *dst++ = *src++;
6416 + }
6417 + cfe_env = 1;
6418 + return;
6419 + }
6420 +
6421 + off = FLASH_MIN;
6422 + while (off <= lim) {
6423 + /* Windowed flash access */
6424 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
6425 + if (header->magic == NVRAM_MAGIC)
6426 + goto found;
6427 + off <<= 1;
6428 + }
6429 +
6430 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
6431 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
6432 + if (header->magic == NVRAM_MAGIC)
6433 + goto found;
6434 +
6435 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
6436 + if (header->magic == NVRAM_MAGIC)
6437 + goto found;
6438 +
6439 + printk("early_nvram_init: NVRAM not found\n");
6440 + return;
6441 +
6442 +found:
6443 + src = (u32 *) header;
6444 + dst = (u32 *) nvram_buf;
6445 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
6446 + *dst++ = *src++;
6447 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
6448 + *dst++ = ltoh32(*src++);
6449 +}
6450 +
6451 +/* Early (before mm or mtd) read-only access to NVRAM */
6452 +static char * __init
6453 +early_nvram_get(const char *name)
6454 +{
6455 + char *var, *value, *end, *eq;
6456 +
6457 + if (!name)
6458 + return NULL;
6459 +
6460 + /* Too early? */
6461 + if (sbh == NULL)
6462 + return NULL;
6463 +
6464 + if (!nvram_buf[0])
6465 + early_nvram_init();
6466 +
6467 + if (cfe_env)
6468 + return cfe_env_get(nvram_buf, name);
6469 +
6470 + /* Look for name=value and return value */
6471 + var = &nvram_buf[sizeof(struct nvram_header)];
6472 + end = nvram_buf + sizeof(nvram_buf) - 2;
6473 + end[0] = end[1] = '\0';
6474 + for (; *var; var = value + strlen(value) + 1) {
6475 + if (!(eq = strchr(var, '=')))
6476 + break;
6477 + value = eq + 1;
6478 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
6479 + return value;
6480 + }
6481 +
6482 + return NULL;
6483 +}
6484 +
6485 +#endif /* !MODULE */
6486 +
6487 +extern char * _nvram_get(const char *name);
6488 +extern int _nvram_set(const char *name, const char *value);
6489 +extern int _nvram_unset(const char *name);
6490 +extern int _nvram_getall(char *buf, int count);
6491 +extern int _nvram_commit(struct nvram_header *header);
6492 +extern int _nvram_init(void);
6493 +extern void _nvram_exit(void);
6494 +
6495 +/* Globals */
6496 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
6497 +static struct semaphore nvram_sem;
6498 +static unsigned long nvram_offset = 0;
6499 +static int nvram_major = -1;
6500 +static devfs_handle_t nvram_handle = NULL;
6501 +static struct mtd_info *nvram_mtd = NULL;
6502 +
6503 +int
6504 +_nvram_read(char *buf)
6505 +{
6506 + struct nvram_header *header = (struct nvram_header *) buf;
6507 + size_t len;
6508 +
6509 + if (!nvram_mtd ||
6510 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
6511 + len != NVRAM_SPACE ||
6512 + header->magic != NVRAM_MAGIC) {
6513 + /* Maybe we can recover some data from early initialization */
6514 + memcpy(buf, nvram_buf, NVRAM_SPACE);
6515 + }
6516 +
6517 + return 0;
6518 +}
6519 +
6520 +struct nvram_tuple *
6521 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
6522 +{
6523 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
6524 + return NULL;
6525 +
6526 + if (!t) {
6527 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
6528 + return NULL;
6529 +
6530 + /* Copy name */
6531 + t->name = (char *) &t[1];
6532 + strcpy(t->name, name);
6533 +
6534 + t->value = NULL;
6535 + }
6536 +
6537 + /* Copy value */
6538 + if (!t->value || strcmp(t->value, value)) {
6539 + t->value = &nvram_buf[nvram_offset];
6540 + strcpy(t->value, value);
6541 + nvram_offset += strlen(value) + 1;
6542 + }
6543 +
6544 + return t;
6545 +}
6546 +
6547 +void
6548 +_nvram_free(struct nvram_tuple *t)
6549 +{
6550 + if (!t)
6551 + nvram_offset = 0;
6552 + else
6553 + kfree(t);
6554 +}
6555 +
6556 +int
6557 +nvram_set(const char *name, const char *value)
6558 +{
6559 + unsigned long flags;
6560 + int ret;
6561 + struct nvram_header *header;
6562 +
6563 + spin_lock_irqsave(&nvram_lock, flags);
6564 + if ((ret = _nvram_set(name, value))) {
6565 + /* Consolidate space and try again */
6566 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
6567 + if (_nvram_commit(header) == 0)
6568 + ret = _nvram_set(name, value);
6569 + kfree(header);
6570 + }
6571 + }
6572 + spin_unlock_irqrestore(&nvram_lock, flags);
6573 +
6574 + return ret;
6575 +}
6576 +
6577 +char *
6578 +real_nvram_get(const char *name)
6579 +{
6580 + unsigned long flags;
6581 + char *value;
6582 +
6583 + spin_lock_irqsave(&nvram_lock, flags);
6584 + value = _nvram_get(name);
6585 + spin_unlock_irqrestore(&nvram_lock, flags);
6586 +
6587 + return value;
6588 +}
6589 +
6590 +char *
6591 +nvram_get(const char *name)
6592 +{
6593 + if (nvram_major >= 0)
6594 + return real_nvram_get(name);
6595 + else
6596 + return early_nvram_get(name);
6597 +}
6598 +
6599 +int
6600 +nvram_unset(const char *name)
6601 +{
6602 + unsigned long flags;
6603 + int ret;
6604 +
6605 + spin_lock_irqsave(&nvram_lock, flags);
6606 + ret = _nvram_unset(name);
6607 + spin_unlock_irqrestore(&nvram_lock, flags);
6608 +
6609 + return ret;
6610 +}
6611 +
6612 +static void
6613 +erase_callback(struct erase_info *done)
6614 +{
6615 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
6616 + wake_up(wait_q);
6617 +}
6618 +
6619 +int
6620 +nvram_commit(void)
6621 +{
6622 + char *buf;
6623 + size_t erasesize, len;
6624 + unsigned int i;
6625 + int ret;
6626 + struct nvram_header *header;
6627 + unsigned long flags;
6628 + u_int32_t offset;
6629 + DECLARE_WAITQUEUE(wait, current);
6630 + wait_queue_head_t wait_q;
6631 + struct erase_info erase;
6632 +
6633 + if (!nvram_mtd) {
6634 + printk("nvram_commit: NVRAM not found\n");
6635 + return -ENODEV;
6636 + }
6637 +
6638 + if (in_interrupt()) {
6639 + printk("nvram_commit: not committing in interrupt\n");
6640 + return -EINVAL;
6641 + }
6642 +
6643 + /* Backup sector blocks to be erased */
6644 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
6645 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
6646 + printk("nvram_commit: out of memory\n");
6647 + return -ENOMEM;
6648 + }
6649 +
6650 + down(&nvram_sem);
6651 +
6652 + if ((i = erasesize - NVRAM_SPACE) > 0) {
6653 + offset = nvram_mtd->size - erasesize;
6654 + len = 0;
6655 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
6656 + if (ret || len != i) {
6657 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
6658 + ret = -EIO;
6659 + goto done;
6660 + }
6661 + header = (struct nvram_header *)(buf + i);
6662 + } else {
6663 + offset = nvram_mtd->size - NVRAM_SPACE;
6664 + header = (struct nvram_header *)buf;
6665 + }
6666 +
6667 + /* Regenerate NVRAM */
6668 + spin_lock_irqsave(&nvram_lock, flags);
6669 + ret = _nvram_commit(header);
6670 + spin_unlock_irqrestore(&nvram_lock, flags);
6671 + if (ret)
6672 + goto done;
6673 +
6674 + /* Erase sector blocks */
6675 + init_waitqueue_head(&wait_q);
6676 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
6677 + erase.mtd = nvram_mtd;
6678 + erase.addr = offset;
6679 + erase.len = nvram_mtd->erasesize;
6680 + erase.callback = erase_callback;
6681 + erase.priv = (u_long) &wait_q;
6682 +
6683 + set_current_state(TASK_INTERRUPTIBLE);
6684 + add_wait_queue(&wait_q, &wait);
6685 +
6686 + /* Unlock sector blocks */
6687 + if (nvram_mtd->unlock)
6688 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
6689 +
6690 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
6691 + set_current_state(TASK_RUNNING);
6692 + remove_wait_queue(&wait_q, &wait);
6693 + printk("nvram_commit: erase error\n");
6694 + goto done;
6695 + }
6696 +
6697 + /* Wait for erase to finish */
6698 + schedule();
6699 + remove_wait_queue(&wait_q, &wait);
6700 + }
6701 +
6702 + /* Write partition up to end of data area */
6703 + offset = nvram_mtd->size - erasesize;
6704 + i = erasesize - NVRAM_SPACE + header->len;
6705 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
6706 + if (ret || len != i) {
6707 + printk("nvram_commit: write error\n");
6708 + ret = -EIO;
6709 + goto done;
6710 + }
6711 +
6712 + offset = nvram_mtd->size - erasesize;
6713 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
6714 +
6715 + done:
6716 + up(&nvram_sem);
6717 + kfree(buf);
6718 + return ret;
6719 +}
6720 +
6721 +int
6722 +nvram_getall(char *buf, int count)
6723 +{
6724 + unsigned long flags;
6725 + int ret;
6726 +
6727 + spin_lock_irqsave(&nvram_lock, flags);
6728 + ret = _nvram_getall(buf, count);
6729 + spin_unlock_irqrestore(&nvram_lock, flags);
6730 +
6731 + return ret;
6732 +}
6733 +
6734 +EXPORT_SYMBOL(nvram_get);
6735 +EXPORT_SYMBOL(nvram_getall);
6736 +EXPORT_SYMBOL(nvram_set);
6737 +EXPORT_SYMBOL(nvram_unset);
6738 +EXPORT_SYMBOL(nvram_commit);
6739 +
6740 +/* User mode interface below */
6741 +
6742 +static ssize_t
6743 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
6744 +{
6745 + char tmp[100], *name = tmp, *value;
6746 + ssize_t ret;
6747 + unsigned long off;
6748 +
6749 + if (count > sizeof(tmp)) {
6750 + if (!(name = kmalloc(count, GFP_KERNEL)))
6751 + return -ENOMEM;
6752 + }
6753 +
6754 + if (copy_from_user(name, buf, count)) {
6755 + ret = -EFAULT;
6756 + goto done;
6757 + }
6758 +
6759 + if (*name == '\0') {
6760 + /* Get all variables */
6761 + ret = nvram_getall(name, count);
6762 + if (ret == 0) {
6763 + if (copy_to_user(buf, name, count)) {
6764 + ret = -EFAULT;
6765 + goto done;
6766 + }
6767 + ret = count;
6768 + }
6769 + } else {
6770 + if (!(value = nvram_get(name))) {
6771 + ret = 0;
6772 + goto done;
6773 + }
6774 +
6775 + /* Provide the offset into mmap() space */
6776 + off = (unsigned long) value - (unsigned long) nvram_buf;
6777 +
6778 + if (put_user(off, (unsigned long *) buf)) {
6779 + ret = -EFAULT;
6780 + goto done;
6781 + }
6782 +
6783 + ret = sizeof(unsigned long);
6784 + }
6785 +
6786 + flush_cache_all();
6787 +
6788 +done:
6789 + if (name != tmp)
6790 + kfree(name);
6791 +
6792 + return ret;
6793 +}
6794 +
6795 +static ssize_t
6796 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
6797 +{
6798 + char tmp[100], *name = tmp, *value;
6799 + ssize_t ret;
6800 +
6801 + if (count > sizeof(tmp)) {
6802 + if (!(name = kmalloc(count, GFP_KERNEL)))
6803 + return -ENOMEM;
6804 + }
6805 +
6806 + if (copy_from_user(name, buf, count)) {
6807 + ret = -EFAULT;
6808 + goto done;
6809 + }
6810 +
6811 + value = name;
6812 + name = strsep(&value, "=");
6813 + if (value)
6814 + ret = nvram_set(name, value) ? : count;
6815 + else
6816 + ret = nvram_unset(name) ? : count;
6817 +
6818 + done:
6819 + if (name != tmp)
6820 + kfree(name);
6821 +
6822 + return ret;
6823 +}
6824 +
6825 +static int
6826 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
6827 +{
6828 + if (cmd != NVRAM_MAGIC)
6829 + return -EINVAL;
6830 + return nvram_commit();
6831 +}
6832 +
6833 +static int
6834 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
6835 +{
6836 + unsigned long offset = virt_to_phys(nvram_buf);
6837 +
6838 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
6839 + vma->vm_page_prot))
6840 + return -EAGAIN;
6841 +
6842 + return 0;
6843 +}
6844 +
6845 +static int
6846 +dev_nvram_open(struct inode *inode, struct file * file)
6847 +{
6848 + MOD_INC_USE_COUNT;
6849 + return 0;
6850 +}
6851 +
6852 +static int
6853 +dev_nvram_release(struct inode *inode, struct file * file)
6854 +{
6855 + MOD_DEC_USE_COUNT;
6856 + return 0;
6857 +}
6858 +
6859 +static struct file_operations dev_nvram_fops = {
6860 + owner: THIS_MODULE,
6861 + open: dev_nvram_open,
6862 + release: dev_nvram_release,
6863 + read: dev_nvram_read,
6864 + write: dev_nvram_write,
6865 + ioctl: dev_nvram_ioctl,
6866 + mmap: dev_nvram_mmap,
6867 +};
6868 +
6869 +static void
6870 +dev_nvram_exit(void)
6871 +{
6872 + int order = 0;
6873 + struct page *page, *end;
6874 +
6875 + if (nvram_handle)
6876 + devfs_unregister(nvram_handle);
6877 +
6878 + if (nvram_major >= 0)
6879 + devfs_unregister_chrdev(nvram_major, "nvram");
6880 +
6881 + if (nvram_mtd)
6882 + put_mtd_device(nvram_mtd);
6883 +
6884 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
6885 + order++;
6886 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
6887 + for (page = virt_to_page(nvram_buf); page <= end; page++)
6888 + mem_map_unreserve(page);
6889 +
6890 + _nvram_exit();
6891 +}
6892 +
6893 +static int __init
6894 +dev_nvram_init(void)
6895 +{
6896 + int order = 0, ret = 0;
6897 + struct page *page, *end;
6898 + unsigned int i;
6899 +
6900 + /* Allocate and reserve memory to mmap() */
6901 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
6902 + order++;
6903 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
6904 + for (page = virt_to_page(nvram_buf); page <= end; page++)
6905 + mem_map_reserve(page);
6906 +
6907 +#ifdef CONFIG_MTD
6908 + /* Find associated MTD device */
6909 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
6910 + nvram_mtd = get_mtd_device(NULL, i);
6911 + if (nvram_mtd) {
6912 + if (!strcmp(nvram_mtd->name, "nvram") &&
6913 + nvram_mtd->size >= NVRAM_SPACE)
6914 + break;
6915 + put_mtd_device(nvram_mtd);
6916 + }
6917 + }
6918 + if (i >= MAX_MTD_DEVICES)
6919 + nvram_mtd = NULL;
6920 +#endif
6921 +
6922 + /* Initialize hash table lock */
6923 + spin_lock_init(&nvram_lock);
6924 +
6925 + /* Initialize commit semaphore */
6926 + init_MUTEX(&nvram_sem);
6927 +
6928 + /* Register char device */
6929 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
6930 + ret = nvram_major;
6931 + goto err;
6932 + }
6933 +
6934 + /* Initialize hash table */
6935 + _nvram_init();
6936 +
6937 + /* Create /dev/nvram handle */
6938 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
6939 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
6940 +
6941 + /* Set the SDRAM NCDL value into NVRAM if not already done */
6942 + if (getintvar(NULL, "sdram_ncdl") == 0) {
6943 + unsigned int ncdl;
6944 + char buf[] = "0x00000000";
6945 +
6946 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
6947 + sprintf(buf, "0x%08x", ncdl);
6948 + nvram_set("sdram_ncdl", buf);
6949 + nvram_commit();
6950 + }
6951 + }
6952 +
6953 + return 0;
6954 +
6955 + err:
6956 + dev_nvram_exit();
6957 + return ret;
6958 +}
6959 +
6960 +module_init(dev_nvram_init);
6961 +module_exit(dev_nvram_exit);
6962 diff -Naur linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
6963 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
6964 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-04-06 15:34:14.000000000 +0200
6965 @@ -0,0 +1,355 @@
6966 +/*
6967 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
6968 + *
6969 + * Copyright 2005, Broadcom Corporation
6970 + * All Rights Reserved.
6971 + *
6972 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6973 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6974 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6975 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6976 + *
6977 + * $Id$
6978 + */
6979 +
6980 +#include <linux/config.h>
6981 +#include <linux/types.h>
6982 +#include <linux/kernel.h>
6983 +#include <linux/sched.h>
6984 +#include <linux/pci.h>
6985 +#include <linux/init.h>
6986 +#include <linux/delay.h>
6987 +#include <asm/io.h>
6988 +#include <asm/irq.h>
6989 +#include <asm/paccess.h>
6990 +
6991 +#include <typedefs.h>
6992 +#include <bcmutils.h>
6993 +#include <sbconfig.h>
6994 +#include <sbutils.h>
6995 +#include <sbpci.h>
6996 +#include <pcicfg.h>
6997 +#include <bcmdevs.h>
6998 +#include <bcmnvram.h>
6999 +
7000 +/* Global SB handle */
7001 +extern sb_t *bcm947xx_sbh;
7002 +extern spinlock_t bcm947xx_sbh_lock;
7003 +
7004 +/* Convenience */
7005 +#define sbh bcm947xx_sbh
7006 +#define sbh_lock bcm947xx_sbh_lock
7007 +
7008 +static int
7009 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
7010 +{
7011 + unsigned long flags;
7012 + int ret;
7013 +
7014 + spin_lock_irqsave(&sbh_lock, flags);
7015 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
7016 + spin_unlock_irqrestore(&sbh_lock, flags);
7017 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7018 +}
7019 +
7020 +static int
7021 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
7022 +{
7023 + unsigned long flags;
7024 + int ret;
7025 +
7026 + spin_lock_irqsave(&sbh_lock, flags);
7027 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
7028 + spin_unlock_irqrestore(&sbh_lock, flags);
7029 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7030 +}
7031 +
7032 +static int
7033 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
7034 +{
7035 + unsigned long flags;
7036 + int ret;
7037 +
7038 + spin_lock_irqsave(&sbh_lock, flags);
7039 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
7040 + spin_unlock_irqrestore(&sbh_lock, flags);
7041 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7042 +}
7043 +
7044 +static int
7045 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
7046 +{
7047 + unsigned long flags;
7048 + int ret;
7049 +
7050 + spin_lock_irqsave(&sbh_lock, flags);
7051 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
7052 + spin_unlock_irqrestore(&sbh_lock, flags);
7053 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7054 +}
7055 +
7056 +static int
7057 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
7058 +{
7059 + unsigned long flags;
7060 + int ret;
7061 +
7062 + spin_lock_irqsave(&sbh_lock, flags);
7063 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
7064 + spin_unlock_irqrestore(&sbh_lock, flags);
7065 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7066 +}
7067 +
7068 +static int
7069 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
7070 +{
7071 + unsigned long flags;
7072 + int ret;
7073 +
7074 + spin_lock_irqsave(&sbh_lock, flags);
7075 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
7076 + spin_unlock_irqrestore(&sbh_lock, flags);
7077 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
7078 +}
7079 +
7080 +static struct pci_ops pcibios_ops = {
7081 + sbpci_read_config_byte,
7082 + sbpci_read_config_word,
7083 + sbpci_read_config_dword,
7084 + sbpci_write_config_byte,
7085 + sbpci_write_config_word,
7086 + sbpci_write_config_dword
7087 +};
7088 +
7089 +
7090 +void __init
7091 +pcibios_init(void)
7092 +{
7093 + ulong flags;
7094 +
7095 + if (!(sbh = sb_kattach()))
7096 + panic("sb_kattach failed");
7097 + spin_lock_init(&sbh_lock);
7098 +
7099 + spin_lock_irqsave(&sbh_lock, flags);
7100 + sbpci_init(sbh);
7101 + spin_unlock_irqrestore(&sbh_lock, flags);
7102 +
7103 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
7104 +
7105 + mdelay(300); //By Joey for Atheros Card
7106 +
7107 + /* Scan the SB bus */
7108 + pci_scan_bus(0, &pcibios_ops, NULL);
7109 +
7110 +}
7111 +
7112 +char * __init
7113 +pcibios_setup(char *str)
7114 +{
7115 + if (!strncmp(str, "ban=", 4)) {
7116 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
7117 + return NULL;
7118 + }
7119 +
7120 + return (str);
7121 +}
7122 +
7123 +static u32 pci_iobase = 0x100;
7124 +static u32 pci_membase = SB_PCI_DMA;
7125 +
7126 +void __init
7127 +pcibios_fixup_bus(struct pci_bus *b)
7128 +{
7129 + struct list_head *ln;
7130 + struct pci_dev *d;
7131 + struct resource *res;
7132 + int pos, size;
7133 + u32 *base;
7134 + u8 irq;
7135 +
7136 + printk("PCI: Fixing up bus %d\n", b->number);
7137 +
7138 + /* Fix up SB */
7139 + if (b->number == 0) {
7140 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
7141 + d = pci_dev_b(ln);
7142 + /* Fix up interrupt lines */
7143 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
7144 + d->irq = irq + 2;
7145 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
7146 + }
7147 + }
7148 +
7149 + /* Fix up external PCI */
7150 + else {
7151 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
7152 + d = pci_dev_b(ln);
7153 + /* Fix up resource bases */
7154 + for (pos = 0; pos < 6; pos++) {
7155 + res = &d->resource[pos];
7156 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
7157 + if (res->end) {
7158 + size = res->end - res->start + 1;
7159 + if (*base & (size - 1))
7160 + *base = (*base + size) & ~(size - 1);
7161 + res->start = *base;
7162 + res->end = res->start + size - 1;
7163 + *base += size;
7164 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
7165 + }
7166 + /* Fix up PCI bridge BAR0 only */
7167 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
7168 + break;
7169 + }
7170 + /* Fix up interrupt lines */
7171 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
7172 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
7173 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
7174 + }
7175 + }
7176 +}
7177 +
7178 +unsigned int
7179 +pcibios_assign_all_busses(void)
7180 +{
7181 + return 1;
7182 +}
7183 +
7184 +void
7185 +pcibios_align_resource(void *data, struct resource *res,
7186 + unsigned long size, unsigned long align)
7187 +{
7188 +}
7189 +
7190 +int
7191 +pcibios_enable_resources(struct pci_dev *dev)
7192 +{
7193 + u16 cmd, old_cmd;
7194 + int idx;
7195 + struct resource *r;
7196 +
7197 + /* External PCI only */
7198 + if (dev->bus->number == 0)
7199 + return 0;
7200 +
7201 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
7202 + old_cmd = cmd;
7203 + for(idx=0; idx<6; idx++) {
7204 + r = &dev->resource[idx];
7205 + if (r->flags & IORESOURCE_IO)
7206 + cmd |= PCI_COMMAND_IO;
7207 + if (r->flags & IORESOURCE_MEM)
7208 + cmd |= PCI_COMMAND_MEMORY;
7209 + }
7210 + if (dev->resource[PCI_ROM_RESOURCE].start)
7211 + cmd |= PCI_COMMAND_MEMORY;
7212 + if (cmd != old_cmd) {
7213 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
7214 + pci_write_config_word(dev, PCI_COMMAND, cmd);
7215 + }
7216 + return 0;
7217 +}
7218 +
7219 +int
7220 +pcibios_enable_device(struct pci_dev *dev, int mask)
7221 +{
7222 + ulong flags;
7223 + uint coreidx;
7224 +
7225 + /* External PCI device enable */
7226 + if (dev->bus->number != 0)
7227 + return pcibios_enable_resources(dev);
7228 +
7229 + /* These cores come out of reset enabled */
7230 + if (dev->device == SB_MIPS ||
7231 + dev->device == SB_MIPS33 ||
7232 + dev->device == SB_EXTIF ||
7233 + dev->device == SB_CC)
7234 + return 0;
7235 +
7236 + spin_lock_irqsave(&sbh_lock, flags);
7237 + coreidx = sb_coreidx(sbh);
7238 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
7239 + return PCIBIOS_DEVICE_NOT_FOUND;
7240 +
7241 + /*
7242 + * The USB core requires a special bit to be set during core
7243 + * reset to enable host (OHCI) mode. Resetting the SB core in
7244 + * pcibios_enable_device() is a hack for compatibility with
7245 + * vanilla usb-ohci so that it does not have to know about
7246 + * SB. A driver that wants to use the USB core in device mode
7247 + * should know about SB and should reset the bit back to 0
7248 + * after calling pcibios_enable_device().
7249 + */
7250 + if (sb_coreid(sbh) == SB_USB) {
7251 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
7252 + sb_core_reset(sbh, 1 << 29);
7253 + } else
7254 + sb_core_reset(sbh, 0);
7255 +
7256 + sb_setcoreidx(sbh, coreidx);
7257 + spin_unlock_irqrestore(&sbh_lock, flags);
7258 +
7259 + return 0;
7260 +}
7261 +
7262 +void
7263 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
7264 + struct resource *res, int resource)
7265 +{
7266 + unsigned long where, size;
7267 + u32 reg;
7268 +
7269 + /* External PCI only */
7270 + if (dev->bus->number == 0)
7271 + return;
7272 +
7273 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
7274 + size = res->end - res->start;
7275 + pci_read_config_dword(dev, where, &reg);
7276 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
7277 + pci_write_config_dword(dev, where, reg);
7278 +}
7279 +
7280 +static void __init
7281 +quirk_sbpci_bridge(struct pci_dev *dev)
7282 +{
7283 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
7284 + return;
7285 +
7286 + printk("PCI: Fixing up bridge\n");
7287 +
7288 + /* Enable PCI bridge bus mastering and memory space */
7289 + pci_set_master(dev);
7290 + pcibios_enable_resources(dev);
7291 +
7292 + /* Enable PCI bridge BAR1 prefetch and burst */
7293 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
7294 +}
7295 +
7296 +struct pci_fixup pcibios_fixups[] = {
7297 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
7298 + { 0 }
7299 +};
7300 +
7301 +/*
7302 + * If we set up a device for bus mastering, we need to check the latency
7303 + * timer as certain crappy BIOSes forget to set it properly.
7304 + */
7305 +unsigned int pcibios_max_latency = 255;
7306 +
7307 +void pcibios_set_master(struct pci_dev *dev)
7308 +{
7309 + u8 lat;
7310 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
7311 + if (lat < 16)
7312 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
7313 + else if (lat > pcibios_max_latency)
7314 + lat = pcibios_max_latency;
7315 + else
7316 + return;
7317 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
7318 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
7319 +}
7320 +
7321 diff -Naur linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
7322 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
7323 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-04-06 15:34:14.000000000 +0200
7324 @@ -0,0 +1,41 @@
7325 +/*
7326 + * Early initialization code for BCM94710 boards
7327 + *
7328 + * Copyright 2004, Broadcom Corporation
7329 + * All Rights Reserved.
7330 + *
7331 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7332 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7333 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7334 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7335 + *
7336 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
7337 + */
7338 +
7339 +#include <linux/config.h>
7340 +#include <linux/init.h>
7341 +#include <linux/kernel.h>
7342 +#include <linux/types.h>
7343 +#include <asm/bootinfo.h>
7344 +
7345 +void __init
7346 +prom_init(int argc, const char **argv)
7347 +{
7348 + unsigned long mem;
7349 +
7350 + mips_machgroup = MACH_GROUP_BRCM;
7351 + mips_machtype = MACH_BCM947XX;
7352 +
7353 + /* Figure out memory size by finding aliases */
7354 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
7355 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
7356 + *(unsigned long *)(prom_init))
7357 + break;
7358 + }
7359 + add_memory_region(0, mem, BOOT_MEM_RAM);
7360 +}
7361 +
7362 +void __init
7363 +prom_free_prom_memory(void)
7364 +{
7365 +}
7366 diff -Naur linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
7367 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
7368 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-04-06 15:34:14.000000000 +0200
7369 @@ -0,0 +1,1038 @@
7370 +/*
7371 + * BCM47XX Sonics SiliconBackplane MIPS core routines
7372 + *
7373 + * Copyright 2005, Broadcom Corporation
7374 + * All Rights Reserved.
7375 + *
7376 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7377 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7378 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7379 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7380 + *
7381 + * $Id$
7382 + */
7383 +
7384 +#include <typedefs.h>
7385 +#include <osl.h>
7386 +#include <sbutils.h>
7387 +#include <bcmdevs.h>
7388 +#include <bcmnvram.h>
7389 +#include <bcmutils.h>
7390 +#include <hndmips.h>
7391 +#include <sbconfig.h>
7392 +#include <sbextif.h>
7393 +#include <sbchipc.h>
7394 +#include <sbmemc.h>
7395 +#include <mipsinc.h>
7396 +#include <sbutils.h>
7397 +
7398 +/*
7399 + * Returns TRUE if an external UART exists at the given base
7400 + * register.
7401 + */
7402 +static bool
7403 +BCMINITFN(serial_exists)(uint8 *regs)
7404 +{
7405 + uint8 save_mcr, status1;
7406 +
7407 + save_mcr = R_REG(&regs[UART_MCR]);
7408 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
7409 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
7410 + W_REG(&regs[UART_MCR], save_mcr);
7411 +
7412 + return (status1 == 0x90);
7413 +}
7414 +
7415 +/*
7416 + * Initializes UART access. The callback function will be called once
7417 + * per found UART.
7418 + */
7419 +void
7420 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
7421 +{
7422 + void *regs;
7423 + ulong base;
7424 + uint irq;
7425 + int i, n;
7426 +
7427 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
7428 + extifregs_t *eir = (extifregs_t *) regs;
7429 + sbconfig_t *sb;
7430 +
7431 + /* Determine external UART register base */
7432 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
7433 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
7434 +
7435 + /* Determine IRQ */
7436 + irq = sb_irq(sbh);
7437 +
7438 + /* Disable GPIO interrupt initially */
7439 + W_REG(&eir->gpiointpolarity, 0);
7440 + W_REG(&eir->gpiointmask, 0);
7441 +
7442 + /* Search for external UARTs */
7443 + n = 2;
7444 + for (i = 0; i < 2; i++) {
7445 + regs = (void *) REG_MAP(base + (i * 8), 8);
7446 + if (BCMINIT(serial_exists)(regs)) {
7447 + /* Set GPIO 1 to be the external UART IRQ */
7448 + W_REG(&eir->gpiointmask, 2);
7449 + if (add)
7450 + add(regs, irq, 13500000, 0);
7451 + }
7452 + }
7453 +
7454 + /* Add internal UART if enabled */
7455 + if (R_REG(&eir->corecontrol) & CC_UE)
7456 + if (add)
7457 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
7458 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
7459 + chipcregs_t *cc = (chipcregs_t *) regs;
7460 + uint32 rev, cap, pll, baud_base, div;
7461 +
7462 + /* Determine core revision and capabilities */
7463 + rev = sb_corerev(sbh);
7464 + cap = R_REG(&cc->capabilities);
7465 + pll = cap & CAP_PLL_MASK;
7466 +
7467 + /* Determine IRQ */
7468 + irq = sb_irq(sbh);
7469 +
7470 + if (pll == PLL_TYPE1) {
7471 + /* PLL clock */
7472 + baud_base = sb_clock_rate(pll,
7473 + R_REG(&cc->clockcontrol_n),
7474 + R_REG(&cc->clockcontrol_m2));
7475 + div = 1;
7476 + } else {
7477 + if (rev >= 11) {
7478 + /* Fixed ALP clock */
7479 + baud_base = 20000000;
7480 + div = 1;
7481 + /* Set the override bit so we don't divide it */
7482 + W_REG(&cc->corecontrol, CC_UARTCLKO);
7483 + } else if (rev >= 3) {
7484 + /* Internal backplane clock */
7485 + baud_base = sb_clock(sbh);
7486 + div = 2; /* Minimum divisor */
7487 + W_REG(&cc->clkdiv,
7488 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
7489 + } else {
7490 + /* Fixed internal backplane clock */
7491 + baud_base = 88000000;
7492 + div = 48;
7493 + }
7494 +
7495 + /* Clock source depends on strapping if UartClkOverride is unset */
7496 + if ((rev > 0) &&
7497 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
7498 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
7499 + /* Internal divided backplane clock */
7500 + baud_base /= div;
7501 + } else {
7502 + /* Assume external clock of 1.8432 MHz */
7503 + baud_base = 1843200;
7504 + }
7505 + }
7506 + }
7507 +
7508 + /* Add internal UARTs */
7509 + n = cap & CAP_UARTS_MASK;
7510 + for (i = 0; i < n; i++) {
7511 + /* Register offset changed after revision 0 */
7512 + if (rev)
7513 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
7514 + else
7515 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
7516 +
7517 + if (add)
7518 + add(regs, irq, baud_base, 0);
7519 + }
7520 + }
7521 +}
7522 +
7523 +/*
7524 + * Initialize jtag master and return handle for
7525 + * jtag_rwreg. Returns NULL on failure.
7526 + */
7527 +void *
7528 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
7529 +{
7530 + void *regs;
7531 +
7532 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
7533 + chipcregs_t *cc = (chipcregs_t *) regs;
7534 + uint32 tmp;
7535 +
7536 + /*
7537 + * Determine jtagm availability from
7538 + * core revision and capabilities.
7539 + */
7540 + tmp = sb_corerev(sbh);
7541 + /*
7542 + * Corerev 10 has jtagm, but the only chip
7543 + * with it does not have a mips, and
7544 + * the layout of the jtagcmd register is
7545 + * different. We'll only accept >= 11.
7546 + */
7547 + if (tmp < 11)
7548 + return (NULL);
7549 +
7550 + tmp = R_REG(&cc->capabilities);
7551 + if ((tmp & CAP_JTAGP) == 0)
7552 + return (NULL);
7553 +
7554 + /* Set clock divider if requested */
7555 + if (clkd != 0) {
7556 + tmp = R_REG(&cc->clkdiv);
7557 + tmp = (tmp & ~CLKD_JTAG) |
7558 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
7559 + W_REG(&cc->clkdiv, tmp);
7560 + }
7561 +
7562 + /* Enable jtagm */
7563 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
7564 + W_REG(&cc->jtagctrl, tmp);
7565 + }
7566 +
7567 + return (regs);
7568 +}
7569 +
7570 +void
7571 +sb_jtagm_disable(void *h)
7572 +{
7573 + chipcregs_t *cc = (chipcregs_t *)h;
7574 +
7575 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
7576 +}
7577 +
7578 +/*
7579 + * Read/write a jtag register. Assumes a target with
7580 + * 8 bit IR and 32 bit DR.
7581 + */
7582 +#define IRWIDTH 8
7583 +#define DRWIDTH 32
7584 +uint32
7585 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
7586 +{
7587 + chipcregs_t *cc = (chipcregs_t *) h;
7588 + uint32 tmp;
7589 +
7590 + W_REG(&cc->jtagir, ir);
7591 + W_REG(&cc->jtagdr, dr);
7592 + tmp = JCMD_START | JCMD_ACC_IRDR |
7593 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
7594 + (DRWIDTH - 1);
7595 + W_REG(&cc->jtagcmd, tmp);
7596 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
7597 + /* OSL_DELAY(1); */
7598 + }
7599 +
7600 + tmp = R_REG(&cc->jtagdr);
7601 + return (tmp);
7602 +}
7603 +
7604 +/* Returns the SB interrupt flag of the current core. */
7605 +uint32
7606 +sb_flag(sb_t *sbh)
7607 +{
7608 + void *regs;
7609 + sbconfig_t *sb;
7610 +
7611 + regs = sb_coreregs(sbh);
7612 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
7613 +
7614 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
7615 +}
7616 +
7617 +static const uint32 sbips_int_mask[] = {
7618 + 0,
7619 + SBIPS_INT1_MASK,
7620 + SBIPS_INT2_MASK,
7621 + SBIPS_INT3_MASK,
7622 + SBIPS_INT4_MASK
7623 +};
7624 +
7625 +static const uint32 sbips_int_shift[] = {
7626 + 0,
7627 + 0,
7628 + SBIPS_INT2_SHIFT,
7629 + SBIPS_INT3_SHIFT,
7630 + SBIPS_INT4_SHIFT
7631 +};
7632 +
7633 +/*
7634 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
7635 + * 0 is returned.
7636 + */
7637 +uint
7638 +sb_irq(sb_t *sbh)
7639 +{
7640 + uint idx;
7641 + void *regs;
7642 + sbconfig_t *sb;
7643 + uint32 flag, sbipsflag;
7644 + uint irq = 0;
7645 +
7646 + flag = sb_flag(sbh);
7647 +
7648 + idx = sb_coreidx(sbh);
7649 +
7650 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
7651 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
7652 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
7653 +
7654 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
7655 + sbipsflag = R_REG(&sb->sbipsflag);
7656 + for (irq = 1; irq <= 4; irq++) {
7657 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
7658 + break;
7659 + }
7660 + if (irq == 5)
7661 + irq = 0;
7662 + }
7663 +
7664 + sb_setcoreidx(sbh, idx);
7665 +
7666 + return irq;
7667 +}
7668 +
7669 +/* Clears the specified MIPS IRQ. */
7670 +static void
7671 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
7672 +{
7673 + void *regs;
7674 + sbconfig_t *sb;
7675 +
7676 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
7677 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
7678 + ASSERT(regs);
7679 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
7680 +
7681 + if (irq == 0)
7682 + W_REG(&sb->sbintvec, 0);
7683 + else
7684 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
7685 +}
7686 +
7687 +/*
7688 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
7689 + * IRQ 0 may be assigned more than once.
7690 + */
7691 +static void
7692 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
7693 +{
7694 + void *regs;
7695 + sbconfig_t *sb;
7696 + uint32 flag;
7697 +
7698 + regs = sb_setcore(sbh, coreid, coreunit);
7699 + ASSERT(regs);
7700 + flag = sb_flag(sbh);
7701 +
7702 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
7703 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
7704 + ASSERT(regs);
7705 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
7706 +
7707 + if (irq == 0)
7708 + OR_REG(&sb->sbintvec, 1 << flag);
7709 + else {
7710 + flag <<= sbips_int_shift[irq];
7711 + ASSERT(!(flag & ~sbips_int_mask[irq]));
7712 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
7713 + W_REG(&sb->sbipsflag, flag);
7714 + }
7715 +}
7716 +
7717 +/*
7718 + * Initializes clocks and interrupts. SB and NVRAM access must be
7719 + * initialized prior to calling.
7720 + */
7721 +void
7722 +BCMINITFN(sb_mips_init)(sb_t *sbh)
7723 +{
7724 + ulong hz, ns, tmp;
7725 + extifregs_t *eir;
7726 + chipcregs_t *cc;
7727 + char *value;
7728 + uint irq;
7729 +
7730 + /* Figure out current SB clock speed */
7731 + if ((hz = sb_clock(sbh)) == 0)
7732 + hz = 100000000;
7733 + ns = 1000000000 / hz;
7734 +
7735 + /* Setup external interface timing */
7736 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
7737 + /* Initialize extif so we can get to the LEDs and external UART */
7738 + W_REG(&eir->prog_config, CF_EN);
7739 +
7740 + /* Set timing for the flash */
7741 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
7742 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
7743 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
7744 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
7745 +
7746 + /* Set programmable interface timing for external uart */
7747 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
7748 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
7749 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
7750 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
7751 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
7752 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
7753 + /* Set timing for the flash */
7754 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
7755 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
7756 + tmp |= CEIL(120, ns); /* W0 = 120nS */
7757 +
7758 + // Added by Chen-I for 5365
7759 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
7760 + {
7761 + W_REG(&cc->flash_waitcount, tmp);
7762 + W_REG(&cc->pcmcia_memwait, tmp);
7763 + }
7764 + else
7765 + {
7766 + if (sb_corerev(sbh) < 9)
7767 + W_REG(&cc->flash_waitcount, tmp);
7768 +
7769 + if ((sb_corerev(sbh) < 9) ||
7770 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
7771 + W_REG(&cc->pcmcia_memwait, tmp);
7772 + }
7773 + }
7774 + }
7775 +
7776 + /* Chip specific initialization */
7777 + switch (BCMINIT(sb_chip)(sbh)) {
7778 + case BCM4710_DEVICE_ID:
7779 + /* Clear interrupt map */
7780 + for (irq = 0; irq <= 4; irq++)
7781 + BCMINIT(sb_clearirq)(sbh, irq);
7782 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
7783 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
7784 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
7785 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
7786 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
7787 + ASSERT(eir);
7788 + value = BCMINIT(nvram_get)("et0phyaddr");
7789 + if (value && !strcmp(value, "31")) {
7790 + /* Enable internal UART */
7791 + W_REG(&eir->corecontrol, CC_UE);
7792 + /* Give USB its own interrupt */
7793 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
7794 + } else {
7795 + /* Disable internal UART */
7796 + W_REG(&eir->corecontrol, 0);
7797 + /* Give Ethernet its own interrupt */
7798 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
7799 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
7800 + }
7801 + break;
7802 + case BCM5350_DEVICE_ID:
7803 + /* Clear interrupt map */
7804 + for (irq = 0; irq <= 4; irq++)
7805 + BCMINIT(sb_clearirq)(sbh, irq);
7806 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
7807 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
7808 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
7809 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
7810 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
7811 + break;
7812 + }
7813 +}
7814 +
7815 +uint32
7816 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
7817 +{
7818 + extifregs_t *eir;
7819 + chipcregs_t *cc;
7820 + uint32 n, m;
7821 + uint idx;
7822 + uint32 pll_type, rate = 0;
7823 +
7824 + /* get index of the current core */
7825 + idx = sb_coreidx(sbh);
7826 + pll_type = PLL_TYPE1;
7827 +
7828 + /* switch to extif or chipc core */
7829 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
7830 + n = R_REG(&eir->clockcontrol_n);
7831 + m = R_REG(&eir->clockcontrol_sb);
7832 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
7833 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
7834 + n = R_REG(&cc->clockcontrol_n);
7835 + if ((pll_type == PLL_TYPE2) ||
7836 + (pll_type == PLL_TYPE4) ||
7837 + (pll_type == PLL_TYPE6) ||
7838 + (pll_type == PLL_TYPE7))
7839 + m = R_REG(&cc->clockcontrol_mips);
7840 + else if (pll_type == PLL_TYPE5) {
7841 + rate = 200000000;
7842 + goto out;
7843 + }
7844 + else if (pll_type == PLL_TYPE3) {
7845 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
7846 + rate = 200000000;
7847 + goto out;
7848 + } else
7849 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
7850 + } else
7851 + m = R_REG(&cc->clockcontrol_sb);
7852 + } else
7853 + goto out;
7854 +
7855 + // Added by Chen-I for 5365
7856 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
7857 + rate = 100000000;
7858 + else
7859 + /* calculate rate */
7860 + rate = sb_clock_rate(pll_type, n, m);
7861 +
7862 + if (pll_type == PLL_TYPE6)
7863 + rate = SB2MIPS_T6(rate);
7864 +
7865 +out:
7866 + /* switch back to previous core */
7867 + sb_setcoreidx(sbh, idx);
7868 +
7869 + return rate;
7870 +}
7871 +
7872 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
7873 +
7874 +static void
7875 +BCMINITFN(handler)(void)
7876 +{
7877 + /* Step 11 */
7878 + __asm__ (
7879 + ".set\tmips32\n\t"
7880 + "ssnop\n\t"
7881 + "ssnop\n\t"
7882 + /* Disable interrupts */
7883 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
7884 + "mfc0 $15, $12\n\t"
7885 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
7886 + "li $14, -31746\n\t"
7887 + "and $15, $15, $14\n\t"
7888 + "mtc0 $15, $12\n\t"
7889 + "eret\n\t"
7890 + "nop\n\t"
7891 + "nop\n\t"
7892 + ".set\tmips0"
7893 + );
7894 +}
7895 +
7896 +/* The following MUST come right after handler() */
7897 +static void
7898 +BCMINITFN(afterhandler)(void)
7899 +{
7900 +}
7901 +
7902 +/*
7903 + * Set the MIPS, backplane and PCI clocks as closely as possible.
7904 + */
7905 +bool
7906 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
7907 +{
7908 + extifregs_t *eir = NULL;
7909 + chipcregs_t *cc = NULL;
7910 + mipsregs_t *mipsr = NULL;
7911 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
7912 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
7913 + uint32 pll_type, sync_mode;
7914 + uint ic_size, ic_lsize;
7915 + uint idx, i;
7916 + typedef struct {
7917 + uint32 mipsclock;
7918 + uint16 n;
7919 + uint32 sb;
7920 + uint32 pci33;
7921 + uint32 pci25;
7922 + } n3m_table_t;
7923 + static n3m_table_t BCMINITDATA(type1_table)[] = {
7924 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
7925 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
7926 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
7927 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
7928 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
7929 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
7930 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
7931 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
7932 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
7933 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
7934 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
7935 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
7936 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
7937 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
7938 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
7939 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
7940 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
7941 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
7942 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
7943 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
7944 + };
7945 + typedef struct {
7946 + uint32 mipsclock;
7947 + uint16 n;
7948 + uint32 m2; /* that is the clockcontrol_m2 */
7949 + } type3_table_t;
7950 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
7951 + { 150000000, 0x311, 0x4020005 },
7952 + { 200000000, 0x311, 0x4020003 },
7953 + };
7954 + typedef struct {
7955 + uint32 mipsclock;
7956 + uint32 sbclock;
7957 + uint16 n;
7958 + uint32 sb;
7959 + uint32 pci33;
7960 + uint32 m2;
7961 + uint32 m3;
7962 + uint32 ratio_cfg;
7963 + uint32 ratio_parm;
7964 + } n4m_table_t;
7965 +
7966 + static n4m_table_t BCMINITDATA(type2_table)[] = {
7967 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7968 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
7969 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
7970 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
7971 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
7972 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
7973 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7974 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
7975 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
7976 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
7977 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7978 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7979 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
7980 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7981 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
7982 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
7983 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
7984 + };
7985 +
7986 + static n4m_table_t BCMINITDATA(type4_table)[] = {
7987 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
7988 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
7989 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
7990 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
7991 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
7992 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
7993 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
7994 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
7995 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
7996 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
7997 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
7998 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
7999 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
8000 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
8001 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
8002 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
8003 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
8004 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
8005 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
8006 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
8007 + };
8008 +
8009 + static n4m_table_t BCMINITDATA(type7_table)[] = {
8010 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
8011 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
8012 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
8013 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
8014 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
8015 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
8016 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
8017 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
8018 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
8019 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
8020 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
8021 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
8022 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
8023 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
8024 + };
8025 +
8026 + ulong start, end, dst;
8027 + bool ret = FALSE;
8028 +
8029 + /* get index of the current core */
8030 + idx = sb_coreidx(sbh);
8031 + clockcontrol_m2 = NULL;
8032 +
8033 + /* switch to extif or chipc core */
8034 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
8035 + pll_type = PLL_TYPE1;
8036 + clockcontrol_n = &eir->clockcontrol_n;
8037 + clockcontrol_sb = &eir->clockcontrol_sb;
8038 + clockcontrol_pci = &eir->clockcontrol_pci;
8039 + clockcontrol_m2 = &cc->clockcontrol_m2;
8040 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
8041 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
8042 + if (pll_type == PLL_TYPE6) {
8043 + clockcontrol_n = NULL;
8044 + clockcontrol_sb = NULL;
8045 + clockcontrol_pci = NULL;
8046 + } else {
8047 + clockcontrol_n = &cc->clockcontrol_n;
8048 + clockcontrol_sb = &cc->clockcontrol_sb;
8049 + clockcontrol_pci = &cc->clockcontrol_pci;
8050 + clockcontrol_m2 = &cc->clockcontrol_m2;
8051 + }
8052 + } else
8053 + goto done;
8054 +
8055 + if (pll_type == PLL_TYPE6) {
8056 + /* Silence compilers */
8057 + orig_n = orig_sb = orig_pci = 0;
8058 + } else {
8059 + /* Store the current clock register values */
8060 + orig_n = R_REG(clockcontrol_n);
8061 + orig_sb = R_REG(clockcontrol_sb);
8062 + orig_pci = R_REG(clockcontrol_pci);
8063 + }
8064 +
8065 + if (pll_type == PLL_TYPE1) {
8066 + /* Keep the current PCI clock if not specified */
8067 + if (pciclock == 0) {
8068 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
8069 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
8070 + }
8071 +
8072 + /* Search for the closest MIPS clock less than or equal to a preferred value */
8073 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
8074 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
8075 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
8076 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
8077 + break;
8078 + }
8079 + if (i == 0) {
8080 + ret = FALSE;
8081 + goto done;
8082 + } else {
8083 + ret = TRUE;
8084 + i--;
8085 + }
8086 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
8087 +
8088 + /* No PLL change */
8089 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
8090 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
8091 + (orig_pci == BCMINIT(type1_table)[i].pci33))
8092 + goto done;
8093 +
8094 + /* Set the PLL controls */
8095 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
8096 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
8097 + if (pciclock == 25000000)
8098 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
8099 + else
8100 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
8101 +
8102 + /* Reset */
8103 + sb_watchdog(sbh, 1);
8104 +
8105 + while (1);
8106 + } else if ((pll_type == PLL_TYPE3) &&
8107 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
8108 + /* 5350 */
8109 + /* Search for the closest MIPS clock less than or equal to a preferred value */
8110 +
8111 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
8112 + if (type3_table[i].mipsclock > mipsclock)
8113 + break;
8114 + }
8115 + if (i == 0) {
8116 + ret = FALSE;
8117 + goto done;
8118 + } else {
8119 + ret = TRUE;
8120 + i--;
8121 + }
8122 + ASSERT(type3_table[i].mipsclock <= mipsclock);
8123 +
8124 + /* No PLL change */
8125 + orig_m2 = R_REG(&cc->clockcontrol_m2);
8126 + if ((orig_n == type3_table[i].n) &&
8127 + (orig_m2 == type3_table[i].m2)) {
8128 + goto done;
8129 + }
8130 +
8131 + /* Set the PLL controls */
8132 + W_REG(clockcontrol_n, type3_table[i].n);
8133 + W_REG(clockcontrol_m2, type3_table[i].m2);
8134 +
8135 + /* Reset */
8136 + sb_watchdog(sbh, 1);
8137 + while (1);
8138 + } else if ((pll_type == PLL_TYPE2) ||
8139 + (pll_type == PLL_TYPE4) ||
8140 + (pll_type == PLL_TYPE6) ||
8141 + (pll_type == PLL_TYPE7)) {
8142 + n4m_table_t *table = NULL, *te;
8143 + uint tabsz = 0;
8144 +
8145 + ASSERT(cc);
8146 +
8147 + orig_mips = R_REG(&cc->clockcontrol_mips);
8148 +
8149 + if (pll_type == PLL_TYPE6) {
8150 + uint32 new_mips = 0;
8151 +
8152 + ret = TRUE;
8153 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
8154 + new_mips = CC_T6_MMASK;
8155 +
8156 + if (orig_mips == new_mips)
8157 + goto done;
8158 +
8159 + W_REG(&cc->clockcontrol_mips, new_mips);
8160 + goto end_fill;
8161 + }
8162 +
8163 + if (pll_type == PLL_TYPE2) {
8164 + table = BCMINIT(type2_table);
8165 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
8166 + } else if (pll_type == PLL_TYPE4) {
8167 + table = BCMINIT(type4_table);
8168 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
8169 + } else if (pll_type == PLL_TYPE7) {
8170 + table = BCMINIT(type7_table);
8171 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
8172 + } else
8173 + ASSERT("No table for plltype" == NULL);
8174 +
8175 + /* Store the current clock register values */
8176 + orig_m2 = R_REG(&cc->clockcontrol_m2);
8177 + orig_ratio_parm = 0;
8178 + orig_ratio_cfg = 0;
8179 +
8180 + /* Look up current ratio */
8181 + for (i = 0; i < tabsz; i++) {
8182 + if ((orig_n == table[i].n) &&
8183 + (orig_sb == table[i].sb) &&
8184 + (orig_pci == table[i].pci33) &&
8185 + (orig_m2 == table[i].m2) &&
8186 + (orig_mips == table[i].m3)) {
8187 + orig_ratio_parm = table[i].ratio_parm;
8188 + orig_ratio_cfg = table[i].ratio_cfg;
8189 + break;
8190 + }
8191 + }
8192 +
8193 + /* Search for the closest MIPS clock greater or equal to a preferred value */
8194 + for (i = 0; i < tabsz; i++) {
8195 + ASSERT(table[i].mipsclock ==
8196 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
8197 + if ((mipsclock <= table[i].mipsclock) &&
8198 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
8199 + break;
8200 + }
8201 + if (i == tabsz) {
8202 + ret = FALSE;
8203 + goto done;
8204 + } else {
8205 + te = &table[i];
8206 + ret = TRUE;
8207 + }
8208 +
8209 + /* No PLL change */
8210 + if ((orig_n == te->n) &&
8211 + (orig_sb == te->sb) &&
8212 + (orig_pci == te->pci33) &&
8213 + (orig_m2 == te->m2) &&
8214 + (orig_mips == te->m3))
8215 + goto done;
8216 +
8217 + /* Set the PLL controls */
8218 + W_REG(clockcontrol_n, te->n);
8219 + W_REG(clockcontrol_sb, te->sb);
8220 + W_REG(clockcontrol_pci, te->pci33);
8221 + W_REG(&cc->clockcontrol_m2, te->m2);
8222 + W_REG(&cc->clockcontrol_mips, te->m3);
8223 +
8224 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
8225 + if ((pll_type == PLL_TYPE7) &&
8226 + (te->sb != te->m2) &&
8227 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
8228 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
8229 +
8230 + /* No ratio change */
8231 + if (orig_ratio_parm == te->ratio_parm)
8232 + goto end_fill;
8233 +
8234 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
8235 +
8236 + /* Preload the code into the cache */
8237 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
8238 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
8239 + while (start < end) {
8240 + cache_op(start, Fill_I);
8241 + start += ic_lsize;
8242 + }
8243 +
8244 + /* Copy the handler */
8245 + start = (ulong) &BCMINIT(handler);
8246 + end = (ulong) &BCMINIT(afterhandler);
8247 + dst = KSEG1ADDR(0x180);
8248 + for (i = 0; i < (end - start); i += 4)
8249 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
8250 +
8251 + /* Preload handler into the cache one line at a time */
8252 + for (i = 0; i < (end - start); i += 4)
8253 + cache_op(dst + i, Fill_I);
8254 +
8255 + /* Clear BEV bit */
8256 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
8257 +
8258 + /* Enable interrupts */
8259 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
8260 +
8261 + /* Enable MIPS timer interrupt */
8262 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
8263 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
8264 + ASSERT(mipsr);
8265 + W_REG(&mipsr->intmask, 1);
8266 +
8267 + start_fill:
8268 + /* step 1, set clock ratios */
8269 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
8270 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
8271 +
8272 + /* step 2: program timer intr */
8273 + W_REG(&mipsr->timer, 100);
8274 + (void) R_REG(&mipsr->timer);
8275 +
8276 + /* step 3, switch to async */
8277 + sync_mode = MFC0(C0_BROADCOM, 4);
8278 + MTC0(C0_BROADCOM, 4, 1 << 22);
8279 +
8280 + /* step 4, set cfg active */
8281 + MTC0(C0_BROADCOM, 2, 0x9);
8282 +
8283 +
8284 + /* steps 5 & 6 */
8285 + __asm__ __volatile__ (
8286 + ".set\tmips3\n\t"
8287 + "wait\n\t"
8288 + ".set\tmips0"
8289 + );
8290 +
8291 + /* step 7, clear cfg_active */
8292 + MTC0(C0_BROADCOM, 2, 0);
8293 +
8294 + /* Additional Step: set back to orig sync mode */
8295 + MTC0(C0_BROADCOM, 4, sync_mode);
8296 +
8297 + /* step 8, fake soft reset */
8298 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
8299 +
8300 + end_fill:
8301 + /* step 9 set watchdog timer */
8302 + sb_watchdog(sbh, 20);
8303 + (void) R_REG(&cc->chipid);
8304 +
8305 + /* step 11 */
8306 + __asm__ __volatile__ (
8307 + ".set\tmips3\n\t"
8308 + "sync\n\t"
8309 + "wait\n\t"
8310 + ".set\tmips0"
8311 + );
8312 + while (1);
8313 + }
8314 +
8315 +done:
8316 + /* switch back to previous core */
8317 + sb_setcoreidx(sbh, idx);
8318 +
8319 + return ret;
8320 +}
8321 +
8322 +/*
8323 + * This also must be run from the cache on 47xx
8324 + * so there are no mips core BIU ops in progress
8325 + * when the PFC is enabled.
8326 + */
8327 +
8328 +static void
8329 +BCMINITFN(_enable_pfc)(uint32 mode)
8330 +{
8331 + /* write range */
8332 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
8333 +
8334 + /* enable */
8335 + *(volatile uint32 *)PFC_CR0 = mode;
8336 +}
8337 +
8338 +void
8339 +BCMINITFN(enable_pfc)(uint32 mode)
8340 +{
8341 + ulong start, end;
8342 + int i;
8343 +
8344 + /* If auto then choose the correct mode for this
8345 + platform, currently we only ever select one mode */
8346 + if (mode == PFC_AUTO)
8347 + mode = PFC_INST;
8348 +
8349 + /* enable prefetch cache if available */
8350 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
8351 + start = (ulong) &BCMINIT(_enable_pfc);
8352 + end = (ulong) &BCMINIT(enable_pfc);
8353 +
8354 + /* Preload handler into the cache one line at a time */
8355 + for (i = 0; i < (end - start); i += 4)
8356 + cache_op(start + i, Fill_I);
8357 +
8358 + BCMINIT(_enable_pfc)(mode);
8359 + }
8360 +}
8361 +
8362 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
8363 +uint32
8364 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
8365 +{
8366 + sbmemcregs_t *memc;
8367 + uint32 ret = 0;
8368 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
8369 + uint idx, rev;
8370 +
8371 + idx = sb_coreidx(sbh);
8372 +
8373 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
8374 + if (memc == 0)
8375 + goto out;
8376 +
8377 + rev = sb_corerev(sbh);
8378 +
8379 + config = R_REG(&memc->config);
8380 + wr = R_REG(&memc->wrncdlcor);
8381 + rd = R_REG(&memc->rdncdlcor);
8382 + misc = R_REG(&memc->miscdlyctl);
8383 + dqsg = R_REG(&memc->dqsgatencdl);
8384 +
8385 + rd &= MEMC_RDNCDLCOR_RD_MASK;
8386 + wr &= MEMC_WRNCDLCOR_WR_MASK;
8387 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
8388 +
8389 + if (config & MEMC_CONFIG_DDR) {
8390 + ret = (wr << 16) | (rd << 8) | dqsg;
8391 + } else {
8392 + if (rev > 0)
8393 + cd = rd;
8394 + else
8395 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
8396 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
8397 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
8398 + ret = (sm << 16) | (sd << 8) | cd;
8399 + }
8400 +
8401 +out:
8402 + /* switch back to previous core */
8403 + sb_setcoreidx(sbh, idx);
8404 +
8405 + return ret;
8406 +}
8407 +
8408 diff -Naur linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
8409 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
8410 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-04-06 15:34:14.000000000 +0200
8411 @@ -0,0 +1,588 @@
8412 +/*
8413 + * Low-Level PCI and SB support for BCM47xx
8414 + *
8415 + * Copyright 2005, Broadcom Corporation
8416 + * All Rights Reserved.
8417 + *
8418 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8419 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8420 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8421 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8422 + *
8423 + * $Id$
8424 + */
8425 +
8426 +#include <typedefs.h>
8427 +#include <pcicfg.h>
8428 +#include <bcmdevs.h>
8429 +#include <sbconfig.h>
8430 +#include <osl.h>
8431 +#include <sbutils.h>
8432 +#include <sbpci.h>
8433 +#include <bcmendian.h>
8434 +#include <bcmutils.h>
8435 +#include <bcmnvram.h>
8436 +#include <hndmips.h>
8437 +
8438 +/* Can free sbpci_init() memory after boot */
8439 +#ifndef linux
8440 +#define __init
8441 +#endif
8442 +
8443 +/* Emulated configuration space */
8444 +static pci_config_regs sb_config_regs[SB_MAXCORES];
8445 +
8446 +/* Banned cores */
8447 +static uint16 pci_ban[32] = { 0 };
8448 +static uint pci_banned = 0;
8449 +
8450 +/* CardBus mode */
8451 +static bool cardbus = FALSE;
8452 +
8453 +/* Disable PCI host core */
8454 +static bool pci_disabled = FALSE;
8455 +
8456 +/*
8457 + * Functions for accessing external PCI configuration space
8458 + */
8459 +
8460 +/* Assume one-hot slot wiring */
8461 +#define PCI_SLOT_MAX 16
8462 +
8463 +static uint32
8464 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
8465 +{
8466 + uint coreidx;
8467 + sbpciregs_t *regs;
8468 + uint32 addr = 0;
8469 +
8470 + /* CardBusMode supports only one device */
8471 + if (cardbus && dev > 1)
8472 + return 0;
8473 +
8474 + coreidx = sb_coreidx(sbh);
8475 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
8476 +
8477 + /* Type 0 transaction */
8478 + if (bus == 1) {
8479 + /* Skip unwired slots */
8480 + if (dev < PCI_SLOT_MAX) {
8481 + /* Slide the PCI window to the appropriate slot */
8482 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
8483 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
8484 + (func << 8) | (off & ~3);
8485 + }
8486 + }
8487 +
8488 + /* Type 1 transaction */
8489 + else {
8490 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
8491 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
8492 + }
8493 +
8494 + sb_setcoreidx(sbh, coreidx);
8495 +
8496 + return addr;
8497 +}
8498 +
8499 +static int
8500 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8501 +{
8502 + uint32 addr, *reg = NULL, val;
8503 + int ret = 0;
8504 +
8505 + if (pci_disabled ||
8506 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
8507 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
8508 + BUSPROBE(val, reg))
8509 + val = 0xffffffff;
8510 +
8511 + val >>= 8 * (off & 3);
8512 + if (len == 4)
8513 + *((uint32 *) buf) = val;
8514 + else if (len == 2)
8515 + *((uint16 *) buf) = (uint16) val;
8516 + else if (len == 1)
8517 + *((uint8 *) buf) = (uint8) val;
8518 + else
8519 + ret = -1;
8520 +
8521 + if (reg)
8522 + REG_UNMAP(reg);
8523 +
8524 + return ret;
8525 +}
8526 +
8527 +static int
8528 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8529 +{
8530 + uint32 addr, *reg = NULL, val;
8531 + int ret = 0;
8532 +
8533 + if (pci_disabled ||
8534 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
8535 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
8536 + BUSPROBE(val, reg))
8537 + goto done;
8538 +
8539 + if (len == 4)
8540 + val = *((uint32 *) buf);
8541 + else if (len == 2) {
8542 + val &= ~(0xffff << (8 * (off & 3)));
8543 + val |= *((uint16 *) buf) << (8 * (off & 3));
8544 + } else if (len == 1) {
8545 + val &= ~(0xff << (8 * (off & 3)));
8546 + val |= *((uint8 *) buf) << (8 * (off & 3));
8547 + } else
8548 + ret = -1;
8549 +
8550 + W_REG(reg, val);
8551 +
8552 + done:
8553 + if (reg)
8554 + REG_UNMAP(reg);
8555 +
8556 + return ret;
8557 +}
8558 +
8559 +/*
8560 + * Functions for accessing translated SB configuration space
8561 + */
8562 +
8563 +static int
8564 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8565 +{
8566 + pci_config_regs *cfg;
8567 +
8568 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
8569 + return -1;
8570 + cfg = &sb_config_regs[dev];
8571 +
8572 + ASSERT(ISALIGNED(off, len));
8573 + ASSERT(ISALIGNED((uintptr)buf, len));
8574 +
8575 + if (len == 4)
8576 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
8577 + else if (len == 2)
8578 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
8579 + else if (len == 1)
8580 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
8581 + else
8582 + return -1;
8583 +
8584 + return 0;
8585 +}
8586 +
8587 +static int
8588 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8589 +{
8590 + uint coreidx, n;
8591 + void *regs;
8592 + sbconfig_t *sb;
8593 + pci_config_regs *cfg;
8594 +
8595 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
8596 + return -1;
8597 + cfg = &sb_config_regs[dev];
8598 +
8599 + ASSERT(ISALIGNED(off, len));
8600 + ASSERT(ISALIGNED((uintptr)buf, len));
8601 +
8602 + /* Emulate BAR sizing */
8603 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
8604 + len == 4 && *((uint32 *) buf) == ~0) {
8605 + coreidx = sb_coreidx(sbh);
8606 + if ((regs = sb_setcoreidx(sbh, dev))) {
8607 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
8608 + /* Highest numbered address match register */
8609 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
8610 + if (off == OFFSETOF(pci_config_regs, base[0]))
8611 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
8612 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
8613 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
8614 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
8615 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
8616 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
8617 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
8618 + }
8619 + sb_setcoreidx(sbh, coreidx);
8620 + return 0;
8621 + }
8622 +
8623 + if (len == 4)
8624 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
8625 + else if (len == 2)
8626 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
8627 + else if (len == 1)
8628 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
8629 + else
8630 + return -1;
8631 +
8632 + return 0;
8633 +}
8634 +
8635 +int
8636 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8637 +{
8638 + if (bus == 0)
8639 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
8640 + else
8641 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
8642 +}
8643 +
8644 +int
8645 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
8646 +{
8647 + if (bus == 0)
8648 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
8649 + else
8650 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
8651 +}
8652 +
8653 +void
8654 +sbpci_ban(uint16 core)
8655 +{
8656 + if (pci_banned < ARRAYSIZE(pci_ban))
8657 + pci_ban[pci_banned++] = core;
8658 +}
8659 +
8660 +static int
8661 +sbpci_init_pci(sb_t *sbh)
8662 +{
8663 + uint chip, chiprev, chippkg, host;
8664 + uint32 boardflags;
8665 + sbpciregs_t *pci;
8666 + sbconfig_t *sb;
8667 + uint32 val;
8668 +
8669 + chip = sb_chip(sbh);
8670 + chiprev = sb_chiprev(sbh);
8671 + chippkg = sb_chippkg(sbh);
8672 +
8673 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
8674 + printf("PCI: no core\n");
8675 + pci_disabled = TRUE;
8676 + return -1;
8677 + }
8678 + sb_core_reset(sbh, 0);
8679 +
8680 + boardflags = (uint32) getintvar(NULL, "boardflags");
8681 +
8682 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
8683 + pci_disabled = TRUE;
8684 +
8685 + /*
8686 + * The 200-pin BCM4712 package does not bond out PCI. Even when
8687 + * PCI is bonded out, some boards may leave the pins
8688 + * floating.
8689 + */
8690 + if (((chip == BCM4712_DEVICE_ID) &&
8691 + ((chippkg == BCM4712SMALL_PKG_ID) ||
8692 + (chippkg == BCM4712MID_PKG_ID))) ||
8693 + (boardflags & BFL_NOPCI))
8694 + pci_disabled = TRUE;
8695 +
8696 + /*
8697 + * If the PCI core should not be touched (disabled, not bonded
8698 + * out, or pins floating), do not even attempt to access core
8699 + * registers. Otherwise, try to determine if it is in host
8700 + * mode.
8701 + */
8702 + if (pci_disabled)
8703 + host = 0;
8704 + else
8705 + host = !BUSPROBE(val, &pci->control);
8706 +
8707 + if (!host) {
8708 + /* Disable PCI interrupts in client mode */
8709 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
8710 + W_REG(&sb->sbintvec, 0);
8711 +
8712 + /* Disable the PCI bridge in client mode */
8713 + sbpci_ban(SB_PCI);
8714 + printf("PCI: Disabled\n");
8715 + } else {
8716 + /* Reset the external PCI bus and enable the clock */
8717 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
8718 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
8719 + OSL_DELAY(150); /* delay > 100 us */
8720 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
8721 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
8722 + OSL_DELAY(1); /* delay 1 us */
8723 +
8724 + /* Enable CardBusMode */
8725 + cardbus = nvram_match("cardbus", "1");
8726 + if (cardbus) {
8727 + printf("PCI: Enabling CardBus\n");
8728 + /* GPIO 1 resets the CardBus device on bcm94710ap */
8729 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
8730 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
8731 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
8732 + }
8733 +
8734 + /* 64 MB I/O access window */
8735 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
8736 + /* 64 MB configuration access window */
8737 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
8738 + /* 1 GB memory access window */
8739 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
8740 +
8741 + /* Enable PCI bridge BAR0 prefetch and burst */
8742 + val = 6;
8743 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
8744 +
8745 + /* Enable PCI interrupts */
8746 + W_REG(&pci->intmask, PCI_INTA);
8747 + }
8748 +
8749 + return 0;
8750 +}
8751 +
8752 +static int
8753 +sbpci_init_cores(sb_t *sbh)
8754 +{
8755 + uint chip, chiprev, chippkg, coreidx, i;
8756 + sbconfig_t *sb;
8757 + pci_config_regs *cfg;
8758 + void *regs;
8759 + char varname[8];
8760 + uint wlidx = 0;
8761 + uint16 vendor, core;
8762 + uint8 class, subclass, progif;
8763 + uint32 val;
8764 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
8765 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
8766 +
8767 + chip = sb_chip(sbh);
8768 + chiprev = sb_chiprev(sbh);
8769 + chippkg = sb_chippkg(sbh);
8770 + coreidx = sb_coreidx(sbh);
8771 +
8772 + /* Scan the SB bus */
8773 + bzero(sb_config_regs, sizeof(sb_config_regs));
8774 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
8775 + cfg->vendor = 0xffff;
8776 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
8777 + continue;
8778 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
8779 +
8780 + /* Read ID register and parse vendor and core */
8781 + val = R_REG(&sb->sbidhigh);
8782 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
8783 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
8784 + progif = 0;
8785 +
8786 + /* Check if this core is banned */
8787 + for (i = 0; i < pci_banned; i++)
8788 + if (core == pci_ban[i])
8789 + break;
8790 + if (i < pci_banned)
8791 + continue;
8792 +
8793 + /* Known vendor translations */
8794 + switch (vendor) {
8795 + case SB_VEND_BCM:
8796 + vendor = VENDOR_BROADCOM;
8797 + break;
8798 + }
8799 +
8800 + /* Determine class based on known core codes */
8801 + switch (core) {
8802 + case SB_ILINE20:
8803 + class = PCI_CLASS_NET;
8804 + subclass = PCI_NET_ETHER;
8805 + core = BCM47XX_ILINE_ID;
8806 + break;
8807 + case SB_ILINE100:
8808 + class = PCI_CLASS_NET;
8809 + subclass = PCI_NET_ETHER;
8810 + core = BCM4610_ILINE_ID;
8811 + break;
8812 + case SB_ENET:
8813 + class = PCI_CLASS_NET;
8814 + subclass = PCI_NET_ETHER;
8815 + core = BCM47XX_ENET_ID;
8816 + break;
8817 + case SB_SDRAM:
8818 + case SB_MEMC:
8819 + class = PCI_CLASS_MEMORY;
8820 + subclass = PCI_MEMORY_RAM;
8821 + break;
8822 + case SB_PCI:
8823 + class = PCI_CLASS_BRIDGE;
8824 + subclass = PCI_BRIDGE_PCI;
8825 + break;
8826 + case SB_MIPS:
8827 + case SB_MIPS33:
8828 + class = PCI_CLASS_CPU;
8829 + subclass = PCI_CPU_MIPS;
8830 + break;
8831 + case SB_CODEC:
8832 + class = PCI_CLASS_COMM;
8833 + subclass = PCI_COMM_MODEM;
8834 + core = BCM47XX_V90_ID;
8835 + break;
8836 + case SB_USB:
8837 + class = PCI_CLASS_SERIAL;
8838 + subclass = PCI_SERIAL_USB;
8839 + progif = 0x10; /* OHCI */
8840 + core = BCM47XX_USB_ID;
8841 + break;
8842 + case SB_USB11H:
8843 + class = PCI_CLASS_SERIAL;
8844 + subclass = PCI_SERIAL_USB;
8845 + progif = 0x10; /* OHCI */
8846 + core = BCM47XX_USBH_ID;
8847 + break;
8848 + case SB_USB11D:
8849 + class = PCI_CLASS_SERIAL;
8850 + subclass = PCI_SERIAL_USB;
8851 + core = BCM47XX_USBD_ID;
8852 + break;
8853 + case SB_IPSEC:
8854 + class = PCI_CLASS_CRYPT;
8855 + subclass = PCI_CRYPT_NETWORK;
8856 + core = BCM47XX_IPSEC_ID;
8857 + break;
8858 + case SB_ROBO:
8859 + class = PCI_CLASS_NET;
8860 + subclass = PCI_NET_OTHER;
8861 + core = BCM47XX_ROBO_ID;
8862 + break;
8863 + case SB_EXTIF:
8864 + case SB_CC:
8865 + class = PCI_CLASS_MEMORY;
8866 + subclass = PCI_MEMORY_FLASH;
8867 + break;
8868 + case SB_D11:
8869 + class = PCI_CLASS_NET;
8870 + subclass = PCI_NET_OTHER;
8871 + /* Let an nvram variable override this */
8872 + sprintf(varname, "wl%did", wlidx);
8873 + wlidx++;
8874 + if ((core = getintvar(NULL, varname)) == 0) {
8875 + if (chip == BCM4712_DEVICE_ID) {
8876 + if (chippkg == BCM4712SMALL_PKG_ID)
8877 + core = BCM4306_D11G_ID;
8878 + else
8879 + core = BCM4306_D11DUAL_ID;
8880 + } else {
8881 + /* 4310 */
8882 + core = BCM4310_D11B_ID;
8883 + }
8884 + }
8885 + break;
8886 +
8887 + default:
8888 + class = subclass = progif = 0xff;
8889 + break;
8890 + }
8891 +
8892 + /* Supported translations */
8893 + cfg->vendor = htol16(vendor);
8894 + cfg->device = htol16(core);
8895 + cfg->rev_id = chiprev;
8896 + cfg->prog_if = progif;
8897 + cfg->sub_class = subclass;
8898 + cfg->base_class = class;
8899 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
8900 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
8901 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
8902 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
8903 + cfg->base[4] = 0;
8904 + cfg->base[5] = 0;
8905 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
8906 + cfg->header_type = PCI_HEADER_BRIDGE;
8907 + else
8908 + cfg->header_type = PCI_HEADER_NORMAL;
8909 + /* Save core interrupt flag */
8910 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
8911 + /* Default to MIPS shared interrupt 0 */
8912 + cfg->int_line = 0;
8913 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
8914 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
8915 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
8916 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
8917 + val = R_REG(&sb->sbipsflag);
8918 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
8919 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
8920 + break;
8921 + }
8922 + if (cfg->int_line > 4)
8923 + cfg->int_line = 0;
8924 + }
8925 + /* Emulated core */
8926 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
8927 + }
8928 +
8929 + sb_setcoreidx(sbh, coreidx);
8930 + return 0;
8931 +}
8932 +
8933 +int __init
8934 +sbpci_init(sb_t *sbh)
8935 +{
8936 + sbpci_init_pci(sbh);
8937 + sbpci_init_cores(sbh);
8938 + return 0;
8939 +}
8940 +
8941 +void
8942 +sbpci_check(sb_t *sbh)
8943 +{
8944 + uint coreidx;
8945 + sbpciregs_t *pci;
8946 + uint32 sbtopci1;
8947 + uint32 buf[64], *ptr, i;
8948 + ulong pa;
8949 + volatile uint j;
8950 +
8951 + coreidx = sb_coreidx(sbh);
8952 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
8953 +
8954 + /* Clear the test array */
8955 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
8956 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
8957 + memset(ptr, 0, sizeof(buf));
8958 +
8959 + /* Point PCI window 1 to memory */
8960 + sbtopci1 = R_REG(&pci->sbtopci1);
8961 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
8962 +
8963 + /* Fill the test array via PCI window 1 */
8964 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
8965 + for (i = 0; i < ARRAYSIZE(buf); i++) {
8966 + for (j = 0; j < 2; j++);
8967 + W_REG(&ptr[i], i);
8968 + }
8969 + REG_UNMAP(ptr);
8970 +
8971 + /* Restore PCI window 1 */
8972 + W_REG(&pci->sbtopci1, sbtopci1);
8973 +
8974 + /* Check the test array */
8975 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
8976 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
8977 + for (i = 0; i < ARRAYSIZE(buf); i++) {
8978 + if (ptr[i] != i)
8979 + break;
8980 + }
8981 +
8982 + /* Change the clock if the test fails */
8983 + if (i < ARRAYSIZE(buf)) {
8984 + uint32 req, cur;
8985 +
8986 + cur = sb_clock(sbh);
8987 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
8988 + for (req = 104000000; req < 176000000; req += 4000000) {
8989 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
8990 + /* This will only reset if the clocks are valid and have changed */
8991 + sb_mips_setclock(sbh, req, 0, 0);
8992 + }
8993 + /* Should not reach here */
8994 + ASSERT(0);
8995 + }
8996 +
8997 + sb_setcoreidx(sbh, coreidx);
8998 +}
8999 +
9000 diff -Naur linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
9001 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
9002 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-04-06 15:34:14.000000000 +0200
9003 @@ -0,0 +1,234 @@
9004 +/*
9005 + * Generic setup routines for Broadcom MIPS boards
9006 + *
9007 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
9008 + *
9009 + * This program is free software; you can redistribute it and/or modify it
9010 + * under the terms of the GNU General Public License as published by the
9011 + * Free Software Foundation; either version 2 of the License, or (at your
9012 + * option) any later version.
9013 + *
9014 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9015 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9016 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9017 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9018 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9019 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9020 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9021 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9022 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9023 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9024 + *
9025 + * You should have received a copy of the GNU General Public License along
9026 + * with this program; if not, write to the Free Software Foundation, Inc.,
9027 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9028 + *
9029 + *
9030 + * Copyright 2005, Broadcom Corporation
9031 + * All Rights Reserved.
9032 + *
9033 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9034 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9035 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9036 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9037 + *
9038 + */
9039 +
9040 +#include <linux/config.h>
9041 +#include <linux/init.h>
9042 +#include <linux/kernel.h>
9043 +#include <linux/module.h>
9044 +#include <linux/serialP.h>
9045 +#include <linux/ide.h>
9046 +#include <asm/bootinfo.h>
9047 +#include <asm/cpu.h>
9048 +#include <asm/time.h>
9049 +#include <asm/reboot.h>
9050 +
9051 +#include <typedefs.h>
9052 +#include <osl.h>
9053 +#include <sbutils.h>
9054 +#include <bcmutils.h>
9055 +#include <bcmnvram.h>
9056 +#include <sbmips.h>
9057 +#include <trxhdr.h>
9058 +
9059 +/* Global SB handle */
9060 +sb_t *bcm947xx_sbh = NULL;
9061 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
9062 +
9063 +/* Convenience */
9064 +#define sbh bcm947xx_sbh
9065 +#define sbh_lock bcm947xx_sbh_lock
9066 +
9067 +extern void bcm947xx_time_init(void);
9068 +extern void bcm947xx_timer_setup(struct irqaction *irq);
9069 +
9070 +#ifdef CONFIG_REMOTE_DEBUG
9071 +extern void set_debug_traps(void);
9072 +extern void rs_kgdb_hook(struct serial_state *);
9073 +extern void breakpoint(void);
9074 +#endif
9075 +
9076 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
9077 +extern struct ide_ops std_ide_ops;
9078 +#endif
9079 +
9080 +/* Kernel command line */
9081 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
9082 +
9083 +void
9084 +bcm947xx_machine_restart(char *command)
9085 +{
9086 + printk("Please stand by while rebooting the system...\n");
9087 +
9088 + /* Set the watchdog timer to reset immediately */
9089 + __cli();
9090 + sb_watchdog(sbh, 1);
9091 + while (1);
9092 +}
9093 +
9094 +void
9095 +bcm947xx_machine_halt(void)
9096 +{
9097 + printk("System halted\n");
9098 +
9099 + /* Disable interrupts and watchdog and spin forever */
9100 + __cli();
9101 + sb_watchdog(sbh, 0);
9102 + while (1);
9103 +}
9104 +
9105 +#ifdef CONFIG_SERIAL
9106 +
9107 +static int ser_line = 0;
9108 +
9109 +typedef struct {
9110 + void *regs;
9111 + uint irq;
9112 + uint baud_base;
9113 + uint reg_shift;
9114 +} serial_port;
9115 +
9116 +static serial_port ports[4];
9117 +static int num_ports = 0;
9118 +
9119 +static void
9120 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
9121 +{
9122 + ports[num_ports].regs = regs;
9123 + ports[num_ports].irq = irq;
9124 + ports[num_ports].baud_base = baud_base;
9125 + ports[num_ports].reg_shift = reg_shift;
9126 + num_ports++;
9127 +}
9128 +
9129 +static void
9130 +do_serial_add(serial_port *port)
9131 +{
9132 + void *regs;
9133 + uint irq;
9134 + uint baud_base;
9135 + uint reg_shift;
9136 + struct serial_struct s;
9137 +
9138 + regs = port->regs;
9139 + irq = port->irq;
9140 + baud_base = port->baud_base;
9141 + reg_shift = port->reg_shift;
9142 +
9143 + memset(&s, 0, sizeof(s));
9144 +
9145 + s.line = ser_line++;
9146 + s.iomem_base = regs;
9147 + s.irq = irq + 2;
9148 + s.baud_base = baud_base / 16;
9149 + s.flags = ASYNC_BOOT_AUTOCONF;
9150 + s.io_type = SERIAL_IO_MEM;
9151 + s.iomem_reg_shift = reg_shift;
9152 +
9153 + if (early_serial_setup(&s) != 0) {
9154 + printk(KERN_ERR "Serial setup failed!\n");
9155 + }
9156 +}
9157 +
9158 +#endif /* CONFIG_SERIAL */
9159 +
9160 +void __init
9161 +brcm_setup(void)
9162 +{
9163 + char *s;
9164 + int i;
9165 + char *value;
9166 +
9167 + /* Get global SB handle */
9168 + sbh = sb_kattach();
9169 +
9170 + /* Initialize clocks and interrupts */
9171 + sb_mips_init(sbh);
9172 +
9173 + if (BCM330X(current_cpu_data.processor_id) &&
9174 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
9175 + /*
9176 + * Now that the sbh is inited set the proper PFC value
9177 + */
9178 + printk("Setting the PFC to its default value\n");
9179 + enable_pfc(PFC_AUTO);
9180 + }
9181 +
9182 +
9183 +#ifdef CONFIG_SERIAL
9184 + sb_serial_init(sbh, serial_add);
9185 +
9186 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
9187 + /* Initialize UARTs */
9188 + s = nvram_get("kernel_args");
9189 + if (!s) s = "";
9190 + if (!strncmp(s, "console=ttyS1", 13)) {
9191 + for (i = num_ports; i; i--)
9192 + do_serial_add(&ports[i - 1]);
9193 + } else {
9194 + for (i = 0; i < num_ports; i++)
9195 + do_serial_add(&ports[i]);
9196 + }
9197 +#endif
9198 +
9199 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
9200 + ide_ops = &std_ide_ops;
9201 +#endif
9202 +
9203 + /* Override default command line arguments */
9204 + value = nvram_get("kernel_cmdline");
9205 + if (value && strlen(value) && strncmp(value, "empty", 5))
9206 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
9207 +
9208 +
9209 + /* Generic setup */
9210 + _machine_restart = bcm947xx_machine_restart;
9211 + _machine_halt = bcm947xx_machine_halt;
9212 + _machine_power_off = bcm947xx_machine_halt;
9213 +
9214 + board_time_init = bcm947xx_time_init;
9215 + board_timer_setup = bcm947xx_timer_setup;
9216 +}
9217 +
9218 +const char *
9219 +get_system_type(void)
9220 +{
9221 + static char s[32];
9222 +
9223 + if (bcm947xx_sbh) {
9224 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
9225 + sb_chiprev(bcm947xx_sbh));
9226 + return s;
9227 + }
9228 + else
9229 + return "Broadcom BCM947XX";
9230 +}
9231 +
9232 +void __init
9233 +bus_error_init(void)
9234 +{
9235 +}
9236 +
9237 +EXPORT_SYMBOL(bcm947xx_sbh);
9238 diff -Naur linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
9239 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
9240 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-04-06 15:34:14.000000000 +0200
9241 @@ -0,0 +1,418 @@
9242 +/*
9243 + * Broadcom SiliconBackplane chipcommon serial flash interface
9244 + *
9245 + * Copyright 2005, Broadcom Corporation
9246 + * All Rights Reserved.
9247 + *
9248 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9249 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9250 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9251 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9252 + *
9253 + * $Id$
9254 + */
9255 +
9256 +#include <osl.h>
9257 +#include <typedefs.h>
9258 +#include <sbconfig.h>
9259 +#include <sbchipc.h>
9260 +#include <mipsinc.h>
9261 +#include <bcmutils.h>
9262 +#include <bcmdevs.h>
9263 +#include <sflash.h>
9264 +
9265 +/* Private global state */
9266 +static struct sflash sflash;
9267 +
9268 +/* Issue a serial flash command */
9269 +static INLINE void
9270 +sflash_cmd(chipcregs_t *cc, uint opcode)
9271 +{
9272 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
9273 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
9274 +}
9275 +
9276 +/* Initialize serial flash access */
9277 +struct sflash *
9278 +sflash_init(chipcregs_t *cc)
9279 +{
9280 + uint32 id, id2;
9281 +
9282 + bzero(&sflash, sizeof(sflash));
9283 +
9284 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
9285 +
9286 + switch (sflash.type) {
9287 + case SFLASH_ST:
9288 + /* Probe for ST chips */
9289 + sflash_cmd(cc, SFLASH_ST_DP);
9290 + sflash_cmd(cc, SFLASH_ST_RES);
9291 + id = R_REG(&cc->flashdata);
9292 + switch (id) {
9293 + case 0x11:
9294 + /* ST M25P20 2 Mbit Serial Flash */
9295 + sflash.blocksize = 64 * 1024;
9296 + sflash.numblocks = 4;
9297 + break;
9298 + case 0x12:
9299 + /* ST M25P40 4 Mbit Serial Flash */
9300 + sflash.blocksize = 64 * 1024;
9301 + sflash.numblocks = 8;
9302 + break;
9303 + case 0x13:
9304 + /* ST M25P80 8 Mbit Serial Flash */
9305 + sflash.blocksize = 64 * 1024;
9306 + sflash.numblocks = 16;
9307 + break;
9308 + case 0x14:
9309 + /* ST M25P16 16 Mbit Serial Flash */
9310 + sflash.blocksize = 64 * 1024;
9311 + sflash.numblocks = 32;
9312 + break;
9313 + case 0x15:
9314 + /* ST M25P32 32 Mbit Serial Flash */
9315 + sflash.blocksize = 64 * 1024;
9316 + sflash.numblocks = 64;
9317 + break;
9318 + case 0xbf:
9319 + W_REG(&cc->flashaddress, 1);
9320 + sflash_cmd(cc, SFLASH_ST_RES);
9321 + id2 = R_REG(&cc->flashdata);
9322 + if (id2 == 0x44) {
9323 + /* SST M25VF80 4 Mbit Serial Flash */
9324 + sflash.blocksize = 64 * 1024;
9325 + sflash.numblocks = 8;
9326 + }
9327 + break;
9328 + }
9329 + break;
9330 +
9331 + case SFLASH_AT:
9332 + /* Probe for Atmel chips */
9333 + sflash_cmd(cc, SFLASH_AT_STATUS);
9334 + id = R_REG(&cc->flashdata) & 0x3c;
9335 + switch (id) {
9336 + case 0xc:
9337 + /* Atmel AT45DB011 1Mbit Serial Flash */
9338 + sflash.blocksize = 256;
9339 + sflash.numblocks = 512;
9340 + break;
9341 + case 0x14:
9342 + /* Atmel AT45DB021 2Mbit Serial Flash */
9343 + sflash.blocksize = 256;
9344 + sflash.numblocks = 1024;
9345 + break;
9346 + case 0x1c:
9347 + /* Atmel AT45DB041 4Mbit Serial Flash */
9348 + sflash.blocksize = 256;
9349 + sflash.numblocks = 2048;
9350 + break;
9351 + case 0x24:
9352 + /* Atmel AT45DB081 8Mbit Serial Flash */
9353 + sflash.blocksize = 256;
9354 + sflash.numblocks = 4096;
9355 + break;
9356 + case 0x2c:
9357 + /* Atmel AT45DB161 16Mbit Serial Flash */
9358 + sflash.blocksize = 512;
9359 + sflash.numblocks = 4096;
9360 + break;
9361 + case 0x34:
9362 + /* Atmel AT45DB321 32Mbit Serial Flash */
9363 + sflash.blocksize = 512;
9364 + sflash.numblocks = 8192;
9365 + break;
9366 + case 0x3c:
9367 + /* Atmel AT45DB642 64Mbit Serial Flash */
9368 + sflash.blocksize = 1024;
9369 + sflash.numblocks = 8192;
9370 + break;
9371 + }
9372 + break;
9373 + }
9374 +
9375 + sflash.size = sflash.blocksize * sflash.numblocks;
9376 + return sflash.size ? &sflash : NULL;
9377 +}
9378 +
9379 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
9380 +int
9381 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
9382 +{
9383 + int cnt;
9384 + uint32 *from, *to;
9385 +
9386 + if (!len)
9387 + return 0;
9388 +
9389 + if ((offset + len) > sflash.size)
9390 + return -22;
9391 +
9392 + if ((len >= 4) && (offset & 3))
9393 + cnt = 4 - (offset & 3);
9394 + else if ((len >= 4) && ((uint32)buf & 3))
9395 + cnt = 4 - ((uint32)buf & 3);
9396 + else
9397 + cnt = len;
9398 +
9399 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
9400 + to = (uint32 *)buf;
9401 +
9402 + if (cnt < 4) {
9403 + bcopy(from, to, cnt);
9404 + return cnt;
9405 + }
9406 +
9407 + while (cnt >= 4) {
9408 + *to++ = *from++;
9409 + cnt -= 4;
9410 + }
9411 +
9412 + return (len - cnt);
9413 +}
9414 +
9415 +/* Poll for command completion. Returns zero when complete. */
9416 +int
9417 +sflash_poll(chipcregs_t *cc, uint offset)
9418 +{
9419 + if (offset >= sflash.size)
9420 + return -22;
9421 +
9422 + switch (sflash.type) {
9423 + case SFLASH_ST:
9424 + /* Check for ST Write In Progress bit */
9425 + sflash_cmd(cc, SFLASH_ST_RDSR);
9426 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
9427 + case SFLASH_AT:
9428 + /* Check for Atmel Ready bit */
9429 + sflash_cmd(cc, SFLASH_AT_STATUS);
9430 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
9431 + }
9432 +
9433 + return 0;
9434 +}
9435 +
9436 +/* Write len bytes starting at offset into buf. Returns number of bytes
9437 + * written. Caller should poll for completion.
9438 + */
9439 +int
9440 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
9441 +{
9442 + struct sflash *sfl;
9443 + int ret = 0;
9444 + bool is4712b0;
9445 + uint32 page, byte, mask;
9446 +
9447 + if (!len)
9448 + return 0;
9449 +
9450 + if ((offset + len) > sflash.size)
9451 + return -22;
9452 +
9453 + sfl = &sflash;
9454 + switch (sfl->type) {
9455 + case SFLASH_ST:
9456 + mask = R_REG(&cc->chipid);
9457 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
9458 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
9459 + /* Enable writes */
9460 + sflash_cmd(cc, SFLASH_ST_WREN);
9461 + if (is4712b0) {
9462 + mask = 1 << 14;
9463 + W_REG(&cc->flashaddress, offset);
9464 + W_REG(&cc->flashdata, *buf++);
9465 + /* Set chip select */
9466 + OR_REG(&cc->gpioout, mask);
9467 + /* Issue a page program with the first byte */
9468 + sflash_cmd(cc, SFLASH_ST_PP);
9469 + ret = 1;
9470 + offset++;
9471 + len--;
9472 + while (len > 0) {
9473 + if ((offset & 255) == 0) {
9474 + /* Page boundary, drop cs and return */
9475 + AND_REG(&cc->gpioout, ~mask);
9476 + if (!sflash_poll(cc, offset)) {
9477 + /* Flash rejected command */
9478 + return -11;
9479 + }
9480 + return ret;
9481 + } else {
9482 + /* Write single byte */
9483 + sflash_cmd(cc, *buf++);
9484 + }
9485 + ret++;
9486 + offset++;
9487 + len--;
9488 + }
9489 + /* All done, drop cs if needed */
9490 + if ((offset & 255) != 1) {
9491 + /* Drop cs */
9492 + AND_REG(&cc->gpioout, ~mask);
9493 + if (!sflash_poll(cc, offset)) {
9494 + /* Flash rejected command */
9495 + return -12;
9496 + }
9497 + }
9498 + } else {
9499 + ret = 1;
9500 + W_REG(&cc->flashaddress, offset);
9501 + W_REG(&cc->flashdata, *buf);
9502 + /* Page program */
9503 + sflash_cmd(cc, SFLASH_ST_PP);
9504 + }
9505 + break;
9506 + case SFLASH_AT:
9507 + mask = sfl->blocksize - 1;
9508 + page = (offset & ~mask) << 1;
9509 + byte = offset & mask;
9510 + /* Read main memory page into buffer 1 */
9511 + if (byte || len < sfl->blocksize) {
9512 + W_REG(&cc->flashaddress, page);
9513 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
9514 + /* 250 us for AT45DB321B */
9515 + SPINWAIT(sflash_poll(cc, offset), 1000);
9516 + ASSERT(!sflash_poll(cc, offset));
9517 + }
9518 + /* Write into buffer 1 */
9519 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
9520 + W_REG(&cc->flashaddress, byte++);
9521 + W_REG(&cc->flashdata, *buf++);
9522 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
9523 + }
9524 + /* Write buffer 1 into main memory page */
9525 + W_REG(&cc->flashaddress, page);
9526 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
9527 + break;
9528 + }
9529 +
9530 + return ret;
9531 +}
9532 +
9533 +/* Erase a region. Returns number of bytes scheduled for erasure.
9534 + * Caller should poll for completion.
9535 + */
9536 +int
9537 +sflash_erase(chipcregs_t *cc, uint offset)
9538 +{
9539 + struct sflash *sfl;
9540 +
9541 + if (offset >= sflash.size)
9542 + return -22;
9543 +
9544 + sfl = &sflash;
9545 + switch (sfl->type) {
9546 + case SFLASH_ST:
9547 + sflash_cmd(cc, SFLASH_ST_WREN);
9548 + W_REG(&cc->flashaddress, offset);
9549 + sflash_cmd(cc, SFLASH_ST_SE);
9550 + return sfl->blocksize;
9551 + case SFLASH_AT:
9552 + W_REG(&cc->flashaddress, offset << 1);
9553 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
9554 + return sfl->blocksize;
9555 + }
9556 +
9557 + return 0;
9558 +}
9559 +
9560 +/*
9561 + * writes the appropriate range of flash, a NULL buf simply erases
9562 + * the region of flash
9563 + */
9564 +int
9565 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
9566 +{
9567 + struct sflash *sfl;
9568 + uchar *block = NULL, *cur_ptr, *blk_ptr;
9569 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
9570 + uint blk_offset, blk_len, copied;
9571 + int bytes, ret = 0;
9572 +
9573 + /* Check address range */
9574 + if (len <= 0)
9575 + return 0;
9576 +
9577 + sfl = &sflash;
9578 + if ((offset + len) > sfl->size)
9579 + return -1;
9580 +
9581 + blocksize = sfl->blocksize;
9582 + mask = blocksize - 1;
9583 +
9584 + /* Allocate a block of mem */
9585 + if (!(block = MALLOC(NULL, blocksize)))
9586 + return -1;
9587 +
9588 + while (len) {
9589 + /* Align offset */
9590 + cur_offset = offset & ~mask;
9591 + cur_length = blocksize;
9592 + cur_ptr = block;
9593 +
9594 + remainder = blocksize - (offset & mask);
9595 + if (len < remainder)
9596 + cur_retlen = len;
9597 + else
9598 + cur_retlen = remainder;
9599 +
9600 + /* buf == NULL means erase only */
9601 + if (buf) {
9602 + /* Copy existing data into holding block if necessary */
9603 + if ((offset & mask) || (len < blocksize)) {
9604 + blk_offset = cur_offset;
9605 + blk_len = cur_length;
9606 + blk_ptr = cur_ptr;
9607 +
9608 + /* Copy entire block */
9609 + while(blk_len) {
9610 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
9611 + blk_offset += copied;
9612 + blk_len -= copied;
9613 + blk_ptr += copied;
9614 + }
9615 + }
9616 +
9617 + /* Copy input data into holding block */
9618 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
9619 + }
9620 +
9621 + /* Erase block */
9622 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
9623 + goto done;
9624 + while (sflash_poll(cc, (uint) cur_offset));
9625 +
9626 + /* buf == NULL means erase only */
9627 + if (!buf) {
9628 + offset += cur_retlen;
9629 + len -= cur_retlen;
9630 + continue;
9631 + }
9632 +
9633 + /* Write holding block */
9634 + while (cur_length > 0) {
9635 + if ((bytes = sflash_write(cc,
9636 + (uint) cur_offset,
9637 + (uint) cur_length,
9638 + (uchar *) cur_ptr)) < 0) {
9639 + ret = bytes;
9640 + goto done;
9641 + }
9642 + while (sflash_poll(cc, (uint) cur_offset));
9643 + cur_offset += bytes;
9644 + cur_length -= bytes;
9645 + cur_ptr += bytes;
9646 + }
9647 +
9648 + offset += cur_retlen;
9649 + len -= cur_retlen;
9650 + buf += cur_retlen;
9651 + }
9652 +
9653 + ret = len;
9654 +done:
9655 + if (block)
9656 + MFREE(NULL, block, blocksize);
9657 + return ret;
9658 +}
9659 +
9660 diff -Naur linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
9661 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
9662 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-04-06 15:34:14.000000000 +0200
9663 @@ -0,0 +1,118 @@
9664 +/*
9665 + * Copyright 2004, Broadcom Corporation
9666 + * All Rights Reserved.
9667 + *
9668 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9669 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9670 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9671 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9672 + *
9673 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
9674 + */
9675 +#include <linux/config.h>
9676 +#include <linux/init.h>
9677 +#include <linux/kernel.h>
9678 +#include <linux/sched.h>
9679 +#include <linux/serial_reg.h>
9680 +#include <linux/interrupt.h>
9681 +#include <asm/addrspace.h>
9682 +#include <asm/io.h>
9683 +#include <asm/time.h>
9684 +
9685 +#include <typedefs.h>
9686 +#include <osl.h>
9687 +#include <sbutils.h>
9688 +#include <bcmnvram.h>
9689 +#include <sbconfig.h>
9690 +#include <sbextif.h>
9691 +#include <sbmips.h>
9692 +
9693 +/* Global SB handle */
9694 +extern void *bcm947xx_sbh;
9695 +extern spinlock_t bcm947xx_sbh_lock;
9696 +
9697 +/* Convenience */
9698 +#define sbh bcm947xx_sbh
9699 +#define sbh_lock bcm947xx_sbh_lock
9700 +
9701 +extern int panic_timeout;
9702 +static int watchdog = 0;
9703 +static u8 *mcr = NULL;
9704 +
9705 +void __init
9706 +bcm947xx_time_init(void)
9707 +{
9708 + unsigned int hz;
9709 + extifregs_t *eir;
9710 +
9711 + /*
9712 + * Use deterministic values for initial counter interrupt
9713 + * so that calibrate delay avoids encountering a counter wrap.
9714 + */
9715 + write_c0_count(0);
9716 + write_c0_compare(0xffff);
9717 +
9718 + if (!(hz = sb_mips_clock(sbh)))
9719 + hz = 100000000;
9720 +
9721 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
9722 + (hz + 500000) / 1000000);
9723 +
9724 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
9725 + mips_hpt_frequency = hz / 2;
9726 +
9727 + /* Set watchdog interval in ms */
9728 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
9729 +
9730 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
9731 + if (watchdog > 0) {
9732 + if (watchdog < 3000)
9733 + watchdog = 3000;
9734 + }
9735 +
9736 +
9737 + /* Set panic timeout in seconds */
9738 + panic_timeout = watchdog / 1000;
9739 +
9740 + /* Setup blink */
9741 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
9742 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
9743 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
9744 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
9745 + }
9746 +}
9747 +
9748 +static void
9749 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
9750 +{
9751 + /* Generic MIPS timer code */
9752 + timer_interrupt(irq, dev_id, regs);
9753 +
9754 + /* Set the watchdog timer to reset after the specified number of ms */
9755 + if (watchdog > 0)
9756 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
9757 +
9758 +#ifdef CONFIG_HWSIM
9759 + (*((int *)0xa0000f1c))++;
9760 +#else
9761 + /* Blink one of the LEDs in the external UART */
9762 + if (mcr && !(jiffies % (HZ/2)))
9763 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
9764 +#endif
9765 +}
9766 +
9767 +static struct irqaction bcm947xx_timer_irqaction = {
9768 + bcm947xx_timer_interrupt,
9769 + SA_INTERRUPT,
9770 + 0,
9771 + "timer",
9772 + NULL,
9773 + NULL
9774 +};
9775 +
9776 +void __init
9777 +bcm947xx_timer_setup(struct irqaction *irq)
9778 +{
9779 + /* Enable the timer interrupt */
9780 + setup_irq(7, &bcm947xx_timer_irqaction);
9781 +}
9782 diff -Naur linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
9783 --- linux.old/arch/mips/config-shared.in 2006-04-06 15:38:09.000000000 +0200
9784 +++ linux.dev/arch/mips/config-shared.in 2006-04-06 15:34:14.000000000 +0200
9785 @@ -208,6 +208,14 @@
9786 fi
9787 define_bool CONFIG_MIPS_RTC y
9788 fi
9789 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
9790 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
9791 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
9792 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
9793 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
9794 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
9795 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
9796 +fi
9797 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
9798 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
9799 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
9800 @@ -229,6 +237,11 @@
9801 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
9802
9803 #
9804 +# Provide an option for a default kernel command line
9805 +#
9806 +string 'Default kernel command string' CONFIG_CMDLINE ""
9807 +
9808 +#
9809 # Select some configuration options automatically based on user selections.
9810 #
9811 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
9812 @@ -554,6 +567,13 @@
9813 define_bool CONFIG_SWAP_IO_SPACE_L y
9814 define_bool CONFIG_BOOT_ELF32 y
9815 fi
9816 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
9817 + define_bool CONFIG_PCI y
9818 + define_bool CONFIG_NONCOHERENT_IO y
9819 + define_bool CONFIG_NEW_TIME_C y
9820 + define_bool CONFIG_NEW_IRQ y
9821 + define_bool CONFIG_HND y
9822 +fi
9823 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
9824 define_bool CONFIG_ARC32 y
9825 define_bool CONFIG_ARC_MEMORY y
9826 @@ -1042,7 +1062,11 @@
9827
9828 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
9829 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
9830 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
9831 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
9832 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
9833 +else
9834 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
9835 +fi
9836 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
9837 if [ "$CONFIG_KGDB" = "y" ]; then
9838 define_bool CONFIG_DEBUG_INFO y
9839 diff -Naur linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
9840 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-04-06 15:38:09.000000000 +0200
9841 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-04-06 15:34:14.000000000 +0200
9842 @@ -162,7 +162,7 @@
9843
9844 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
9845 {
9846 - switch (c->processor_id & 0xff00) {
9847 + switch (c->processor_id & PRID_IMP_MASK) {
9848 case PRID_IMP_R2000:
9849 c->cputype = CPU_R2000;
9850 c->isa_level = MIPS_CPU_ISA_I;
9851 @@ -172,7 +172,7 @@
9852 c->tlbsize = 64;
9853 break;
9854 case PRID_IMP_R3000:
9855 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
9856 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
9857 if (cpu_has_confreg())
9858 c->cputype = CPU_R3081E;
9859 else
9860 @@ -187,12 +187,12 @@
9861 break;
9862 case PRID_IMP_R4000:
9863 if (read_c0_config() & CONF_SC) {
9864 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
9865 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
9866 c->cputype = CPU_R4400PC;
9867 else
9868 c->cputype = CPU_R4000PC;
9869 } else {
9870 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
9871 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
9872 c->cputype = CPU_R4400SC;
9873 else
9874 c->cputype = CPU_R4000SC;
9875 @@ -438,7 +438,7 @@
9876 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
9877 {
9878 decode_config1(c);
9879 - switch (c->processor_id & 0xff00) {
9880 + switch (c->processor_id & PRID_IMP_MASK) {
9881 case PRID_IMP_4KC:
9882 c->cputype = CPU_4KC;
9883 c->isa_level = MIPS_CPU_ISA_M32;
9884 @@ -479,10 +479,10 @@
9885 {
9886 decode_config1(c);
9887 c->options |= MIPS_CPU_PREFETCH;
9888 - switch (c->processor_id & 0xff00) {
9889 + switch (c->processor_id & PRID_IMP_MASK) {
9890 case PRID_IMP_AU1_REV1:
9891 case PRID_IMP_AU1_REV2:
9892 - switch ((c->processor_id >> 24) & 0xff) {
9893 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
9894 case 0:
9895 c->cputype = CPU_AU1000;
9896 break;
9897 @@ -510,10 +510,34 @@
9898 }
9899 }
9900
9901 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
9902 +{
9903 + decode_config1(c);
9904 + c->options |= MIPS_CPU_PREFETCH;
9905 + switch (c->processor_id & PRID_IMP_MASK) {
9906 + case PRID_IMP_BCM4710:
9907 + c->cputype = CPU_BCM4710;
9908 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
9909 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
9910 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
9911 + break;
9912 + case PRID_IMP_4KC:
9913 + case PRID_IMP_BCM3302:
9914 + c->cputype = CPU_BCM3302;
9915 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
9916 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
9917 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
9918 + break;
9919 + default:
9920 + c->cputype = CPU_UNKNOWN;
9921 + break;
9922 + }
9923 +}
9924 +
9925 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
9926 {
9927 decode_config1(c);
9928 - switch (c->processor_id & 0xff00) {
9929 + switch (c->processor_id & PRID_IMP_MASK) {
9930 case PRID_IMP_SB1:
9931 c->cputype = CPU_SB1;
9932 c->isa_level = MIPS_CPU_ISA_M64;
9933 @@ -535,7 +559,7 @@
9934 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
9935 {
9936 decode_config1(c);
9937 - switch (c->processor_id & 0xff00) {
9938 + switch (c->processor_id & PRID_IMP_MASK) {
9939 case PRID_IMP_SR71000:
9940 c->cputype = CPU_SR71000;
9941 c->isa_level = MIPS_CPU_ISA_M64;
9942 @@ -560,7 +584,7 @@
9943 c->cputype = CPU_UNKNOWN;
9944
9945 c->processor_id = read_c0_prid();
9946 - switch (c->processor_id & 0xff0000) {
9947 + switch (c->processor_id & PRID_COMP_MASK) {
9948
9949 case PRID_COMP_LEGACY:
9950 cpu_probe_legacy(c);
9951 @@ -571,6 +595,9 @@
9952 case PRID_COMP_ALCHEMY:
9953 cpu_probe_alchemy(c);
9954 break;
9955 + case PRID_COMP_BROADCOM:
9956 + cpu_probe_broadcom(c);
9957 + break;
9958 case PRID_COMP_SIBYTE:
9959 cpu_probe_sibyte(c);
9960 break;
9961 diff -Naur linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
9962 --- linux.old/arch/mips/kernel/head.S 2006-04-06 15:38:09.000000000 +0200
9963 +++ linux.dev/arch/mips/kernel/head.S 2006-04-06 15:34:14.000000000 +0200
9964 @@ -28,12 +28,20 @@
9965 #include <asm/mipsregs.h>
9966 #include <asm/stackframe.h>
9967
9968 +#ifdef CONFIG_BCM4710
9969 +#undef eret
9970 +#define eret nop; nop; eret
9971 +#endif
9972 +
9973 .text
9974 + j kernel_entry
9975 + nop
9976 +
9977 /*
9978 * Reserved space for exception handlers.
9979 * Necessary for machines which link their kernels at KSEG0.
9980 */
9981 - .fill 0x400
9982 + .fill 0x3f4
9983
9984 /* The following two symbols are used for kernel profiling. */
9985 EXPORT(stext)
9986 diff -Naur linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
9987 --- linux.old/arch/mips/kernel/proc.c 2006-04-06 15:38:09.000000000 +0200
9988 +++ linux.dev/arch/mips/kernel/proc.c 2006-04-06 15:34:14.000000000 +0200
9989 @@ -78,9 +78,10 @@
9990 [CPU_AU1550] "Au1550",
9991 [CPU_24K] "MIPS 24K",
9992 [CPU_AU1200] "Au1200",
9993 + [CPU_BCM4710] "BCM4710",
9994 + [CPU_BCM3302] "BCM3302",
9995 };
9996
9997 -
9998 static int show_cpuinfo(struct seq_file *m, void *v)
9999 {
10000 unsigned int version = current_cpu_data.processor_id;
10001 diff -Naur linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
10002 --- linux.old/arch/mips/kernel/setup.c 2006-04-06 15:38:09.000000000 +0200
10003 +++ linux.dev/arch/mips/kernel/setup.c 2006-04-06 15:34:14.000000000 +0200
10004 @@ -493,6 +493,7 @@
10005 void swarm_setup(void);
10006 void hp_setup(void);
10007 void au1x00_setup(void);
10008 + void brcm_setup(void);
10009 void frame_info_init(void);
10010
10011 frame_info_init();
10012 @@ -691,6 +692,11 @@
10013 pmc_yosemite_setup();
10014 break;
10015 #endif
10016 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
10017 + case MACH_GROUP_BRCM:
10018 + brcm_setup();
10019 + break;
10020 +#endif
10021 default:
10022 panic("Unsupported architecture");
10023 }
10024 diff -Naur linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
10025 --- linux.old/arch/mips/kernel/traps.c 2006-04-06 15:38:09.000000000 +0200
10026 +++ linux.dev/arch/mips/kernel/traps.c 2006-04-06 15:34:14.000000000 +0200
10027 @@ -920,6 +920,7 @@
10028 void __init trap_init(void)
10029 {
10030 extern char except_vec1_generic;
10031 + extern char except_vec2_generic;
10032 extern char except_vec3_generic, except_vec3_r4000;
10033 extern char except_vec_ejtag_debug;
10034 extern char except_vec4;
10035 @@ -927,6 +928,7 @@
10036
10037 /* Copy the generic exception handler code to it's final destination. */
10038 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
10039 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
10040
10041 /*
10042 * Setup default vectors
10043 @@ -985,6 +987,12 @@
10044 set_except_vector(13, handle_tr);
10045 set_except_vector(22, handle_mdmx);
10046
10047 + if (current_cpu_data.cputype == CPU_SB1) {
10048 + /* Enable timer interrupt and scd mapped interrupt */
10049 + clear_c0_status(0xf000);
10050 + set_c0_status(0xc00);
10051 + }
10052 +
10053 if (cpu_has_fpu && !cpu_has_nofpuex)
10054 set_except_vector(15, handle_fpe);
10055
10056 diff -Naur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
10057 --- linux.old/arch/mips/mm/c-r4k.c 2006-04-06 15:38:09.000000000 +0200
10058 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-04-06 15:34:15.000000000 +0200
10059 @@ -1166,3 +1166,47 @@
10060 build_clear_page();
10061 build_copy_page();
10062 }
10063 +
10064 +#ifdef CONFIG_BCM4704
10065 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
10066 +{
10067 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
10068 + int i;
10069 + for (i = 0; i < nbytes; i += ic_lsize)
10070 + fill_icache_line((addr + i));
10071 +}
10072 +
10073 +/*
10074 + * This must be run from the cache on 4704A0
10075 + * so there are no mips core BIU ops in progress
10076 + * when the PFC is enabled.
10077 + */
10078 +#define PFC_CR0 0xff400000 /* control reg 0 */
10079 +#define PFC_CR1 0xff400004 /* control reg 1 */
10080 +static void __init enable_pfc(u32 mode)
10081 +{
10082 + /* write range */
10083 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
10084 +
10085 + /* enable */
10086 + *(volatile u32 *)PFC_CR0 = mode;
10087 +}
10088 +#endif
10089 +
10090 +
10091 +void check_enable_mips_pfc(int val)
10092 +{
10093 +
10094 +#ifdef CONFIG_BCM4704
10095 + struct cpuinfo_mips *c = &current_cpu_data;
10096 +
10097 + /* enable prefetch cache */
10098 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
10099 + && (read_c0_diag() & (1 << 29))) {
10100 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
10101 + enable_pfc(val);
10102 + }
10103 +#endif
10104 +}
10105 +
10106 +
10107 diff -Naur linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
10108 --- linux.old/arch/mips/pci/Makefile 2006-04-06 15:38:09.000000000 +0200
10109 +++ linux.dev/arch/mips/pci/Makefile 2006-04-06 15:34:14.000000000 +0200
10110 @@ -13,7 +13,9 @@
10111 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
10112 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
10113 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
10114 +ifndef CONFIG_BCM947XX
10115 obj-y += pci.o
10116 +endif
10117 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
10118
10119 include $(TOPDIR)/Rules.make
10120 diff -Naur linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
10121 --- linux.old/drivers/char/serial.c 2006-04-06 15:38:09.000000000 +0200
10122 +++ linux.dev/drivers/char/serial.c 2006-04-06 15:34:14.000000000 +0200
10123 @@ -444,6 +444,10 @@
10124 return inb(info->port+1);
10125 #endif
10126 case SERIAL_IO_MEM:
10127 +#ifdef CONFIG_BCM4310
10128 + readb((unsigned long) info->iomem_base +
10129 + (UART_SCR<<info->iomem_reg_shift));
10130 +#endif
10131 return readb((unsigned long) info->iomem_base +
10132 (offset<<info->iomem_reg_shift));
10133 default:
10134 @@ -464,6 +468,9 @@
10135 case SERIAL_IO_MEM:
10136 writeb(value, (unsigned long) info->iomem_base +
10137 (offset<<info->iomem_reg_shift));
10138 +#ifdef CONFIG_BCM4704
10139 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
10140 +#endif
10141 break;
10142 default:
10143 outb(value, info->port+offset);
10144 @@ -1728,7 +1735,7 @@
10145 /* Special case since 134 is really 134.5 */
10146 quot = (2*baud_base / 269);
10147 else if (baud)
10148 - quot = baud_base / baud;
10149 + quot = (baud_base + (baud / 2)) / baud;
10150 }
10151 /* If the quotient is zero refuse the change */
10152 if (!quot && old_termios) {
10153 @@ -1745,12 +1752,12 @@
10154 /* Special case since 134 is really 134.5 */
10155 quot = (2*baud_base / 269);
10156 else if (baud)
10157 - quot = baud_base / baud;
10158 + quot = (baud_base + (baud / 2)) / baud;
10159 }
10160 }
10161 /* As a last resort, if the quotient is zero, default to 9600 bps */
10162 if (!quot)
10163 - quot = baud_base / 9600;
10164 + quot = (baud_base + 4800) / 9600;
10165 /*
10166 * Work around a bug in the Oxford Semiconductor 952 rev B
10167 * chip which causes it to seriously miscalculate baud rates
10168 @@ -5994,6 +6001,13 @@
10169 * Divisor, bytesize and parity
10170 */
10171 state = rs_table + co->index;
10172 + /*
10173 + * Safe guard: state structure must have been initialized
10174 + */
10175 + if (state->iomem_base == NULL) {
10176 + printk("!unable to setup serial console!\n");
10177 + return -1;
10178 + }
10179 if (doflow)
10180 state->flags |= ASYNC_CONS_FLOW;
10181 info = &async_sercons;
10182 @@ -6007,7 +6021,7 @@
10183 info->io_type = state->io_type;
10184 info->iomem_base = state->iomem_base;
10185 info->iomem_reg_shift = state->iomem_reg_shift;
10186 - quot = state->baud_base / baud;
10187 + quot = (state->baud_base + (baud / 2)) / baud;
10188 cval = cflag & (CSIZE | CSTOPB);
10189 #if defined(__powerpc__) || defined(__alpha__)
10190 cval >>= 8;
10191 diff -Naur linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
10192 --- linux.old/drivers/net/Config.in 2006-04-06 15:38:09.000000000 +0200
10193 +++ linux.dev/drivers/net/Config.in 2006-04-06 15:34:14.000000000 +0200
10194 @@ -2,6 +2,8 @@
10195 # Network device configuration
10196 #
10197
10198 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
10199 +
10200 source drivers/net/arcnet/Config.in
10201
10202 tristate 'Dummy net driver support' CONFIG_DUMMY
10203 diff -Naur linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
10204 --- linux.old/drivers/net/Makefile 2006-04-06 15:38:09.000000000 +0200
10205 +++ linux.dev/drivers/net/Makefile 2006-04-06 16:45:29.000000000 +0200
10206 @@ -3,6 +3,8 @@
10207 # Makefile for the Linux network (ethercard) device drivers.
10208 #
10209
10210 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
10211 +
10212 obj-y :=
10213 obj-m :=
10214 obj-n :=
10215 @@ -39,6 +41,9 @@
10216 obj-$(CONFIG_ISDN) += slhc.o
10217 endif
10218
10219 +subdir-$(CONFIG_HND) += hnd
10220 +subdir-$(CONFIG_WL) += wl
10221 +subdir-$(CONFIG_WL2) += wl2
10222 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
10223 subdir-$(CONFIG_NET_WIRELESS) += wireless
10224 subdir-$(CONFIG_TULIP) += tulip
10225 @@ -69,6 +74,10 @@
10226 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
10227 obj-$(CONFIG_SUNGEM) += sungem.o
10228
10229 +ifeq ($(CONFIG_HND),y)
10230 + obj-y += hnd/hnd.o
10231 +endif
10232 +
10233 obj-$(CONFIG_MACE) += mace.o
10234 obj-$(CONFIG_BMAC) += bmac.o
10235 obj-$(CONFIG_GMAC) += gmac.o
10236 diff -Naur linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
10237 --- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
10238 +++ linux.dev/drivers/net/hnd/Makefile 2006-04-06 16:20:00.000000000 +0200
10239 @@ -0,0 +1,19 @@
10240 +#
10241 +# Makefile for the BCM47xx specific kernel interface routines
10242 +# under Linux.
10243 +#
10244 +
10245 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
10246 +
10247 +O_TARGET := hnd.o
10248 +
10249 +HND_OBJS := bcmutils.o linux_osl.o sbutils.o bcmsrom.o
10250 +
10251 +export-objs := shared_ksyms.o
10252 +obj-y := shared_ksyms.o $(HND_OBJS)
10253 +obj-m := $(O_TARGET)
10254 +
10255 +include $(TOPDIR)/Rules.make
10256 +
10257 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
10258 + sh -e $< $(HND_OBJS) > $@
10259 diff -Naur linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
10260 --- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
10261 +++ linux.dev/drivers/net/hnd/bcmsrom.c 2006-04-06 15:34:14.000000000 +0200
10262 @@ -0,0 +1,938 @@
10263 +/*
10264 + * Misc useful routines to access NIC SROM/OTP .
10265 + *
10266 + * Copyright 2005, Broadcom Corporation
10267 + * All Rights Reserved.
10268 + *
10269 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10270 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10271 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10272 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10273 + * $Id$
10274 + */
10275 +
10276 +#include <typedefs.h>
10277 +#include <osl.h>
10278 +#include <bcmutils.h>
10279 +#include <bcmsrom.h>
10280 +#include <bcmdevs.h>
10281 +#include <bcmendian.h>
10282 +#include <sbpcmcia.h>
10283 +#include <pcicfg.h>
10284 +#include <sbutils.h>
10285 +#include <bcmnvram.h>
10286 +
10287 +struct ether_addr {
10288 + uint8 octet[6];
10289 +} PACKED;
10290 +
10291 +#define VARS_MAX 4096 /* should be reduced */
10292 +
10293 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
10294 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
10295 +
10296 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
10297 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
10298 +static int initvars_flash_sb(void *sbh, char **vars, int *count);
10299 +static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
10300 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
10301 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
10302 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
10303 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
10304 +
10305 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
10306 +static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
10307 +
10308 +/*
10309 + * Initialize local vars from the right source for this platform.
10310 + * Return 0 on success, nonzero on error.
10311 + */
10312 +int
10313 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
10314 +{
10315 + ASSERT(bustype == BUSTYPE(bustype));
10316 + if (vars == NULL || count == NULL)
10317 + return (0);
10318 +
10319 + switch (BUSTYPE(bustype)) {
10320 + case SB_BUS:
10321 + case JTAG_BUS:
10322 + return initvars_flash_sb(sbh, vars, count);
10323 +
10324 + case PCI_BUS:
10325 + ASSERT(curmap); /* can not be NULL */
10326 + return initvars_srom_pci(sbh, curmap, vars, count);
10327 +
10328 + case PCMCIA_BUS:
10329 + return initvars_cis_pcmcia(sbh, osh, vars, count);
10330 +
10331 +
10332 + default:
10333 + ASSERT(0);
10334 + }
10335 + return (-1);
10336 +}
10337 +
10338 +/* support only 16-bit word read from srom */
10339 +int
10340 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
10341 +{
10342 + void *srom;
10343 + uint i, off, nw;
10344 +
10345 + ASSERT(bustype == BUSTYPE(bustype));
10346 +
10347 + /* check input - 16-bit access only */
10348 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
10349 + return 1;
10350 +
10351 + off = byteoff / 2;
10352 + nw = nbytes / 2;
10353 +
10354 + if (BUSTYPE(bustype) == PCI_BUS) {
10355 + if (!curmap)
10356 + return 1;
10357 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
10358 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
10359 + return 1;
10360 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
10361 + for (i = 0; i < nw; i++) {
10362 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
10363 + return 1;
10364 + }
10365 + } else {
10366 + return 1;
10367 + }
10368 +
10369 + return 0;
10370 +}
10371 +
10372 +/* support only 16-bit word write into srom */
10373 +int
10374 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
10375 +{
10376 + uint16 *srom;
10377 + uint i, off, nw, crc_range;
10378 + uint16 image[SPROM_SIZE], *p;
10379 + uint8 crc;
10380 + volatile uint32 val32;
10381 +
10382 + ASSERT(bustype == BUSTYPE(bustype));
10383 +
10384 + /* check input - 16-bit access only */
10385 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
10386 + return 1;
10387 +
10388 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
10389 +
10390 + /* if changes made inside crc cover range */
10391 + if (byteoff < crc_range) {
10392 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
10393 + /* read data including entire first 64 words from srom */
10394 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
10395 + return 1;
10396 + /* make changes */
10397 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
10398 + /* calculate crc */
10399 + htol16_buf(image, crc_range);
10400 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
10401 + ltoh16_buf(image, crc_range);
10402 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
10403 + p = image;
10404 + off = 0;
10405 + } else {
10406 + p = buf;
10407 + off = byteoff / 2;
10408 + nw = nbytes / 2;
10409 + }
10410 +
10411 + if (BUSTYPE(bustype) == PCI_BUS) {
10412 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
10413 + /* enable writes to the SPROM */
10414 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
10415 + val32 |= SPROM_WRITEEN;
10416 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
10417 + bcm_mdelay(WRITE_ENABLE_DELAY);
10418 + /* write srom */
10419 + for (i = 0; i < nw; i++) {
10420 + W_REG(&srom[off + i], p[i]);
10421 + bcm_mdelay(WRITE_WORD_DELAY);
10422 + }
10423 + /* disable writes to the SPROM */
10424 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
10425 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
10426 + /* enable writes to the SPROM */
10427 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
10428 + return 1;
10429 + bcm_mdelay(WRITE_ENABLE_DELAY);
10430 + /* write srom */
10431 + for (i = 0; i < nw; i++) {
10432 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
10433 + bcm_mdelay(WRITE_WORD_DELAY);
10434 + }
10435 + /* disable writes to the SPROM */
10436 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
10437 + return 1;
10438 + } else {
10439 + return 1;
10440 + }
10441 +
10442 + bcm_mdelay(WRITE_ENABLE_DELAY);
10443 + return 0;
10444 +}
10445 +
10446 +
10447 +static int
10448 +srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
10449 +{
10450 + char eabuf[32];
10451 + char *vp, *base;
10452 + uint8 tup, tlen, sromrev = 1;
10453 + int i, j;
10454 + uint varsize;
10455 + bool ag_init = FALSE;
10456 + uint32 w32;
10457 +
10458 + ASSERT(vars);
10459 + ASSERT(count);
10460 +
10461 + base = vp = MALLOC(osh, VARS_MAX);
10462 + ASSERT(vp);
10463 + if (!vp)
10464 + return -2;
10465 +
10466 + i = 0;
10467 + do {
10468 + tup = cis[i++];
10469 + tlen = cis[i++];
10470 + if ((i + tlen) >= CIS_SIZE)
10471 + break;
10472 +
10473 + switch (tup) {
10474 + case CISTPL_MANFID:
10475 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
10476 + vp++;
10477 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
10478 + vp++;
10479 + break;
10480 +
10481 + case CISTPL_FUNCE:
10482 + if (cis[i] == LAN_NID) {
10483 + ASSERT(cis[i + 1] == 6);
10484 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
10485 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
10486 + vp++;
10487 + }
10488 + break;
10489 +
10490 + case CISTPL_CFTABLE:
10491 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
10492 + vp++;
10493 + break;
10494 +
10495 + case CISTPL_BRCM_HNBU:
10496 + switch (cis[i]) {
10497 + case HNBU_SROMREV:
10498 + sromrev = cis[i + 1];
10499 + break;
10500 +
10501 + case HNBU_CHIPID:
10502 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
10503 + vp++;
10504 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
10505 + vp++;
10506 + if (tlen == 7) {
10507 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
10508 + vp++;
10509 + }
10510 + break;
10511 +
10512 + case HNBU_BOARDREV:
10513 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
10514 + vp++;
10515 + break;
10516 +
10517 + case HNBU_AA:
10518 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
10519 + vp++;
10520 + break;
10521 +
10522 + case HNBU_AG:
10523 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
10524 + vp++;
10525 + ag_init = TRUE;
10526 + break;
10527 +
10528 + case HNBU_CC:
10529 + ASSERT(sromrev > 1);
10530 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
10531 + vp++;
10532 + break;
10533 +
10534 + case HNBU_PAPARMS:
10535 + if (tlen == 2) {
10536 + ASSERT(sromrev == 1);
10537 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
10538 + vp++;
10539 + } else if (tlen >= 9) {
10540 + if (tlen == 10) {
10541 + ASSERT(sromrev == 2);
10542 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
10543 + vp++;
10544 + } else
10545 + ASSERT(tlen == 9);
10546 +
10547 + for (j = 0; j < 3; j++) {
10548 + vp += sprintf(vp, "pa0b%d=%d", j,
10549 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
10550 + vp++;
10551 + }
10552 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
10553 + vp++;
10554 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
10555 + vp++;
10556 + } else
10557 + ASSERT(tlen >= 9);
10558 + break;
10559 +
10560 + case HNBU_OEM:
10561 + ASSERT(sromrev == 1);
10562 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
10563 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
10564 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
10565 + vp++;
10566 + break;
10567 +
10568 + case HNBU_BOARDFLAGS:
10569 + w32 = (cis[i + 2] << 8) + cis[i + 1];
10570 + if (tlen == 5)
10571 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
10572 + vp += sprintf(vp, "boardflags=0x%x", w32);
10573 + vp++;
10574 + break;
10575 +
10576 + case HNBU_LEDS:
10577 + if (cis[i + 1] != 0xff) {
10578 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
10579 + vp++;
10580 + }
10581 + if (cis[i + 2] != 0xff) {
10582 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
10583 + vp++;
10584 + }
10585 + if (cis[i + 3] != 0xff) {
10586 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
10587 + vp++;
10588 + }
10589 + if (cis[i + 4] != 0xff) {
10590 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
10591 + vp++;
10592 + }
10593 + break;
10594 +
10595 + case HNBU_CCODE:
10596 + ASSERT(sromrev > 1);
10597 + vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
10598 + vp++;
10599 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
10600 + vp++;
10601 + break;
10602 +
10603 + case HNBU_CCKPO:
10604 + ASSERT(sromrev > 2);
10605 + vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
10606 + vp++;
10607 + break;
10608 +
10609 + case HNBU_OFDMPO:
10610 + ASSERT(sromrev > 2);
10611 + vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
10612 + (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
10613 + vp++;
10614 + break;
10615 + }
10616 + break;
10617 +
10618 + }
10619 + i += tlen;
10620 + } while (tup != 0xff);
10621 +
10622 + /* Set the srom version */
10623 + vp += sprintf(vp, "sromrev=%d", sromrev);
10624 + vp++;
10625 +
10626 + /* if there is no antenna gain field, set default */
10627 + if (ag_init == FALSE) {
10628 + ASSERT(sromrev == 1);
10629 + vp += sprintf(vp, "ag0=%d", 0xff);
10630 + vp++;
10631 + }
10632 +
10633 + /* final nullbyte terminator */
10634 + *vp++ = '\0';
10635 + varsize = (uint)(vp - base);
10636 +
10637 + ASSERT((vp - base) < VARS_MAX);
10638 +
10639 + if (varsize == VARS_MAX) {
10640 + *vars = base;
10641 + } else {
10642 + vp = MALLOC(osh, varsize);
10643 + ASSERT(vp);
10644 + if (vp)
10645 + bcopy(base, vp, varsize);
10646 + MFREE(osh, base, VARS_MAX);
10647 + *vars = vp;
10648 + if (!vp) {
10649 + *count = 0;
10650 + return -2;
10651 + }
10652 + }
10653 + *count = varsize;
10654 +
10655 + return (0);
10656 +}
10657 +
10658 +
10659 +/* set PCMCIA sprom command register */
10660 +static int
10661 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
10662 +{
10663 + uint8 status = 0;
10664 + uint wait_cnt = 1000;
10665 +
10666 + /* write sprom command register */
10667 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
10668 +
10669 + /* wait status */
10670 + while (wait_cnt--) {
10671 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
10672 + if (status & SROM_DONE)
10673 + return 0;
10674 + }
10675 +
10676 + return 1;
10677 +}
10678 +
10679 +/* read a word from the PCMCIA srom */
10680 +static int
10681 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
10682 +{
10683 + uint8 addr_l, addr_h, data_l, data_h;
10684 +
10685 + addr_l = (uint8)((addr * 2) & 0xff);
10686 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
10687 +
10688 + /* set address */
10689 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
10690 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
10691 +
10692 + /* do read */
10693 + if (sprom_cmd_pcmcia(osh, SROM_READ))
10694 + return 1;
10695 +
10696 + /* read data */
10697 + data_h = data_l = 0;
10698 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
10699 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
10700 +
10701 + *data = (data_h << 8) | data_l;
10702 + return 0;
10703 +}
10704 +
10705 +/* write a word to the PCMCIA srom */
10706 +static int
10707 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
10708 +{
10709 + uint8 addr_l, addr_h, data_l, data_h;
10710 +
10711 + addr_l = (uint8)((addr * 2) & 0xff);
10712 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
10713 + data_l = (uint8)(data & 0xff);
10714 + data_h = (uint8)((data >> 8) & 0xff);
10715 +
10716 + /* set address */
10717 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
10718 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
10719 +
10720 + /* write data */
10721 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
10722 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
10723 +
10724 + /* do write */
10725 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
10726 +}
10727 +
10728 +/*
10729 + * Read in and validate sprom.
10730 + * Return 0 on success, nonzero on error.
10731 + */
10732 +static int
10733 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
10734 +{
10735 + int err = 0;
10736 + uint i;
10737 +
10738 + /* read the sprom */
10739 + for (i = 0; i < nwords; i++)
10740 + buf[i] = R_REG(&sprom[wordoff + i]);
10741 +
10742 + if (check_crc) {
10743 + /* fixup the endianness so crc8 will pass */
10744 + htol16_buf(buf, nwords * 2);
10745 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
10746 + err = 1;
10747 + /* now correct the endianness of the byte array */
10748 + ltoh16_buf(buf, nwords * 2);
10749 + }
10750 +
10751 + return err;
10752 +}
10753 +
10754 +/*
10755 +* Create variable table from memory.
10756 +* Return 0 on success, nonzero on error.
10757 +*/
10758 +static int
10759 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
10760 +{
10761 + int c = (int)(end - start);
10762 +
10763 + /* do it only when there is more than just the null string */
10764 + if (c > 1) {
10765 + char *vp = MALLOC(osh, c);
10766 + ASSERT(vp);
10767 + if (!vp)
10768 + return BCME_NOMEM;
10769 + bcopy(start, vp, c);
10770 + *vars = vp;
10771 + *count = c;
10772 + }
10773 + else {
10774 + *vars = NULL;
10775 + *count = 0;
10776 + }
10777 +
10778 + return 0;
10779 +}
10780 +
10781 +/*
10782 +* Find variables with <devpath> from flash. 'base' points to the beginning
10783 +* of the table upon enter and to the end of the table upon exit when success.
10784 +* Return 0 on success, nonzero on error.
10785 +*/
10786 +static int
10787 +initvars_flash(osl_t *osh, char **base, int size, char *devpath)
10788 +{
10789 + char *vp = *base;
10790 + char *flash;
10791 + int err;
10792 + char *s;
10793 + uint l, dl, copy_len;
10794 +
10795 + /* allocate memory and read in flash */
10796 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
10797 + return BCME_NOMEM;
10798 + if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
10799 + goto exit;
10800 +
10801 + /* grab vars with the <devpath> prefix in name */
10802 + dl = strlen(devpath);
10803 + for (s = flash; s && *s; s += l + 1) {
10804 + l = strlen(s);
10805 +
10806 + /* skip non-matching variable */
10807 + if (strncmp(s, devpath, dl))
10808 + continue;
10809 +
10810 + /* is there enough room to copy? */
10811 + copy_len = l - dl + 1;
10812 + if (size < (int)copy_len) {
10813 + err = BCME_BUFTOOSHORT;
10814 + goto exit;
10815 + }
10816 +
10817 + /* no prefix, just the name=value */
10818 + strcpy(vp, &s[dl]);
10819 + vp += copy_len;
10820 + size -= copy_len;
10821 + }
10822 +
10823 + /* add null string as terminator */
10824 + if (size < 1) {
10825 + err = BCME_BUFTOOSHORT;
10826 + goto exit;
10827 + }
10828 + *vp++ = '\0';
10829 +
10830 + *base = vp;
10831 +
10832 +exit: MFREE(osh, flash, NVRAM_SPACE);
10833 + return err;
10834 +}
10835 +
10836 +/*
10837 + * Initialize nonvolatile variable table from flash.
10838 + * Return 0 on success, nonzero on error.
10839 + */
10840 +static int
10841 +initvars_flash_sb(void *sbh, char **vars, int *count)
10842 +{
10843 + osl_t *osh = sb_osh(sbh);
10844 + char devpath[SB_DEVPATH_BUFSZ];
10845 + char *vp, *base;
10846 + int err;
10847 +
10848 + ASSERT(vars);
10849 + ASSERT(count);
10850 +
10851 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
10852 + return err;
10853 +
10854 + base = vp = MALLOC(osh, VARS_MAX);
10855 + ASSERT(vp);
10856 + if (!vp)
10857 + return BCME_NOMEM;
10858 +
10859 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
10860 + goto err;
10861 +
10862 + err = initvars_table(osh, base, vp, vars, count);
10863 +
10864 +err: MFREE(osh, base, VARS_MAX);
10865 + return err;
10866 +}
10867 +
10868 +/*
10869 + * Initialize nonvolatile variable table from sprom.
10870 + * Return 0 on success, nonzero on error.
10871 + */
10872 +static int
10873 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
10874 +{
10875 + uint16 w, b[64];
10876 + uint8 sromrev;
10877 + struct ether_addr ea;
10878 + char eabuf[32];
10879 + uint32 w32;
10880 + int woff, i;
10881 + char *vp, *base;
10882 + osl_t *osh = sb_osh(sbh);
10883 + bool flash = FALSE;
10884 + char name[SB_DEVPATH_BUFSZ+16], *value;
10885 + char devpath[SB_DEVPATH_BUFSZ];
10886 + int err;
10887 +
10888 + /*
10889 + * Apply CRC over SROM content regardless SROM is present or not,
10890 + * and use variable <devpath>sromrev's existance in flash to decide
10891 + * if we should return an error when CRC fails or read SROM variables
10892 + * from flash.
10893 + */
10894 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
10895 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
10896 + return err;
10897 + sprintf(name, "%ssromrev", devpath);
10898 + if (!(value = getvar(NULL, name)))
10899 + return (-1);
10900 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
10901 + flash = TRUE;
10902 + }
10903 + /* srom is good */
10904 + else {
10905 + /* top word of sprom contains version and crc8 */
10906 + sromrev = b[63] & 0xff;
10907 + /* bcm4401 sroms misprogrammed */
10908 + if (sromrev == 0x10)
10909 + sromrev = 1;
10910 + }
10911 +
10912 + /* srom version check */
10913 + if (sromrev > 3)
10914 + return (-2);
10915 +
10916 + ASSERT(vars);
10917 + ASSERT(count);
10918 +
10919 + base = vp = MALLOC(osh, VARS_MAX);
10920 + ASSERT(vp);
10921 + if (!vp)
10922 + return -2;
10923 +
10924 + /* read variables from flash */
10925 + if (flash) {
10926 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
10927 + goto err;
10928 + goto done;
10929 + }
10930 +
10931 + vp += sprintf(vp, "sromrev=%d", sromrev);
10932 + vp++;
10933 +
10934 + if (sromrev >= 3) {
10935 + /* New section takes over the 3th hardware function space */
10936 +
10937 + /* Words 22+23 are 11a (mid) ofdm power offsets */
10938 + w32 = ((uint32)b[23] << 16) | b[22];
10939 + vp += sprintf(vp, "ofdmapo=%d", w32);
10940 + vp++;
10941 +
10942 + /* Words 24+25 are 11a (low) ofdm power offsets */
10943 + w32 = ((uint32)b[25] << 16) | b[24];
10944 + vp += sprintf(vp, "ofdmalpo=%d", w32);
10945 + vp++;
10946 +
10947 + /* Words 26+27 are 11a (high) ofdm power offsets */
10948 + w32 = ((uint32)b[27] << 16) | b[26];
10949 + vp += sprintf(vp, "ofdmahpo=%d", w32);
10950 + vp++;
10951 +
10952 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
10953 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
10954 + vp += sprintf(vp, "gpiotimerval=%d", w32);
10955 +
10956 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
10957 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
10958 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
10959 + vp += sprintf(vp, "gpiotimerval=%d", w32);
10960 +
10961 + vp++;
10962 + }
10963 +
10964 + if (sromrev >= 2) {
10965 + /* New section takes over the 4th hardware function space */
10966 +
10967 + /* Word 29 is max power 11a high/low */
10968 + w = b[29];
10969 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
10970 + vp++;
10971 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
10972 + vp++;
10973 +
10974 + /* Words 30-32 set the 11alow pa settings,
10975 + * 33-35 are the 11ahigh ones.
10976 + */
10977 + for (i = 0; i < 3; i++) {
10978 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
10979 + vp++;
10980 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
10981 + vp++;
10982 + }
10983 + w = b[59];
10984 + if (w == 0)
10985 + vp += sprintf(vp, "ccode=");
10986 + else
10987 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
10988 + vp++;
10989 +
10990 + }
10991 +
10992 + /* parameter section of sprom starts at byte offset 72 */
10993 + woff = 72/2;
10994 +
10995 + /* first 6 bytes are il0macaddr */
10996 + ea.octet[0] = (b[woff] >> 8) & 0xff;
10997 + ea.octet[1] = b[woff] & 0xff;
10998 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
10999 + ea.octet[3] = b[woff+1] & 0xff;
11000 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
11001 + ea.octet[5] = b[woff+2] & 0xff;
11002 + woff += 3;
11003 + bcm_ether_ntoa((uchar*)&ea, eabuf);
11004 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
11005 + vp++;
11006 +
11007 + /* next 6 bytes are et0macaddr */
11008 + ea.octet[0] = (b[woff] >> 8) & 0xff;
11009 + ea.octet[1] = b[woff] & 0xff;
11010 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
11011 + ea.octet[3] = b[woff+1] & 0xff;
11012 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
11013 + ea.octet[5] = b[woff+2] & 0xff;
11014 + woff += 3;
11015 + bcm_ether_ntoa((uchar*)&ea, eabuf);
11016 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
11017 + vp++;
11018 +
11019 + /* next 6 bytes are et1macaddr */
11020 + ea.octet[0] = (b[woff] >> 8) & 0xff;
11021 + ea.octet[1] = b[woff] & 0xff;
11022 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
11023 + ea.octet[3] = b[woff+1] & 0xff;
11024 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
11025 + ea.octet[5] = b[woff+2] & 0xff;
11026 + woff += 3;
11027 + bcm_ether_ntoa((uchar*)&ea, eabuf);
11028 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
11029 + vp++;
11030 +
11031 + /*
11032 + * Enet phy settings one or two singles or a dual
11033 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
11034 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
11035 + * Bit 14 : Mdio for enet0
11036 + * Bit 15 : Mdio for enet1
11037 + */
11038 + w = b[woff];
11039 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
11040 + vp++;
11041 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
11042 + vp++;
11043 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
11044 + vp++;
11045 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
11046 + vp++;
11047 +
11048 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
11049 + w = b[46];
11050 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
11051 + vp++;
11052 +
11053 + if (sromrev > 1)
11054 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
11055 + else
11056 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
11057 + vp++;
11058 +
11059 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
11060 + vp++;
11061 +
11062 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
11063 + vp++;
11064 +
11065 + /* Words 47-49 set the (wl) pa settings */
11066 + woff = 47;
11067 +
11068 + for (i = 0; i < 3; i++) {
11069 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
11070 + vp++;
11071 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
11072 + vp++;
11073 + }
11074 +
11075 + /*
11076 + * Words 50-51 set the customer-configured wl led behavior.
11077 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
11078 + * LED behavior values defined in wlioctl.h .
11079 + */
11080 + w = b[50];
11081 + if ((w != 0) && (w != 0xffff)) {
11082 + /* gpio0 */
11083 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
11084 + vp++;
11085 +
11086 + /* gpio1 */
11087 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
11088 + vp++;
11089 + }
11090 + w = b[51];
11091 + if ((w != 0) && (w != 0xffff)) {
11092 + /* gpio2 */
11093 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
11094 + vp++;
11095 +
11096 + /* gpio3 */
11097 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
11098 + vp++;
11099 + }
11100 +
11101 + /* Word 52 is max power 0/1 */
11102 + w = b[52];
11103 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
11104 + vp++;
11105 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
11106 + vp++;
11107 +
11108 + /* Word 56 is idle tssi target 0/1 */
11109 + w = b[56];
11110 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
11111 + vp++;
11112 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
11113 + vp++;
11114 +
11115 + /* Word 57 is boardflags, if not programmed make it zero */
11116 + w32 = (uint32)b[57];
11117 + if (w32 == 0xffff) w32 = 0;
11118 + if (sromrev > 1) {
11119 + /* Word 28 is the high bits of boardflags */
11120 + w32 |= (uint32)b[28] << 16;
11121 + }
11122 + vp += sprintf(vp, "boardflags=%d", w32);
11123 + vp++;
11124 +
11125 + /* Word 58 is antenna gain 0/1 */
11126 + w = b[58];
11127 + vp += sprintf(vp, "ag0=%d", w & 0xff);
11128 + vp++;
11129 +
11130 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
11131 + vp++;
11132 +
11133 + if (sromrev == 1) {
11134 + /* set the oem string */
11135 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
11136 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
11137 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
11138 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
11139 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
11140 + vp++;
11141 + } else if (sromrev == 2) {
11142 + /* Word 60 OFDM tx power offset from CCK level */
11143 + /* OFDM Power Offset - opo */
11144 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
11145 + vp++;
11146 + } else {
11147 + /* Word 60: cck power offsets */
11148 + vp += sprintf(vp, "cckpo=%d", b[60]);
11149 + vp++;
11150 +
11151 + /* Words 61+62: 11g ofdm power offsets */
11152 + w32 = ((uint32)b[62] << 16) | b[61];
11153 + vp += sprintf(vp, "ofdmgpo=%d", w32);
11154 + vp++;
11155 + }
11156 +
11157 + /* final nullbyte terminator */
11158 + *vp++ = '\0';
11159 +
11160 + ASSERT((vp - base) <= VARS_MAX);
11161 +
11162 +done: err = initvars_table(osh, base, vp, vars, count);
11163 +
11164 +err: MFREE(osh, base, VARS_MAX);
11165 + return err;
11166 +}
11167 +
11168 +/*
11169 + * Read the cis and call parsecis to initialize the vars.
11170 + * Return 0 on success, nonzero on error.
11171 + */
11172 +static int
11173 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
11174 +{
11175 + uint8 *cis = NULL;
11176 + int rc;
11177 + uint data_sz;
11178 +
11179 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
11180 +
11181 + if ((cis = MALLOC(osh, data_sz)) == NULL)
11182 + return (-2);
11183 +
11184 + if (sb_pcmciarev(sbh) == 1) {
11185 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
11186 + MFREE(osh, cis, data_sz);
11187 + return (-1);
11188 + }
11189 + /* fix up endianess for 16-bit data vs 8-bit parsing */
11190 + ltoh16_buf((uint16 *)cis, data_sz);
11191 + } else
11192 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
11193 +
11194 + rc = srom_parsecis(osh, cis, vars, count);
11195 +
11196 + MFREE(osh, cis, data_sz);
11197 +
11198 + return (rc);
11199 +}
11200 +
11201 diff -Naur linux.old/drivers/net/hnd/bcmutils.c linux.dev/drivers/net/hnd/bcmutils.c
11202 --- linux.old/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
11203 +++ linux.dev/drivers/net/hnd/bcmutils.c 2006-04-06 16:05:56.000000000 +0200
11204 @@ -0,0 +1,875 @@
11205 +/*
11206 + * Misc useful OS-independent routines.
11207 + *
11208 + * Copyright 2005, Broadcom Corporation
11209 + * All Rights Reserved.
11210 + *
11211 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11212 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11213 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11214 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11215 + * $Id$
11216 + */
11217 +
11218 +#include <typedefs.h>
11219 +#ifdef BCMDRIVER
11220 +#include <osl.h>
11221 +#include <sbutils.h>
11222 +#include <bcmnvram.h>
11223 +#else
11224 +#include <stdio.h>
11225 +#include <string.h>
11226 +#endif
11227 +#include <bcmutils.h>
11228 +#include <bcmendian.h>
11229 +#include <bcmdevs.h>
11230 +
11231 +#ifdef BCMDRIVER
11232 +unsigned char bcm_ctype[] = {
11233 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
11234 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
11235 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
11236 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
11237 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
11238 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
11239 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
11240 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
11241 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
11242 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
11243 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
11244 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
11245 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
11246 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
11247 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
11248 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
11249 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
11250 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
11251 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
11252 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
11253 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
11254 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
11255 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
11256 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
11257 +};
11258 +
11259 +uchar
11260 +bcm_toupper(uchar c)
11261 +{
11262 + if (bcm_islower(c))
11263 + c -= 'a'-'A';
11264 + return (c);
11265 +}
11266 +
11267 +ulong
11268 +bcm_strtoul(char *cp, char **endp, uint base)
11269 +{
11270 + ulong result, value;
11271 + bool minus;
11272 +
11273 + minus = FALSE;
11274 +
11275 + while (bcm_isspace(*cp))
11276 + cp++;
11277 +
11278 + if (cp[0] == '+')
11279 + cp++;
11280 + else if (cp[0] == '-') {
11281 + minus = TRUE;
11282 + cp++;
11283 + }
11284 +
11285 + if (base == 0) {
11286 + if (cp[0] == '0') {
11287 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
11288 + base = 16;
11289 + cp = &cp[2];
11290 + } else {
11291 + base = 8;
11292 + cp = &cp[1];
11293 + }
11294 + } else
11295 + base = 10;
11296 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
11297 + cp = &cp[2];
11298 + }
11299 +
11300 + result = 0;
11301 +
11302 + while (bcm_isxdigit(*cp) &&
11303 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
11304 + result = result*base + value;
11305 + cp++;
11306 + }
11307 +
11308 + if (minus)
11309 + result = (ulong)(result * -1);
11310 +
11311 + if (endp)
11312 + *endp = (char *)cp;
11313 +
11314 + return (result);
11315 +}
11316 +
11317 +uint
11318 +bcm_atoi(char *s)
11319 +{
11320 + uint n;
11321 +
11322 + n = 0;
11323 +
11324 + while (bcm_isdigit(*s))
11325 + n = (n * 10) + *s++ - '0';
11326 + return (n);
11327 +}
11328 +
11329 +/* return pointer to location of substring 'needle' in 'haystack' */
11330 +char*
11331 +bcmstrstr(char *haystack, char *needle)
11332 +{
11333 + int len, nlen;
11334 + int i;
11335 +
11336 + if ((haystack == NULL) || (needle == NULL))
11337 + return (haystack);
11338 +
11339 + nlen = strlen(needle);
11340 + len = strlen(haystack) - nlen + 1;
11341 +
11342 + for (i = 0; i < len; i++)
11343 + if (bcmp(needle, &haystack[i], nlen) == 0)
11344 + return (&haystack[i]);
11345 + return (NULL);
11346 +}
11347 +
11348 +char*
11349 +bcmstrcat(char *dest, const char *src)
11350 +{
11351 + strcpy(&dest[strlen(dest)], src);
11352 + return (dest);
11353 +}
11354 +
11355 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
11356 +/* registry routine buffer preparation utility functions:
11357 + * parameter order is like strncpy, but returns count
11358 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
11359 + */
11360 +ulong
11361 +wchar2ascii(
11362 + char *abuf,
11363 + ushort *wbuf,
11364 + ushort wbuflen,
11365 + ulong abuflen
11366 +)
11367 +{
11368 + ulong copyct = 1;
11369 + ushort i;
11370 +
11371 + if (abuflen == 0)
11372 + return 0;
11373 +
11374 + /* wbuflen is in bytes */
11375 + wbuflen /= sizeof(ushort);
11376 +
11377 + for (i = 0; i < wbuflen; ++i) {
11378 + if (--abuflen == 0)
11379 + break;
11380 + *abuf++ = (char) *wbuf++;
11381 + ++copyct;
11382 + }
11383 + *abuf = '\0';
11384 +
11385 + return copyct;
11386 +}
11387 +#endif
11388 +
11389 +char*
11390 +bcm_ether_ntoa(char *ea, char *buf)
11391 +{
11392 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
11393 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
11394 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
11395 + return (buf);
11396 +}
11397 +
11398 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
11399 +int
11400 +bcm_ether_atoe(char *p, char *ea)
11401 +{
11402 + int i = 0;
11403 +
11404 + for (;;) {
11405 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
11406 + if (!*p++ || i == 6)
11407 + break;
11408 + }
11409 +
11410 + return (i == 6);
11411 +}
11412 +
11413 +void
11414 +bcm_mdelay(uint ms)
11415 +{
11416 + uint i;
11417 +
11418 + for (i = 0; i < ms; i++) {
11419 + OSL_DELAY(1000);
11420 + }
11421 +}
11422 +
11423 +/*
11424 + * Search the name=value vars for a specific one and return its value.
11425 + * Returns NULL if not found.
11426 + */
11427 +char*
11428 +getvar(char *vars, char *name)
11429 +{
11430 + char *s;
11431 + int len;
11432 +
11433 + len = strlen(name);
11434 +
11435 + /* first look in vars[] */
11436 + for (s = vars; s && *s; ) {
11437 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
11438 + return (&s[len+1]);
11439 +
11440 + while (*s++)
11441 + ;
11442 + }
11443 +
11444 + /* then query nvram */
11445 + return (BCMINIT(nvram_get)(name));
11446 +}
11447 +
11448 +/*
11449 + * Search the vars for a specific one and return its value as
11450 + * an integer. Returns 0 if not found.
11451 + */
11452 +int
11453 +getintvar(char *vars, char *name)
11454 +{
11455 + char *val;
11456 +
11457 + if ((val = getvar(vars, name)) == NULL)
11458 + return (0);
11459 +
11460 + return (bcm_strtoul(val, NULL, 0));
11461 +}
11462 +
11463 +
11464 +/* Search for token in comma separated token-string */
11465 +static int
11466 +findmatch(char *string, char *name)
11467 +{
11468 + uint len;
11469 + char *c;
11470 +
11471 + len = strlen(name);
11472 + while ((c = strchr(string, ',')) != NULL) {
11473 + if (len == (uint)(c - string) && !strncmp(string, name, len))
11474 + return 1;
11475 + string = c + 1;
11476 + }
11477 +
11478 + return (!strcmp(string, name));
11479 +}
11480 +
11481 +/* Return gpio pin number assigned to the named pin */
11482 +/*
11483 +* Variable should be in format:
11484 +*
11485 +* gpio<N>=pin_name,pin_name
11486 +*
11487 +* This format allows multiple features to share the gpio with mutual
11488 +* understanding.
11489 +*
11490 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
11491 +* and if def_pin is not used by others.
11492 +*/
11493 +uint
11494 +getgpiopin(char *vars, char *pin_name, uint def_pin)
11495 +{
11496 + char name[] = "gpioXXXX";
11497 + char *val;
11498 + uint pin;
11499 +
11500 + /* Go thru all possibilities till a match in pin name */
11501 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
11502 + sprintf(name, "gpio%d", pin);
11503 + val = getvar(vars, name);
11504 + if (val && findmatch(val, pin_name))
11505 + return pin;
11506 + }
11507 +
11508 + if (def_pin != GPIO_PIN_NOTDEFINED) {
11509 + /* make sure the default pin is not used by someone else */
11510 + sprintf(name, "gpio%d", def_pin);
11511 + if (getvar(vars, name)) {
11512 + def_pin = GPIO_PIN_NOTDEFINED;
11513 + }
11514 + }
11515 +
11516 + return def_pin;
11517 +}
11518 +
11519 +
11520 +static char bcm_undeferrstr[BCME_STRLEN];
11521 +
11522 +static const char *bcmerrorstrtable[] = \
11523 +{ "OK", /* 0 */
11524 + "Undefined error", /* BCME_ERROR */
11525 + "Bad Argument", /* BCME_BADARG*/
11526 + "Bad Option", /* BCME_BADOPTION*/
11527 + "Not up", /* BCME_NOTUP */
11528 + "Not down", /* BCME_NOTDOWN */
11529 + "Not AP", /* BCME_NOTAP */
11530 + "Not STA", /* BCME_NOTSTA */
11531 + "Bad Key Index", /* BCME_BADKEYIDX */
11532 + "Radio Off", /* BCME_RADIOOFF */
11533 + "Not band locked", /* BCME_NOTBANDLOCKED */
11534 + "No clock", /* BCME_NOCLK */
11535 + "Bad Rate valueset", /* BCME_BADRATESET */
11536 + "Bad Band", /* BCME_BADBAND */
11537 + "Buffer too short", /* BCME_BUFTOOSHORT */
11538 + "Buffer too length", /* BCME_BUFTOOLONG */
11539 + "Busy", /* BCME_BUSY */
11540 + "Not Associated", /* BCME_NOTASSOCIATED */
11541 + "Bad SSID len", /* BCME_BADSSIDLEN */
11542 + "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
11543 + "Bad Channel", /* BCME_BADCHAN */
11544 + "Bad Address", /* BCME_BADADDR */
11545 + "Not Enough Resources", /* BCME_NORESOURCE */
11546 + "Unsupported", /* BCME_UNSUPPORTED */
11547 + "Bad length", /* BCME_BADLENGTH */
11548 + "Not Ready", /* BCME_NOTREADY */
11549 + "Not Permitted", /* BCME_EPERM */
11550 + "No Memory", /* BCME_NOMEM */
11551 + "Associated", /* BCME_ASSOCIATED */
11552 + "Not In Range", /* BCME_RANGE */
11553 + "Not Found" /* BCME_NOTFOUND */
11554 + };
11555 +
11556 +/* Convert the Error codes into related Error strings */
11557 +const char *
11558 +bcmerrorstr(int bcmerror)
11559 +{
11560 + int abs_bcmerror;
11561 +
11562 + abs_bcmerror = ABS(bcmerror);
11563 +
11564 + /* check if someone added a bcmerror code but forgot to add errorstring */
11565 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
11566 + if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
11567 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
11568 + return bcm_undeferrstr;
11569 + }
11570 +
11571 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
11572 +
11573 + return bcmerrorstrtable[abs_bcmerror];
11574 +}
11575 +#endif /* #ifdef BCMDRIVER */
11576 +
11577 +
11578 +/*******************************************************************************
11579 + * crc8
11580 + *
11581 + * Computes a crc8 over the input data using the polynomial:
11582 + *
11583 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
11584 + *
11585 + * The caller provides the initial value (either CRC8_INIT_VALUE
11586 + * or the previous returned value) to allow for processing of
11587 + * discontiguous blocks of data. When generating the CRC the
11588 + * caller is responsible for complementing the final return value
11589 + * and inserting it into the byte stream. When checking, a final
11590 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
11591 + *
11592 + * Reference: Dallas Semiconductor Application Note 27
11593 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
11594 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
11595 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
11596 + *
11597 + ******************************************************************************/
11598 +
11599 +static uint8 crc8_table[256] = {
11600 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
11601 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
11602 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
11603 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
11604 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
11605 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
11606 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
11607 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
11608 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
11609 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
11610 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
11611 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
11612 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
11613 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
11614 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
11615 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
11616 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
11617 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
11618 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
11619 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
11620 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
11621 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
11622 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
11623 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
11624 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
11625 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
11626 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
11627 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
11628 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
11629 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
11630 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
11631 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
11632 +};
11633 +
11634 +#define CRC_INNER_LOOP(n, c, x) \
11635 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
11636 +
11637 +uint8
11638 +hndcrc8(
11639 + uint8 *pdata, /* pointer to array of data to process */
11640 + uint nbytes, /* number of input data bytes to process */
11641 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
11642 +)
11643 +{
11644 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
11645 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
11646 + while (nbytes-- > 0)
11647 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
11648 +
11649 + return crc;
11650 +}
11651 +
11652 +/*******************************************************************************
11653 + * crc16
11654 + *
11655 + * Computes a crc16 over the input data using the polynomial:
11656 + *
11657 + * x^16 + x^12 +x^5 + 1
11658 + *
11659 + * The caller provides the initial value (either CRC16_INIT_VALUE
11660 + * or the previous returned value) to allow for processing of
11661 + * discontiguous blocks of data. When generating the CRC the
11662 + * caller is responsible for complementing the final return value
11663 + * and inserting it into the byte stream. When checking, a final
11664 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
11665 + *
11666 + * Reference: Dallas Semiconductor Application Note 27
11667 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
11668 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
11669 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
11670 + *
11671 + ******************************************************************************/
11672 +
11673 +static uint16 crc16_table[256] = {
11674 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
11675 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
11676 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
11677 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
11678 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
11679 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
11680 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
11681 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
11682 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
11683 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
11684 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
11685 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
11686 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
11687 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
11688 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
11689 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
11690 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
11691 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
11692 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
11693 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
11694 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
11695 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
11696 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
11697 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
11698 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
11699 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
11700 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
11701 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
11702 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
11703 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
11704 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
11705 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
11706 +};
11707 +
11708 +uint16
11709 +hndcrc16(
11710 + uint8 *pdata, /* pointer to array of data to process */
11711 + uint nbytes, /* number of input data bytes to process */
11712 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
11713 +)
11714 +{
11715 + while (nbytes-- > 0)
11716 + CRC_INNER_LOOP(16, crc, *pdata++);
11717 + return crc;
11718 +}
11719 +
11720 +static uint32 crc32_table[256] = {
11721 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
11722 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
11723 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
11724 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
11725 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
11726 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
11727 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
11728 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
11729 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
11730 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
11731 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
11732 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
11733 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
11734 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
11735 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
11736 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
11737 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
11738 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
11739 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
11740 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
11741 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
11742 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
11743 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
11744 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
11745 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
11746 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
11747 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
11748 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
11749 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
11750 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
11751 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
11752 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
11753 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
11754 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
11755 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
11756 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
11757 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
11758 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
11759 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
11760 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
11761 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
11762 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
11763 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
11764 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
11765 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
11766 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
11767 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
11768 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
11769 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
11770 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
11771 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
11772 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
11773 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
11774 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
11775 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
11776 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
11777 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
11778 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
11779 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
11780 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
11781 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
11782 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
11783 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
11784 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
11785 +};
11786 +
11787 +uint32
11788 +hndcrc32(
11789 + uint8 *pdata, /* pointer to array of data to process */
11790 + uint nbytes, /* number of input data bytes to process */
11791 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
11792 +)
11793 +{
11794 + uint8 *pend;
11795 +#ifdef __mips__
11796 + uint8 tmp[4];
11797 + ulong *tptr = (ulong *)tmp;
11798 +
11799 + /* in case the beginning of the buffer isn't aligned */
11800 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
11801 + nbytes -= (pend - pdata);
11802 + while (pdata < pend)
11803 + CRC_INNER_LOOP(32, crc, *pdata++);
11804 +
11805 + /* handle bulk of data as 32-bit words */
11806 + pend = pdata + (nbytes & 0xfffffffc);
11807 + while (pdata < pend) {
11808 + tptr = *((ulong *) pdata);
11809 + *((ulong *) pdata) += 1;
11810 + CRC_INNER_LOOP(32, crc, tmp[0]);
11811 + CRC_INNER_LOOP(32, crc, tmp[1]);
11812 + CRC_INNER_LOOP(32, crc, tmp[2]);
11813 + CRC_INNER_LOOP(32, crc, tmp[3]);
11814 + }
11815 +
11816 + /* 1-3 bytes at end of buffer */
11817 + pend = pdata + (nbytes & 0x03);
11818 + while (pdata < pend)
11819 + CRC_INNER_LOOP(32, crc, *pdata++);
11820 +#else
11821 + pend = pdata + nbytes;
11822 + while (pdata < pend)
11823 + CRC_INNER_LOOP(32, crc, *pdata++);
11824 +#endif
11825 +
11826 + return crc;
11827 +}
11828 +
11829 +#ifdef notdef
11830 +#define CLEN 1499
11831 +#define CBUFSIZ (CLEN+4)
11832 +#define CNBUFS 5
11833 +
11834 +void testcrc32(void)
11835 +{
11836 + uint j,k,l;
11837 + uint8 *buf;
11838 + uint len[CNBUFS];
11839 + uint32 crcr;
11840 + uint32 crc32tv[CNBUFS] =
11841 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
11842 +
11843 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
11844 +
11845 + /* step through all possible alignments */
11846 + for (l=0;l<=4;l++) {
11847 + for (j=0; j<CNBUFS; j++) {
11848 + len[j] = CLEN;
11849 + for (k=0; k<len[j]; k++)
11850 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
11851 + }
11852 +
11853 + for (j=0; j<CNBUFS; j++) {
11854 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
11855 + ASSERT(crcr == crc32tv[j]);
11856 + }
11857 + }
11858 +
11859 + MFREE(buf, CBUFSIZ*CNBUFS);
11860 + return;
11861 +}
11862 +#endif
11863 +
11864 +
11865 +/*
11866 + * Advance from the current 1-byte tag/1-byte length/variable-length value
11867 + * triple, to the next, returning a pointer to the next.
11868 + * If the current or next TLV is invalid (does not fit in given buffer length),
11869 + * NULL is returned.
11870 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
11871 + * by the TLV paramter's length if it is valid.
11872 + */
11873 +bcm_tlv_t *
11874 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
11875 +{
11876 + int len;
11877 +
11878 + /* validate current elt */
11879 + if (!bcm_valid_tlv(elt, *buflen))
11880 + return NULL;
11881 +
11882 + /* advance to next elt */
11883 + len = elt->len;
11884 + elt = (bcm_tlv_t*)(elt->data + len);
11885 + *buflen -= (2 + len);
11886 +
11887 + /* validate next elt */
11888 + if (!bcm_valid_tlv(elt, *buflen))
11889 + return NULL;
11890 +
11891 + return elt;
11892 +}
11893 +
11894 +/*
11895 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
11896 + * triples, returning a pointer to the substring whose first element
11897 + * matches tag
11898 + */
11899 +bcm_tlv_t *
11900 +bcm_parse_tlvs(void *buf, int buflen, uint key)
11901 +{
11902 + bcm_tlv_t *elt;
11903 + int totlen;
11904 +
11905 + elt = (bcm_tlv_t*)buf;
11906 + totlen = buflen;
11907 +
11908 + /* find tagged parameter */
11909 + while (totlen >= 2) {
11910 + int len = elt->len;
11911 +
11912 + /* validate remaining totlen */
11913 + if ((elt->id == key) && (totlen >= (len + 2)))
11914 + return (elt);
11915 +
11916 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
11917 + totlen -= (len + 2);
11918 + }
11919 +
11920 + return NULL;
11921 +}
11922 +
11923 +/*
11924 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
11925 + * triples, returning a pointer to the substring whose first element
11926 + * matches tag. Stop parsing when we see an element whose ID is greater
11927 + * than the target key.
11928 + */
11929 +bcm_tlv_t *
11930 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
11931 +{
11932 + bcm_tlv_t *elt;
11933 + int totlen;
11934 +
11935 + elt = (bcm_tlv_t*)buf;
11936 + totlen = buflen;
11937 +
11938 + /* find tagged parameter */
11939 + while (totlen >= 2) {
11940 + uint id = elt->id;
11941 + int len = elt->len;
11942 +
11943 + /* Punt if we start seeing IDs > than target key */
11944 + if (id > key)
11945 + return(NULL);
11946 +
11947 + /* validate remaining totlen */
11948 + if ((id == key) && (totlen >= (len + 2)))
11949 + return (elt);
11950 +
11951 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
11952 + totlen -= (len + 2);
11953 + }
11954 + return NULL;
11955 +}
11956 +/* routine to dump fields in a fileddesc structure */
11957 +
11958 +uint
11959 +bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
11960 +{
11961 + uint filled_len;
11962 + uint len;
11963 + struct fielddesc *cur_ptr;
11964 +
11965 + filled_len = 0;
11966 + cur_ptr = fielddesc_array;
11967 +
11968 + while (bufsize > (filled_len + 64)) {
11969 + if (cur_ptr->nameandfmt == NULL)
11970 + break;
11971 + len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
11972 + buf += len;
11973 + filled_len += len;
11974 + cur_ptr++;
11975 + }
11976 + return filled_len;
11977 +}
11978 +
11979 +uint
11980 +bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
11981 +{
11982 + uint len;
11983 +
11984 + len = strlen(name) + 1;
11985 +
11986 + if ((len + datalen) > buflen)
11987 + return 0;
11988 +
11989 + strcpy(buf, name);
11990 +
11991 + /* append data onto the end of the name string */
11992 + memcpy(&buf[len], data, datalen);
11993 + len += datalen;
11994 +
11995 + return len;
11996 +}
11997 +
11998 +/* Quarter dBm units to mW
11999 + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
12000 + * Table is offset so the last entry is largest mW value that fits in
12001 + * a uint16.
12002 + */
12003 +
12004 +#define QDBM_OFFSET 153
12005 +#define QDBM_TABLE_LEN 40
12006 +
12007 +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
12008 + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
12009 + */
12010 +#define QDBM_TABLE_LOW_BOUND 6493
12011 +
12012 +/* Largest mW value that will round down to the last table entry,
12013 + * QDBM_OFFSET + QDBM_TABLE_LEN-1.
12014 + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
12015 + */
12016 +#define QDBM_TABLE_HIGH_BOUND 64938
12017 +
12018 +static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
12019 +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
12020 +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
12021 +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
12022 +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
12023 +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
12024 +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
12025 +};
12026 +
12027 +uint16
12028 +bcm_qdbm_to_mw(uint8 qdbm)
12029 +{
12030 + uint factor = 1;
12031 + int idx = qdbm - QDBM_OFFSET;
12032 +
12033 + if (idx > QDBM_TABLE_LEN) {
12034 + /* clamp to max uint16 mW value */
12035 + return 0xFFFF;
12036 + }
12037 +
12038 + /* scale the qdBm index up to the range of the table 0-40
12039 + * where an offset of 40 qdBm equals a factor of 10 mW.
12040 + */
12041 + while (idx < 0) {
12042 + idx += 40;
12043 + factor *= 10;
12044 + }
12045 +
12046 + /* return the mW value scaled down to the correct factor of 10,
12047 + * adding in factor/2 to get proper rounding. */
12048 + return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
12049 +}
12050 +
12051 +uint8
12052 +bcm_mw_to_qdbm(uint16 mw)
12053 +{
12054 + uint8 qdbm;
12055 + int offset;
12056 + uint mw_uint = mw;
12057 + uint boundary;
12058 +
12059 + /* handle boundary case */
12060 + if (mw_uint <= 1)
12061 + return 0;
12062 +
12063 + offset = QDBM_OFFSET;
12064 +
12065 + /* move mw into the range of the table */
12066 + while (mw_uint < QDBM_TABLE_LOW_BOUND) {
12067 + mw_uint *= 10;
12068 + offset -= 40;
12069 + }
12070 +
12071 + for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
12072 + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
12073 + if (mw_uint < boundary) break;
12074 + }
12075 +
12076 + qdbm += (uint8)offset;
12077 +
12078 + return(qdbm);
12079 +}
12080 diff -Naur linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
12081 --- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
12082 +++ linux.dev/drivers/net/hnd/linux_osl.c 2006-04-06 15:34:15.000000000 +0200
12083 @@ -0,0 +1,708 @@
12084 +/*
12085 + * Linux OS Independent Layer
12086 + *
12087 + * Copyright 2005, Broadcom Corporation
12088 + * All Rights Reserved.
12089 + *
12090 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12091 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12092 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12093 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12094 + *
12095 + * $Id$
12096 + */
12097 +
12098 +#define LINUX_OSL
12099 +
12100 +#include <typedefs.h>
12101 +#include <bcmendian.h>
12102 +#include <linux/module.h>
12103 +#include <linuxver.h>
12104 +#include <osl.h>
12105 +#include <bcmutils.h>
12106 +#include <linux/delay.h>
12107 +#ifdef mips
12108 +#include <asm/paccess.h>
12109 +#endif
12110 +#include <pcicfg.h>
12111 +
12112 +#define PCI_CFG_RETRY 10
12113 +
12114 +#define OS_HANDLE_MAGIC 0x1234abcd
12115 +#define BCM_MEM_FILENAME_LEN 24
12116 +
12117 +typedef struct bcm_mem_link {
12118 + struct bcm_mem_link *prev;
12119 + struct bcm_mem_link *next;
12120 + uint size;
12121 + int line;
12122 + char file[BCM_MEM_FILENAME_LEN];
12123 +} bcm_mem_link_t;
12124 +
12125 +struct os_handle {
12126 + uint magic;
12127 + void *pdev;
12128 + uint malloced;
12129 + uint failed;
12130 + bcm_mem_link_t *dbgmem_list;
12131 +};
12132 +
12133 +static int16 linuxbcmerrormap[] = \
12134 +{ 0, /* 0 */
12135 + -EINVAL, /* BCME_ERROR */
12136 + -EINVAL, /* BCME_BADARG*/
12137 + -EINVAL, /* BCME_BADOPTION*/
12138 + -EINVAL, /* BCME_NOTUP */
12139 + -EINVAL, /* BCME_NOTDOWN */
12140 + -EINVAL, /* BCME_NOTAP */
12141 + -EINVAL, /* BCME_NOTSTA */
12142 + -EINVAL, /* BCME_BADKEYIDX */
12143 + -EINVAL, /* BCME_RADIOOFF */
12144 + -EINVAL, /* BCME_NOTBANDLOCKED */
12145 + -EINVAL, /* BCME_NOCLK */
12146 + -EINVAL, /* BCME_BADRATESET */
12147 + -EINVAL, /* BCME_BADBAND */
12148 + -E2BIG, /* BCME_BUFTOOSHORT */
12149 + -E2BIG, /* BCME_BUFTOOLONG */
12150 + -EBUSY, /* BCME_BUSY */
12151 + -EINVAL, /* BCME_NOTASSOCIATED */
12152 + -EINVAL, /* BCME_BADSSIDLEN */
12153 + -EINVAL, /* BCME_OUTOFRANGECHAN */
12154 + -EINVAL, /* BCME_BADCHAN */
12155 + -EFAULT, /* BCME_BADADDR */
12156 + -ENOMEM, /* BCME_NORESOURCE */
12157 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
12158 + -EMSGSIZE, /* BCME_BADLENGTH */
12159 + -EINVAL, /* BCME_NOTREADY */
12160 + -EPERM, /* BCME_NOTPERMITTED */
12161 + -ENOMEM, /* BCME_NOMEM */
12162 + -EINVAL, /* BCME_ASSOCIATED */
12163 + -ERANGE, /* BCME_RANGE */
12164 + -EINVAL /* BCME_NOTFOUND */
12165 +};
12166 +
12167 +/* translate bcmerrors into linux errors*/
12168 +int
12169 +osl_error(int bcmerror)
12170 +{
12171 + int abs_bcmerror;
12172 + int array_size = ARRAYSIZE(linuxbcmerrormap);
12173 +
12174 + abs_bcmerror = ABS(bcmerror);
12175 +
12176 + if (bcmerror > 0)
12177 + abs_bcmerror = 0;
12178 +
12179 + else if (abs_bcmerror >= array_size)
12180 + abs_bcmerror = BCME_ERROR;
12181 +
12182 + return linuxbcmerrormap[abs_bcmerror];
12183 +}
12184 +
12185 +osl_t *
12186 +osl_attach(void *pdev)
12187 +{
12188 + osl_t *osh;
12189 +
12190 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
12191 + ASSERT(osh);
12192 +
12193 + /*
12194 + * check the cases where
12195 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
12196 + * dependent error code
12197 + * 2. Error code is added to the bcmerror table, but forgot to add the
12198 + * corresponding errorstring(dummy call to bcmerrorstr)
12199 + */
12200 + bcmerrorstr(0);
12201 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
12202 +
12203 + osh->magic = OS_HANDLE_MAGIC;
12204 + osh->malloced = 0;
12205 + osh->failed = 0;
12206 + osh->dbgmem_list = NULL;
12207 + osh->pdev = pdev;
12208 +
12209 + return osh;
12210 +}
12211 +
12212 +void
12213 +osl_detach(osl_t *osh)
12214 +{
12215 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
12216 + kfree(osh);
12217 +}
12218 +
12219 +void*
12220 +osl_pktget(osl_t *osh, uint len, bool send)
12221 +{
12222 + struct sk_buff *skb;
12223 +
12224 + if ((skb = dev_alloc_skb(len)) == NULL)
12225 + return (NULL);
12226 +
12227 + skb_put(skb, len);
12228 +
12229 + /* ensure the cookie field is cleared */
12230 + PKTSETCOOKIE(skb, NULL);
12231 +
12232 + return ((void*) skb);
12233 +}
12234 +
12235 +void
12236 +osl_pktfree(void *p)
12237 +{
12238 + struct sk_buff *skb, *nskb;
12239 +
12240 + skb = (struct sk_buff*) p;
12241 +
12242 + /* perversion: we use skb->next to chain multi-skb packets */
12243 + while (skb) {
12244 + nskb = skb->next;
12245 + skb->next = NULL;
12246 + if (skb->destructor) {
12247 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
12248 + dev_kfree_skb_any(skb);
12249 + } else {
12250 + /* can free immediately (even in_irq()) if destructor does not exist */
12251 + dev_kfree_skb(skb);
12252 + }
12253 + skb = nskb;
12254 + }
12255 +}
12256 +
12257 +uint32
12258 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
12259 +{
12260 + uint val;
12261 + uint retry=PCI_CFG_RETRY;
12262 +
12263 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12264 +
12265 + /* only 4byte access supported */
12266 + ASSERT(size == 4);
12267 +
12268 + do {
12269 + pci_read_config_dword(osh->pdev, offset, &val);
12270 + if (val != 0xffffffff)
12271 + break;
12272 + } while (retry--);
12273 +
12274 +
12275 + return (val);
12276 +}
12277 +
12278 +void
12279 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
12280 +{
12281 + uint retry=PCI_CFG_RETRY;
12282 +
12283 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12284 +
12285 + /* only 4byte access supported */
12286 + ASSERT(size == 4);
12287 +
12288 + do {
12289 + pci_write_config_dword(osh->pdev, offset, val);
12290 + if (offset!=PCI_BAR0_WIN)
12291 + break;
12292 + if (osl_pci_read_config(osh,offset,size) == val)
12293 + break;
12294 + } while (retry--);
12295 +
12296 +}
12297 +
12298 +/* return bus # for the pci device pointed by osh->pdev */
12299 +uint
12300 +osl_pci_bus(osl_t *osh)
12301 +{
12302 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
12303 +
12304 + return ((struct pci_dev *)osh->pdev)->bus->number;
12305 +}
12306 +
12307 +/* return slot # for the pci device pointed by osh->pdev */
12308 +uint
12309 +osl_pci_slot(osl_t *osh)
12310 +{
12311 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
12312 +
12313 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
12314 +}
12315 +
12316 +static void
12317 +osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
12318 +{
12319 +}
12320 +
12321 +void
12322 +osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
12323 +{
12324 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
12325 +}
12326 +
12327 +void
12328 +osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
12329 +{
12330 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
12331 +}
12332 +
12333 +
12334 +#ifdef BCMDBG_MEM
12335 +
12336 +void*
12337 +osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
12338 +{
12339 + bcm_mem_link_t *p;
12340 + char* basename;
12341 +
12342 + ASSERT(size);
12343 +
12344 + if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
12345 + return (NULL);
12346 +
12347 + p->size = size;
12348 + p->line = line;
12349 +
12350 + basename = strrchr(file, '/');
12351 + /* skip the '/' */
12352 + if (basename)
12353 + basename++;
12354 +
12355 + if (!basename)
12356 + basename = file;
12357 +
12358 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
12359 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
12360 +
12361 + /* link this block */
12362 + p->prev = NULL;
12363 + p->next = osh->dbgmem_list;
12364 + if (p->next)
12365 + p->next->prev = p;
12366 + osh->dbgmem_list = p;
12367 +
12368 + return p + 1;
12369 +}
12370 +
12371 +void
12372 +osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
12373 +{
12374 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
12375 +
12376 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12377 +
12378 + if (p->size == 0) {
12379 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
12380 + (uint)addr, size, line, file);
12381 + ASSERT(p->size);
12382 + return;
12383 + }
12384 +
12385 + if (p->size != size) {
12386 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
12387 + size, p->size, (uint)addr, line, file);
12388 + ASSERT(p->size == size);
12389 + return;
12390 + }
12391 +
12392 + /* unlink this block */
12393 + if (p->prev)
12394 + p->prev->next = p->next;
12395 + if (p->next)
12396 + p->next->prev = p->prev;
12397 + if (osh->dbgmem_list == p)
12398 + osh->dbgmem_list = p->next;
12399 + p->next = p->prev = NULL;
12400 +
12401 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
12402 +}
12403 +
12404 +char*
12405 +osl_debug_memdump(osl_t *osh, char *buf, uint sz)
12406 +{
12407 + bcm_mem_link_t *p;
12408 + char *obuf;
12409 +
12410 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12411 + obuf = buf;
12412 +
12413 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
12414 + for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
12415 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
12416 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
12417 +
12418 + return (obuf);
12419 +}
12420 +
12421 +#endif /* BCMDBG_MEM */
12422 +
12423 +void*
12424 +osl_malloc(osl_t *osh, uint size)
12425 +{
12426 + void *addr;
12427 +
12428 + /* only ASSERT if osh is defined */
12429 + if (osh)
12430 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
12431 +
12432 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
12433 + if(osh)
12434 + osh->failed++;
12435 + return (NULL);
12436 + }
12437 + if (osh)
12438 + osh->malloced += size;
12439 +
12440 + return (addr);
12441 +}
12442 +
12443 +void
12444 +osl_mfree(osl_t *osh, void *addr, uint size)
12445 +{
12446 + if (osh) {
12447 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
12448 + osh->malloced -= size;
12449 + }
12450 + kfree(addr);
12451 +}
12452 +
12453 +uint
12454 +osl_malloced(osl_t *osh)
12455 +{
12456 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12457 + return (osh->malloced);
12458 +}
12459 +
12460 +uint osl_malloc_failed(osl_t *osh)
12461 +{
12462 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12463 + return (osh->failed);
12464 +}
12465 +
12466 +void*
12467 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
12468 +{
12469 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12470 +
12471 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
12472 +}
12473 +
12474 +void
12475 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
12476 +{
12477 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12478 +
12479 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
12480 +}
12481 +
12482 +uint
12483 +osl_dma_map(osl_t *osh, void *va, uint size, int direction)
12484 +{
12485 + int dir;
12486 +
12487 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12488 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
12489 + return (pci_map_single(osh->pdev, va, size, dir));
12490 +}
12491 +
12492 +void
12493 +osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
12494 +{
12495 + int dir;
12496 +
12497 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
12498 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
12499 + pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
12500 +}
12501 +
12502 +#if defined(BINOSL)
12503 +void
12504 +osl_assert(char *exp, char *file, int line)
12505 +{
12506 + char tempbuf[255];
12507 +
12508 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
12509 + panic(tempbuf);
12510 +}
12511 +#endif /* BCMDBG || BINOSL */
12512 +
12513 +void
12514 +osl_delay(uint usec)
12515 +{
12516 + uint d;
12517 +
12518 + while (usec > 0) {
12519 + d = MIN(usec, 1000);
12520 + udelay(d);
12521 + usec -= d;
12522 + }
12523 +}
12524 +
12525 +/*
12526 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
12527 + */
12528 +#ifdef BINOSL
12529 +
12530 +int
12531 +osl_printf(const char *format, ...)
12532 +{
12533 + va_list args;
12534 + char buf[1024];
12535 + int len;
12536 +
12537 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
12538 + va_start(args, format);
12539 + len = vsprintf(buf, format, args);
12540 + va_end(args);
12541 +
12542 + if (len > sizeof (buf)) {
12543 + printk("osl_printf: buffer overrun\n");
12544 + return (0);
12545 + }
12546 +
12547 + return (printk(buf));
12548 +}
12549 +
12550 +int
12551 +osl_sprintf(char *buf, const char *format, ...)
12552 +{
12553 + va_list args;
12554 + int rc;
12555 +
12556 + va_start(args, format);
12557 + rc = vsprintf(buf, format, args);
12558 + va_end(args);
12559 + return (rc);
12560 +}
12561 +
12562 +int
12563 +osl_strcmp(const char *s1, const char *s2)
12564 +{
12565 + return (strcmp(s1, s2));
12566 +}
12567 +
12568 +int
12569 +osl_strncmp(const char *s1, const char *s2, uint n)
12570 +{
12571 + return (strncmp(s1, s2, n));
12572 +}
12573 +
12574 +int
12575 +osl_strlen(const char *s)
12576 +{
12577 + return (strlen(s));
12578 +}
12579 +
12580 +char*
12581 +osl_strcpy(char *d, const char *s)
12582 +{
12583 + return (strcpy(d, s));
12584 +}
12585 +
12586 +char*
12587 +osl_strncpy(char *d, const char *s, uint n)
12588 +{
12589 + return (strncpy(d, s, n));
12590 +}
12591 +
12592 +void
12593 +bcopy(const void *src, void *dst, int len)
12594 +{
12595 + memcpy(dst, src, len);
12596 +}
12597 +
12598 +int
12599 +bcmp(const void *b1, const void *b2, int len)
12600 +{
12601 + return (memcmp(b1, b2, len));
12602 +}
12603 +
12604 +void
12605 +bzero(void *b, int len)
12606 +{
12607 + memset(b, '\0', len);
12608 +}
12609 +
12610 +uint32
12611 +osl_readl(volatile uint32 *r)
12612 +{
12613 + return (readl(r));
12614 +}
12615 +
12616 +uint16
12617 +osl_readw(volatile uint16 *r)
12618 +{
12619 + return (readw(r));
12620 +}
12621 +
12622 +uint8
12623 +osl_readb(volatile uint8 *r)
12624 +{
12625 + return (readb(r));
12626 +}
12627 +
12628 +void
12629 +osl_writel(uint32 v, volatile uint32 *r)
12630 +{
12631 + writel(v, r);
12632 +}
12633 +
12634 +void
12635 +osl_writew(uint16 v, volatile uint16 *r)
12636 +{
12637 + writew(v, r);
12638 +}
12639 +
12640 +void
12641 +osl_writeb(uint8 v, volatile uint8 *r)
12642 +{
12643 + writeb(v, r);
12644 +}
12645 +
12646 +void *
12647 +osl_uncached(void *va)
12648 +{
12649 +#ifdef mips
12650 + return ((void*)KSEG1ADDR(va));
12651 +#else
12652 + return ((void*)va);
12653 +#endif
12654 +}
12655 +
12656 +uint
12657 +osl_getcycles(void)
12658 +{
12659 + uint cycles;
12660 +
12661 +#if defined(mips)
12662 + cycles = read_c0_count() * 2;
12663 +#elif defined(__i386__)
12664 + rdtscl(cycles);
12665 +#else
12666 + cycles = 0;
12667 +#endif
12668 + return cycles;
12669 +}
12670 +
12671 +void *
12672 +osl_reg_map(uint32 pa, uint size)
12673 +{
12674 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
12675 +}
12676 +
12677 +void
12678 +osl_reg_unmap(void *va)
12679 +{
12680 + iounmap(va);
12681 +}
12682 +
12683 +int
12684 +osl_busprobe(uint32 *val, uint32 addr)
12685 +{
12686 +#ifdef mips
12687 + return get_dbe(*val, (uint32*)addr);
12688 +#else
12689 + *val = readl(addr);
12690 + return 0;
12691 +#endif
12692 +}
12693 +
12694 +uchar*
12695 +osl_pktdata(osl_t *osh, void *skb)
12696 +{
12697 + return (((struct sk_buff*)skb)->data);
12698 +}
12699 +
12700 +uint
12701 +osl_pktlen(osl_t *osh, void *skb)
12702 +{
12703 + return (((struct sk_buff*)skb)->len);
12704 +}
12705 +
12706 +uint
12707 +osl_pktheadroom(osl_t *osh, void *skb)
12708 +{
12709 + return (uint) skb_headroom((struct sk_buff *) skb);
12710 +}
12711 +
12712 +uint
12713 +osl_pkttailroom(osl_t *osh, void *skb)
12714 +{
12715 + return (uint) skb_tailroom((struct sk_buff *) skb);
12716 +}
12717 +
12718 +void*
12719 +osl_pktnext(osl_t *osh, void *skb)
12720 +{
12721 + return (((struct sk_buff*)skb)->next);
12722 +}
12723 +
12724 +void
12725 +osl_pktsetnext(void *skb, void *x)
12726 +{
12727 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
12728 +}
12729 +
12730 +void
12731 +osl_pktsetlen(osl_t *osh, void *skb, uint len)
12732 +{
12733 + __skb_trim((struct sk_buff*)skb, len);
12734 +}
12735 +
12736 +uchar*
12737 +osl_pktpush(osl_t *osh, void *skb, int bytes)
12738 +{
12739 + return (skb_push((struct sk_buff*)skb, bytes));
12740 +}
12741 +
12742 +uchar*
12743 +osl_pktpull(osl_t *osh, void *skb, int bytes)
12744 +{
12745 + return (skb_pull((struct sk_buff*)skb, bytes));
12746 +}
12747 +
12748 +void*
12749 +osl_pktdup(osl_t *osh, void *skb)
12750 +{
12751 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
12752 +}
12753 +
12754 +void*
12755 +osl_pktcookie(void *skb)
12756 +{
12757 + return ((void*)((struct sk_buff*)skb)->csum);
12758 +}
12759 +
12760 +void
12761 +osl_pktsetcookie(void *skb, void *x)
12762 +{
12763 + ((struct sk_buff*)skb)->csum = (uint)x;
12764 +}
12765 +
12766 +void*
12767 +osl_pktlink(void *skb)
12768 +{
12769 + return (((struct sk_buff*)skb)->prev);
12770 +}
12771 +
12772 +void
12773 +osl_pktsetlink(void *skb, void *x)
12774 +{
12775 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
12776 +}
12777 +
12778 +uint
12779 +osl_pktprio(void *skb)
12780 +{
12781 + return (((struct sk_buff*)skb)->priority);
12782 +}
12783 +
12784 +void
12785 +osl_pktsetprio(void *skb, uint x)
12786 +{
12787 + ((struct sk_buff*)skb)->priority = x;
12788 +}
12789 +
12790 +
12791 +#endif /* BINOSL */
12792 diff -Naur linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
12793 --- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
12794 +++ linux.dev/drivers/net/hnd/sbutils.c 2006-04-06 15:34:15.000000000 +0200
12795 @@ -0,0 +1,2837 @@
12796 +/*
12797 + * Misc utility routines for accessing chip-specific features
12798 + * of the SiliconBackplane-based Broadcom chips.
12799 + *
12800 + * Copyright 2005, Broadcom Corporation
12801 + * All Rights Reserved.
12802 + *
12803 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12804 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12805 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12806 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12807 + * $Id$
12808 + */
12809 +
12810 +#include <typedefs.h>
12811 +#include <osl.h>
12812 +#include <sbutils.h>
12813 +#include <bcmutils.h>
12814 +#include <bcmdevs.h>
12815 +#include <sbconfig.h>
12816 +#include <sbchipc.h>
12817 +#include <sbpci.h>
12818 +#include <sbpcie.h>
12819 +#include <pcicfg.h>
12820 +#include <sbpcmcia.h>
12821 +#include <sbextif.h>
12822 +#include <bcmsrom.h>
12823 +
12824 +/* debug/trace */
12825 +#define SB_ERROR(args)
12826 +
12827 +
12828 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12829 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12830 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12831 +
12832 +/* misc sb info needed by some of the routines */
12833 +typedef struct sb_info {
12834 +
12835 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
12836 +
12837 + void *osh; /* osl os handle */
12838 + void *sdh; /* bcmsdh handle */
12839 +
12840 + void *curmap; /* current regs va */
12841 + void *regs[SB_MAXCORES]; /* other regs va */
12842 +
12843 + uint curidx; /* current core index */
12844 + uint dev_coreid; /* the core provides driver functions */
12845 +
12846 + bool memseg; /* flag to toggle MEM_SEG register */
12847 +
12848 + uint gpioidx; /* gpio control core index */
12849 + uint gpioid; /* gpio control coretype */
12850 +
12851 + uint numcores; /* # discovered cores */
12852 + uint coreid[SB_MAXCORES]; /* id of each core */
12853 +
12854 + void *intr_arg; /* interrupt callback function arg */
12855 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
12856 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
12857 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
12858 +
12859 +} sb_info_t;
12860 +
12861 +/* local prototypes */
12862 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12863 + uint bustype, void *sdh, char **vars, int *varsz);
12864 +static void BCMINIT(sb_scan)(sb_info_t *si);
12865 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12866 +static uint _sb_coreidx(sb_info_t *si);
12867 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12868 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
12869 +static uint BCMINIT(sb_chip2numcores)(uint chip);
12870 +static bool sb_ispcie(sb_info_t *si);
12871 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12872 +static int sb_pci_fixcfg(sb_info_t *si);
12873 +
12874 +/* routines to access mdio slave device registers */
12875 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12876 +static void BCMINIT(sb_war30841)(sb_info_t *si);
12877 +
12878 +/* delay needed between the mdio control/ mdiodata register data access */
12879 +#define PR28829_DELAY() OSL_DELAY(10)
12880 +
12881 +
12882 +/* global variable to indicate reservation/release of gpio's*/
12883 +static uint32 sb_gpioreservation = 0;
12884 +
12885 +#define SB_INFO(sbh) (sb_info_t*)sbh
12886 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
12887 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
12888 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12889 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12890 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12891 +#define BADIDX (SB_MAXCORES+1)
12892 +#define NOREV -1
12893 +
12894 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12895 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12896 +
12897 +/* sonicsrev */
12898 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12899 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12900 +
12901 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
12902 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
12903 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
12904 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
12905 +
12906 +/*
12907 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12908 + * after core switching to avoid invalid register accesss inside ISR.
12909 + */
12910 +#define INTR_OFF(si, intr_val) \
12911 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12912 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12913 +#define INTR_RESTORE(si, intr_val) \
12914 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12915 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12916 +
12917 +/* dynamic clock control defines */
12918 +#define LPOMINFREQ 25000 /* low power oscillator min */
12919 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12920 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12921 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12922 +#define PCIMINFREQ 25000000 /* 25 MHz */
12923 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12924 +
12925 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12926 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12927 +
12928 +#define MIN_DUMPBUFLEN 32 /* debug */
12929 +
12930 +/* different register spaces to access thr'u pcie indirect access*/
12931 +#define PCIE_CONFIGREGS 1
12932 +#define PCIE_PCIEREGS 2
12933 +
12934 +/* GPIO Based LED powersave defines */
12935 +#define DEFAULT_GPIO_ONTIME 10
12936 +#define DEFAULT_GPIO_OFFTIME 90
12937 +
12938 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12939 +
12940 +static uint32
12941 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12942 +{
12943 + uint8 tmp;
12944 + uint32 val, intr_val = 0;
12945 +
12946 +
12947 + /*
12948 + * compact flash only has 11 bits address, while we needs 12 bits address.
12949 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12950 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12951 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12952 + */
12953 + if(si->memseg) {
12954 + INTR_OFF(si, intr_val);
12955 + tmp = 1;
12956 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12957 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
12958 + }
12959 +
12960 + val = R_REG(sbr);
12961 +
12962 + if(si->memseg) {
12963 + tmp = 0;
12964 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12965 + INTR_RESTORE(si, intr_val);
12966 + }
12967 +
12968 + return (val);
12969 +}
12970 +
12971 +static void
12972 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12973 +{
12974 + uint8 tmp;
12975 + volatile uint32 dummy;
12976 + uint32 intr_val = 0;
12977 +
12978 +
12979 + /*
12980 + * compact flash only has 11 bits address, while we needs 12 bits address.
12981 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12982 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12983 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12984 + */
12985 + if(si->memseg) {
12986 + INTR_OFF(si, intr_val);
12987 + tmp = 1;
12988 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12989 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
12990 + }
12991 +
12992 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12993 +#ifdef IL_BIGENDIAN
12994 + dummy = R_REG(sbr);
12995 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12996 + dummy = R_REG(sbr);
12997 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
12998 +#else
12999 + dummy = R_REG(sbr);
13000 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
13001 + dummy = R_REG(sbr);
13002 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
13003 +#endif
13004 + } else
13005 + W_REG(sbr, v);
13006 +
13007 + if(si->memseg) {
13008 + tmp = 0;
13009 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
13010 + INTR_RESTORE(si, intr_val);
13011 + }
13012 +}
13013 +
13014 +/*
13015 + * Allocate a sb handle.
13016 + * devid - pci device id (used to determine chip#)
13017 + * osh - opaque OS handle
13018 + * regs - virtual address of initial core registers
13019 + * bustype - pci/pcmcia/sb/sdio/etc
13020 + * vars - pointer to a pointer area for "environment" variables
13021 + * varsz - pointer to int to return the size of the vars
13022 + */
13023 +sb_t *
13024 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
13025 + uint bustype, void *sdh, char **vars, int *varsz)
13026 +{
13027 + sb_info_t *si;
13028 +
13029 + /* alloc sb_info_t */
13030 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
13031 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
13032 + return (NULL);
13033 + }
13034 +
13035 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
13036 + MFREE(osh, si, sizeof (sb_info_t));
13037 + return (NULL);
13038 + }
13039 + return (sb_t *)si;
13040 +}
13041 +
13042 +/* Using sb_kattach depends on SB_BUS support, either implicit */
13043 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
13044 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
13045 +
13046 +/* global kernel resource */
13047 +static sb_info_t ksi;
13048 +
13049 +/* generic kernel variant of sb_attach() */
13050 +sb_t *
13051 +BCMINITFN(sb_kattach)()
13052 +{
13053 + uint32 *regs;
13054 +
13055 + if (ksi.curmap == NULL) {
13056 + uint32 cid;
13057 +
13058 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
13059 + cid = R_REG((uint32 *)regs);
13060 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
13061 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
13062 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
13063 + uint32 *scc, val;
13064 +
13065 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
13066 + val = R_REG(scc);
13067 + SB_ERROR((" initial scc = 0x%x\n", val));
13068 + val |= SCC_SS_XTAL;
13069 + W_REG(scc, val);
13070 + }
13071 +
13072 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
13073 + SB_BUS, NULL, NULL, NULL) == NULL) {
13074 + return NULL;
13075 + }
13076 + }
13077 +
13078 + return (sb_t *)&ksi;
13079 +}
13080 +#endif
13081 +
13082 +static sb_info_t *
13083 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
13084 + uint bustype, void *sdh, char **vars, int *varsz)
13085 +{
13086 + uint origidx;
13087 + chipcregs_t *cc;
13088 + sbconfig_t *sb;
13089 + uint32 w;
13090 +
13091 + ASSERT(GOODREGS(regs));
13092 +
13093 + bzero((uchar*)si, sizeof (sb_info_t));
13094 +
13095 + si->sb.buscoreidx = si->gpioidx = BADIDX;
13096 +
13097 + si->osh = osh;
13098 + si->curmap = regs;
13099 + si->sdh = sdh;
13100 +
13101 + /* check to see if we are a sb core mimic'ing a pci core */
13102 + if (bustype == PCI_BUS) {
13103 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
13104 + bustype = SB_BUS;
13105 + else
13106 + bustype = PCI_BUS;
13107 + }
13108 +
13109 + si->sb.bustype = bustype;
13110 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
13111 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
13112 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
13113 + return NULL;
13114 + }
13115 +
13116 + /* need to set memseg flag for CF card first before any sb registers access */
13117 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
13118 + si->memseg = TRUE;
13119 +
13120 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
13121 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
13122 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
13123 +
13124 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
13125 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
13126 + if (!GOODCOREADDR(w))
13127 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
13128 + }
13129 +
13130 + /* initialize current core index value */
13131 + si->curidx = _sb_coreidx(si);
13132 +
13133 + if (si->curidx == BADIDX) {
13134 + SB_ERROR(("sb_doattach: bad core index\n"));
13135 + return NULL;
13136 + }
13137 +
13138 + /* get sonics backplane revision */
13139 + sb = REGS2SB(si->curmap);
13140 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
13141 +
13142 + /* keep and reuse the initial register mapping */
13143 + origidx = si->curidx;
13144 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
13145 + si->regs[origidx] = regs;
13146 +
13147 + /* is core-0 a chipcommon core? */
13148 + si->numcores = 1;
13149 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
13150 + if (sb_coreid(&si->sb) != SB_CC)
13151 + cc = NULL;
13152 +
13153 + /* determine chip id and rev */
13154 + if (cc) {
13155 + /* chip common core found! */
13156 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
13157 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
13158 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
13159 + } else {
13160 + /* The only pcmcia chip without a chipcommon core is a 4301 */
13161 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
13162 + devid = BCM4301_DEVICE_ID;
13163 +
13164 + /* no chip common core -- must convert device id to chip id */
13165 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
13166 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
13167 + sb_setcoreidx(&si->sb, origidx);
13168 + return NULL;
13169 + }
13170 + }
13171 +
13172 + /* get chipcommon rev */
13173 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
13174 +
13175 + /* determine numcores */
13176 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
13177 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
13178 + else
13179 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
13180 +
13181 + /* return to original core */
13182 + sb_setcoreidx(&si->sb, origidx);
13183 +
13184 + /* sanity checks */
13185 + ASSERT(si->sb.chip);
13186 +
13187 + /* scan for cores */
13188 + BCMINIT(sb_scan)(si);
13189 +
13190 + /* fixup necessary chip/core configurations */
13191 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
13192 + if (sb_pci_fixcfg(si)) {
13193 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
13194 + return NULL;
13195 + }
13196 + }
13197 +
13198 + /* srom_var_init() depends on sb_scan() info */
13199 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
13200 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
13201 + return (NULL);
13202 + }
13203 +
13204 + if (cc == NULL) {
13205 + /*
13206 + * The chip revision number is hardwired into all
13207 + * of the pci function config rev fields and is
13208 + * independent from the individual core revision numbers.
13209 + * For example, the "A0" silicon of each chip is chip rev 0.
13210 + * For PCMCIA we get it from the CIS instead.
13211 + */
13212 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
13213 + ASSERT(vars);
13214 + si->sb.chiprev = getintvar(*vars, "chiprev");
13215 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
13216 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
13217 + si->sb.chiprev = w & 0xff;
13218 + } else
13219 + si->sb.chiprev = 0;
13220 + }
13221 +
13222 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
13223 + w = getintvar(*vars, "regwindowsz");
13224 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
13225 + }
13226 +
13227 + /* gpio control core is required */
13228 + if (!GOODIDX(si->gpioidx)) {
13229 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
13230 + return NULL;
13231 + }
13232 +
13233 + /* get boardtype and boardrev */
13234 + switch (BUSTYPE(si->sb.bustype)) {
13235 + case PCI_BUS:
13236 + /* do a pci config read to get subsystem id and subvendor id */
13237 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
13238 + si->sb.boardvendor = w & 0xffff;
13239 + si->sb.boardtype = (w >> 16) & 0xffff;
13240 + break;
13241 +
13242 + case PCMCIA_BUS:
13243 + case SDIO_BUS:
13244 + si->sb.boardvendor = getintvar(*vars, "manfid");
13245 + si->sb.boardtype = getintvar(*vars, "prodid");
13246 + break;
13247 +
13248 + case SB_BUS:
13249 + case JTAG_BUS:
13250 + si->sb.boardvendor = VENDOR_BROADCOM;
13251 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
13252 + si->sb.boardtype = 0xffff;
13253 + break;
13254 + }
13255 +
13256 + if (si->sb.boardtype == 0) {
13257 + SB_ERROR(("sb_doattach: unknown board type\n"));
13258 + ASSERT(si->sb.boardtype);
13259 + }
13260 +
13261 + /* setup the GPIO based LED powersave register */
13262 + if (si->sb.ccrev >= 16) {
13263 + w = getintvar(*vars, "gpiotimerval");
13264 + if (!w)
13265 + w = DEFAULT_GPIOTIMERVAL;
13266 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
13267 + }
13268 +
13269 +
13270 + return (si);
13271 +}
13272 +
13273 +uint
13274 +sb_coreid(sb_t *sbh)
13275 +{
13276 + sb_info_t *si;
13277 + sbconfig_t *sb;
13278 +
13279 + si = SB_INFO(sbh);
13280 + sb = REGS2SB(si->curmap);
13281 +
13282 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
13283 +}
13284 +
13285 +uint
13286 +sb_coreidx(sb_t *sbh)
13287 +{
13288 + sb_info_t *si;
13289 +
13290 + si = SB_INFO(sbh);
13291 + return (si->curidx);
13292 +}
13293 +
13294 +/* return current index of core */
13295 +static uint
13296 +_sb_coreidx(sb_info_t *si)
13297 +{
13298 + sbconfig_t *sb;
13299 + uint32 sbaddr = 0;
13300 +
13301 + ASSERT(si);
13302 +
13303 + switch (BUSTYPE(si->sb.bustype)) {
13304 + case SB_BUS:
13305 + sb = REGS2SB(si->curmap);
13306 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
13307 + break;
13308 +
13309 + case PCI_BUS:
13310 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
13311 + break;
13312 +
13313 + case PCMCIA_BUS: {
13314 + uint8 tmp = 0;
13315 +
13316 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13317 + sbaddr = (uint)tmp << 12;
13318 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13319 + sbaddr |= (uint)tmp << 16;
13320 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13321 + sbaddr |= (uint)tmp << 24;
13322 + break;
13323 + }
13324 +
13325 +#ifdef BCMJTAG
13326 + case JTAG_BUS:
13327 + sbaddr = (uint32)si->curmap;
13328 + break;
13329 +#endif /* BCMJTAG */
13330 +
13331 + default:
13332 + ASSERT(0);
13333 + }
13334 +
13335 + if (!GOODCOREADDR(sbaddr))
13336 + return BADIDX;
13337 +
13338 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
13339 +}
13340 +
13341 +uint
13342 +sb_corevendor(sb_t *sbh)
13343 +{
13344 + sb_info_t *si;
13345 + sbconfig_t *sb;
13346 +
13347 + si = SB_INFO(sbh);
13348 + sb = REGS2SB(si->curmap);
13349 +
13350 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
13351 +}
13352 +
13353 +uint
13354 +sb_corerev(sb_t *sbh)
13355 +{
13356 + sb_info_t *si;
13357 + sbconfig_t *sb;
13358 + uint sbidh;
13359 +
13360 + si = SB_INFO(sbh);
13361 + sb = REGS2SB(si->curmap);
13362 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
13363 +
13364 + return (SBCOREREV(sbidh));
13365 +}
13366 +
13367 +void *
13368 +sb_osh(sb_t *sbh)
13369 +{
13370 + sb_info_t *si;
13371 +
13372 + si = SB_INFO(sbh);
13373 + return si->osh;
13374 +}
13375 +
13376 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
13377 +
13378 +/* set/clear sbtmstatelow core-specific flags */
13379 +uint32
13380 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
13381 +{
13382 + sb_info_t *si;
13383 + sbconfig_t *sb;
13384 + uint32 w;
13385 +
13386 + si = SB_INFO(sbh);
13387 + sb = REGS2SB(si->curmap);
13388 +
13389 + ASSERT((val & ~mask) == 0);
13390 + ASSERT((mask & ~SBTML_ALLOW) == 0);
13391 +
13392 + /* mask and set */
13393 + if (mask || val) {
13394 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
13395 + W_SBREG(si, &sb->sbtmstatelow, w);
13396 + }
13397 +
13398 + /* return the new value */
13399 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
13400 +}
13401 +
13402 +/* set/clear sbtmstatehigh core-specific flags */
13403 +uint32
13404 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
13405 +{
13406 + sb_info_t *si;
13407 + sbconfig_t *sb;
13408 + uint32 w;
13409 +
13410 + si = SB_INFO(sbh);
13411 + sb = REGS2SB(si->curmap);
13412 +
13413 + ASSERT((val & ~mask) == 0);
13414 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
13415 +
13416 + /* mask and set */
13417 + if (mask || val) {
13418 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
13419 + W_SBREG(si, &sb->sbtmstatehigh, w);
13420 + }
13421 +
13422 + /* return the new value */
13423 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
13424 +}
13425 +
13426 +/* caller needs to take care of core-specific bist hazards */
13427 +int
13428 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
13429 +{
13430 + uint32 sblo;
13431 + uint coreidx;
13432 + sb_info_t *si;
13433 + int result = 0;
13434 +
13435 + si = SB_INFO(sbh);
13436 +
13437 + coreidx = sb_findcoreidx(si, coreid, coreunit);
13438 + if (!GOODIDX(coreidx))
13439 + result = BCME_ERROR;
13440 + else {
13441 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
13442 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
13443 +
13444 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
13445 +
13446 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
13447 + result = BCME_ERROR;
13448 +
13449 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
13450 + }
13451 +
13452 + return result;
13453 +}
13454 +
13455 +bool
13456 +sb_iscoreup(sb_t *sbh)
13457 +{
13458 + sb_info_t *si;
13459 + sbconfig_t *sb;
13460 +
13461 + si = SB_INFO(sbh);
13462 + sb = REGS2SB(si->curmap);
13463 +
13464 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
13465 +}
13466 +
13467 +/*
13468 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
13469 + * switch back to the original core, and return the new value.
13470 + */
13471 +static uint
13472 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
13473 +{
13474 + uint origidx;
13475 + uint32 *r;
13476 + uint w;
13477 + uint intr_val = 0;
13478 +
13479 + ASSERT(GOODIDX(coreidx));
13480 + ASSERT(regoff < SB_CORE_SIZE);
13481 + ASSERT((val & ~mask) == 0);
13482 +
13483 + INTR_OFF(si, intr_val);
13484 +
13485 + /* save current core index */
13486 + origidx = sb_coreidx(&si->sb);
13487 +
13488 + /* switch core */
13489 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
13490 +
13491 + /* mask and set */
13492 + if (mask || val) {
13493 + if (regoff >= SBCONFIGOFF) {
13494 + w = (R_SBREG(si, r) & ~mask) | val;
13495 + W_SBREG(si, r, w);
13496 + } else {
13497 + w = (R_REG(r) & ~mask) | val;
13498 + W_REG(r, w);
13499 + }
13500 + }
13501 +
13502 + /* readback */
13503 + if (regoff >= SBCONFIGOFF)
13504 + w = R_SBREG(si, r);
13505 + else
13506 + w = R_REG(r);
13507 +
13508 + /* restore core index */
13509 + if (origidx != coreidx)
13510 + sb_setcoreidx(&si->sb, origidx);
13511 +
13512 + INTR_RESTORE(si, intr_val);
13513 + return (w);
13514 +}
13515 +
13516 +#define DWORD_ALIGN(x) (x & ~(0x03))
13517 +#define BYTE_POS(x) (x & 0x3)
13518 +#define WORD_POS(x) (x & 0x1)
13519 +
13520 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
13521 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
13522 +
13523 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
13524 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
13525 +
13526 +#define read_pci_cfg_byte(a) \
13527 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
13528 +
13529 +#define read_pci_cfg_write(a) \
13530 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
13531 +
13532 +
13533 +/* return TRUE if requested capability exists in the PCI config space */
13534 +static bool
13535 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
13536 +{
13537 + uint8 cap_id;
13538 + uint8 cap_ptr;
13539 + uint32 bufsize;
13540 + uint8 byte_val;
13541 +
13542 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13543 + return FALSE;
13544 +
13545 + /* check for Header type 0*/
13546 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
13547 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
13548 + return FALSE;
13549 +
13550 + /* check if the capability pointer field exists */
13551 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
13552 + if (!(byte_val & PCI_CAPPTR_PRESENT))
13553 + return FALSE;
13554 +
13555 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
13556 + /* check if the capability pointer is 0x00 */
13557 + if (cap_ptr == 0x00)
13558 + return FALSE;
13559 +
13560 +
13561 + /* loop thr'u the capability list and see if the pcie capabilty exists */
13562 +
13563 + cap_id = read_pci_cfg_byte(cap_ptr);
13564 +
13565 + while (cap_id != req_cap_id) {
13566 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
13567 + if (cap_ptr == 0x00) break;
13568 + cap_id = read_pci_cfg_byte(cap_ptr);
13569 + }
13570 + if (cap_id != req_cap_id) {
13571 + return FALSE;
13572 + }
13573 + /* found the caller requested capability */
13574 + if ((buf != NULL) && (buflen != NULL)) {
13575 + bufsize = *buflen;
13576 + if (!bufsize) goto end;
13577 + *buflen = 0;
13578 + /* copy the cpability data excluding cap ID and next ptr */
13579 + cap_ptr += 2;
13580 + if ((bufsize + cap_ptr) > SZPCR)
13581 + bufsize = SZPCR - cap_ptr;
13582 + *buflen = bufsize;
13583 + while (bufsize--) {
13584 + *buf = read_pci_cfg_byte(cap_ptr);
13585 + cap_ptr++;
13586 + buf++;
13587 + }
13588 + }
13589 +end:
13590 + return TRUE;
13591 +}
13592 +
13593 +/* return TRUE if PCIE capability exists the pci config space */
13594 +static bool
13595 +sb_ispcie(sb_info_t *si)
13596 +{
13597 + return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
13598 +}
13599 +
13600 +/* scan the sb enumerated space to identify all cores */
13601 +static void
13602 +BCMINITFN(sb_scan)(sb_info_t *si)
13603 +{
13604 + uint origidx;
13605 + uint i;
13606 + bool pci;
13607 + bool pcie;
13608 + uint pciidx;
13609 + uint pcieidx;
13610 + uint pcirev;
13611 + uint pcierev;
13612 +
13613 +
13614 +
13615 + /* numcores should already be set */
13616 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
13617 +
13618 + /* save current core index */
13619 + origidx = sb_coreidx(&si->sb);
13620 +
13621 + si->sb.buscorerev = NOREV;
13622 + si->sb.buscoreidx = BADIDX;
13623 +
13624 + si->gpioidx = BADIDX;
13625 +
13626 + pci = pcie = FALSE;
13627 + pcirev = pcierev = NOREV;
13628 + pciidx = pcieidx = BADIDX;
13629 +
13630 + for (i = 0; i < si->numcores; i++) {
13631 + sb_setcoreidx(&si->sb, i);
13632 + si->coreid[i] = sb_coreid(&si->sb);
13633 +
13634 + if (si->coreid[i] == SB_PCI) {
13635 + pciidx = i;
13636 + pcirev = sb_corerev(&si->sb);
13637 + pci = TRUE;
13638 + } else if (si->coreid[i] == SB_PCIE) {
13639 + pcieidx = i;
13640 + pcierev = sb_corerev(&si->sb);
13641 + pcie = TRUE;
13642 + } else if (si->coreid[i] == SB_PCMCIA) {
13643 + si->sb.buscorerev = sb_corerev(&si->sb);
13644 + si->sb.buscoretype = si->coreid[i];
13645 + si->sb.buscoreidx = i;
13646 + }
13647 + }
13648 + if (pci && pcie) {
13649 + if (sb_ispcie(si))
13650 + pci = FALSE;
13651 + else
13652 + pcie = FALSE;
13653 + }
13654 + if (pci) {
13655 + si->sb.buscoretype = SB_PCI;
13656 + si->sb.buscorerev = pcirev;
13657 + si->sb.buscoreidx = pciidx;
13658 + }
13659 + else if (pcie) {
13660 + si->sb.buscoretype = SB_PCIE;
13661 + si->sb.buscorerev = pcierev;
13662 + si->sb.buscoreidx = pcieidx;
13663 + }
13664 +
13665 + /*
13666 + * Find the gpio "controlling core" type and index.
13667 + * Precedence:
13668 + * - if there's a chip common core - use that
13669 + * - else if there's a pci core (rev >= 2) - use that
13670 + * - else there had better be an extif core (4710 only)
13671 + */
13672 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
13673 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
13674 + si->gpioid = SB_CC;
13675 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
13676 + si->gpioidx = si->sb.buscoreidx;
13677 + si->gpioid = SB_PCI;
13678 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
13679 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
13680 + si->gpioid = SB_EXTIF;
13681 + } else
13682 + ASSERT(si->gpioidx != BADIDX);
13683 +
13684 + /* return to original core index */
13685 + sb_setcoreidx(&si->sb, origidx);
13686 +}
13687 +
13688 +/* may be called with core in reset */
13689 +void
13690 +sb_detach(sb_t *sbh)
13691 +{
13692 + sb_info_t *si;
13693 + uint idx;
13694 +
13695 + si = SB_INFO(sbh);
13696 +
13697 + if (si == NULL)
13698 + return;
13699 +
13700 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
13701 + for (idx = 0; idx < SB_MAXCORES; idx++)
13702 + if (si->regs[idx]) {
13703 + REG_UNMAP(si->regs[idx]);
13704 + si->regs[idx] = NULL;
13705 + }
13706 +
13707 + if (si != &ksi)
13708 + MFREE(si->osh, si, sizeof (sb_info_t));
13709 +}
13710 +
13711 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
13712 +static uint
13713 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
13714 +{
13715 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
13716 + return (BCM4710_DEVICE_ID);
13717 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
13718 + return (BCM4402_DEVICE_ID);
13719 + if (pcidev == BCM4401_ENET_ID)
13720 + return (BCM4402_DEVICE_ID);
13721 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
13722 + return (BCM4307_DEVICE_ID);
13723 + if (pcidev == BCM4301_DEVICE_ID)
13724 + return (BCM4301_DEVICE_ID);
13725 +
13726 + return (0);
13727 +}
13728 +
13729 +/* convert chip number to number of i/o cores */
13730 +static uint
13731 +BCMINITFN(sb_chip2numcores)(uint chip)
13732 +{
13733 + if (chip == BCM4710_DEVICE_ID)
13734 + return (9);
13735 + if (chip == BCM4402_DEVICE_ID)
13736 + return (3);
13737 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
13738 + return (5);
13739 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
13740 + return (6);
13741 + if (chip == BCM4704_DEVICE_ID)
13742 + return (9);
13743 + if (chip == BCM5365_DEVICE_ID)
13744 + return (7);
13745 +
13746 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13747 + ASSERT(0);
13748 + return (1);
13749 +}
13750 +
13751 +/* return index of coreid or BADIDX if not found */
13752 +static uint
13753 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
13754 +{
13755 + uint found;
13756 + uint i;
13757 +
13758 + found = 0;
13759 +
13760 + for (i = 0; i < si->numcores; i++)
13761 + if (si->coreid[i] == coreid) {
13762 + if (found == coreunit)
13763 + return (i);
13764 + found++;
13765 + }
13766 +
13767 + return (BADIDX);
13768 +}
13769 +
13770 +/*
13771 + * this function changes logical "focus" to the indiciated core,
13772 + * must be called with interrupt off.
13773 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13774 + */
13775 +void*
13776 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13777 +{
13778 + sb_info_t *si;
13779 + uint32 sbaddr;
13780 + uint8 tmp;
13781 +
13782 + si = SB_INFO(sbh);
13783 +
13784 + if (coreidx >= si->numcores)
13785 + return (NULL);
13786 +
13787 + /*
13788 + * If the user has provided an interrupt mask enabled function,
13789 + * then assert interrupts are disabled before switching the core.
13790 + */
13791 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13792 +
13793 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13794 +
13795 + switch (BUSTYPE(si->sb.bustype)) {
13796 + case SB_BUS:
13797 + /* map new one */
13798 + if (!si->regs[coreidx]) {
13799 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13800 + ASSERT(GOODREGS(si->regs[coreidx]));
13801 + }
13802 + si->curmap = si->regs[coreidx];
13803 + break;
13804 +
13805 + case PCI_BUS:
13806 + /* point bar0 window */
13807 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13808 + break;
13809 +
13810 + case PCMCIA_BUS:
13811 + tmp = (sbaddr >> 12) & 0x0f;
13812 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13813 + tmp = (sbaddr >> 16) & 0xff;
13814 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13815 + tmp = (sbaddr >> 24) & 0xff;
13816 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13817 + break;
13818 +#ifdef BCMJTAG
13819 + case JTAG_BUS:
13820 + /* map new one */
13821 + if (!si->regs[coreidx]) {
13822 + si->regs[coreidx] = (void *)sbaddr;
13823 + ASSERT(GOODREGS(si->regs[coreidx]));
13824 + }
13825 + si->curmap = si->regs[coreidx];
13826 + break;
13827 +#endif /* BCMJTAG */
13828 + }
13829 +
13830 + si->curidx = coreidx;
13831 +
13832 + return (si->curmap);
13833 +}
13834 +
13835 +/*
13836 + * this function changes logical "focus" to the indiciated core,
13837 + * must be called with interrupt off.
13838 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13839 + */
13840 +void*
13841 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13842 +{
13843 + sb_info_t *si;
13844 + uint idx;
13845 +
13846 + si = SB_INFO(sbh);
13847 + idx = sb_findcoreidx(si, coreid, coreunit);
13848 + if (!GOODIDX(idx))
13849 + return (NULL);
13850 +
13851 + return (sb_setcoreidx(sbh, idx));
13852 +}
13853 +
13854 +/* return chip number */
13855 +uint
13856 +BCMINITFN(sb_chip)(sb_t *sbh)
13857 +{
13858 + sb_info_t *si;
13859 +
13860 + si = SB_INFO(sbh);
13861 + return (si->sb.chip);
13862 +}
13863 +
13864 +/* return chip revision number */
13865 +uint
13866 +BCMINITFN(sb_chiprev)(sb_t *sbh)
13867 +{
13868 + sb_info_t *si;
13869 +
13870 + si = SB_INFO(sbh);
13871 + return (si->sb.chiprev);
13872 +}
13873 +
13874 +/* return chip common revision number */
13875 +uint
13876 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
13877 +{
13878 + sb_info_t *si;
13879 +
13880 + si = SB_INFO(sbh);
13881 + return (si->sb.ccrev);
13882 +}
13883 +
13884 +/* return chip package option */
13885 +uint
13886 +BCMINITFN(sb_chippkg)(sb_t *sbh)
13887 +{
13888 + sb_info_t *si;
13889 +
13890 + si = SB_INFO(sbh);
13891 + return (si->sb.chippkg);
13892 +}
13893 +
13894 +/* return PCI core rev. */
13895 +uint
13896 +BCMINITFN(sb_pcirev)(sb_t *sbh)
13897 +{
13898 + sb_info_t *si;
13899 +
13900 + si = SB_INFO(sbh);
13901 + return (si->sb.buscorerev);
13902 +}
13903 +
13904 +bool
13905 +BCMINITFN(sb_war16165)(sb_t *sbh)
13906 +{
13907 + sb_info_t *si;
13908 +
13909 + si = SB_INFO(sbh);
13910 +
13911 + return (PCI(si) && (si->sb.buscorerev <= 10));
13912 +}
13913 +
13914 +static void
13915 +BCMINITFN(sb_war30841)(sb_info_t *si)
13916 +{
13917 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13918 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13919 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13920 +}
13921 +
13922 +/* return PCMCIA core rev. */
13923 +uint
13924 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13925 +{
13926 + sb_info_t *si;
13927 +
13928 + si = SB_INFO(sbh);
13929 + return (si->sb.buscorerev);
13930 +}
13931 +
13932 +/* return board vendor id */
13933 +uint
13934 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
13935 +{
13936 + sb_info_t *si;
13937 +
13938 + si = SB_INFO(sbh);
13939 + return (si->sb.boardvendor);
13940 +}
13941 +
13942 +/* return boardtype */
13943 +uint
13944 +BCMINITFN(sb_boardtype)(sb_t *sbh)
13945 +{
13946 + sb_info_t *si;
13947 + char *var;
13948 +
13949 + si = SB_INFO(sbh);
13950 +
13951 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13952 + /* boardtype format is a hex string */
13953 + si->sb.boardtype = getintvar(NULL, "boardtype");
13954 +
13955 + /* backward compatibility for older boardtype string format */
13956 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13957 + if (!strcmp(var, "bcm94710dev"))
13958 + si->sb.boardtype = BCM94710D_BOARD;
13959 + else if (!strcmp(var, "bcm94710ap"))
13960 + si->sb.boardtype = BCM94710AP_BOARD;
13961 + else if (!strcmp(var, "bu4710"))
13962 + si->sb.boardtype = BU4710_BOARD;
13963 + else if (!strcmp(var, "bcm94702mn"))
13964 + si->sb.boardtype = BCM94702MN_BOARD;
13965 + else if (!strcmp(var, "bcm94710r1"))
13966 + si->sb.boardtype = BCM94710R1_BOARD;
13967 + else if (!strcmp(var, "bcm94710r4"))
13968 + si->sb.boardtype = BCM94710R4_BOARD;
13969 + else if (!strcmp(var, "bcm94702cpci"))
13970 + si->sb.boardtype = BCM94702CPCI_BOARD;
13971 + else if (!strcmp(var, "bcm95380_rr"))
13972 + si->sb.boardtype = BCM95380RR_BOARD;
13973 + }
13974 + }
13975 +
13976 + return (si->sb.boardtype);
13977 +}
13978 +
13979 +/* return bus type of sbh device */
13980 +uint
13981 +sb_bus(sb_t *sbh)
13982 +{
13983 + sb_info_t *si;
13984 +
13985 + si = SB_INFO(sbh);
13986 + return (si->sb.bustype);
13987 +}
13988 +
13989 +/* return bus core type */
13990 +uint
13991 +sb_buscoretype(sb_t *sbh)
13992 +{
13993 + sb_info_t *si;
13994 +
13995 + si = SB_INFO(sbh);
13996 +
13997 + return (si->sb.buscoretype);
13998 +}
13999 +
14000 +/* return bus core revision */
14001 +uint
14002 +sb_buscorerev(sb_t *sbh)
14003 +{
14004 + sb_info_t *si;
14005 + si = SB_INFO(sbh);
14006 +
14007 + return (si->sb.buscorerev);
14008 +}
14009 +
14010 +/* return list of found cores */
14011 +uint
14012 +sb_corelist(sb_t *sbh, uint coreid[])
14013 +{
14014 + sb_info_t *si;
14015 +
14016 + si = SB_INFO(sbh);
14017 +
14018 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
14019 + return (si->numcores);
14020 +}
14021 +
14022 +/* return current register mapping */
14023 +void *
14024 +sb_coreregs(sb_t *sbh)
14025 +{
14026 + sb_info_t *si;
14027 +
14028 + si = SB_INFO(sbh);
14029 + ASSERT(GOODREGS(si->curmap));
14030 +
14031 + return (si->curmap);
14032 +}
14033 +
14034 +
14035 +/* do buffered registers update */
14036 +void
14037 +sb_commit(sb_t *sbh)
14038 +{
14039 + sb_info_t *si;
14040 + uint origidx;
14041 + uint intr_val = 0;
14042 +
14043 + si = SB_INFO(sbh);
14044 +
14045 + origidx = si->curidx;
14046 + ASSERT(GOODIDX(origidx));
14047 +
14048 + INTR_OFF(si, intr_val);
14049 +
14050 + /* switch over to chipcommon core if there is one, else use pci */
14051 + if (si->sb.ccrev != NOREV) {
14052 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14053 +
14054 + /* do the buffer registers update */
14055 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
14056 + W_REG(&ccregs->broadcastdata, 0x0);
14057 + } else if (PCI(si)) {
14058 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
14059 +
14060 + /* do the buffer registers update */
14061 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
14062 + W_REG(&pciregs->bcastdata, 0x0);
14063 + } else
14064 + ASSERT(0);
14065 +
14066 + /* restore core index */
14067 + sb_setcoreidx(sbh, origidx);
14068 + INTR_RESTORE(si, intr_val);
14069 +}
14070 +
14071 +/* reset and re-enable a core */
14072 +void
14073 +sb_core_reset(sb_t *sbh, uint32 bits)
14074 +{
14075 + sb_info_t *si;
14076 + sbconfig_t *sb;
14077 + volatile uint32 dummy;
14078 +
14079 + si = SB_INFO(sbh);
14080 + ASSERT(GOODREGS(si->curmap));
14081 + sb = REGS2SB(si->curmap);
14082 +
14083 + /*
14084 + * Must do the disable sequence first to work for arbitrary current core state.
14085 + */
14086 + sb_core_disable(sbh, bits);
14087 +
14088 + /*
14089 + * Now do the initialization sequence.
14090 + */
14091 +
14092 + /* set reset while enabling the clock and forcing them on throughout the core */
14093 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
14094 + dummy = R_SBREG(si, &sb->sbtmstatelow);
14095 + OSL_DELAY(1);
14096 +
14097 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
14098 + W_SBREG(si, &sb->sbtmstatehigh, 0);
14099 + }
14100 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
14101 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
14102 + }
14103 +
14104 + /* clear reset and allow it to propagate throughout the core */
14105 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
14106 + dummy = R_SBREG(si, &sb->sbtmstatelow);
14107 + OSL_DELAY(1);
14108 +
14109 + /* leave clock enabled */
14110 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
14111 + dummy = R_SBREG(si, &sb->sbtmstatelow);
14112 + OSL_DELAY(1);
14113 +}
14114 +
14115 +void
14116 +sb_core_tofixup(sb_t *sbh)
14117 +{
14118 + sb_info_t *si;
14119 + sbconfig_t *sb;
14120 +
14121 + si = SB_INFO(sbh);
14122 +
14123 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
14124 + return;
14125 +
14126 + ASSERT(GOODREGS(si->curmap));
14127 + sb = REGS2SB(si->curmap);
14128 +
14129 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
14130 + SET_SBREG(si, &sb->sbimconfiglow,
14131 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
14132 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
14133 + } else {
14134 + if (sb_coreid(sbh) == SB_PCI) {
14135 + SET_SBREG(si, &sb->sbimconfiglow,
14136 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
14137 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
14138 + } else {
14139 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
14140 + }
14141 + }
14142 +
14143 + sb_commit(sbh);
14144 +}
14145 +
14146 +/*
14147 + * Set the initiator timeout for the "master core".
14148 + * The master core is defined to be the core in control
14149 + * of the chip and so it issues accesses to non-memory
14150 + * locations (Because of dma *any* core can access memeory).
14151 + *
14152 + * The routine uses the bus to decide who is the master:
14153 + * SB_BUS => mips
14154 + * JTAG_BUS => chipc
14155 + * PCI_BUS => pci or pcie
14156 + * PCMCIA_BUS => pcmcia
14157 + * SDIO_BUS => pcmcia
14158 + *
14159 + * This routine exists so callers can disable initiator
14160 + * timeouts so accesses to very slow devices like otp
14161 + * won't cause an abort. The routine allows arbitrary
14162 + * settings of the service and request timeouts, though.
14163 + *
14164 + * Returns the timeout state before changing it or -1
14165 + * on error.
14166 + */
14167 +
14168 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
14169 +
14170 +uint32
14171 +sb_set_initiator_to(sb_t *sbh, uint32 to)
14172 +{
14173 + sb_info_t *si;
14174 + uint origidx, idx;
14175 + uint intr_val = 0;
14176 + uint32 tmp, ret = 0xffffffff;
14177 + sbconfig_t *sb;
14178 +
14179 + si = SB_INFO(sbh);
14180 +
14181 + if ((to & ~TO_MASK) != 0)
14182 + return ret;
14183 +
14184 + /* Figure out the master core */
14185 + idx = BADIDX;
14186 + switch (BUSTYPE(si->sb.bustype)) {
14187 + case PCI_BUS:
14188 + idx = si->sb.buscoreidx;
14189 + break;
14190 + case JTAG_BUS:
14191 + idx = SB_CC_IDX;
14192 + break;
14193 + case PCMCIA_BUS:
14194 + case SDIO_BUS:
14195 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
14196 + break;
14197 + case SB_BUS:
14198 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
14199 + idx = sb_findcoreidx(si, SB_MIPS, 0);
14200 + break;
14201 + default:
14202 + ASSERT(0);
14203 + }
14204 + if (idx == BADIDX)
14205 + return ret;
14206 +
14207 + INTR_OFF(si, intr_val);
14208 + origidx = sb_coreidx(sbh);
14209 +
14210 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
14211 +
14212 + tmp = R_SBREG(si, &sb->sbimconfiglow);
14213 + ret = tmp & TO_MASK;
14214 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
14215 +
14216 + sb_commit(sbh);
14217 + sb_setcoreidx(sbh, origidx);
14218 + INTR_RESTORE(si, intr_val);
14219 + return ret;
14220 +}
14221 +
14222 +void
14223 +sb_core_disable(sb_t *sbh, uint32 bits)
14224 +{
14225 + sb_info_t *si;
14226 + volatile uint32 dummy;
14227 + uint32 rej;
14228 + sbconfig_t *sb;
14229 +
14230 + si = SB_INFO(sbh);
14231 +
14232 + ASSERT(GOODREGS(si->curmap));
14233 + sb = REGS2SB(si->curmap);
14234 +
14235 + /* if core is already in reset, just return */
14236 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
14237 + return;
14238 +
14239 + /* reject value changed between sonics 2.2 and 2.3 */
14240 + if (si->sb.sonicsrev == SONICS_2_2)
14241 + rej = (1 << SBTML_REJ_SHIFT);
14242 + else
14243 + rej = (2 << SBTML_REJ_SHIFT);
14244 +
14245 + /* if clocks are not enabled, put into reset and return */
14246 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
14247 + goto disable;
14248 +
14249 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
14250 + OR_SBREG(si, &sb->sbtmstatelow, rej);
14251 + dummy = R_SBREG(si, &sb->sbtmstatelow);
14252 + OSL_DELAY(1);
14253 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
14254 +
14255 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
14256 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
14257 + dummy = R_SBREG(si, &sb->sbimstate);
14258 + OSL_DELAY(1);
14259 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
14260 + }
14261 +
14262 + /* set reset and reject while enabling the clocks */
14263 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
14264 + dummy = R_SBREG(si, &sb->sbtmstatelow);
14265 + OSL_DELAY(10);
14266 +
14267 + /* don't forget to clear the initiator reject bit */
14268 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
14269 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
14270 +
14271 +disable:
14272 + /* leave reset and reject asserted */
14273 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
14274 + OSL_DELAY(1);
14275 +}
14276 +
14277 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
14278 +void
14279 +sb_watchdog(sb_t *sbh, uint ticks)
14280 +{
14281 + sb_info_t *si = SB_INFO(sbh);
14282 +
14283 + /* instant NMI */
14284 + switch (si->gpioid) {
14285 + case SB_CC:
14286 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
14287 + break;
14288 + case SB_EXTIF:
14289 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
14290 + break;
14291 + }
14292 +}
14293 +
14294 +/* initialize the pcmcia core */
14295 +void
14296 +sb_pcmcia_init(sb_t *sbh)
14297 +{
14298 + sb_info_t *si;
14299 + uint8 cor;
14300 +
14301 + si = SB_INFO(sbh);
14302 +
14303 + /* enable d11 mac interrupts */
14304 + if (si->sb.chip == BCM4301_DEVICE_ID) {
14305 + /* Have to use FCR2 in 4301 */
14306 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
14307 + cor |= COR_IRQEN | COR_FUNEN;
14308 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
14309 + } else {
14310 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
14311 + cor |= COR_IRQEN | COR_FUNEN;
14312 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
14313 + }
14314 +
14315 +}
14316 +
14317 +
14318 +/*
14319 + * Configure the pci core for pci client (NIC) action
14320 + * coremask is the bitvec of cores by index to be enabled.
14321 + */
14322 +void
14323 +sb_pci_setup(sb_t *sbh, uint coremask)
14324 +{
14325 + sb_info_t *si;
14326 + sbconfig_t *sb;
14327 + sbpciregs_t *pciregs;
14328 + uint32 sbflag;
14329 + uint32 w;
14330 + uint idx;
14331 + int reg_val;
14332 +
14333 + si = SB_INFO(sbh);
14334 +
14335 + /* if not pci bus, we're done */
14336 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
14337 + return;
14338 +
14339 + ASSERT(PCI(si) || PCIE(si));
14340 + ASSERT(si->sb.buscoreidx != BADIDX);
14341 +
14342 + /* get current core index */
14343 + idx = si->curidx;
14344 +
14345 + /* we interrupt on this backplane flag number */
14346 + ASSERT(GOODREGS(si->curmap));
14347 + sb = REGS2SB(si->curmap);
14348 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
14349 +
14350 + /* switch over to pci core */
14351 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
14352 + sb = REGS2SB(pciregs);
14353 +
14354 + /*
14355 + * Enable sb->pci interrupts. Assume
14356 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
14357 + */
14358 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
14359 + /* pci config write to set this core bit in PCIIntMask */
14360 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
14361 + w |= (coremask << PCI_SBIM_SHIFT);
14362 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
14363 + } else {
14364 + /* set sbintvec bit for our flag number */
14365 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
14366 + }
14367 +
14368 + if (PCI(si)) {
14369 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
14370 + if (si->sb.buscorerev >= 11)
14371 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
14372 + if (si->sb.buscorerev < 5) {
14373 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
14374 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
14375 + sb_commit(sbh);
14376 + }
14377 + }
14378 +
14379 + if (PCIE(si) && (si->sb.buscorerev == 0)) {
14380 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
14381 + reg_val |= 0x8;
14382 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
14383 +
14384 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
14385 + reg_val &= ~(0x40);
14386 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
14387 +
14388 + BCMINIT(sb_war30841)(si);
14389 + }
14390 +
14391 + /* switch back to previous core */
14392 + sb_setcoreidx(sbh, idx);
14393 +}
14394 +
14395 +uint32
14396 +sb_base(uint32 admatch)
14397 +{
14398 + uint32 base;
14399 + uint type;
14400 +
14401 + type = admatch & SBAM_TYPE_MASK;
14402 + ASSERT(type < 3);
14403 +
14404 + base = 0;
14405 +
14406 + if (type == 0) {
14407 + base = admatch & SBAM_BASE0_MASK;
14408 + } else if (type == 1) {
14409 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
14410 + base = admatch & SBAM_BASE1_MASK;
14411 + } else if (type == 2) {
14412 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
14413 + base = admatch & SBAM_BASE2_MASK;
14414 + }
14415 +
14416 + return (base);
14417 +}
14418 +
14419 +uint32
14420 +sb_size(uint32 admatch)
14421 +{
14422 + uint32 size;
14423 + uint type;
14424 +
14425 + type = admatch & SBAM_TYPE_MASK;
14426 + ASSERT(type < 3);
14427 +
14428 + size = 0;
14429 +
14430 + if (type == 0) {
14431 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
14432 + } else if (type == 1) {
14433 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
14434 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
14435 + } else if (type == 2) {
14436 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
14437 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
14438 + }
14439 +
14440 + return (size);
14441 +}
14442 +
14443 +/* return the core-type instantiation # of the current core */
14444 +uint
14445 +sb_coreunit(sb_t *sbh)
14446 +{
14447 + sb_info_t *si;
14448 + uint idx;
14449 + uint coreid;
14450 + uint coreunit;
14451 + uint i;
14452 +
14453 + si = SB_INFO(sbh);
14454 + coreunit = 0;
14455 +
14456 + idx = si->curidx;
14457 +
14458 + ASSERT(GOODREGS(si->curmap));
14459 + coreid = sb_coreid(sbh);
14460 +
14461 + /* count the cores of our type */
14462 + for (i = 0; i < idx; i++)
14463 + if (si->coreid[i] == coreid)
14464 + coreunit++;
14465 +
14466 + return (coreunit);
14467 +}
14468 +
14469 +static INLINE uint32
14470 +factor6(uint32 x)
14471 +{
14472 + switch (x) {
14473 + case CC_F6_2: return 2;
14474 + case CC_F6_3: return 3;
14475 + case CC_F6_4: return 4;
14476 + case CC_F6_5: return 5;
14477 + case CC_F6_6: return 6;
14478 + case CC_F6_7: return 7;
14479 + default: return 0;
14480 + }
14481 +}
14482 +
14483 +/* calculate the speed the SB would run at given a set of clockcontrol values */
14484 +uint32
14485 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
14486 +{
14487 + uint32 n1, n2, clock, m1, m2, m3, mc;
14488 +
14489 + n1 = n & CN_N1_MASK;
14490 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
14491 +
14492 + if (pll_type == PLL_TYPE6) {
14493 + if (m & CC_T6_MMASK)
14494 + return CC_T6_M1;
14495 + else
14496 + return CC_T6_M0;
14497 + } else if ((pll_type == PLL_TYPE1) ||
14498 + (pll_type == PLL_TYPE3) ||
14499 + (pll_type == PLL_TYPE4) ||
14500 + (pll_type == PLL_TYPE7)) {
14501 + n1 = factor6(n1);
14502 + n2 += CC_F5_BIAS;
14503 + } else if (pll_type == PLL_TYPE2) {
14504 + n1 += CC_T2_BIAS;
14505 + n2 += CC_T2_BIAS;
14506 + ASSERT((n1 >= 2) && (n1 <= 7));
14507 + ASSERT((n2 >= 5) && (n2 <= 23));
14508 + } else if (pll_type == PLL_TYPE5) {
14509 + return (100000000);
14510 + } else
14511 + ASSERT(0);
14512 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
14513 + if ((pll_type == PLL_TYPE3) ||
14514 + (pll_type == PLL_TYPE7)) {
14515 + clock = CC_CLOCK_BASE2 * n1 * n2;
14516 + }
14517 + else
14518 + clock = CC_CLOCK_BASE1 * n1 * n2;
14519 +
14520 + if (clock == 0)
14521 + return 0;
14522 +
14523 + m1 = m & CC_M1_MASK;
14524 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
14525 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
14526 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
14527 +
14528 + if ((pll_type == PLL_TYPE1) ||
14529 + (pll_type == PLL_TYPE3) ||
14530 + (pll_type == PLL_TYPE4) ||
14531 + (pll_type == PLL_TYPE7)) {
14532 + m1 = factor6(m1);
14533 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
14534 + m2 += CC_F5_BIAS;
14535 + else
14536 + m2 = factor6(m2);
14537 + m3 = factor6(m3);
14538 +
14539 + switch (mc) {
14540 + case CC_MC_BYPASS: return (clock);
14541 + case CC_MC_M1: return (clock / m1);
14542 + case CC_MC_M1M2: return (clock / (m1 * m2));
14543 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
14544 + case CC_MC_M1M3: return (clock / (m1 * m3));
14545 + default: return (0);
14546 + }
14547 + } else {
14548 + ASSERT(pll_type == PLL_TYPE2);
14549 +
14550 + m1 += CC_T2_BIAS;
14551 + m2 += CC_T2M2_BIAS;
14552 + m3 += CC_T2_BIAS;
14553 + ASSERT((m1 >= 2) && (m1 <= 7));
14554 + ASSERT((m2 >= 3) && (m2 <= 10));
14555 + ASSERT((m3 >= 2) && (m3 <= 7));
14556 +
14557 + if ((mc & CC_T2MC_M1BYP) == 0)
14558 + clock /= m1;
14559 + if ((mc & CC_T2MC_M2BYP) == 0)
14560 + clock /= m2;
14561 + if ((mc & CC_T2MC_M3BYP) == 0)
14562 + clock /= m3;
14563 +
14564 + return(clock);
14565 + }
14566 +}
14567 +
14568 +/* returns the current speed the SB is running at */
14569 +uint32
14570 +sb_clock(sb_t *sbh)
14571 +{
14572 + sb_info_t *si;
14573 + extifregs_t *eir;
14574 + chipcregs_t *cc;
14575 + uint32 n, m;
14576 + uint idx;
14577 + uint32 pll_type, rate;
14578 + uint intr_val = 0;
14579 +
14580 + si = SB_INFO(sbh);
14581 + idx = si->curidx;
14582 + pll_type = PLL_TYPE1;
14583 +
14584 + INTR_OFF(si, intr_val);
14585 +
14586 + /* switch to extif or chipc core */
14587 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
14588 + n = R_REG(&eir->clockcontrol_n);
14589 + m = R_REG(&eir->clockcontrol_sb);
14590 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
14591 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
14592 + n = R_REG(&cc->clockcontrol_n);
14593 + if (pll_type == PLL_TYPE6)
14594 + m = R_REG(&cc->clockcontrol_mips);
14595 + else if (pll_type == PLL_TYPE3)
14596 + {
14597 + // Added by Chen-I for 5365
14598 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
14599 + m = R_REG(&cc->clockcontrol_sb);
14600 + else
14601 + m = R_REG(&cc->clockcontrol_m2);
14602 + }
14603 + else
14604 + m = R_REG(&cc->clockcontrol_sb);
14605 + } else {
14606 + INTR_RESTORE(si, intr_val);
14607 + return 0;
14608 + }
14609 +
14610 + // Added by Chen-I for 5365
14611 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
14612 + {
14613 + rate = 100000000;
14614 + }
14615 + else
14616 + {
14617 + /* calculate rate */
14618 + rate = sb_clock_rate(pll_type, n, m);
14619 + if (pll_type == PLL_TYPE3)
14620 + rate = rate / 2;
14621 + }
14622 +
14623 + /* switch back to previous core */
14624 + sb_setcoreidx(sbh, idx);
14625 +
14626 + INTR_RESTORE(si, intr_val);
14627 +
14628 + return rate;
14629 +}
14630 +
14631 +/* change logical "focus" to the gpio core for optimized access */
14632 +void*
14633 +sb_gpiosetcore(sb_t *sbh)
14634 +{
14635 + sb_info_t *si;
14636 +
14637 + si = SB_INFO(sbh);
14638 +
14639 + return (sb_setcoreidx(sbh, si->gpioidx));
14640 +}
14641 +
14642 +/* mask&set gpiocontrol bits */
14643 +uint32
14644 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14645 +{
14646 + sb_info_t *si;
14647 + uint regoff;
14648 +
14649 + si = SB_INFO(sbh);
14650 + regoff = 0;
14651 +
14652 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14653 +
14654 + /* gpios could be shared on router platforms */
14655 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14656 + mask = priority ? (sb_gpioreservation & mask) :
14657 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14658 + val &= mask;
14659 + }
14660 +
14661 + switch (si->gpioid) {
14662 + case SB_CC:
14663 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
14664 + break;
14665 +
14666 + case SB_PCI:
14667 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
14668 + break;
14669 +
14670 + case SB_EXTIF:
14671 + return (0);
14672 + }
14673 +
14674 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14675 +}
14676 +
14677 +/* mask&set gpio output enable bits */
14678 +uint32
14679 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14680 +{
14681 + sb_info_t *si;
14682 + uint regoff;
14683 +
14684 + si = SB_INFO(sbh);
14685 + regoff = 0;
14686 +
14687 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14688 +
14689 + /* gpios could be shared on router platforms */
14690 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14691 + mask = priority ? (sb_gpioreservation & mask) :
14692 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14693 + val &= mask;
14694 + }
14695 +
14696 + switch (si->gpioid) {
14697 + case SB_CC:
14698 + regoff = OFFSETOF(chipcregs_t, gpioouten);
14699 + break;
14700 +
14701 + case SB_PCI:
14702 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
14703 + break;
14704 +
14705 + case SB_EXTIF:
14706 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
14707 + break;
14708 + }
14709 +
14710 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14711 +}
14712 +
14713 +/* mask&set gpio output bits */
14714 +uint32
14715 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14716 +{
14717 + sb_info_t *si;
14718 + uint regoff;
14719 +
14720 + si = SB_INFO(sbh);
14721 + regoff = 0;
14722 +
14723 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14724 +
14725 + /* gpios could be shared on router platforms */
14726 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14727 + mask = priority ? (sb_gpioreservation & mask) :
14728 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14729 + val &= mask;
14730 + }
14731 +
14732 + switch (si->gpioid) {
14733 + case SB_CC:
14734 + regoff = OFFSETOF(chipcregs_t, gpioout);
14735 + break;
14736 +
14737 + case SB_PCI:
14738 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14739 + break;
14740 +
14741 + case SB_EXTIF:
14742 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14743 + break;
14744 + }
14745 +
14746 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14747 +}
14748 +
14749 +/* reserve one gpio */
14750 +uint32
14751 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14752 +{
14753 + sb_info_t *si;
14754 +
14755 + si = SB_INFO(sbh);
14756 +
14757 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14758 +
14759 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
14760 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14761 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14762 + return -1;
14763 + }
14764 + /* make sure only one bit is set */
14765 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14766 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14767 + return -1;
14768 + }
14769 +
14770 + /* already reserved */
14771 + if (sb_gpioreservation & gpio_bitmask)
14772 + return -1;
14773 + /* set reservation */
14774 + sb_gpioreservation |= gpio_bitmask;
14775 +
14776 + return sb_gpioreservation;
14777 +}
14778 +
14779 +/* release one gpio */
14780 +/*
14781 + * releasing the gpio doesn't change the current value on the GPIO last write value
14782 + * persists till some one overwrites it
14783 +*/
14784 +
14785 +uint32
14786 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14787 +{
14788 + sb_info_t *si;
14789 +
14790 + si = SB_INFO(sbh);
14791 +
14792 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14793 +
14794 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
14795 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14796 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14797 + return -1;
14798 + }
14799 + /* make sure only one bit is set */
14800 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14801 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14802 + return -1;
14803 + }
14804 +
14805 + /* already released */
14806 + if (!(sb_gpioreservation & gpio_bitmask))
14807 + return -1;
14808 +
14809 + /* clear reservation */
14810 + sb_gpioreservation &= ~gpio_bitmask;
14811 +
14812 + return sb_gpioreservation;
14813 +}
14814 +
14815 +/* return the current gpioin register value */
14816 +uint32
14817 +sb_gpioin(sb_t *sbh)
14818 +{
14819 + sb_info_t *si;
14820 + uint regoff;
14821 +
14822 + si = SB_INFO(sbh);
14823 + regoff = 0;
14824 +
14825 + switch (si->gpioid) {
14826 + case SB_CC:
14827 + regoff = OFFSETOF(chipcregs_t, gpioin);
14828 + break;
14829 +
14830 + case SB_PCI:
14831 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14832 + break;
14833 +
14834 + case SB_EXTIF:
14835 + regoff = OFFSETOF(extifregs_t, gpioin);
14836 + break;
14837 + }
14838 +
14839 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14840 +}
14841 +
14842 +/* mask&set gpio interrupt polarity bits */
14843 +uint32
14844 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14845 +{
14846 + sb_info_t *si;
14847 + uint regoff;
14848 +
14849 + si = SB_INFO(sbh);
14850 + regoff = 0;
14851 +
14852 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14853 +
14854 + /* gpios could be shared on router platforms */
14855 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14856 + mask = priority ? (sb_gpioreservation & mask) :
14857 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14858 + val &= mask;
14859 + }
14860 +
14861 + switch (si->gpioid) {
14862 + case SB_CC:
14863 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14864 + break;
14865 +
14866 + case SB_PCI:
14867 + /* pci gpio implementation does not support interrupt polarity */
14868 + ASSERT(0);
14869 + break;
14870 +
14871 + case SB_EXTIF:
14872 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14873 + break;
14874 + }
14875 +
14876 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14877 +}
14878 +
14879 +/* mask&set gpio interrupt mask bits */
14880 +uint32
14881 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14882 +{
14883 + sb_info_t *si;
14884 + uint regoff;
14885 +
14886 + si = SB_INFO(sbh);
14887 + regoff = 0;
14888 +
14889 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14890 +
14891 + /* gpios could be shared on router platforms */
14892 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14893 + mask = priority ? (sb_gpioreservation & mask) :
14894 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14895 + val &= mask;
14896 + }
14897 +
14898 + switch (si->gpioid) {
14899 + case SB_CC:
14900 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14901 + break;
14902 +
14903 + case SB_PCI:
14904 + /* pci gpio implementation does not support interrupt mask */
14905 + ASSERT(0);
14906 + break;
14907 +
14908 + case SB_EXTIF:
14909 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14910 + break;
14911 + }
14912 +
14913 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14914 +}
14915 +
14916 +/* assign the gpio to an led */
14917 +uint32
14918 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14919 +{
14920 + sb_info_t *si;
14921 +
14922 + si = SB_INFO(sbh);
14923 + if (si->sb.ccrev < 16)
14924 + return -1;
14925 +
14926 + /* gpio led powersave reg */
14927 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14928 +}
14929 +
14930 +/* mask&set gpio timer val */
14931 +uint32
14932 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14933 +{
14934 + sb_info_t *si;
14935 + si = SB_INFO(sbh);
14936 +
14937 + if (si->sb.ccrev < 16)
14938 + return -1;
14939 +
14940 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14941 +}
14942 +
14943 +
14944 +/* return the slow clock source - LPO, XTAL, or PCI */
14945 +static uint
14946 +sb_slowclk_src(sb_info_t *si)
14947 +{
14948 + chipcregs_t *cc;
14949 +
14950 +
14951 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14952 +
14953 + if (si->sb.ccrev < 6) {
14954 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
14955 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
14956 + return (SCC_SS_PCI);
14957 + else
14958 + return (SCC_SS_XTAL);
14959 + } else if (si->sb.ccrev < 10) {
14960 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14961 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
14962 + } else /* Insta-clock */
14963 + return (SCC_SS_XTAL);
14964 +}
14965 +
14966 +/* return the ILP (slowclock) min or max frequency */
14967 +static uint
14968 +sb_slowclk_freq(sb_info_t *si, bool max)
14969 +{
14970 + chipcregs_t *cc;
14971 + uint32 slowclk;
14972 + uint div;
14973 +
14974 +
14975 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14976 +
14977 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14978 +
14979 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14980 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
14981 +
14982 + slowclk = sb_slowclk_src(si);
14983 + if (si->sb.ccrev < 6) {
14984 + if (slowclk == SCC_SS_PCI)
14985 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14986 + else
14987 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14988 + } else if (si->sb.ccrev < 10) {
14989 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14990 + if (slowclk == SCC_SS_LPO)
14991 + return (max? LPOMAXFREQ : LPOMINFREQ);
14992 + else if (slowclk == SCC_SS_XTAL)
14993 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14994 + else if (slowclk == SCC_SS_PCI)
14995 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14996 + else
14997 + ASSERT(0);
14998 + } else {
14999 + /* Chipc rev 10 is InstaClock */
15000 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
15001 + div = 4 * (div + 1);
15002 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
15003 + }
15004 + return (0);
15005 +}
15006 +
15007 +static void
15008 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
15009 +{
15010 + chipcregs_t * cc;
15011 + uint slowmaxfreq, pll_delay, slowclk;
15012 + uint pll_on_delay, fref_sel_delay;
15013 +
15014 + pll_delay = PLL_DELAY;
15015 +
15016 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
15017 + * since the xtal will also be powered down by dynamic clk control logic.
15018 + */
15019 + slowclk = sb_slowclk_src(si);
15020 + if (slowclk != SCC_SS_XTAL)
15021 + pll_delay += XTAL_ON_DELAY;
15022 +
15023 + /* Starting with 4318 it is ILP that is used for the delays */
15024 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
15025 +
15026 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
15027 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
15028 +
15029 + cc = (chipcregs_t *)chipcregs;
15030 + W_REG(&cc->pll_on_delay, pll_on_delay);
15031 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
15032 +}
15033 +
15034 +int
15035 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
15036 +{
15037 + sb_info_t *si;
15038 + uint origidx;
15039 + chipcregs_t *cc;
15040 + uint intr_val = 0;
15041 + uint err = 0;
15042 +
15043 + si = SB_INFO(sbh);
15044 +
15045 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
15046 + if (si->sb.ccrev < 6)
15047 + return 1;
15048 +
15049 + /* chipcommon cores rev10 are a whole new ball game */
15050 + if (si->sb.ccrev >= 10)
15051 + return 1;
15052 +
15053 + if (set && ((*div % 4) || (*div < 4)))
15054 + return 2;
15055 +
15056 + INTR_OFF(si, intr_val);
15057 + origidx = si->curidx;
15058 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
15059 + ASSERT(cc != NULL);
15060 +
15061 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
15062 + err = 3;
15063 + goto done;
15064 + }
15065 +
15066 + if (set) {
15067 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
15068 + sb_clkctl_setdelay(sbh, (void *)cc);
15069 + } else
15070 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
15071 +
15072 +done:
15073 + sb_setcoreidx(sbh, origidx);
15074 + INTR_RESTORE(si, intr_val);
15075 + return err;
15076 +}
15077 +
15078 +/* initialize power control delay registers */
15079 +void sb_clkctl_init(sb_t *sbh)
15080 +{
15081 + sb_info_t *si;
15082 + uint origidx;
15083 + chipcregs_t *cc;
15084 +
15085 + si = SB_INFO(sbh);
15086 +
15087 + origidx = si->curidx;
15088 +
15089 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
15090 + return;
15091 +
15092 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
15093 + goto done;
15094 +
15095 + /* 4317pc does not work with SlowClock less than 5 MHz */
15096 + if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
15097 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
15098 +
15099 + /* set all Instaclk chip ILP to 1 MHz */
15100 + else if (si->sb.ccrev >= 10)
15101 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
15102 +
15103 + sb_clkctl_setdelay(si, (void *)cc);
15104 +
15105 +done:
15106 + sb_setcoreidx(sbh, origidx);
15107 +}
15108 +void sb_pwrctl_init(sb_t *sbh)
15109 +{
15110 +sb_clkctl_init(sbh);
15111 +}
15112 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
15113 +uint16
15114 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
15115 +{
15116 + sb_info_t *si;
15117 + uint origidx;
15118 + chipcregs_t *cc;
15119 + uint slowminfreq;
15120 + uint16 fpdelay;
15121 + uint intr_val = 0;
15122 +
15123 + si = SB_INFO(sbh);
15124 + fpdelay = 0;
15125 + origidx = si->curidx;
15126 +
15127 + INTR_OFF(si, intr_val);
15128 +
15129 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
15130 + goto done;
15131 +
15132 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
15133 + goto done;
15134 +
15135 + slowminfreq = sb_slowclk_freq(si, FALSE);
15136 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
15137 +
15138 +done:
15139 + sb_setcoreidx(sbh, origidx);
15140 + INTR_RESTORE(si, intr_val);
15141 + return (fpdelay);
15142 +}
15143 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
15144 +{
15145 +return sb_clkctl_fast_pwrup_delay(sbh);
15146 +}
15147 +/* turn primary xtal and/or pll off/on */
15148 +int
15149 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
15150 +{
15151 + sb_info_t *si;
15152 + uint32 in, out, outen;
15153 +
15154 + si = SB_INFO(sbh);
15155 +
15156 + switch (BUSTYPE(si->sb.bustype)) {
15157 +
15158 +
15159 + case PCMCIA_BUS:
15160 + return (0);
15161 +
15162 +
15163 + case PCI_BUS:
15164 +
15165 + /* pcie core doesn't have any mapping to control the xtal pu */
15166 + if (PCIE(si))
15167 + return -1;
15168 +
15169 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
15170 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
15171 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
15172 +
15173 + /*
15174 + * Avoid glitching the clock if GPRS is already using it.
15175 + * We can't actually read the state of the PLLPD so we infer it
15176 + * by the value of XTAL_PU which *is* readable via gpioin.
15177 + */
15178 + if (on && (in & PCI_CFG_GPIO_XTAL))
15179 + return (0);
15180 +
15181 + if (what & XTAL)
15182 + outen |= PCI_CFG_GPIO_XTAL;
15183 + if (what & PLL)
15184 + outen |= PCI_CFG_GPIO_PLL;
15185 +
15186 + if (on) {
15187 + /* turn primary xtal on */
15188 + if (what & XTAL) {
15189 + out |= PCI_CFG_GPIO_XTAL;
15190 + if (what & PLL)
15191 + out |= PCI_CFG_GPIO_PLL;
15192 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
15193 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
15194 + OSL_DELAY(XTAL_ON_DELAY);
15195 + }
15196 +
15197 + /* turn pll on */
15198 + if (what & PLL) {
15199 + out &= ~PCI_CFG_GPIO_PLL;
15200 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
15201 + OSL_DELAY(2000);
15202 + }
15203 + } else {
15204 + if (what & XTAL)
15205 + out &= ~PCI_CFG_GPIO_XTAL;
15206 + if (what & PLL)
15207 + out |= PCI_CFG_GPIO_PLL;
15208 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
15209 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
15210 + }
15211 +
15212 + default:
15213 + return (-1);
15214 + }
15215 +
15216 + return (0);
15217 +}
15218 +
15219 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
15220 +{
15221 +return sb_clkctl_xtal(sbh,what,on);
15222 +}
15223 +
15224 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
15225 +/* returns true if ignore pll off is set and false if it is not */
15226 +bool
15227 +sb_clkctl_clk(sb_t *sbh, uint mode)
15228 +{
15229 + sb_info_t *si;
15230 + uint origidx;
15231 + chipcregs_t *cc;
15232 + uint32 scc;
15233 + bool forcefastclk=FALSE;
15234 + uint intr_val = 0;
15235 +
15236 + si = SB_INFO(sbh);
15237 +
15238 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
15239 + if (si->sb.ccrev < 6)
15240 + return (FALSE);
15241 +
15242 + /* chipcommon cores rev10 are a whole new ball game */
15243 + if (si->sb.ccrev >= 10)
15244 + return (FALSE);
15245 +
15246 + INTR_OFF(si, intr_val);
15247 +
15248 + origidx = si->curidx;
15249 +
15250 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
15251 + ASSERT(cc != NULL);
15252 +
15253 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
15254 + goto done;
15255 +
15256 + switch (mode) {
15257 + case CLK_FAST: /* force fast (pll) clock */
15258 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
15259 + sb_clkctl_xtal(&si->sb, XTAL, ON);
15260 +
15261 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
15262 + break;
15263 +
15264 + case CLK_DYNAMIC: /* enable dynamic clock control */
15265 + scc = R_REG(&cc->slow_clk_ctl);
15266 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
15267 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
15268 + scc |= SCC_XC;
15269 + W_REG(&cc->slow_clk_ctl, scc);
15270 +
15271 + /* for dynamic control, we have to release our xtal_pu "force on" */
15272 + if (scc & SCC_XC)
15273 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
15274 + break;
15275 +
15276 + default:
15277 + ASSERT(0);
15278 + }
15279 +
15280 + /* Is the h/w forcing the use of the fast clk */
15281 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
15282 +
15283 +done:
15284 + sb_setcoreidx(sbh, origidx);
15285 + INTR_RESTORE(si, intr_val);
15286 + return (forcefastclk);
15287 +}
15288 +
15289 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
15290 +{
15291 +return sb_clkctl_clk(sbh, mode);
15292 +}
15293 +/* register driver interrupt disabling and restoring callback functions */
15294 +void
15295 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
15296 +{
15297 + sb_info_t *si;
15298 +
15299 + si = SB_INFO(sbh);
15300 + si->intr_arg = intr_arg;
15301 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
15302 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
15303 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
15304 + /* save current core id. when this function called, the current core
15305 + * must be the core which provides driver functions(il, et, wl, etc.)
15306 + */
15307 + si->dev_coreid = si->coreid[si->curidx];
15308 +}
15309 +
15310 +
15311 +void
15312 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
15313 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
15314 +{
15315 + uint vendor, core, unit;
15316 + uint chip, chippkg;
15317 + char varname[8];
15318 + uint8 class, subclass, progif;
15319 +
15320 + vendor = sb_corevendor(sbh);
15321 + core = sb_coreid(sbh);
15322 + unit = sb_coreunit(sbh);
15323 +
15324 + chip = BCMINIT(sb_chip)(sbh);
15325 + chippkg = BCMINIT(sb_chippkg)(sbh);
15326 +
15327 + progif = 0;
15328 +
15329 + /* Known vendor translations */
15330 + switch (vendor) {
15331 + case SB_VEND_BCM:
15332 + vendor = VENDOR_BROADCOM;
15333 + break;
15334 + }
15335 +
15336 + /* Determine class based on known core codes */
15337 + switch (core) {
15338 + case SB_ILINE20:
15339 + class = PCI_CLASS_NET;
15340 + subclass = PCI_NET_ETHER;
15341 + core = BCM47XX_ILINE_ID;
15342 + break;
15343 + case SB_ENET:
15344 + class = PCI_CLASS_NET;
15345 + subclass = PCI_NET_ETHER;
15346 + core = BCM47XX_ENET_ID;
15347 + break;
15348 + case SB_SDRAM:
15349 + case SB_MEMC:
15350 + class = PCI_CLASS_MEMORY;
15351 + subclass = PCI_MEMORY_RAM;
15352 + break;
15353 + case SB_PCI:
15354 + case SB_PCIE:
15355 + class = PCI_CLASS_BRIDGE;
15356 + subclass = PCI_BRIDGE_PCI;
15357 + break;
15358 + case SB_MIPS:
15359 + case SB_MIPS33:
15360 + class = PCI_CLASS_CPU;
15361 + subclass = PCI_CPU_MIPS;
15362 + break;
15363 + case SB_CODEC:
15364 + class = PCI_CLASS_COMM;
15365 + subclass = PCI_COMM_MODEM;
15366 + core = BCM47XX_V90_ID;
15367 + break;
15368 + case SB_USB:
15369 + class = PCI_CLASS_SERIAL;
15370 + subclass = PCI_SERIAL_USB;
15371 + progif = 0x10; /* OHCI */
15372 + core = BCM47XX_USB_ID;
15373 + break;
15374 + case SB_USB11H:
15375 + class = PCI_CLASS_SERIAL;
15376 + subclass = PCI_SERIAL_USB;
15377 + progif = 0x10; /* OHCI */
15378 + core = BCM47XX_USBH_ID;
15379 + break;
15380 + case SB_USB11D:
15381 + class = PCI_CLASS_SERIAL;
15382 + subclass = PCI_SERIAL_USB;
15383 + core = BCM47XX_USBD_ID;
15384 + break;
15385 + case SB_IPSEC:
15386 + class = PCI_CLASS_CRYPT;
15387 + subclass = PCI_CRYPT_NETWORK;
15388 + core = BCM47XX_IPSEC_ID;
15389 + break;
15390 + case SB_ROBO:
15391 + class = PCI_CLASS_NET;
15392 + subclass = PCI_NET_OTHER;
15393 + core = BCM47XX_ROBO_ID;
15394 + break;
15395 + case SB_EXTIF:
15396 + case SB_CC:
15397 + class = PCI_CLASS_MEMORY;
15398 + subclass = PCI_MEMORY_FLASH;
15399 + break;
15400 + case SB_D11:
15401 + class = PCI_CLASS_NET;
15402 + subclass = PCI_NET_OTHER;
15403 + /* Let an nvram variable override this */
15404 + sprintf(varname, "wl%did", unit);
15405 + if ((core = getintvar(NULL, varname)) == 0) {
15406 + if (chip == BCM4712_DEVICE_ID) {
15407 + if (chippkg == BCM4712SMALL_PKG_ID)
15408 + core = BCM4306_D11G_ID;
15409 + else
15410 + core = BCM4306_D11DUAL_ID;
15411 + }
15412 + }
15413 + break;
15414 +
15415 + default:
15416 + class = subclass = progif = 0xff;
15417 + break;
15418 + }
15419 +
15420 + *pcivendor = (uint16)vendor;
15421 + *pcidevice = (uint16)core;
15422 + *pciclass = class;
15423 + *pcisubclass = subclass;
15424 + *pciprogif = progif;
15425 +}
15426 +
15427 +
15428 +
15429 +
15430 +/* use the mdio interface to write to mdio slaves */
15431 +static int
15432 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
15433 +{
15434 + uint mdiodata;
15435 + uint i = 0;
15436 + sbpcieregs_t *pcieregs;
15437 +
15438 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
15439 + ASSERT (pcieregs);
15440 +
15441 + /* enable mdio access to SERDES */
15442 + W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
15443 +
15444 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
15445 + (physmedia << MDIODATA_DEVADDR_SHF) |
15446 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
15447 +
15448 + W_REG((&pcieregs->mdiodata), mdiodata);
15449 +
15450 + PR28829_DELAY();
15451 +
15452 + /* retry till the transaction is complete */
15453 + while ( i < 10 ) {
15454 + if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
15455 + /* Disable mdio access to SERDES */
15456 + W_REG((&pcieregs->mdiocontrol), 0);
15457 + return 0;
15458 + }
15459 + OSL_DELAY(1000);
15460 + i++;
15461 + }
15462 +
15463 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
15464 + /* Disable mdio access to SERDES */
15465 + W_REG((&pcieregs->mdiocontrol), 0);
15466 + ASSERT(0);
15467 + return 1;
15468 +
15469 +}
15470 +
15471 +/* indirect way to read pcie config regs*/
15472 +uint
15473 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
15474 +{
15475 + sb_info_t *si;
15476 + sb_t *sbh;
15477 + uint retval = 0xFFFFFFFF;
15478 + sbpcieregs_t *pcieregs;
15479 + uint addrtype;
15480 +
15481 + sbh = (sb_t *)sb;
15482 + si = SB_INFO(sbh);
15483 + ASSERT (PCIE(si));
15484 +
15485 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
15486 + ASSERT (pcieregs);
15487 +
15488 + addrtype = (uint)((uintptr)arg1);
15489 + switch(addrtype) {
15490 + case PCIE_CONFIGREGS:
15491 + W_REG((&pcieregs->configaddr),offset);
15492 + retval = R_REG(&(pcieregs->configdata));
15493 + break;
15494 + case PCIE_PCIEREGS:
15495 + W_REG(&(pcieregs->pcieaddr),offset);
15496 + retval = R_REG(&(pcieregs->pciedata));
15497 + break;
15498 + default:
15499 + ASSERT(0);
15500 + break;
15501 + }
15502 + return retval;
15503 +}
15504 +
15505 +/* indirect way to write pcie config/mdio/pciecore regs*/
15506 +uint
15507 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
15508 +{
15509 + sb_info_t *si;
15510 + sbpcieregs_t *pcieregs;
15511 + uint addrtype;
15512 +
15513 + si = SB_INFO(sbh);
15514 + ASSERT (PCIE(si));
15515 +
15516 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
15517 + ASSERT (pcieregs);
15518 +
15519 + addrtype = (uint)((uintptr)arg1);
15520 +
15521 + switch(addrtype) {
15522 + case PCIE_CONFIGREGS:
15523 + W_REG((&pcieregs->configaddr),offset);
15524 + W_REG((&pcieregs->configdata),val);
15525 + break;
15526 + case PCIE_PCIEREGS:
15527 + W_REG((&pcieregs->pcieaddr),offset);
15528 + W_REG((&pcieregs->pciedata),val);
15529 + break;
15530 + default:
15531 + ASSERT(0);
15532 + break;
15533 + }
15534 + return 0;
15535 +}
15536 +
15537 +
15538 +/* Build device path. Support SB, PCI, and JTAG for now. */
15539 +int
15540 +sb_devpath(sb_t *sbh, char *path, int size)
15541 +{
15542 + ASSERT(path);
15543 + ASSERT(size >= SB_DEVPATH_BUFSZ);
15544 +
15545 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
15546 + case SB_BUS:
15547 + case JTAG_BUS:
15548 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
15549 + break;
15550 + case PCI_BUS:
15551 + ASSERT((SB_INFO(sbh))->osh);
15552 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
15553 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
15554 + break;
15555 + case PCMCIA_BUS:
15556 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
15557 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
15558 + sprintf(path, "pc/%u/%u/", 1, 1);
15559 + break;
15560 + case SDIO_BUS:
15561 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
15562 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
15563 + break;
15564 + default:
15565 + ASSERT(0);
15566 + break;
15567 + }
15568 +
15569 + return 0;
15570 +}
15571 +
15572 +/* Fix chip's configuration. The current core may be changed upon return */
15573 +static int
15574 +sb_pci_fixcfg(sb_info_t *si)
15575 +{
15576 + uint origidx, pciidx;
15577 + sbpciregs_t *pciregs;
15578 + sbpcieregs_t *pcieregs;
15579 + uint16 val16, *reg16;
15580 + char name[SB_DEVPATH_BUFSZ+16], *value;
15581 + char devpath[SB_DEVPATH_BUFSZ];
15582 +
15583 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
15584 +
15585 + /* Fix PCI(e) SROM shadow area */
15586 + /* save the current index */
15587 + origidx = sb_coreidx(&si->sb);
15588 +
15589 + /* check 'pi' is correct and fix it if not */
15590 + if (si->sb.buscoretype == SB_PCIE) {
15591 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
15592 + ASSERT(pcieregs);
15593 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
15594 + }
15595 + else if (si->sb.buscoretype == SB_PCI) {
15596 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
15597 + ASSERT(pciregs);
15598 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
15599 + }
15600 + else {
15601 + ASSERT(0);
15602 + return -1;
15603 + }
15604 + pciidx = sb_coreidx(&si->sb);
15605 + val16 = R_REG(reg16);
15606 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
15607 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
15608 + W_REG(reg16, val16);
15609 + }
15610 +
15611 + /* restore the original index */
15612 + sb_setcoreidx(&si->sb, origidx);
15613 +
15614 + /* Fix bar0window */
15615 + /* !do it last, it changes the current core! */
15616 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
15617 + return -1;
15618 + sprintf(name, "%sb0w", devpath);
15619 + if ((value = getvar(NULL, name))) {
15620 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
15621 + bcm_strtoul(value, NULL, 16));
15622 + /* update curidx since the current core is changed */
15623 + si->curidx = _sb_coreidx(si);
15624 + if (si->curidx == BADIDX) {
15625 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
15626 + return -1;
15627 + }
15628 + }
15629 +
15630 + return 0;
15631 +}
15632 +
15633 diff -Naur linux.old/drivers/net/hnd/shared_ksyms.sh linux.dev/drivers/net/hnd/shared_ksyms.sh
15634 --- linux.old/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
15635 +++ linux.dev/drivers/net/hnd/shared_ksyms.sh 2006-04-06 15:34:15.000000000 +0200
15636 @@ -0,0 +1,21 @@
15637 +#!/bin/sh
15638 +#
15639 +# Copyright 2004, Broadcom Corporation
15640 +# All Rights Reserved.
15641 +#
15642 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15643 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15644 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15645 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15646 +#
15647 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
15648 +#
15649 +
15650 +cat <<EOF
15651 +#include <linux/config.h>
15652 +#include <linux/module.h>
15653 +EOF
15654 +
15655 +for file in $* ; do
15656 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
15657 +done
15658 diff -Naur linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
15659 --- linux.old/drivers/net/wireless/Config.in 2006-04-06 15:38:09.000000000 +0200
15660 +++ linux.dev/drivers/net/wireless/Config.in 2006-04-06 17:04:48.000000000 +0200
15661 @@ -13,6 +13,8 @@
15662 fi
15663
15664 if [ "$CONFIG_PCI" = "y" ]; then
15665 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support (old)' CONFIG_WL
15666 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support (new)' CONFIG_WL2
15667 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
15668 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
15669 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
15670 diff -Naur linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
15671 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
15672 +++ linux.dev/drivers/net/wl/Makefile 2006-04-06 16:56:38.000000000 +0200
15673 @@ -0,0 +1,27 @@
15674 +#
15675 +# Makefile for the Broadcom wl driver
15676 +#
15677 +# Copyright 2004, Broadcom Corporation
15678 +# All Rights Reserved.
15679 +#
15680 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15681 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15682 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15683 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15684 +#
15685 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
15686 +
15687 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
15688 +
15689 +O_TARGET := wl.o
15690 +
15691 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
15692 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
15693 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
15694 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
15695 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
15696 +obj-y += compat.o hnddma.o
15697 +
15698 +obj-m := $(O_TARGET)
15699 +
15700 +include $(TOPDIR)/Rules.make
15701 diff -Naur linux.old/drivers/net/wl/compat.c linux.dev/drivers/net/wl/compat.c
15702 --- linux.old/drivers/net/wl/compat.c 1970-01-01 01:00:00.000000000 +0100
15703 +++ linux.dev/drivers/net/wl/compat.c 2006-04-06 17:12:19.000000000 +0200
15704 @@ -0,0 +1,237 @@
15705 +/*
15706 + * Misc useful OS-independent routines.
15707 + *
15708 + * Copyright 2005, Broadcom Corporation
15709 + * All Rights Reserved.
15710 + *
15711 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15712 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15713 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15714 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15715 + * $Id$
15716 + */
15717 +
15718 +#include <typedefs.h>
15719 +#ifdef BCMDRIVER
15720 +#include <osl.h>
15721 +#include <sbutils.h>
15722 +#include <bcmnvram.h>
15723 +#else
15724 +#include <stdio.h>
15725 +#include <string.h>
15726 +#endif
15727 +#include "pktq.h"
15728 +#include <bcmutils.h>
15729 +#include <bcmendian.h>
15730 +#include <bcmdevs.h>
15731 +
15732 +#ifdef BCMDRIVER
15733 +/* copy a pkt buffer chain into a buffer */
15734 +uint
15735 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
15736 +{
15737 + uint n, ret = 0;
15738 +
15739 + if (len < 0)
15740 + len = 4096; /* "infinite" */
15741 +
15742 + /* skip 'offset' bytes */
15743 + for (; p && offset; p = PKTNEXT(osh, p)) {
15744 + if (offset < (uint)PKTLEN(osh, p))
15745 + break;
15746 + offset -= PKTLEN(osh, p);
15747 + }
15748 +
15749 + if (!p)
15750 + return 0;
15751 +
15752 + /* copy the data */
15753 + for (; p && len; p = PKTNEXT(osh, p)) {
15754 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
15755 + bcopy(PKTDATA(osh, p) + offset, buf, n);
15756 + buf += n;
15757 + len -= n;
15758 + ret += n;
15759 + offset = 0;
15760 + }
15761 +
15762 + return ret;
15763 +}
15764 +
15765 +/* return total length of buffer chain */
15766 +uint
15767 +pkttotlen(osl_t *osh, void *p)
15768 +{
15769 + uint total;
15770 +
15771 + total = 0;
15772 + for (; p; p = PKTNEXT(osh, p))
15773 + total += PKTLEN(osh, p);
15774 + return (total);
15775 +}
15776 +
15777 +void
15778 +pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
15779 +{
15780 + q->head = q->tail = NULL;
15781 + q->maxlen = maxlen;
15782 + q->len = 0;
15783 + if (prio_map) {
15784 + q->priority = TRUE;
15785 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
15786 + }
15787 + else
15788 + q->priority = FALSE;
15789 +}
15790 +
15791 +
15792 +/* should always check pktq_full before calling pktenq */
15793 +void
15794 +pktenq(struct pktq *q, void *p, bool lifo)
15795 +{
15796 + void *next, *prev;
15797 +
15798 + /* allow 10 pkts slack */
15799 + ASSERT(q->len < (q->maxlen + 10));
15800 +
15801 + /* Queueing chains not allowed */
15802 + ASSERT(PKTLINK(p) == NULL);
15803 +
15804 + /* Queue is empty */
15805 + if (q->tail == NULL) {
15806 + ASSERT(q->head == NULL);
15807 + q->head = q->tail = p;
15808 + }
15809 +
15810 + /* Insert at head or tail */
15811 + else if (q->priority == FALSE) {
15812 + /* Insert at head (LIFO) */
15813 + if (lifo) {
15814 + PKTSETLINK(p, q->head);
15815 + q->head = p;
15816 + }
15817 + /* Insert at tail (FIFO) */
15818 + else {
15819 + ASSERT(PKTLINK(q->tail) == NULL);
15820 + PKTSETLINK(q->tail, p);
15821 + PKTSETLINK(p, NULL);
15822 + q->tail = p;
15823 + }
15824 + }
15825 +
15826 + /* Insert by priority */
15827 + else {
15828 + /* legal priorities 0-7 */
15829 + ASSERT(PKTPRIO(p) <= MAXPRIO);
15830 +
15831 + ASSERT(q->head);
15832 + ASSERT(q->tail);
15833 + /* Shortcut to insertion at tail */
15834 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
15835 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
15836 + prev = q->tail;
15837 + next = NULL;
15838 + }
15839 + /* Insert at head or in the middle */
15840 + else {
15841 + prev = NULL;
15842 + next = q->head;
15843 + }
15844 + /* Walk the queue */
15845 + for (; next; prev = next, next = PKTLINK(next)) {
15846 + /* Priority queue invariant */
15847 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
15848 + /* Insert at head of string of packets of same priority (LIFO) */
15849 + if (lifo) {
15850 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
15851 + break;
15852 + }
15853 + /* Insert at tail of string of packets of same priority (FIFO) */
15854 + else {
15855 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
15856 + break;
15857 + }
15858 + }
15859 + /* Insert at tail */
15860 + if (next == NULL) {
15861 + ASSERT(PKTLINK(q->tail) == NULL);
15862 + PKTSETLINK(q->tail, p);
15863 + PKTSETLINK(p, NULL);
15864 + q->tail = p;
15865 + }
15866 + /* Insert in the middle */
15867 + else if (prev) {
15868 + PKTSETLINK(prev, p);
15869 + PKTSETLINK(p, next);
15870 + }
15871 + /* Insert at head */
15872 + else {
15873 + PKTSETLINK(p, q->head);
15874 + q->head = p;
15875 + }
15876 + }
15877 +
15878 + /* List invariants after insertion */
15879 + ASSERT(q->head);
15880 + ASSERT(PKTLINK(q->tail) == NULL);
15881 +
15882 + q->len++;
15883 +}
15884 +
15885 +/* dequeue packet at head */
15886 +void*
15887 +pktdeq(struct pktq *q)
15888 +{
15889 + void *p;
15890 +
15891 + if ((p = q->head)) {
15892 + ASSERT(q->tail);
15893 + q->head = PKTLINK(p);
15894 + PKTSETLINK(p, NULL);
15895 + q->len--;
15896 + if (q->head == NULL)
15897 + q->tail = NULL;
15898 + }
15899 + else {
15900 + ASSERT(q->tail == NULL);
15901 + }
15902 +
15903 + return (p);
15904 +}
15905 +
15906 +/* dequeue packet at tail */
15907 +void*
15908 +pktdeqtail(struct pktq *q)
15909 +{
15910 + void *p;
15911 + void *next, *prev;
15912 +
15913 + if (q->head == q->tail) { /* last packet on queue or queue empty */
15914 + p = q->head;
15915 + q->head = q->tail = NULL;
15916 + q->len = 0;
15917 + return(p);
15918 + }
15919 +
15920 + /* start walk at head */
15921 + prev = NULL;
15922 + next = q->head;
15923 +
15924 + /* Walk the queue to find prev of q->tail */
15925 + for (; next; prev = next, next = PKTLINK(next)) {
15926 + if (next == q->tail)
15927 + break;
15928 + }
15929 +
15930 + ASSERT(prev);
15931 +
15932 + PKTSETLINK(prev, NULL);
15933 + q->tail = prev;
15934 + q->len--;
15935 + p = next;
15936 +
15937 + return (p);
15938 +}
15939 +#endif
15940 +
15941 +
15942 diff -Naur linux.old/drivers/net/wl/hnddma.c linux.dev/drivers/net/wl/hnddma.c
15943 --- linux.old/drivers/net/wl/hnddma.c 1970-01-01 01:00:00.000000000 +0100
15944 +++ linux.dev/drivers/net/wl/hnddma.c 2006-04-06 16:58:24.000000000 +0200
15945 @@ -0,0 +1,1453 @@
15946 +/*
15947 + * Generic Broadcom Home Networking Division (HND) DMA module.
15948 + * This supports the following chips: BCM42xx, 44xx, 47xx .
15949 + *
15950 + * Copyright 2005, Broadcom Corporation
15951 + * All Rights Reserved.
15952 + *
15953 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15954 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15955 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15956 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15957 + *
15958 + * $Id$
15959 + */
15960 +
15961 +#include <typedefs.h>
15962 +#include <osl.h>
15963 +#include <bcmendian.h>
15964 +#include <sbconfig.h>
15965 +#include <bcmutils.h>
15966 +#include <bcmdevs.h>
15967 +#include <sbutils.h>
15968 +
15969 +struct dma_info; /* forward declaration */
15970 +#define di_t struct dma_info
15971 +
15972 +#include "sbhnddma.h"
15973 +#include "hnddma.h"
15974 +
15975 +/* debug/trace */
15976 +#define DMA_ERROR(args)
15977 +#define DMA_TRACE(args)
15978 +
15979 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
15980 +static uint dma_msg_level =
15981 + 0;
15982 +
15983 +#define MAXNAMEL 8
15984 +
15985 +/* dma engine software state */
15986 +typedef struct dma_info {
15987 + hnddma_t hnddma; /* exported structure */
15988 + uint *msg_level; /* message level pointer */
15989 + char name[MAXNAMEL]; /* callers name for diag msgs */
15990 +
15991 + void *osh; /* os handle */
15992 + sb_t *sbh; /* sb handle */
15993 +
15994 + bool dma64; /* dma64 enabled */
15995 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
15996 +
15997 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
15998 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
15999 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
16000 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
16001 +
16002 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
16003 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
16004 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
16005 + uint ntxd; /* # tx descriptors tunable */
16006 + uint txin; /* index of next descriptor to reclaim */
16007 + uint txout; /* index of next descriptor to post */
16008 + uint txavail; /* # free tx descriptors */
16009 + void **txp; /* pointer to parallel array of pointers to packets */
16010 + ulong txdpa; /* physical address of descriptor ring */
16011 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
16012 + uint txdalloc; /* #bytes allocated for the ring */
16013 +
16014 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
16015 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
16016 + uint nrxd; /* # rx descriptors tunable */
16017 + uint rxin; /* index of next descriptor to reclaim */
16018 + uint rxout; /* index of next descriptor to post */
16019 + void **rxp; /* pointer to parallel array of pointers to packets */
16020 + ulong rxdpa; /* physical address of descriptor ring */
16021 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
16022 + uint rxdalloc; /* #bytes allocated for the ring */
16023 +
16024 + /* tunables */
16025 + uint rxbufsize; /* rx buffer size in bytes */
16026 + uint nrxpost; /* # rx buffers to keep posted */
16027 + uint rxoffset; /* rxcontrol offset */
16028 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
16029 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
16030 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
16031 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
16032 +} dma_info_t;
16033 +
16034 +#ifdef BCMDMA64
16035 +#define DMA64_ENAB(di) ((di)->dma64)
16036 +#else
16037 +#define DMA64_ENAB(di) (0)
16038 +#endif
16039 +
16040 +/* descriptor bumping macros */
16041 +#define XXD(x, n) ((x) & ((n) - 1))
16042 +#define TXD(x) XXD((x), di->ntxd)
16043 +#define RXD(x) XXD((x), di->nrxd)
16044 +#define NEXTTXD(i) TXD(i + 1)
16045 +#define PREVTXD(i) TXD(i - 1)
16046 +#define NEXTRXD(i) RXD(i + 1)
16047 +#define NTXDACTIVE(h, t) TXD(t - h)
16048 +#define NRXDACTIVE(h, t) RXD(t - h)
16049 +
16050 +/* macros to convert between byte offsets and indexes */
16051 +#define B2I(bytes, type) ((bytes) / sizeof(type))
16052 +#define I2B(index, type) ((index) * sizeof(type))
16053 +
16054 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
16055 +#define PCI32ADDR_HIGH_SHIFT 30
16056 +
16057 +
16058 +/* prototypes */
16059 +static bool dma_isaddrext(dma_info_t *di);
16060 +static bool dma_alloc(dma_info_t *di, uint direction);
16061 +
16062 +static bool dma32_alloc(dma_info_t *di, uint direction);
16063 +static void dma32_txreset(dma_info_t *di);
16064 +static void dma32_rxreset(dma_info_t *di);
16065 +static bool dma32_txsuspendedidle(dma_info_t *di);
16066 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16067 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
16068 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
16069 +static void dma32_txrotate(di_t *di);
16070 +
16071 +/* prototype or stubs */
16072 +#ifdef BCMDMA64
16073 +static bool dma64_alloc(dma_info_t *di, uint direction);
16074 +static void dma64_txreset(dma_info_t *di);
16075 +static void dma64_rxreset(dma_info_t *di);
16076 +static bool dma64_txsuspendedidle(dma_info_t *di);
16077 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16078 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
16079 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
16080 +static void dma64_txrotate(di_t *di);
16081 +#else
16082 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
16083 +static void dma64_txreset(dma_info_t *di) {}
16084 +static void dma64_rxreset(dma_info_t *di) {}
16085 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
16086 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
16087 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
16088 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
16089 +static void dma64_txrotate(di_t *di) { return; }
16090 +#endif
16091 +
16092 +/* old dmaregs struct for compatibility */
16093 +typedef volatile struct {
16094 + /* transmit channel */
16095 + uint32 xmtcontrol; /* enable, et al */
16096 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
16097 + uint32 xmtptr; /* last descriptor posted to chip */
16098 + uint32 xmtstatus; /* current active descriptor, et al */
16099 +
16100 + /* receive channel */
16101 + uint32 rcvcontrol; /* enable, et al */
16102 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
16103 + uint32 rcvptr; /* last descriptor posted to chip */
16104 + uint32 rcvstatus; /* current active descriptor, et al */
16105 +} dmaregs_t;
16106 +
16107 +void*
16108 +dma_attach(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
16109 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
16110 +{
16111 + dma_info_t *di;
16112 + uint size;
16113 + dma32regs_t *dmaregstx = regs;
16114 + dma32regs_t *dmaregsrx = dmaregstx + 1;
16115 +
16116 + /* allocate private info structure */
16117 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
16118 + return (NULL);
16119 + }
16120 + bzero((char*)di, sizeof (dma_info_t));
16121 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
16122 +
16123 + /* check arguments */
16124 + ASSERT(ISPOWEROF2(ntxd));
16125 + ASSERT(ISPOWEROF2(nrxd));
16126 + if (nrxd == 0)
16127 + ASSERT(dmaregsrx == NULL);
16128 + if (ntxd == 0)
16129 + ASSERT(dmaregstx == NULL);
16130 +
16131 + ASSERT(ntxd <= D32MAXDD);
16132 + ASSERT(nrxd <= D32MAXDD);
16133 + di->d32txregs = (dma32regs_t *)dmaregstx;
16134 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
16135 +
16136 + /* make a private copy of our callers name */
16137 + strncpy(di->name, name, MAXNAMEL);
16138 + di->name[MAXNAMEL-1] = '\0';
16139 +
16140 + di->osh = osh;
16141 + di->sbh = NULL;
16142 +
16143 + /* save tunables */
16144 + di->ntxd = ntxd;
16145 + di->nrxd = nrxd;
16146 + di->rxbufsize = rxbufsize;
16147 + di->nrxpost = nrxpost;
16148 + di->rxoffset = rxoffset;
16149 +
16150 + di->ddoffsetlow = ddoffset;
16151 + di->dataoffsetlow = dataoffset;
16152 + di->ddoffsethigh = 0;
16153 + di->dataoffsethigh = 0;
16154 +
16155 + di->addrext = 0;
16156 +
16157 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
16158 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
16159 +
16160 + /* allocate tx packet pointer vector */
16161 + if (ntxd) {
16162 + size = ntxd * sizeof (void*);
16163 + if ((di->txp = MALLOC(osh, size)) == NULL) {
16164 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
16165 + goto fail;
16166 + }
16167 + bzero((char*)di->txp, size);
16168 + }
16169 +
16170 + /* allocate rx packet pointer vector */
16171 + if (nrxd) {
16172 + size = nrxd * sizeof (void*);
16173 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
16174 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
16175 + goto fail;
16176 + }
16177 + bzero((char*)di->rxp, size);
16178 + }
16179 +
16180 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
16181 + if (ntxd) {
16182 + if (!dma_alloc(di, DMA_TX))
16183 + goto fail;
16184 + }
16185 +
16186 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
16187 + if (nrxd) {
16188 + if (!dma_alloc(di, DMA_RX))
16189 + goto fail;
16190 + }
16191 +
16192 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
16193 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
16194 + goto fail;
16195 + }
16196 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
16197 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
16198 + goto fail;
16199 + }
16200 +
16201 + return ((void*)di);
16202 +
16203 +fail:
16204 + dma_detach((void*)di);
16205 + return (NULL);
16206 +}
16207 +
16208 +
16209 +static bool
16210 +dma_alloc(dma_info_t *di, uint direction)
16211 +{
16212 + if (DMA64_ENAB(di)) {
16213 + return dma64_alloc(di, direction);
16214 + } else {
16215 + return dma32_alloc(di, direction);
16216 + }
16217 +}
16218 +
16219 +/* may be called with core in reset */
16220 +void
16221 +dma_detach(dma_info_t *di)
16222 +{
16223 + if (di == NULL)
16224 + return;
16225 +
16226 + DMA_TRACE(("%s: dma_detach\n", di->name));
16227 +
16228 + /* shouldn't be here if descriptors are unreclaimed */
16229 + ASSERT(di->txin == di->txout);
16230 + ASSERT(di->rxin == di->rxout);
16231 +
16232 + /* free dma descriptor rings */
16233 + if (di->txd32)
16234 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
16235 + if (di->rxd32)
16236 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
16237 +
16238 + /* free packet pointer vectors */
16239 + if (di->txp)
16240 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
16241 + if (di->rxp)
16242 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
16243 +
16244 + /* free our private info structure */
16245 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
16246 +}
16247 +
16248 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
16249 +static bool
16250 +dma_isaddrext(dma_info_t *di)
16251 +{
16252 + uint32 w;
16253 +
16254 + if (DMA64_ENAB(di)) {
16255 + OR_REG(&di->d64txregs->control, D64_XC_AE);
16256 + w = R_REG(&di->d32txregs->control);
16257 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
16258 + return ((w & XC_AE) == D64_XC_AE);
16259 + } else {
16260 + OR_REG(&di->d32txregs->control, XC_AE);
16261 + w = R_REG(&di->d32txregs->control);
16262 + AND_REG(&di->d32txregs->control, ~XC_AE);
16263 + return ((w & XC_AE) == XC_AE);
16264 + }
16265 +}
16266 +
16267 +void
16268 +dma_txreset(dma_info_t *di)
16269 +{
16270 + DMA_TRACE(("%s: dma_txreset\n", di->name));
16271 +
16272 + if (DMA64_ENAB(di))
16273 + dma64_txreset(di);
16274 + else
16275 + dma32_txreset(di);
16276 +}
16277 +
16278 +void
16279 +dma_rxreset(dma_info_t *di)
16280 +{
16281 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
16282 +
16283 + if (DMA64_ENAB(di))
16284 + dma64_rxreset(di);
16285 + else
16286 + dma32_rxreset(di);
16287 +}
16288 +
16289 +/* initialize descriptor table base address */
16290 +static void
16291 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
16292 +{
16293 + if (DMA64_ENAB(di)) {
16294 + if (direction == DMA_TX) {
16295 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
16296 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
16297 + } else {
16298 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
16299 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
16300 + }
16301 + } else {
16302 + uint32 offset = di->ddoffsetlow;
16303 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
16304 + if (direction == DMA_TX)
16305 + W_REG(&di->d32txregs->addr, (pa + offset));
16306 + else
16307 + W_REG(&di->d32rxregs->addr, (pa + offset));
16308 + } else {
16309 + /* dma32 address extension */
16310 + uint32 ae;
16311 + ASSERT(di->addrext);
16312 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
16313 +
16314 + if (direction == DMA_TX) {
16315 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
16316 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
16317 + } else {
16318 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
16319 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
16320 + }
16321 + }
16322 + }
16323 +}
16324 +
16325 +/* init the tx or rx descriptor */
16326 +static INLINE void
16327 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
16328 +{
16329 + uint offset = di->dataoffsetlow;
16330 +
16331 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
16332 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
16333 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
16334 + } else {
16335 + /* address extension */
16336 + uint32 ae;
16337 + ASSERT(di->addrext);
16338 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
16339 +
16340 + *ctrl |= (ae << CTRL_AE_SHIFT);
16341 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
16342 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
16343 + }
16344 +}
16345 +
16346 +/* init the tx or rx descriptor */
16347 +static INLINE void
16348 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
16349 +{
16350 + uint32 bufaddr_low = pa + di->dataoffsetlow;
16351 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
16352 +
16353 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
16354 +
16355 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
16356 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
16357 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
16358 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
16359 +}
16360 +
16361 +void
16362 +dma_txinit(dma_info_t *di)
16363 +{
16364 + DMA_TRACE(("%s: dma_txinit\n", di->name));
16365 +
16366 + di->txin = di->txout = 0;
16367 + di->txavail = di->ntxd - 1;
16368 +
16369 + /* clear tx descriptor ring */
16370 + if (DMA64_ENAB(di)) {
16371 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
16372 + W_REG(&di->d64txregs->control, XC_XE);
16373 + dma_ddtable_init(di, DMA_TX, di->txdpa);
16374 + } else {
16375 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
16376 + W_REG(&di->d32txregs->control, XC_XE);
16377 + dma_ddtable_init(di, DMA_TX, di->txdpa);
16378 + }
16379 +}
16380 +
16381 +bool
16382 +dma_txenabled(dma_info_t *di)
16383 +{
16384 + uint32 xc;
16385 +
16386 + /* If the chip is dead, it is not enabled :-) */
16387 + if (DMA64_ENAB(di)) {
16388 + xc = R_REG(&di->d64txregs->control);
16389 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
16390 + } else {
16391 + xc = R_REG(&di->d32txregs->control);
16392 + return ((xc != 0xffffffff) && (xc & XC_XE));
16393 + }
16394 +}
16395 +
16396 +void
16397 +dma_txsuspend(dma_info_t *di)
16398 +{
16399 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
16400 + if (DMA64_ENAB(di))
16401 + OR_REG(&di->d64txregs->control, D64_XC_SE);
16402 + else
16403 + OR_REG(&di->d32txregs->control, XC_SE);
16404 +}
16405 +
16406 +void
16407 +dma_txresume(dma_info_t *di)
16408 +{
16409 + DMA_TRACE(("%s: dma_txresume\n", di->name));
16410 + if (DMA64_ENAB(di))
16411 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
16412 + else
16413 + AND_REG(&di->d32txregs->control, ~XC_SE);
16414 +}
16415 +
16416 +bool
16417 +dma_txsuspendedidle(dma_info_t *di)
16418 +{
16419 + if (DMA64_ENAB(di))
16420 + return dma64_txsuspendedidle(di);
16421 + else
16422 + return dma32_txsuspendedidle(di);
16423 +}
16424 +
16425 +bool
16426 +dma_txsuspended(dma_info_t *di)
16427 +{
16428 + if (DMA64_ENAB(di))
16429 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
16430 + else
16431 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
16432 +}
16433 +
16434 +bool
16435 +dma_txstopped(dma_info_t *di)
16436 +{
16437 + if (DMA64_ENAB(di))
16438 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
16439 + else
16440 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
16441 +}
16442 +
16443 +bool
16444 +dma_rxstopped(dma_info_t *di)
16445 +{
16446 + if (DMA64_ENAB(di))
16447 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
16448 + else
16449 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
16450 +}
16451 +
16452 +void
16453 +dma_fifoloopbackenable(dma_info_t *di)
16454 +{
16455 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
16456 + if (DMA64_ENAB(di))
16457 + OR_REG(&di->d64txregs->control, D64_XC_LE);
16458 + else
16459 + OR_REG(&di->d32txregs->control, XC_LE);
16460 +}
16461 +
16462 +void
16463 +dma_rxinit(dma_info_t *di)
16464 +{
16465 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
16466 +
16467 + di->rxin = di->rxout = 0;
16468 +
16469 + /* clear rx descriptor ring */
16470 + if (DMA64_ENAB(di)) {
16471 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
16472 + dma_rxenable(di);
16473 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
16474 + } else {
16475 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
16476 + dma_rxenable(di);
16477 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
16478 + }
16479 +}
16480 +
16481 +void
16482 +dma_rxenable(dma_info_t *di)
16483 +{
16484 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
16485 + if (DMA64_ENAB(di))
16486 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
16487 + else
16488 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
16489 +}
16490 +
16491 +bool
16492 +dma_rxenabled(dma_info_t *di)
16493 +{
16494 + uint32 rc;
16495 +
16496 + if (DMA64_ENAB(di)) {
16497 + rc = R_REG(&di->d64rxregs->control);
16498 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
16499 + } else {
16500 + rc = R_REG(&di->d32rxregs->control);
16501 + return ((rc != 0xffffffff) && (rc & RC_RE));
16502 + }
16503 +}
16504 +
16505 +
16506 +/* !! tx entry routine */
16507 +int
16508 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
16509 +{
16510 + if (DMA64_ENAB(di)) {
16511 + return dma64_txfast(di, p0, coreflags);
16512 + } else {
16513 + return dma32_txfast(di, p0, coreflags);
16514 + }
16515 +}
16516 +
16517 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
16518 +void*
16519 +dma_rx(dma_info_t *di)
16520 +{
16521 + void *p;
16522 + uint len;
16523 + int skiplen = 0;
16524 +
16525 + while ((p = dma_getnextrxp(di, FALSE))) {
16526 + /* skip giant packets which span multiple rx descriptors */
16527 + if (skiplen > 0) {
16528 + skiplen -= di->rxbufsize;
16529 + if (skiplen < 0)
16530 + skiplen = 0;
16531 + PKTFREE(di->osh, p, FALSE);
16532 + continue;
16533 + }
16534 +
16535 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
16536 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
16537 +
16538 + /* bad frame length check */
16539 + if (len > (di->rxbufsize - di->rxoffset)) {
16540 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
16541 + if (len > 0)
16542 + skiplen = len - (di->rxbufsize - di->rxoffset);
16543 + PKTFREE(di->osh, p, FALSE);
16544 + di->hnddma.rxgiants++;
16545 + continue;
16546 + }
16547 +
16548 + /* set actual length */
16549 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
16550 +
16551 + break;
16552 + }
16553 +
16554 + return (p);
16555 +}
16556 +
16557 +/* post receive buffers */
16558 +void
16559 +dma_rxfill(dma_info_t *di)
16560 +{
16561 + void *p;
16562 + uint rxin, rxout;
16563 + uint32 ctrl;
16564 + uint n;
16565 + uint i;
16566 + uint32 pa;
16567 + uint rxbufsize;
16568 +
16569 + /*
16570 + * Determine how many receive buffers we're lacking
16571 + * from the full complement, allocate, initialize,
16572 + * and post them, then update the chip rx lastdscr.
16573 + */
16574 +
16575 + rxin = di->rxin;
16576 + rxout = di->rxout;
16577 + rxbufsize = di->rxbufsize;
16578 +
16579 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
16580 +
16581 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
16582 +
16583 + for (i = 0; i < n; i++) {
16584 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
16585 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
16586 + di->hnddma.rxnobuf++;
16587 + break;
16588 + }
16589 +
16590 + /* Do a cached write instead of uncached write since DMA_MAP
16591 + * will flush the cache. */
16592 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
16593 +
16594 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
16595 + ASSERT(ISALIGNED(pa, 4));
16596 +
16597 + /* save the free packet pointer */
16598 + ASSERT(di->rxp[rxout] == NULL);
16599 + di->rxp[rxout] = p;
16600 +
16601 + if (DMA64_ENAB(di)) {
16602 + /* prep the descriptor control value */
16603 + if (rxout == (di->nrxd - 1))
16604 + ctrl = CTRL_EOT;
16605 +
16606 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
16607 + } else {
16608 + /* prep the descriptor control value */
16609 + ctrl = rxbufsize;
16610 + if (rxout == (di->nrxd - 1))
16611 + ctrl |= CTRL_EOT;
16612 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
16613 + }
16614 +
16615 + rxout = NEXTRXD(rxout);
16616 + }
16617 +
16618 + di->rxout = rxout;
16619 +
16620 + /* update the chip lastdscr pointer */
16621 + if (DMA64_ENAB(di)) {
16622 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
16623 + } else {
16624 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
16625 + }
16626 +}
16627 +
16628 +void
16629 +dma_txreclaim(dma_info_t *di, bool forceall)
16630 +{
16631 + void *p;
16632 +
16633 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
16634 +
16635 + while ((p = dma_getnexttxp(di, forceall)))
16636 + PKTFREE(di->osh, p, TRUE);
16637 +}
16638 +
16639 +/*
16640 + * Reclaim next completed txd (txds if using chained buffers) and
16641 + * return associated packet.
16642 + * If 'force' is true, reclaim txd(s) and return associated packet
16643 + * regardless of the value of the hardware "curr" pointer.
16644 + */
16645 +void*
16646 +dma_getnexttxp(dma_info_t *di, bool forceall)
16647 +{
16648 + if (DMA64_ENAB(di)) {
16649 + return dma64_getnexttxp(di, forceall);
16650 + } else {
16651 + return dma32_getnexttxp(di, forceall);
16652 + }
16653 +}
16654 +
16655 +/* like getnexttxp but no reclaim */
16656 +void*
16657 +dma_peeknexttxp(dma_info_t *di)
16658 +{
16659 + uint end, i;
16660 +
16661 + if (DMA64_ENAB(di)) {
16662 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
16663 + } else {
16664 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
16665 + }
16666 +
16667 + for (i = di->txin; i != end; i = NEXTTXD(i))
16668 + if (di->txp[i])
16669 + return (di->txp[i]);
16670 +
16671 + return (NULL);
16672 +}
16673 +
16674 +/*
16675 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
16676 + */
16677 +void
16678 +dma_txrotate(di_t *di)
16679 +{
16680 + if (DMA64_ENAB(di)) {
16681 + dma64_txrotate(di);
16682 + } else {
16683 + dma32_txrotate(di);
16684 + }
16685 +}
16686 +
16687 +void
16688 +dma_rxreclaim(dma_info_t *di)
16689 +{
16690 + void *p;
16691 +
16692 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
16693 +
16694 + while ((p = dma_getnextrxp(di, TRUE)))
16695 + PKTFREE(di->osh, p, FALSE);
16696 +}
16697 +
16698 +void *
16699 +dma_getnextrxp(dma_info_t *di, bool forceall)
16700 +{
16701 + if (DMA64_ENAB(di)) {
16702 + return dma64_getnextrxp(di, forceall);
16703 + } else {
16704 + return dma32_getnextrxp(di, forceall);
16705 + }
16706 +}
16707 +
16708 +uintptr
16709 +dma_getvar(dma_info_t *di, char *name)
16710 +{
16711 + if (!strcmp(name, "&txavail"))
16712 + return ((uintptr) &di->txavail);
16713 + else {
16714 + ASSERT(0);
16715 + }
16716 + return (0);
16717 +}
16718 +
16719 +void
16720 +dma_txblock(dma_info_t *di)
16721 +{
16722 + di->txavail = 0;
16723 +}
16724 +
16725 +void
16726 +dma_txunblock(dma_info_t *di)
16727 +{
16728 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
16729 +}
16730 +
16731 +uint
16732 +dma_txactive(dma_info_t *di)
16733 +{
16734 + return (NTXDACTIVE(di->txin, di->txout));
16735 +}
16736 +
16737 +void
16738 +dma_rxpiomode(dma32regs_t *regs)
16739 +{
16740 + W_REG(&regs->control, RC_FM);
16741 +}
16742 +
16743 +void
16744 +dma_txpioloopback(dma32regs_t *regs)
16745 +{
16746 + OR_REG(&regs->control, XC_LE);
16747 +}
16748 +
16749 +
16750 +
16751 +
16752 +/*** 32 bits DMA non-inline functions ***/
16753 +static bool
16754 +dma32_alloc(dma_info_t *di, uint direction)
16755 +{
16756 + uint size;
16757 + uint ddlen;
16758 + void *va;
16759 +
16760 + ddlen = sizeof (dma32dd_t);
16761 +
16762 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
16763 +
16764 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
16765 + size += D32RINGALIGN;
16766 +
16767 +
16768 + if (direction == DMA_TX) {
16769 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
16770 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
16771 + return FALSE;
16772 + }
16773 +
16774 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
16775 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
16776 + di->txdpa += di->txdalign;
16777 + di->txdalloc = size;
16778 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
16779 + } else {
16780 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
16781 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
16782 + return FALSE;
16783 + }
16784 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
16785 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
16786 + di->rxdpa += di->rxdalign;
16787 + di->rxdalloc = size;
16788 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
16789 + }
16790 +
16791 + return TRUE;
16792 +}
16793 +
16794 +static void
16795 +dma32_txreset(dma_info_t *di)
16796 +{
16797 + uint32 status;
16798 +
16799 + /* suspend tx DMA first */
16800 + W_REG(&di->d32txregs->control, XC_SE);
16801 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
16802 + status != XS_XS_IDLE &&
16803 + status != XS_XS_STOPPED,
16804 + 10000);
16805 +
16806 + W_REG(&di->d32txregs->control, 0);
16807 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
16808 + 10000);
16809 +
16810 + if (status != XS_XS_DISABLED) {
16811 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
16812 + }
16813 +
16814 + /* wait for the last transaction to complete */
16815 + OSL_DELAY(300);
16816 +}
16817 +
16818 +static void
16819 +dma32_rxreset(dma_info_t *di)
16820 +{
16821 + uint32 status;
16822 +
16823 + W_REG(&di->d32rxregs->control, 0);
16824 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
16825 + 10000);
16826 +
16827 + if (status != RS_RS_DISABLED) {
16828 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
16829 + }
16830 +}
16831 +
16832 +static bool
16833 +dma32_txsuspendedidle(dma_info_t *di)
16834 +{
16835 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
16836 + return 0;
16837 +
16838 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
16839 + return 0;
16840 +
16841 + OSL_DELAY(2);
16842 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
16843 +}
16844 +
16845 +/*
16846 + * supports full 32bit dma engine buffer addressing so
16847 + * dma buffers can cross 4 Kbyte page boundaries.
16848 + */
16849 +static int
16850 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
16851 +{
16852 + void *p, *next;
16853 + uchar *data;
16854 + uint len;
16855 + uint txout;
16856 + uint32 ctrl;
16857 + uint32 pa;
16858 +
16859 + DMA_TRACE(("%s: dma_txfast\n", di->name));
16860 +
16861 + txout = di->txout;
16862 + ctrl = 0;
16863 +
16864 + /*
16865 + * Walk the chain of packet buffers
16866 + * allocating and initializing transmit descriptor entries.
16867 + */
16868 + for (p = p0; p; p = next) {
16869 + data = PKTDATA(di->osh, p);
16870 + len = PKTLEN(di->osh, p);
16871 + next = PKTNEXT(di->osh, p);
16872 +
16873 + /* return nonzero if out of tx descriptors */
16874 + if (NEXTTXD(txout) == di->txin)
16875 + goto outoftxd;
16876 +
16877 + if (len == 0)
16878 + continue;
16879 +
16880 + /* get physical address of buffer start */
16881 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
16882 +
16883 + /* build the descriptor control value */
16884 + ctrl = len & CTRL_BC_MASK;
16885 +
16886 + ctrl |= coreflags;
16887 +
16888 + if (p == p0)
16889 + ctrl |= CTRL_SOF;
16890 + if (next == NULL)
16891 + ctrl |= (CTRL_IOC | CTRL_EOF);
16892 + if (txout == (di->ntxd - 1))
16893 + ctrl |= CTRL_EOT;
16894 +
16895 + if (DMA64_ENAB(di)) {
16896 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
16897 + } else {
16898 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
16899 + }
16900 +
16901 + ASSERT(di->txp[txout] == NULL);
16902 +
16903 + txout = NEXTTXD(txout);
16904 + }
16905 +
16906 + /* if last txd eof not set, fix it */
16907 + if (!(ctrl & CTRL_EOF))
16908 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
16909 +
16910 + /* save the packet */
16911 + di->txp[PREVTXD(txout)] = p0;
16912 +
16913 + /* bump the tx descriptor index */
16914 + di->txout = txout;
16915 +
16916 + /* kick the chip */
16917 + if (DMA64_ENAB(di)) {
16918 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
16919 + } else {
16920 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
16921 + }
16922 +
16923 + /* tx flow control */
16924 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
16925 +
16926 + return (0);
16927 +
16928 + outoftxd:
16929 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
16930 + PKTFREE(di->osh, p0, TRUE);
16931 + di->txavail = 0;
16932 + di->hnddma.txnobuf++;
16933 + return (-1);
16934 +}
16935 +
16936 +static void*
16937 +dma32_getnexttxp(dma_info_t *di, bool forceall)
16938 +{
16939 + uint start, end, i;
16940 + void *txp;
16941 +
16942 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
16943 +
16944 + txp = NULL;
16945 +
16946 + start = di->txin;
16947 + if (forceall)
16948 + end = di->txout;
16949 + else
16950 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
16951 +
16952 + if ((start == 0) && (end > di->txout))
16953 + goto bogus;
16954 +
16955 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
16956 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
16957 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
16958 +
16959 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
16960 + txp = di->txp[i];
16961 + di->txp[i] = NULL;
16962 + }
16963 +
16964 + di->txin = i;
16965 +
16966 + /* tx flow control */
16967 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
16968 +
16969 + return (txp);
16970 +
16971 +bogus:
16972 +/*
16973 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
16974 + start, end, di->txout, forceall));
16975 +*/
16976 + return (NULL);
16977 +}
16978 +
16979 +static void *
16980 +dma32_getnextrxp(dma_info_t *di, bool forceall)
16981 +{
16982 + uint i;
16983 + void *rxp;
16984 +
16985 + /* if forcing, dma engine must be disabled */
16986 + ASSERT(!forceall || !dma_rxenabled(di));
16987 +
16988 + i = di->rxin;
16989 +
16990 + /* return if no packets posted */
16991 + if (i == di->rxout)
16992 + return (NULL);
16993 +
16994 + /* ignore curr if forceall */
16995 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
16996 + return (NULL);
16997 +
16998 + /* get the packet pointer that corresponds to the rx descriptor */
16999 + rxp = di->rxp[i];
17000 + ASSERT(rxp);
17001 + di->rxp[i] = NULL;
17002 +
17003 + /* clear this packet from the descriptor ring */
17004 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
17005 + di->rxbufsize, DMA_RX, rxp);
17006 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
17007 +
17008 + di->rxin = NEXTRXD(i);
17009 +
17010 + return (rxp);
17011 +}
17012 +
17013 +static void
17014 +dma32_txrotate(di_t *di)
17015 +{
17016 + uint ad;
17017 + uint nactive;
17018 + uint rot;
17019 + uint old, new;
17020 + uint32 w;
17021 + uint first, last;
17022 +
17023 + ASSERT(dma_txsuspendedidle(di));
17024 +
17025 + nactive = dma_txactive(di);
17026 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
17027 + rot = TXD(ad - di->txin);
17028 +
17029 + ASSERT(rot < di->ntxd);
17030 +
17031 + /* full-ring case is a lot harder - don't worry about this */
17032 + if (rot >= (di->ntxd - nactive)) {
17033 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
17034 + return;
17035 + }
17036 +
17037 + first = di->txin;
17038 + last = PREVTXD(di->txout);
17039 +
17040 + /* move entries starting at last and moving backwards to first */
17041 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
17042 + new = TXD(old + rot);
17043 +
17044 + /*
17045 + * Move the tx dma descriptor.
17046 + * EOT is set only in the last entry in the ring.
17047 + */
17048 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
17049 + if (new == (di->ntxd - 1))
17050 + w |= CTRL_EOT;
17051 + W_SM(&di->txd32[new].ctrl, w);
17052 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
17053 +
17054 + /* zap the old tx dma descriptor address field */
17055 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
17056 +
17057 + /* move the corresponding txp[] entry */
17058 + ASSERT(di->txp[new] == NULL);
17059 + di->txp[new] = di->txp[old];
17060 + di->txp[old] = NULL;
17061 + }
17062 +
17063 + /* update txin and txout */
17064 + di->txin = ad;
17065 + di->txout = TXD(di->txout + rot);
17066 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17067 +
17068 + /* kick the chip */
17069 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
17070 +}
17071 +
17072 +/*** 64 bits DMA non-inline functions ***/
17073 +
17074 +#ifdef BCMDMA64
17075 +
17076 +static bool
17077 +dma64_alloc(dma_info_t *di, uint direction)
17078 +{
17079 + uint size;
17080 + uint ddlen;
17081 + uint32 alignbytes;
17082 + void *va;
17083 +
17084 + ddlen = sizeof (dma64dd_t);
17085 +
17086 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17087 +
17088 + alignbytes = di->dma64align;
17089 +
17090 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
17091 + size += alignbytes;
17092 +
17093 +
17094 + if (direction == DMA_TX) {
17095 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17096 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17097 + return FALSE;
17098 + }
17099 +
17100 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
17101 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
17102 + di->txdpa += di->txdalign;
17103 + di->txdalloc = size;
17104 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
17105 + } else {
17106 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17107 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17108 + return FALSE;
17109 + }
17110 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
17111 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
17112 + di->rxdpa += di->rxdalign;
17113 + di->rxdalloc = size;
17114 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
17115 + }
17116 +
17117 + return TRUE;
17118 +}
17119 +
17120 +static void
17121 +dma64_txreset(dma_info_t *di)
17122 +{
17123 + uint32 status;
17124 +
17125 + /* suspend tx DMA first */
17126 + W_REG(&di->d64txregs->control, D64_XC_SE);
17127 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
17128 + status != D64_XS0_XS_IDLE &&
17129 + status != D64_XS0_XS_STOPPED,
17130 + 10000);
17131 +
17132 + W_REG(&di->d64txregs->control, 0);
17133 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
17134 + 10000);
17135 +
17136 + if (status != D64_XS0_XS_DISABLED) {
17137 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17138 + }
17139 +
17140 + /* wait for the last transaction to complete */
17141 + OSL_DELAY(300);
17142 +}
17143 +
17144 +static void
17145 +dma64_rxreset(dma_info_t *di)
17146 +{
17147 + uint32 status;
17148 +
17149 + W_REG(&di->d64rxregs->control, 0);
17150 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
17151 + 10000);
17152 +
17153 + if (status != D64_RS0_RS_DISABLED) {
17154 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17155 + }
17156 +}
17157 +
17158 +static bool
17159 +dma64_txsuspendedidle(dma_info_t *di)
17160 +{
17161 +
17162 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
17163 + return 0;
17164 +
17165 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
17166 + return 1;
17167 +
17168 + return 0;
17169 +}
17170 +
17171 +/*
17172 + * supports full 32bit dma engine buffer addressing so
17173 + * dma buffers can cross 4 Kbyte page boundaries.
17174 + */
17175 +static int
17176 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17177 +{
17178 + void *p, *next;
17179 + uchar *data;
17180 + uint len;
17181 + uint txout;
17182 + uint32 flags;
17183 + uint32 pa;
17184 +
17185 + DMA_TRACE(("%s: dma_txfast\n", di->name));
17186 +
17187 + txout = di->txout;
17188 + flags = 0;
17189 +
17190 + /*
17191 + * Walk the chain of packet buffers
17192 + * allocating and initializing transmit descriptor entries.
17193 + */
17194 + for (p = p0; p; p = next) {
17195 + data = PKTDATA(di->osh, p);
17196 + len = PKTLEN(di->osh, p);
17197 + next = PKTNEXT(di->osh, p);
17198 +
17199 + /* return nonzero if out of tx descriptors */
17200 + if (NEXTTXD(txout) == di->txin)
17201 + goto outoftxd;
17202 +
17203 + if (len == 0)
17204 + continue;
17205 +
17206 + /* get physical address of buffer start */
17207 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
17208 +
17209 + flags = coreflags;
17210 +
17211 + if (p == p0)
17212 + flags |= D64_CTRL1_SOF;
17213 + if (next == NULL)
17214 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
17215 + if (txout == (di->ntxd - 1))
17216 + flags |= D64_CTRL1_EOT;
17217 +
17218 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
17219 +
17220 + ASSERT(di->txp[txout] == NULL);
17221 +
17222 + txout = NEXTTXD(txout);
17223 + }
17224 +
17225 + /* if last txd eof not set, fix it */
17226 + if (!(flags & D64_CTRL1_EOF))
17227 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
17228 +
17229 + /* save the packet */
17230 + di->txp[PREVTXD(txout)] = p0;
17231 +
17232 + /* bump the tx descriptor index */
17233 + di->txout = txout;
17234 +
17235 + /* kick the chip */
17236 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
17237 +
17238 + /* tx flow control */
17239 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17240 +
17241 + return (0);
17242 +
17243 +outoftxd:
17244 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
17245 + PKTFREE(di->osh, p0, TRUE);
17246 + di->txavail = 0;
17247 + di->hnddma.txnobuf++;
17248 + return (-1);
17249 +}
17250 +
17251 +static void*
17252 +dma64_getnexttxp(dma_info_t *di, bool forceall)
17253 +{
17254 + uint start, end, i;
17255 + void *txp;
17256 +
17257 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
17258 +
17259 + txp = NULL;
17260 +
17261 + start = di->txin;
17262 + if (forceall)
17263 + end = di->txout;
17264 + else
17265 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
17266 +
17267 + if ((start == 0) && (end > di->txout))
17268 + goto bogus;
17269 +
17270 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
17271 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
17272 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
17273 +
17274 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
17275 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
17276 +
17277 + txp = di->txp[i];
17278 + di->txp[i] = NULL;
17279 + }
17280 +
17281 + di->txin = i;
17282 +
17283 + /* tx flow control */
17284 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17285 +
17286 + return (txp);
17287 +
17288 +bogus:
17289 +/*
17290 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
17291 + start, end, di->txout, forceall));
17292 +*/
17293 + return (NULL);
17294 +}
17295 +
17296 +static void *
17297 +dma64_getnextrxp(dma_info_t *di, bool forceall)
17298 +{
17299 + uint i;
17300 + void *rxp;
17301 +
17302 + /* if forcing, dma engine must be disabled */
17303 + ASSERT(!forceall || !dma_rxenabled(di));
17304 +
17305 + i = di->rxin;
17306 +
17307 + /* return if no packets posted */
17308 + if (i == di->rxout)
17309 + return (NULL);
17310 +
17311 + /* ignore curr if forceall */
17312 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
17313 + return (NULL);
17314 +
17315 + /* get the packet pointer that corresponds to the rx descriptor */
17316 + rxp = di->rxp[i];
17317 + ASSERT(rxp);
17318 + di->rxp[i] = NULL;
17319 +
17320 + /* clear this packet from the descriptor ring */
17321 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
17322 + di->rxbufsize, DMA_RX, rxp);
17323 +
17324 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
17325 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
17326 +
17327 + di->rxin = NEXTRXD(i);
17328 +
17329 + return (rxp);
17330 +}
17331 +
17332 +static void
17333 +dma64_txrotate(di_t *di)
17334 +{
17335 + uint ad;
17336 + uint nactive;
17337 + uint rot;
17338 + uint old, new;
17339 + uint32 w;
17340 + uint first, last;
17341 +
17342 + ASSERT(dma_txsuspendedidle(di));
17343 +
17344 + nactive = dma_txactive(di);
17345 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
17346 + rot = TXD(ad - di->txin);
17347 +
17348 + ASSERT(rot < di->ntxd);
17349 +
17350 + /* full-ring case is a lot harder - don't worry about this */
17351 + if (rot >= (di->ntxd - nactive)) {
17352 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
17353 + return;
17354 + }
17355 +
17356 + first = di->txin;
17357 + last = PREVTXD(di->txout);
17358 +
17359 + /* move entries starting at last and moving backwards to first */
17360 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
17361 + new = TXD(old + rot);
17362 +
17363 + /*
17364 + * Move the tx dma descriptor.
17365 + * EOT is set only in the last entry in the ring.
17366 + */
17367 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
17368 + if (new == (di->ntxd - 1))
17369 + w |= D64_CTRL1_EOT;
17370 + W_SM(&di->txd64[new].ctrl1, w);
17371 +
17372 + w = R_SM(&di->txd64[old].ctrl2);
17373 + W_SM(&di->txd64[new].ctrl2, w);
17374 +
17375 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
17376 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
17377 +
17378 + /* zap the old tx dma descriptor address field */
17379 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
17380 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
17381 +
17382 + /* move the corresponding txp[] entry */
17383 + ASSERT(di->txp[new] == NULL);
17384 + di->txp[new] = di->txp[old];
17385 + di->txp[old] = NULL;
17386 + }
17387 +
17388 + /* update txin and txout */
17389 + di->txin = ad;
17390 + di->txout = TXD(di->txout + rot);
17391 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17392 +
17393 + /* kick the chip */
17394 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
17395 +}
17396 +
17397 +#endif
17398 +
17399 diff -Naur linux.old/drivers/net/wl/hnddma.h linux.dev/drivers/net/wl/hnddma.h
17400 --- linux.old/drivers/net/wl/hnddma.h 1970-01-01 01:00:00.000000000 +0100
17401 +++ linux.dev/drivers/net/wl/hnddma.h 2006-04-06 16:57:44.000000000 +0200
17402 @@ -0,0 +1,69 @@
17403 +/*
17404 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
17405 + * This supports the following chips: BCM42xx, 44xx, 47xx .
17406 + *
17407 + * Copyright 2005, Broadcom Corporation
17408 + * All Rights Reserved.
17409 + *
17410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17414 + * $Id$
17415 + */
17416 +
17417 +#ifndef _hnddma_h_
17418 +#define _hnddma_h_
17419 +
17420 +/* export structure */
17421 +typedef volatile struct {
17422 + /* rx error counters */
17423 + uint rxgiants; /* rx giant frames */
17424 + uint rxnobuf; /* rx out of dma descriptors */
17425 + /* tx error counters */
17426 + uint txnobuf; /* tx out of dma descriptors */
17427 +} hnddma_t;
17428 +
17429 +#ifndef di_t
17430 +#define di_t void
17431 +#endif
17432 +
17433 +#ifndef osl_t
17434 +#define osl_t void
17435 +#endif
17436 +
17437 +/* externs */
17438 +extern void dma_detach(di_t *di);
17439 +extern void dma_txreset(di_t *di);
17440 +extern void dma_rxreset(di_t *di);
17441 +extern void dma_txinit(di_t *di);
17442 +extern bool dma_txenabled(di_t *di);
17443 +extern void dma_rxinit(di_t *di);
17444 +extern void dma_rxenable(di_t *di);
17445 +extern bool dma_rxenabled(di_t *di);
17446 +extern void dma_txsuspend(di_t *di);
17447 +extern void dma_txresume(di_t *di);
17448 +extern bool dma_txsuspended(di_t *di);
17449 +extern bool dma_txsuspendedidle(di_t *di);
17450 +extern bool dma_txstopped(di_t *di);
17451 +extern bool dma_rxstopped(di_t *di);
17452 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
17453 +extern void dma_fifoloopbackenable(di_t *di);
17454 +extern void *dma_rx(di_t *di);
17455 +extern void dma_rxfill(di_t *di);
17456 +extern void dma_txreclaim(di_t *di, bool forceall);
17457 +extern void dma_rxreclaim(di_t *di);
17458 +extern uintptr dma_getvar(di_t *di, char *name);
17459 +extern void *dma_getnexttxp(di_t *di, bool forceall);
17460 +extern void *dma_peeknexttxp(di_t *di);
17461 +extern void *dma_getnextrxp(di_t *di, bool forceall);
17462 +extern void dma_txblock(di_t *di);
17463 +extern void dma_txunblock(di_t *di);
17464 +extern uint dma_txactive(di_t *di);
17465 +extern void dma_txrotate(di_t *di);
17466 +
17467 +extern void dma_rxpiomode(dma32regs_t *);
17468 +extern void dma_txpioloopback(dma32regs_t *);
17469 +
17470 +
17471 +#endif /* _hnddma_h_ */
17472 diff -Naur linux.old/drivers/net/wl/pktq.h linux.dev/drivers/net/wl/pktq.h
17473 --- linux.old/drivers/net/wl/pktq.h 1970-01-01 01:00:00.000000000 +0100
17474 +++ linux.dev/drivers/net/wl/pktq.h 2006-04-06 17:32:52.000000000 +0200
17475 @@ -0,0 +1,48 @@
17476 +/*
17477 + * Misc useful os-independent macros and functions.
17478 + *
17479 + * Copyright 2005, Broadcom Corporation
17480 + * All Rights Reserved.
17481 + *
17482 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17483 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17484 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17485 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17486 + * $Id$
17487 + */
17488 +
17489 +#ifndef _pktq_h_
17490 +#define _pktq_h_
17491 +
17492 +/*** driver-only section ***/
17493 +#ifdef BCMDRIVER
17494 +
17495 +/* generic osl packet queue */
17496 +struct pktq {
17497 + void *head; /* first packet to dequeue */
17498 + void *tail; /* last packet to dequeue */
17499 + uint len; /* number of queued packets */
17500 + uint maxlen; /* maximum number of queued packets */
17501 + bool priority; /* enqueue by packet priority */
17502 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
17503 +};
17504 +#define DEFAULT_QLEN 128
17505 +
17506 +#define pktq_len(q) ((q)->len)
17507 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
17508 +#define pktq_head(q) ((q)->head)
17509 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
17510 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
17511 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
17512 +
17513 +/* externs */
17514 +/* packet */
17515 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
17516 +extern uint pkttotlen(osl_t *osh, void *);
17517 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
17518 +extern void pktenq(struct pktq *q, void *p, bool lifo);
17519 +extern void *pktdeq(struct pktq *q);
17520 +extern void *pktdeqtail(struct pktq *q);
17521 +
17522 +#endif
17523 +#endif /* _pktq_h_ */
17524 diff -Naur linux.old/drivers/net/wl/sbhnddma.h linux.dev/drivers/net/wl/sbhnddma.h
17525 --- linux.old/drivers/net/wl/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
17526 +++ linux.dev/drivers/net/wl/sbhnddma.h 2006-04-06 15:34:14.000000000 +0200
17527 @@ -0,0 +1,312 @@
17528 +/*
17529 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
17530 + * This supports the following chips: BCM42xx, 44xx, 47xx .
17531 + *
17532 + * Copyright 2005, Broadcom Corporation
17533 + * All Rights Reserved.
17534 + *
17535 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17536 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17537 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17538 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17539 + * $Id$
17540 + */
17541 +
17542 +#ifndef _sbhnddma_h_
17543 +#define _sbhnddma_h_
17544 +
17545 +
17546 +/* 2byte-wide pio register set per channel(xmt or rcv) */
17547 +typedef volatile struct {
17548 + uint16 fifocontrol;
17549 + uint16 fifodata;
17550 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
17551 + uint16 PAD;
17552 +} pio2regs_t;
17553 +
17554 +/* a pair of pio channels(tx and rx) */
17555 +typedef volatile struct {
17556 + pio2regs_t tx;
17557 + pio2regs_t rx;
17558 +} pio2regp_t;
17559 +
17560 +/* 4byte-wide pio register set per channel(xmt or rcv) */
17561 +typedef volatile struct {
17562 + uint32 fifocontrol;
17563 + uint32 fifodata;
17564 +} pio4regs_t;
17565 +
17566 +/* a pair of pio channels(tx and rx) */
17567 +typedef volatile struct {
17568 + pio4regs_t tx;
17569 + pio4regs_t rx;
17570 +} pio4regp_t;
17571 +
17572 +
17573 +
17574 +/* DMA structure:
17575 + * support two DMA engines: 32 bits address or 64 bit addressing
17576 + * basic DMA register set is per channel(transmit or receive)
17577 + * a pair of channels is defined for convenience
17578 + */
17579 +
17580 +
17581 +/*** 32 bits addressing ***/
17582 +
17583 +/* dma registers per channel(xmt or rcv) */
17584 +typedef volatile struct {
17585 + uint32 control; /* enable, et al */
17586 + uint32 addr; /* descriptor ring base address (4K aligned) */
17587 + uint32 ptr; /* last descriptor posted to chip */
17588 + uint32 status; /* current active descriptor, et al */
17589 +} dma32regs_t;
17590 +
17591 +typedef volatile struct {
17592 + dma32regs_t xmt; /* dma tx channel */
17593 + dma32regs_t rcv; /* dma rx channel */
17594 +} dma32regp_t;
17595 +
17596 +typedef volatile struct { /* diag access */
17597 + uint32 fifoaddr; /* diag address */
17598 + uint32 fifodatalow; /* low 32bits of data */
17599 + uint32 fifodatahigh; /* high 32bits of data */
17600 + uint32 pad; /* reserved */
17601 +} dma32diag_t;
17602 +
17603 +/*
17604 + * DMA Descriptor
17605 + * Descriptors are only read by the hardware, never written back.
17606 + */
17607 +typedef volatile struct {
17608 + uint32 ctrl; /* misc control bits & bufcount */
17609 + uint32 addr; /* data buffer address */
17610 +} dma32dd_t;
17611 +
17612 +/*
17613 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
17614 + */
17615 +#define D32MAXRINGSZ 4096
17616 +#define D32RINGALIGN 4096
17617 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
17618 +
17619 +/* transmit channel control */
17620 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
17621 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
17622 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
17623 +#define XC_FL ((uint32)1 << 4) /* flush request */
17624 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
17625 +#define XC_AE_SHIFT 16
17626 +
17627 +/* transmit descriptor table pointer */
17628 +#define XP_LD_MASK 0xfff /* last valid descriptor */
17629 +
17630 +/* transmit channel status */
17631 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
17632 +#define XS_XS_MASK 0xf000 /* transmit state */
17633 +#define XS_XS_SHIFT 12
17634 +#define XS_XS_DISABLED 0x0000 /* disabled */
17635 +#define XS_XS_ACTIVE 0x1000 /* active */
17636 +#define XS_XS_IDLE 0x2000 /* idle wait */
17637 +#define XS_XS_STOPPED 0x3000 /* stopped */
17638 +#define XS_XS_SUSP 0x4000 /* suspend pending */
17639 +#define XS_XE_MASK 0xf0000 /* transmit errors */
17640 +#define XS_XE_SHIFT 16
17641 +#define XS_XE_NOERR 0x00000 /* no error */
17642 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
17643 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
17644 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
17645 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
17646 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
17647 +#define XS_AD_SHIFT 20
17648 +
17649 +/* receive channel control */
17650 +#define RC_RE ((uint32)1 << 0) /* receive enable */
17651 +#define RC_RO_MASK 0xfe /* receive frame offset */
17652 +#define RC_RO_SHIFT 1
17653 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
17654 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
17655 +#define RC_AE_SHIFT 16
17656 +
17657 +/* receive descriptor table pointer */
17658 +#define RP_LD_MASK 0xfff /* last valid descriptor */
17659 +
17660 +/* receive channel status */
17661 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
17662 +#define RS_RS_MASK 0xf000 /* receive state */
17663 +#define RS_RS_SHIFT 12
17664 +#define RS_RS_DISABLED 0x0000 /* disabled */
17665 +#define RS_RS_ACTIVE 0x1000 /* active */
17666 +#define RS_RS_IDLE 0x2000 /* idle wait */
17667 +#define RS_RS_STOPPED 0x3000 /* reserved */
17668 +#define RS_RE_MASK 0xf0000 /* receive errors */
17669 +#define RS_RE_SHIFT 16
17670 +#define RS_RE_NOERR 0x00000 /* no error */
17671 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
17672 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
17673 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
17674 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
17675 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
17676 +#define RS_AD_SHIFT 20
17677 +
17678 +/* fifoaddr */
17679 +#define FA_OFF_MASK 0xffff /* offset */
17680 +#define FA_SEL_MASK 0xf0000 /* select */
17681 +#define FA_SEL_SHIFT 16
17682 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
17683 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
17684 +#define FA_SEL_RDD 0x40000 /* receive dma data */
17685 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
17686 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
17687 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
17688 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
17689 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
17690 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
17691 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
17692 +
17693 +/* descriptor control flags */
17694 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
17695 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
17696 +#define CTRL_AE_SHIFT 16
17697 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
17698 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
17699 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
17700 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
17701 +
17702 +/* control flags in the range [27:20] are core-specific and not defined here */
17703 +#define CTRL_CORE_MASK 0x0ff00000
17704 +
17705 +/*** 64 bits addressing ***/
17706 +
17707 +/* dma registers per channel(xmt or rcv) */
17708 +typedef volatile struct {
17709 + uint32 control; /* enable, et al */
17710 + uint32 ptr; /* last descriptor posted to chip */
17711 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
17712 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
17713 + uint32 status0; /* current descriptor, xmt state */
17714 + uint32 status1; /* active descriptor, xmt error */
17715 +} dma64regs_t;
17716 +
17717 +typedef volatile struct {
17718 + dma64regs_t tx; /* dma64 tx channel */
17719 + dma64regs_t rx; /* dma64 rx channel */
17720 +} dma64regp_t;
17721 +
17722 +typedef volatile struct { /* diag access */
17723 + uint32 fifoaddr; /* diag address */
17724 + uint32 fifodatalow; /* low 32bits of data */
17725 + uint32 fifodatahigh; /* high 32bits of data */
17726 + uint32 pad; /* reserved */
17727 +} dma64diag_t;
17728 +
17729 +/*
17730 + * DMA Descriptor
17731 + * Descriptors are only read by the hardware, never written back.
17732 + */
17733 +typedef volatile struct {
17734 + uint32 ctrl1; /* misc control bits & bufcount */
17735 + uint32 ctrl2; /* buffer count and address extension */
17736 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
17737 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
17738 +} dma64dd_t;
17739 +
17740 +/*
17741 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
17742 + */
17743 +#define D64MAXRINGSZ 8192
17744 +#define D64RINGALIGN 8192
17745 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
17746 +
17747 +/* transmit channel control */
17748 +#define D64_XC_XE 0x00000001 /* transmit enable */
17749 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
17750 +#define D64_XC_LE 0x00000004 /* loopback enable */
17751 +#define D64_XC_FL 0x00000010 /* flush request */
17752 +#define D64_XC_AE 0x00110000 /* address extension bits */
17753 +#define D64_XC_AE_SHIFT 16
17754 +
17755 +/* transmit descriptor table pointer */
17756 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
17757 +
17758 +/* transmit channel status */
17759 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
17760 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
17761 +#define D64_XS0_XS_SHIFT 28
17762 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
17763 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
17764 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
17765 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
17766 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
17767 +
17768 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
17769 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
17770 +#define D64_XS1_XE_SHIFT 28
17771 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
17772 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
17773 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
17774 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
17775 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
17776 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
17777 +
17778 +/* receive channel control */
17779 +#define D64_RC_RE 0x00000001 /* receive enable */
17780 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
17781 +#define D64_RC_RO_SHIFT 1
17782 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
17783 +#define D64_RC_AE 0x00110000 /* address extension bits */
17784 +#define D64_RC_AE_SHIFT 16
17785 +
17786 +/* receive descriptor table pointer */
17787 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
17788 +
17789 +/* receive channel status */
17790 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
17791 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
17792 +#define D64_RS0_RS_SHIFT 28
17793 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
17794 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
17795 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
17796 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
17797 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
17798 +
17799 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
17800 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
17801 +#define D64_RS1_RE_SHIFT 28
17802 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
17803 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
17804 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
17805 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
17806 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
17807 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
17808 +
17809 +/* fifoaddr */
17810 +#define D64_FA_OFF_MASK 0xffff /* offset */
17811 +#define D64_FA_SEL_MASK 0xf0000 /* select */
17812 +#define D64_FA_SEL_SHIFT 16
17813 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
17814 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
17815 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
17816 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
17817 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
17818 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
17819 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
17820 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
17821 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
17822 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
17823 +
17824 +/* descriptor control flags 1 */
17825 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
17826 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
17827 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
17828 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
17829 +
17830 +/* descriptor control flags 2 */
17831 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
17832 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
17833 +#define D64_CTRL2_AE_SHIFT 16
17834 +
17835 +/* control flags in the range [27:20] are core-specific and not defined here */
17836 +#define D64_CTRL_CORE_MASK 0x0ff00000
17837 +
17838 +
17839 +#endif /* _sbhnddma_h_ */
17840 diff -Naur linux.old/drivers/net/wl2/Makefile linux.dev/drivers/net/wl2/Makefile
17841 --- linux.old/drivers/net/wl2/Makefile 1970-01-01 01:00:00.000000000 +0100
17842 +++ linux.dev/drivers/net/wl2/Makefile 2006-04-06 16:56:27.000000000 +0200
17843 @@ -0,0 +1,23 @@
17844 +#
17845 +# Makefile for the Broadcom wl driver
17846 +#
17847 +# Copyright 2004, Broadcom Corporation
17848 +# All Rights Reserved.
17849 +#
17850 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17851 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17852 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17853 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17854 +#
17855 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
17856 +
17857 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
17858 +
17859 +O_TARGET := wl.o
17860 +
17861 +obj-y := wl_apsta.o
17862 +obj-y += compat.o hnddma.o
17863 +
17864 +obj-m := $(O_TARGET)
17865 +
17866 +include $(TOPDIR)/Rules.make
17867 diff -Naur linux.old/drivers/net/wl2/compat.c linux.dev/drivers/net/wl2/compat.c
17868 --- linux.old/drivers/net/wl2/compat.c 1970-01-01 01:00:00.000000000 +0100
17869 +++ linux.dev/drivers/net/wl2/compat.c 2006-04-06 17:08:21.000000000 +0200
17870 @@ -0,0 +1,376 @@
17871 +/*
17872 + * Misc useful OS-independent routines.
17873 + *
17874 + * Copyright 2005, Broadcom Corporation
17875 + * All Rights Reserved.
17876 + *
17877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17881 + * $Id$
17882 + */
17883 +
17884 +#include <typedefs.h>
17885 +#ifdef BCMDRIVER
17886 +#include <osl.h>
17887 +#include <sbutils.h>
17888 +#include <bcmnvram.h>
17889 +#else
17890 +#include <stdio.h>
17891 +#include <string.h>
17892 +#endif
17893 +#include "pktq.h"
17894 +#include <bcmutils.h>
17895 +#include <bcmendian.h>
17896 +#include <bcmdevs.h>
17897 +
17898 +#ifdef BCMDRIVER
17899 +/* copy a pkt buffer chain into a buffer */
17900 +uint
17901 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
17902 +{
17903 + uint n, ret = 0;
17904 +
17905 + if (len < 0)
17906 + len = 4096; /* "infinite" */
17907 +
17908 + /* skip 'offset' bytes */
17909 + for (; p && offset; p = PKTNEXT(osh, p)) {
17910 + if (offset < (uint)PKTLEN(osh, p))
17911 + break;
17912 + offset -= PKTLEN(osh, p);
17913 + }
17914 +
17915 + if (!p)
17916 + return 0;
17917 +
17918 + /* copy the data */
17919 + for (; p && len; p = PKTNEXT(osh, p)) {
17920 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
17921 + bcopy(PKTDATA(osh, p) + offset, buf, n);
17922 + buf += n;
17923 + len -= n;
17924 + ret += n;
17925 + offset = 0;
17926 + }
17927 +
17928 + return ret;
17929 +}
17930 +
17931 +/* return total length of buffer chain */
17932 +uint
17933 +pkttotlen(osl_t *osh, void *p)
17934 +{
17935 + uint total;
17936 +
17937 + total = 0;
17938 + for (; p; p = PKTNEXT(osh, p))
17939 + total += PKTLEN(osh, p);
17940 + return (total);
17941 +}
17942 +
17943 +/*
17944 + * osl multiple-precedence packet queue
17945 + * hi_prec is always >= the number of the highest non-empty queue
17946 + */
17947 +
17948 +void *
17949 +pktq_penq(struct pktq *pq, int prec, void *p)
17950 +{
17951 + struct pktq_prec *q;
17952 +
17953 + ASSERT(prec >= 0 && prec < pq->num_prec);
17954 + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */
17955 +
17956 + ASSERT(!pktq_full(pq));
17957 + ASSERT(!pktq_pfull(pq, prec));
17958 +
17959 + q = &pq->q[prec];
17960 +
17961 + if (q->head)
17962 + PKTSETLINK(q->tail, p);
17963 + else
17964 + q->head = p;
17965 +
17966 + q->tail = p;
17967 + q->len++;
17968 +
17969 + if (pq->hi_prec < prec)
17970 + pq->hi_prec = (uint8)prec;
17971 +
17972 + pq->len++;
17973 +
17974 + return p;
17975 +}
17976 +
17977 +void *
17978 +pktq_penq_head(struct pktq *pq, int prec, void *p)
17979 +{
17980 + struct pktq_prec *q;
17981 +
17982 + ASSERT(prec >= 0 && prec < pq->num_prec);
17983 + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */
17984 +
17985 + ASSERT(!pktq_full(pq));
17986 + ASSERT(!pktq_pfull(pq, prec));
17987 +
17988 + q = &pq->q[prec];
17989 +
17990 + if (q->head)
17991 + PKTSETLINK(p, q->head);
17992 + else
17993 + q->tail = p;
17994 +
17995 + q->head = p;
17996 + q->len++;
17997 +
17998 + if (pq->hi_prec < prec)
17999 + pq->hi_prec = (uint8)prec;
18000 +
18001 + pq->len++;
18002 +
18003 + return p;
18004 +}
18005 +
18006 +void *
18007 +pktq_pdeq(struct pktq *pq, int prec)
18008 +{
18009 + struct pktq_prec *q;
18010 + void *p;
18011 +
18012 + ASSERT(prec >= 0 && prec < pq->num_prec);
18013 +
18014 + q = &pq->q[prec];
18015 +
18016 + if ((p = q->head) == NULL)
18017 + return NULL;
18018 +
18019 + if ((q->head = PKTLINK(p)) == NULL)
18020 + q->tail = NULL;
18021 +
18022 + q->len--;
18023 +
18024 + pq->len--;
18025 +
18026 + PKTSETLINK(p, NULL);
18027 +
18028 + return p;
18029 +}
18030 +
18031 +void *
18032 +pktq_pdeq_tail(struct pktq *pq, int prec)
18033 +{
18034 + struct pktq_prec *q;
18035 + void *p, *prev;
18036 +
18037 + ASSERT(prec >= 0 && prec < pq->num_prec);
18038 +
18039 + q = &pq->q[prec];
18040 +
18041 + if ((p = q->head) == NULL)
18042 + return NULL;
18043 +
18044 + for (prev = NULL; p != q->tail; p = PKTLINK(p))
18045 + prev = p;
18046 +
18047 + if (prev)
18048 + PKTSETLINK(prev, NULL);
18049 + else
18050 + q->head = NULL;
18051 +
18052 + q->tail = prev;
18053 + q->len--;
18054 +
18055 + pq->len--;
18056 +
18057 + return p;
18058 +}
18059 +
18060 +void
18061 +pktq_init(struct pktq *pq, int num_prec, int max)
18062 +{
18063 + int prec;
18064 +
18065 + ASSERT(num_prec >= 0 && num_prec <= PKTQ_MAX_PREC);
18066 +
18067 + bzero(pq, sizeof (*pq));
18068 +
18069 + pq->num_prec = (uint16)num_prec;
18070 +
18071 + pq->max = (uint16)max;
18072 +
18073 + for (prec = 0; prec < num_prec; prec++)
18074 + pq->q[prec].max = pq->max;
18075 +}
18076 +
18077 +void *
18078 +pktq_deq(struct pktq *pq, int *prec_out)
18079 +{
18080 + struct pktq_prec *q;
18081 + void *p;
18082 + int prec;
18083 +
18084 + if (pq->len == 0)
18085 + return NULL;
18086 +
18087 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
18088 + pq->hi_prec--;
18089 +
18090 + q = &pq->q[prec];
18091 +
18092 + if ((p = q->head) == NULL)
18093 + return NULL;
18094 +
18095 + if ((q->head = PKTLINK(p)) == NULL)
18096 + q->tail = NULL;
18097 +
18098 + q->len--;
18099 +
18100 + if (prec_out)
18101 + *prec_out = prec;
18102 +
18103 + pq->len--;
18104 +
18105 + PKTSETLINK(p, NULL);
18106 +
18107 + return p;
18108 +}
18109 +
18110 +void *
18111 +pktq_deq_tail(struct pktq *pq, int *prec_out)
18112 +{
18113 + struct pktq_prec *q;
18114 + void *p, *prev;
18115 + int prec;
18116 +
18117 + if (pq->len == 0)
18118 + return NULL;
18119 +
18120 + for (prec = 0; prec < pq->hi_prec; prec++)
18121 + if (pq->q[prec].head)
18122 + break;
18123 +
18124 + q = &pq->q[prec];
18125 +
18126 + if ((p = q->head) == NULL)
18127 + return NULL;
18128 +
18129 + for (prev = NULL; p != q->tail; p = PKTLINK(p))
18130 + prev = p;
18131 +
18132 + if (prev)
18133 + PKTSETLINK(prev, NULL);
18134 + else
18135 + q->head = NULL;
18136 +
18137 + q->tail = prev;
18138 + q->len--;
18139 +
18140 + if (prec_out)
18141 + *prec_out = prec;
18142 +
18143 + pq->len--;
18144 +
18145 + PKTSETLINK(p, NULL);
18146 +
18147 + return p;
18148 +}
18149 +
18150 +void *
18151 +pktq_peek(struct pktq *pq, int *prec_out)
18152 +{
18153 + void *p;
18154 + int prec;
18155 +
18156 + if (pq->len == 0)
18157 + return NULL;
18158 +
18159 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
18160 + pq->hi_prec--;
18161 +
18162 + if ((p = pq->q[prec].head) == NULL)
18163 + return NULL;
18164 +
18165 + if (prec_out)
18166 + *prec_out = prec;
18167 +
18168 + return p;
18169 +}
18170 +
18171 +void *
18172 +pktq_peek_tail(struct pktq *pq, int *prec_out)
18173 +{
18174 + void *p;
18175 + int prec;
18176 +
18177 + if (pq->len == 0)
18178 + return NULL;
18179 +
18180 + for (prec = 0; prec < pq->hi_prec; prec++)
18181 + if (pq->q[prec].head)
18182 + break;
18183 +
18184 + if ((p = pq->q[prec].tail) == NULL)
18185 + return NULL;
18186 +
18187 + if (prec_out)
18188 + *prec_out = prec;
18189 +
18190 + return p;
18191 +}
18192 +
18193 +int
18194 +pktq_mlen(struct pktq *pq, uint prec_bmp)
18195 +{
18196 + int prec, len;
18197 +
18198 + len = 0;
18199 +
18200 + for (prec = 0; prec <= pq->hi_prec; prec++)
18201 + if (prec_bmp & (1 << prec))
18202 + len += pq->q[prec].len;
18203 +
18204 + return len;
18205 +}
18206 +
18207 +void *
18208 +pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out)
18209 +{
18210 + struct pktq_prec *q;
18211 + void *p;
18212 + int prec;
18213 +
18214 + if (pq->len == 0)
18215 + return NULL;
18216 +
18217 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
18218 + pq->hi_prec--;
18219 +
18220 + while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL)
18221 + if (prec-- == 0)
18222 + return NULL;
18223 +
18224 + q = &pq->q[prec];
18225 +
18226 + if ((p = q->head) == NULL)
18227 + return NULL;
18228 +
18229 + if ((q->head = PKTLINK(p)) == NULL)
18230 + q->tail = NULL;
18231 +
18232 + q->len--;
18233 +
18234 + if (prec_out)
18235 + *prec_out = prec;
18236 +
18237 + pq->len--;
18238 +
18239 + PKTSETLINK(p, NULL);
18240 +
18241 + return p;
18242 +}
18243 +
18244 +#endif
18245 +
18246 +
18247 diff -Naur linux.old/drivers/net/wl2/hnddma.c linux.dev/drivers/net/wl2/hnddma.c
18248 --- linux.old/drivers/net/wl2/hnddma.c 1970-01-01 01:00:00.000000000 +0100
18249 +++ linux.dev/drivers/net/wl2/hnddma.c 2006-04-06 16:32:33.000000000 +0200
18250 @@ -0,0 +1,1487 @@
18251 +/*
18252 + * Generic Broadcom Home Networking Division (HND) DMA module.
18253 + * This supports the following chips: BCM42xx, 44xx, 47xx .
18254 + *
18255 + * Copyright 2005, Broadcom Corporation
18256 + * All Rights Reserved.
18257 + *
18258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18262 + *
18263 + * $Id$
18264 + */
18265 +
18266 +#include <typedefs.h>
18267 +#include <osl.h>
18268 +#include <bcmendian.h>
18269 +#include <sbconfig.h>
18270 +#include <bcmutils.h>
18271 +#include <bcmdevs.h>
18272 +#include <sbutils.h>
18273 +
18274 +struct dma_info; /* forward declaration */
18275 +#define di_t struct dma_info
18276 +
18277 +#include "sbhnddma.h"
18278 +#include "hnddma.h"
18279 +
18280 +/* debug/trace */
18281 +#define DMA_ERROR(args)
18282 +#define DMA_TRACE(args)
18283 +
18284 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
18285 +static uint dma_msg_level =
18286 + 0;
18287 +
18288 +#define MAXNAMEL 8
18289 +
18290 +/* dma engine software state */
18291 +typedef struct dma_info {
18292 + hnddma_t hnddma; /* exported structure */
18293 + uint *msg_level; /* message level pointer */
18294 + char name[MAXNAMEL]; /* callers name for diag msgs */
18295 +
18296 + void *osh; /* os handle */
18297 + sb_t *sbh; /* sb handle */
18298 +
18299 + bool dma64; /* dma64 enabled */
18300 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
18301 +
18302 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
18303 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
18304 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
18305 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
18306 +
18307 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
18308 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
18309 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
18310 + uint ntxd; /* # tx descriptors tunable */
18311 + uint txin; /* index of next descriptor to reclaim */
18312 + uint txout; /* index of next descriptor to post */
18313 + uint txavail; /* # free tx descriptors */
18314 + void **txp; /* pointer to parallel array of pointers to packets */
18315 + ulong txdpa; /* physical address of descriptor ring */
18316 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
18317 + uint txdalloc; /* #bytes allocated for the ring */
18318 +
18319 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
18320 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
18321 + uint nrxd; /* # rx descriptors tunable */
18322 + uint rxin; /* index of next descriptor to reclaim */
18323 + uint rxout; /* index of next descriptor to post */
18324 + void **rxp; /* pointer to parallel array of pointers to packets */
18325 + ulong rxdpa; /* physical address of descriptor ring */
18326 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
18327 + uint rxdalloc; /* #bytes allocated for the ring */
18328 +
18329 + /* tunables */
18330 + uint rxbufsize; /* rx buffer size in bytes */
18331 + uint nrxpost; /* # rx buffers to keep posted */
18332 + uint rxoffset; /* rxcontrol offset */
18333 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
18334 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
18335 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
18336 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
18337 +} dma_info_t;
18338 +
18339 +#ifdef BCMDMA64
18340 +#define DMA64_ENAB(di) ((di)->dma64)
18341 +#else
18342 +#define DMA64_ENAB(di) (0)
18343 +#endif
18344 +
18345 +/* descriptor bumping macros */
18346 +#define XXD(x, n) ((x) & ((n) - 1))
18347 +#define TXD(x) XXD((x), di->ntxd)
18348 +#define RXD(x) XXD((x), di->nrxd)
18349 +#define NEXTTXD(i) TXD(i + 1)
18350 +#define PREVTXD(i) TXD(i - 1)
18351 +#define NEXTRXD(i) RXD(i + 1)
18352 +#define NTXDACTIVE(h, t) TXD(t - h)
18353 +#define NRXDACTIVE(h, t) RXD(t - h)
18354 +
18355 +/* macros to convert between byte offsets and indexes */
18356 +#define B2I(bytes, type) ((bytes) / sizeof(type))
18357 +#define I2B(index, type) ((index) * sizeof(type))
18358 +
18359 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
18360 +#define PCI32ADDR_HIGH_SHIFT 30
18361 +
18362 +
18363 +/* prototypes */
18364 +static bool dma_isaddrext(dma_info_t *di);
18365 +static bool dma_alloc(dma_info_t *di, uint direction);
18366 +
18367 +static bool dma32_alloc(dma_info_t *di, uint direction);
18368 +static void dma32_txreset(dma_info_t *di);
18369 +static void dma32_rxreset(dma_info_t *di);
18370 +static bool dma32_txsuspendedidle(dma_info_t *di);
18371 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
18372 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
18373 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
18374 +static void dma32_txrotate(di_t *di);
18375 +
18376 +/* prototype or stubs */
18377 +#ifdef BCMDMA64
18378 +static bool dma64_alloc(dma_info_t *di, uint direction);
18379 +static void dma64_txreset(dma_info_t *di);
18380 +static void dma64_rxreset(dma_info_t *di);
18381 +static bool dma64_txsuspendedidle(dma_info_t *di);
18382 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
18383 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
18384 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
18385 +static void dma64_txrotate(di_t *di);
18386 +#else
18387 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
18388 +static void dma64_txreset(dma_info_t *di) {}
18389 +static void dma64_rxreset(dma_info_t *di) {}
18390 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
18391 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
18392 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
18393 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
18394 +static void dma64_txrotate(di_t *di) { return; }
18395 +#endif
18396 +
18397 +
18398 +
18399 +void*
18400 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
18401 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
18402 +{
18403 + dma_info_t *di;
18404 + uint size;
18405 +
18406 + /* allocate private info structure */
18407 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
18408 + return (NULL);
18409 + }
18410 + bzero((char*)di, sizeof (dma_info_t));
18411 +
18412 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
18413 +
18414 + if (sbh != NULL)
18415 + di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
18416 +
18417 +#ifndef BCMDMA64
18418 + if (di->dma64) {
18419 + DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
18420 + goto fail;
18421 + }
18422 +#endif
18423 +
18424 + /* check arguments */
18425 + ASSERT(ISPOWEROF2(ntxd));
18426 + ASSERT(ISPOWEROF2(nrxd));
18427 + if (nrxd == 0)
18428 + ASSERT(dmaregsrx == NULL);
18429 + if (ntxd == 0)
18430 + ASSERT(dmaregstx == NULL);
18431 +
18432 +
18433 + /* init dma reg pointer */
18434 + if (di->dma64) {
18435 + ASSERT(ntxd <= D64MAXDD);
18436 + ASSERT(nrxd <= D64MAXDD);
18437 + di->d64txregs = (dma64regs_t *)dmaregstx;
18438 + di->d64rxregs = (dma64regs_t *)dmaregsrx;
18439 +
18440 + di->dma64align = D64RINGALIGN;
18441 + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
18442 + /* for smaller dd table, HW relax the alignment requirement */
18443 + di->dma64align = D64RINGALIGN / 2;
18444 + }
18445 + } else {
18446 + ASSERT(ntxd <= D32MAXDD);
18447 + ASSERT(nrxd <= D32MAXDD);
18448 + di->d32txregs = (dma32regs_t *)dmaregstx;
18449 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
18450 + }
18451 +
18452 +
18453 + /* make a private copy of our callers name */
18454 + strncpy(di->name, name, MAXNAMEL);
18455 + di->name[MAXNAMEL-1] = '\0';
18456 +
18457 + di->osh = osh;
18458 + di->sbh = sbh;
18459 +
18460 + /* save tunables */
18461 + di->ntxd = ntxd;
18462 + di->nrxd = nrxd;
18463 + di->rxbufsize = rxbufsize;
18464 + di->nrxpost = nrxpost;
18465 + di->rxoffset = rxoffset;
18466 +
18467 + /*
18468 + * figure out the DMA physical address offset for dd and data
18469 + * for old chips w/o sb, use zero
18470 + * for new chips w sb,
18471 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
18472 + * Other bus: use zero
18473 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
18474 + */
18475 + di->ddoffsetlow = 0;
18476 + di->dataoffsetlow = 0;
18477 + if (sbh != NULL) {
18478 + if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
18479 + if ((sbh->buscoretype == SB_PCIE) && di->dma64){
18480 + di->ddoffsetlow = 0;
18481 + di->ddoffsethigh = SB_PCIE_DMA_H32;
18482 + } else {
18483 + di->ddoffsetlow = SB_PCI_DMA;
18484 + di->ddoffsethigh = 0;
18485 + }
18486 + di->dataoffsetlow = di->ddoffsetlow;
18487 + di->dataoffsethigh = di->ddoffsethigh;
18488 + }
18489 +#if defined(__mips__) && defined(IL_BIGENDIAN)
18490 + /* use sdram swapped region for data buffers but not dma descriptors */
18491 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
18492 +#endif
18493 + }
18494 +
18495 + di->addrext = dma_isaddrext(di);
18496 +
18497 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
18498 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
18499 +
18500 + /* allocate tx packet pointer vector */
18501 + if (ntxd) {
18502 + size = ntxd * sizeof (void*);
18503 + if ((di->txp = MALLOC(osh, size)) == NULL) {
18504 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
18505 + goto fail;
18506 + }
18507 + bzero((char*)di->txp, size);
18508 + }
18509 +
18510 + /* allocate rx packet pointer vector */
18511 + if (nrxd) {
18512 + size = nrxd * sizeof (void*);
18513 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
18514 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
18515 + goto fail;
18516 + }
18517 + bzero((char*)di->rxp, size);
18518 + }
18519 +
18520 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
18521 + if (ntxd) {
18522 + if (!dma_alloc(di, DMA_TX))
18523 + goto fail;
18524 + }
18525 +
18526 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
18527 + if (nrxd) {
18528 + if (!dma_alloc(di, DMA_RX))
18529 + goto fail;
18530 + }
18531 +
18532 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
18533 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
18534 + goto fail;
18535 + }
18536 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
18537 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
18538 + goto fail;
18539 + }
18540 +
18541 + return ((void*)di);
18542 +
18543 +fail:
18544 + dma_detach((void*)di);
18545 + return (NULL);
18546 +}
18547 +
18548 +static bool
18549 +dma_alloc(dma_info_t *di, uint direction)
18550 +{
18551 + if (DMA64_ENAB(di)) {
18552 + return dma64_alloc(di, direction);
18553 + } else {
18554 + return dma32_alloc(di, direction);
18555 + }
18556 +}
18557 +
18558 +/* may be called with core in reset */
18559 +void
18560 +dma_detach(dma_info_t *di)
18561 +{
18562 + if (di == NULL)
18563 + return;
18564 +
18565 + DMA_TRACE(("%s: dma_detach\n", di->name));
18566 +
18567 + /* shouldn't be here if descriptors are unreclaimed */
18568 + ASSERT(di->txin == di->txout);
18569 + ASSERT(di->rxin == di->rxout);
18570 +
18571 + /* free dma descriptor rings */
18572 + if (di->txd32)
18573 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
18574 + if (di->rxd32)
18575 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
18576 +
18577 + /* free packet pointer vectors */
18578 + if (di->txp)
18579 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
18580 + if (di->rxp)
18581 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
18582 +
18583 + /* free our private info structure */
18584 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
18585 +}
18586 +
18587 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
18588 +static bool
18589 +dma_isaddrext(dma_info_t *di)
18590 +{
18591 + uint32 w;
18592 +
18593 + if (DMA64_ENAB(di)) {
18594 + OR_REG(&di->d64txregs->control, D64_XC_AE);
18595 + w = R_REG(&di->d32txregs->control);
18596 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
18597 + return ((w & XC_AE) == D64_XC_AE);
18598 + } else {
18599 + OR_REG(&di->d32txregs->control, XC_AE);
18600 + w = R_REG(&di->d32txregs->control);
18601 + AND_REG(&di->d32txregs->control, ~XC_AE);
18602 + return ((w & XC_AE) == XC_AE);
18603 + }
18604 +}
18605 +
18606 +void
18607 +dma_txreset(dma_info_t *di)
18608 +{
18609 + DMA_TRACE(("%s: dma_txreset\n", di->name));
18610 +
18611 + if (DMA64_ENAB(di))
18612 + dma64_txreset(di);
18613 + else
18614 + dma32_txreset(di);
18615 +}
18616 +
18617 +void
18618 +dma_rxreset(dma_info_t *di)
18619 +{
18620 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
18621 +
18622 + if (DMA64_ENAB(di))
18623 + dma64_rxreset(di);
18624 + else
18625 + dma32_rxreset(di);
18626 +}
18627 +
18628 +/* initialize descriptor table base address */
18629 +static void
18630 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
18631 +{
18632 + if (DMA64_ENAB(di)) {
18633 + if (direction == DMA_TX) {
18634 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
18635 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
18636 + } else {
18637 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
18638 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
18639 + }
18640 + } else {
18641 + uint32 offset = di->ddoffsetlow;
18642 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
18643 + if (direction == DMA_TX)
18644 + W_REG(&di->d32txregs->addr, (pa + offset));
18645 + else
18646 + W_REG(&di->d32rxregs->addr, (pa + offset));
18647 + } else {
18648 + /* dma32 address extension */
18649 + uint32 ae;
18650 + ASSERT(di->addrext);
18651 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
18652 +
18653 + if (direction == DMA_TX) {
18654 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
18655 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
18656 + } else {
18657 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
18658 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
18659 + }
18660 + }
18661 + }
18662 +}
18663 +
18664 +/* init the tx or rx descriptor */
18665 +static INLINE void
18666 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
18667 +{
18668 + uint offset = di->dataoffsetlow;
18669 +
18670 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
18671 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
18672 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
18673 + } else {
18674 + /* address extension */
18675 + uint32 ae;
18676 + ASSERT(di->addrext);
18677 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
18678 +
18679 + *ctrl |= (ae << CTRL_AE_SHIFT);
18680 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
18681 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
18682 + }
18683 +}
18684 +
18685 +/* init the tx or rx descriptor */
18686 +static INLINE void
18687 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
18688 +{
18689 + uint32 bufaddr_low = pa + di->dataoffsetlow;
18690 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
18691 +
18692 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
18693 +
18694 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
18695 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
18696 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
18697 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
18698 +}
18699 +
18700 +void
18701 +dma_txinit(dma_info_t *di)
18702 +{
18703 + DMA_TRACE(("%s: dma_txinit\n", di->name));
18704 +
18705 + di->txin = di->txout = 0;
18706 + di->txavail = di->ntxd - 1;
18707 +
18708 + /* clear tx descriptor ring */
18709 + if (DMA64_ENAB(di)) {
18710 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
18711 + W_REG(&di->d64txregs->control, XC_XE);
18712 + dma_ddtable_init(di, DMA_TX, di->txdpa);
18713 + } else {
18714 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
18715 + W_REG(&di->d32txregs->control, XC_XE);
18716 + dma_ddtable_init(di, DMA_TX, di->txdpa);
18717 + }
18718 +}
18719 +
18720 +bool
18721 +dma_txenabled(dma_info_t *di)
18722 +{
18723 + uint32 xc;
18724 +
18725 + /* If the chip is dead, it is not enabled :-) */
18726 + if (DMA64_ENAB(di)) {
18727 + xc = R_REG(&di->d64txregs->control);
18728 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
18729 + } else {
18730 + xc = R_REG(&di->d32txregs->control);
18731 + return ((xc != 0xffffffff) && (xc & XC_XE));
18732 + }
18733 +}
18734 +
18735 +void
18736 +dma_txsuspend(dma_info_t *di)
18737 +{
18738 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
18739 + if (DMA64_ENAB(di))
18740 + OR_REG(&di->d64txregs->control, D64_XC_SE);
18741 + else
18742 + OR_REG(&di->d32txregs->control, XC_SE);
18743 +}
18744 +
18745 +void
18746 +dma_txresume(dma_info_t *di)
18747 +{
18748 + DMA_TRACE(("%s: dma_txresume\n", di->name));
18749 + if (DMA64_ENAB(di))
18750 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
18751 + else
18752 + AND_REG(&di->d32txregs->control, ~XC_SE);
18753 +}
18754 +
18755 +bool
18756 +dma_txsuspendedidle(dma_info_t *di)
18757 +{
18758 + if (DMA64_ENAB(di))
18759 + return dma64_txsuspendedidle(di);
18760 + else
18761 + return dma32_txsuspendedidle(di);
18762 +}
18763 +
18764 +bool
18765 +dma_txsuspended(dma_info_t *di)
18766 +{
18767 + if (DMA64_ENAB(di))
18768 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
18769 + else
18770 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
18771 +}
18772 +
18773 +bool
18774 +dma_txstopped(dma_info_t *di)
18775 +{
18776 + if (DMA64_ENAB(di))
18777 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
18778 + else
18779 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
18780 +}
18781 +
18782 +bool
18783 +dma_rxstopped(dma_info_t *di)
18784 +{
18785 + if (DMA64_ENAB(di))
18786 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
18787 + else
18788 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
18789 +}
18790 +
18791 +void
18792 +dma_fifoloopbackenable(dma_info_t *di)
18793 +{
18794 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
18795 + if (DMA64_ENAB(di))
18796 + OR_REG(&di->d64txregs->control, D64_XC_LE);
18797 + else
18798 + OR_REG(&di->d32txregs->control, XC_LE);
18799 +}
18800 +
18801 +void
18802 +dma_rxinit(dma_info_t *di)
18803 +{
18804 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
18805 +
18806 + di->rxin = di->rxout = 0;
18807 +
18808 + /* clear rx descriptor ring */
18809 + if (DMA64_ENAB(di)) {
18810 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
18811 + dma_rxenable(di);
18812 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
18813 + } else {
18814 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
18815 + dma_rxenable(di);
18816 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
18817 + }
18818 +}
18819 +
18820 +void
18821 +dma_rxenable(dma_info_t *di)
18822 +{
18823 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
18824 + if (DMA64_ENAB(di))
18825 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
18826 + else
18827 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
18828 +}
18829 +
18830 +bool
18831 +dma_rxenabled(dma_info_t *di)
18832 +{
18833 + uint32 rc;
18834 +
18835 + if (DMA64_ENAB(di)) {
18836 + rc = R_REG(&di->d64rxregs->control);
18837 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
18838 + } else {
18839 + rc = R_REG(&di->d32rxregs->control);
18840 + return ((rc != 0xffffffff) && (rc & RC_RE));
18841 + }
18842 +}
18843 +
18844 +
18845 +/* !! tx entry routine */
18846 +int
18847 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
18848 +{
18849 + if (DMA64_ENAB(di)) {
18850 + return dma64_txfast(di, p0, coreflags);
18851 + } else {
18852 + return dma32_txfast(di, p0, coreflags);
18853 + }
18854 +}
18855 +
18856 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
18857 +void*
18858 +dma_rx(dma_info_t *di)
18859 +{
18860 + void *p;
18861 + uint len;
18862 + int skiplen = 0;
18863 +
18864 + while ((p = dma_getnextrxp(di, FALSE))) {
18865 + /* skip giant packets which span multiple rx descriptors */
18866 + if (skiplen > 0) {
18867 + skiplen -= di->rxbufsize;
18868 + if (skiplen < 0)
18869 + skiplen = 0;
18870 + PKTFREE(di->osh, p, FALSE);
18871 + continue;
18872 + }
18873 +
18874 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
18875 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
18876 +
18877 + /* bad frame length check */
18878 + if (len > (di->rxbufsize - di->rxoffset)) {
18879 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
18880 + if (len > 0)
18881 + skiplen = len - (di->rxbufsize - di->rxoffset);
18882 + PKTFREE(di->osh, p, FALSE);
18883 + di->hnddma.rxgiants++;
18884 + continue;
18885 + }
18886 +
18887 + /* set actual length */
18888 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
18889 +
18890 + break;
18891 + }
18892 +
18893 + return (p);
18894 +}
18895 +
18896 +/* post receive buffers */
18897 +void
18898 +dma_rxfill(dma_info_t *di)
18899 +{
18900 + void *p;
18901 + uint rxin, rxout;
18902 + uint32 ctrl;
18903 + uint n;
18904 + uint i;
18905 + uint32 pa;
18906 + uint rxbufsize;
18907 +
18908 + /*
18909 + * Determine how many receive buffers we're lacking
18910 + * from the full complement, allocate, initialize,
18911 + * and post them, then update the chip rx lastdscr.
18912 + */
18913 +
18914 + rxin = di->rxin;
18915 + rxout = di->rxout;
18916 + rxbufsize = di->rxbufsize;
18917 +
18918 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
18919 +
18920 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
18921 +
18922 + for (i = 0; i < n; i++) {
18923 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
18924 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
18925 + di->hnddma.rxnobuf++;
18926 + break;
18927 + }
18928 +
18929 + /* Do a cached write instead of uncached write since DMA_MAP
18930 + * will flush the cache. */
18931 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
18932 +
18933 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
18934 + ASSERT(ISALIGNED(pa, 4));
18935 +
18936 + /* save the free packet pointer */
18937 + ASSERT(di->rxp[rxout] == NULL);
18938 + di->rxp[rxout] = p;
18939 +
18940 + if (DMA64_ENAB(di)) {
18941 + /* prep the descriptor control value */
18942 + if (rxout == (di->nrxd - 1))
18943 + ctrl = CTRL_EOT;
18944 +
18945 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
18946 + } else {
18947 + /* prep the descriptor control value */
18948 + ctrl = rxbufsize;
18949 + if (rxout == (di->nrxd - 1))
18950 + ctrl |= CTRL_EOT;
18951 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
18952 + }
18953 +
18954 + rxout = NEXTRXD(rxout);
18955 + }
18956 +
18957 + di->rxout = rxout;
18958 +
18959 + /* update the chip lastdscr pointer */
18960 + if (DMA64_ENAB(di)) {
18961 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
18962 + } else {
18963 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
18964 + }
18965 +}
18966 +
18967 +void
18968 +dma_txreclaim(dma_info_t *di, bool forceall)
18969 +{
18970 + void *p;
18971 +
18972 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
18973 +
18974 + while ((p = dma_getnexttxp(di, forceall)))
18975 + PKTFREE(di->osh, p, TRUE);
18976 +}
18977 +
18978 +/*
18979 + * Reclaim next completed txd (txds if using chained buffers) and
18980 + * return associated packet.
18981 + * If 'force' is true, reclaim txd(s) and return associated packet
18982 + * regardless of the value of the hardware "curr" pointer.
18983 + */
18984 +void*
18985 +dma_getnexttxp(dma_info_t *di, bool forceall)
18986 +{
18987 + if (DMA64_ENAB(di)) {
18988 + return dma64_getnexttxp(di, forceall);
18989 + } else {
18990 + return dma32_getnexttxp(di, forceall);
18991 + }
18992 +}
18993 +
18994 +/* like getnexttxp but no reclaim */
18995 +void*
18996 +dma_peeknexttxp(dma_info_t *di)
18997 +{
18998 + uint end, i;
18999 +
19000 + if (DMA64_ENAB(di)) {
19001 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
19002 + } else {
19003 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
19004 + }
19005 +
19006 + for (i = di->txin; i != end; i = NEXTTXD(i))
19007 + if (di->txp[i])
19008 + return (di->txp[i]);
19009 +
19010 + return (NULL);
19011 +}
19012 +
19013 +/*
19014 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
19015 + */
19016 +void
19017 +dma_txrotate(di_t *di)
19018 +{
19019 + if (DMA64_ENAB(di)) {
19020 + dma64_txrotate(di);
19021 + } else {
19022 + dma32_txrotate(di);
19023 + }
19024 +}
19025 +
19026 +void
19027 +dma_rxreclaim(dma_info_t *di)
19028 +{
19029 + void *p;
19030 +
19031 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
19032 +
19033 + while ((p = dma_getnextrxp(di, TRUE)))
19034 + PKTFREE(di->osh, p, FALSE);
19035 +}
19036 +
19037 +void *
19038 +dma_getnextrxp(dma_info_t *di, bool forceall)
19039 +{
19040 + if (DMA64_ENAB(di)) {
19041 + return dma64_getnextrxp(di, forceall);
19042 + } else {
19043 + return dma32_getnextrxp(di, forceall);
19044 + }
19045 +}
19046 +
19047 +uintptr
19048 +dma_getvar(dma_info_t *di, char *name)
19049 +{
19050 + if (!strcmp(name, "&txavail"))
19051 + return ((uintptr) &di->txavail);
19052 + else {
19053 + ASSERT(0);
19054 + }
19055 + return (0);
19056 +}
19057 +
19058 +void
19059 +dma_txblock(dma_info_t *di)
19060 +{
19061 + di->txavail = 0;
19062 +}
19063 +
19064 +void
19065 +dma_txunblock(dma_info_t *di)
19066 +{
19067 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19068 +}
19069 +
19070 +uint
19071 +dma_txactive(dma_info_t *di)
19072 +{
19073 + return (NTXDACTIVE(di->txin, di->txout));
19074 +}
19075 +
19076 +void
19077 +dma_rxpiomode(dma32regs_t *regs)
19078 +{
19079 + W_REG(&regs->control, RC_FM);
19080 +}
19081 +
19082 +void
19083 +dma_txpioloopback(dma32regs_t *regs)
19084 +{
19085 + OR_REG(&regs->control, XC_LE);
19086 +}
19087 +
19088 +
19089 +
19090 +
19091 +/*** 32 bits DMA non-inline functions ***/
19092 +static bool
19093 +dma32_alloc(dma_info_t *di, uint direction)
19094 +{
19095 + uint size;
19096 + uint ddlen;
19097 + void *va;
19098 +
19099 + ddlen = sizeof (dma32dd_t);
19100 +
19101 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
19102 +
19103 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
19104 + size += D32RINGALIGN;
19105 +
19106 +
19107 + if (direction == DMA_TX) {
19108 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
19109 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
19110 + return FALSE;
19111 + }
19112 +
19113 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
19114 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
19115 + di->txdpa += di->txdalign;
19116 + di->txdalloc = size;
19117 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
19118 + } else {
19119 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
19120 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
19121 + return FALSE;
19122 + }
19123 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
19124 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
19125 + di->rxdpa += di->rxdalign;
19126 + di->rxdalloc = size;
19127 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
19128 + }
19129 +
19130 + return TRUE;
19131 +}
19132 +
19133 +static void
19134 +dma32_txreset(dma_info_t *di)
19135 +{
19136 + uint32 status;
19137 +
19138 + /* suspend tx DMA first */
19139 + W_REG(&di->d32txregs->control, XC_SE);
19140 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
19141 + status != XS_XS_IDLE &&
19142 + status != XS_XS_STOPPED,
19143 + 10000);
19144 +
19145 + W_REG(&di->d32txregs->control, 0);
19146 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
19147 + 10000);
19148 +
19149 + if (status != XS_XS_DISABLED) {
19150 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
19151 + }
19152 +
19153 + /* wait for the last transaction to complete */
19154 + OSL_DELAY(300);
19155 +}
19156 +
19157 +static void
19158 +dma32_rxreset(dma_info_t *di)
19159 +{
19160 + uint32 status;
19161 +
19162 + W_REG(&di->d32rxregs->control, 0);
19163 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
19164 + 10000);
19165 +
19166 + if (status != RS_RS_DISABLED) {
19167 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
19168 + }
19169 +}
19170 +
19171 +static bool
19172 +dma32_txsuspendedidle(dma_info_t *di)
19173 +{
19174 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
19175 + return 0;
19176 +
19177 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
19178 + return 0;
19179 +
19180 + OSL_DELAY(2);
19181 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
19182 +}
19183 +
19184 +/*
19185 + * supports full 32bit dma engine buffer addressing so
19186 + * dma buffers can cross 4 Kbyte page boundaries.
19187 + */
19188 +static int
19189 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
19190 +{
19191 + void *p, *next;
19192 + uchar *data;
19193 + uint len;
19194 + uint txout;
19195 + uint32 ctrl;
19196 + uint32 pa;
19197 +
19198 + DMA_TRACE(("%s: dma_txfast\n", di->name));
19199 +
19200 + txout = di->txout;
19201 + ctrl = 0;
19202 +
19203 + /*
19204 + * Walk the chain of packet buffers
19205 + * allocating and initializing transmit descriptor entries.
19206 + */
19207 + for (p = p0; p; p = next) {
19208 + data = PKTDATA(di->osh, p);
19209 + len = PKTLEN(di->osh, p);
19210 + next = PKTNEXT(di->osh, p);
19211 +
19212 + /* return nonzero if out of tx descriptors */
19213 + if (NEXTTXD(txout) == di->txin)
19214 + goto outoftxd;
19215 +
19216 + if (len == 0)
19217 + continue;
19218 +
19219 + /* get physical address of buffer start */
19220 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
19221 +
19222 + /* build the descriptor control value */
19223 + ctrl = len & CTRL_BC_MASK;
19224 +
19225 + ctrl |= coreflags;
19226 +
19227 + if (p == p0)
19228 + ctrl |= CTRL_SOF;
19229 + if (next == NULL)
19230 + ctrl |= (CTRL_IOC | CTRL_EOF);
19231 + if (txout == (di->ntxd - 1))
19232 + ctrl |= CTRL_EOT;
19233 +
19234 + if (DMA64_ENAB(di)) {
19235 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
19236 + } else {
19237 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
19238 + }
19239 +
19240 + ASSERT(di->txp[txout] == NULL);
19241 +
19242 + txout = NEXTTXD(txout);
19243 + }
19244 +
19245 + /* if last txd eof not set, fix it */
19246 + if (!(ctrl & CTRL_EOF))
19247 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
19248 +
19249 + /* save the packet */
19250 + di->txp[PREVTXD(txout)] = p0;
19251 +
19252 + /* bump the tx descriptor index */
19253 + di->txout = txout;
19254 +
19255 + /* kick the chip */
19256 + if (DMA64_ENAB(di)) {
19257 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
19258 + } else {
19259 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
19260 + }
19261 +
19262 + /* tx flow control */
19263 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19264 +
19265 + return (0);
19266 +
19267 + outoftxd:
19268 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
19269 + PKTFREE(di->osh, p0, TRUE);
19270 + di->txavail = 0;
19271 + di->hnddma.txnobuf++;
19272 + return (-1);
19273 +}
19274 +
19275 +static void*
19276 +dma32_getnexttxp(dma_info_t *di, bool forceall)
19277 +{
19278 + uint start, end, i;
19279 + void *txp;
19280 +
19281 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
19282 +
19283 + txp = NULL;
19284 +
19285 + start = di->txin;
19286 + if (forceall)
19287 + end = di->txout;
19288 + else
19289 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
19290 +
19291 + if ((start == 0) && (end > di->txout))
19292 + goto bogus;
19293 +
19294 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
19295 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
19296 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
19297 +
19298 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
19299 + txp = di->txp[i];
19300 + di->txp[i] = NULL;
19301 + }
19302 +
19303 + di->txin = i;
19304 +
19305 + /* tx flow control */
19306 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19307 +
19308 + return (txp);
19309 +
19310 +bogus:
19311 +/*
19312 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
19313 + start, end, di->txout, forceall));
19314 +*/
19315 + return (NULL);
19316 +}
19317 +
19318 +static void *
19319 +dma32_getnextrxp(dma_info_t *di, bool forceall)
19320 +{
19321 + uint i;
19322 + void *rxp;
19323 +
19324 + /* if forcing, dma engine must be disabled */
19325 + ASSERT(!forceall || !dma_rxenabled(di));
19326 +
19327 + i = di->rxin;
19328 +
19329 + /* return if no packets posted */
19330 + if (i == di->rxout)
19331 + return (NULL);
19332 +
19333 + /* ignore curr if forceall */
19334 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
19335 + return (NULL);
19336 +
19337 + /* get the packet pointer that corresponds to the rx descriptor */
19338 + rxp = di->rxp[i];
19339 + ASSERT(rxp);
19340 + di->rxp[i] = NULL;
19341 +
19342 + /* clear this packet from the descriptor ring */
19343 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
19344 + di->rxbufsize, DMA_RX, rxp);
19345 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
19346 +
19347 + di->rxin = NEXTRXD(i);
19348 +
19349 + return (rxp);
19350 +}
19351 +
19352 +static void
19353 +dma32_txrotate(di_t *di)
19354 +{
19355 + uint ad;
19356 + uint nactive;
19357 + uint rot;
19358 + uint old, new;
19359 + uint32 w;
19360 + uint first, last;
19361 +
19362 + ASSERT(dma_txsuspendedidle(di));
19363 +
19364 + nactive = dma_txactive(di);
19365 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
19366 + rot = TXD(ad - di->txin);
19367 +
19368 + ASSERT(rot < di->ntxd);
19369 +
19370 + /* full-ring case is a lot harder - don't worry about this */
19371 + if (rot >= (di->ntxd - nactive)) {
19372 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
19373 + return;
19374 + }
19375 +
19376 + first = di->txin;
19377 + last = PREVTXD(di->txout);
19378 +
19379 + /* move entries starting at last and moving backwards to first */
19380 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
19381 + new = TXD(old + rot);
19382 +
19383 + /*
19384 + * Move the tx dma descriptor.
19385 + * EOT is set only in the last entry in the ring.
19386 + */
19387 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
19388 + if (new == (di->ntxd - 1))
19389 + w |= CTRL_EOT;
19390 + W_SM(&di->txd32[new].ctrl, w);
19391 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
19392 +
19393 + /* zap the old tx dma descriptor address field */
19394 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
19395 +
19396 + /* move the corresponding txp[] entry */
19397 + ASSERT(di->txp[new] == NULL);
19398 + di->txp[new] = di->txp[old];
19399 + di->txp[old] = NULL;
19400 + }
19401 +
19402 + /* update txin and txout */
19403 + di->txin = ad;
19404 + di->txout = TXD(di->txout + rot);
19405 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19406 +
19407 + /* kick the chip */
19408 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
19409 +}
19410 +
19411 +/*** 64 bits DMA non-inline functions ***/
19412 +
19413 +#ifdef BCMDMA64
19414 +
19415 +static bool
19416 +dma64_alloc(dma_info_t *di, uint direction)
19417 +{
19418 + uint size;
19419 + uint ddlen;
19420 + uint32 alignbytes;
19421 + void *va;
19422 +
19423 + ddlen = sizeof (dma64dd_t);
19424 +
19425 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
19426 +
19427 + alignbytes = di->dma64align;
19428 +
19429 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
19430 + size += alignbytes;
19431 +
19432 +
19433 + if (direction == DMA_TX) {
19434 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
19435 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
19436 + return FALSE;
19437 + }
19438 +
19439 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
19440 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
19441 + di->txdpa += di->txdalign;
19442 + di->txdalloc = size;
19443 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
19444 + } else {
19445 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
19446 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
19447 + return FALSE;
19448 + }
19449 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
19450 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
19451 + di->rxdpa += di->rxdalign;
19452 + di->rxdalloc = size;
19453 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
19454 + }
19455 +
19456 + return TRUE;
19457 +}
19458 +
19459 +static void
19460 +dma64_txreset(dma_info_t *di)
19461 +{
19462 + uint32 status;
19463 +
19464 + /* suspend tx DMA first */
19465 + W_REG(&di->d64txregs->control, D64_XC_SE);
19466 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
19467 + status != D64_XS0_XS_IDLE &&
19468 + status != D64_XS0_XS_STOPPED,
19469 + 10000);
19470 +
19471 + W_REG(&di->d64txregs->control, 0);
19472 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
19473 + 10000);
19474 +
19475 + if (status != D64_XS0_XS_DISABLED) {
19476 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
19477 + }
19478 +
19479 + /* wait for the last transaction to complete */
19480 + OSL_DELAY(300);
19481 +}
19482 +
19483 +static void
19484 +dma64_rxreset(dma_info_t *di)
19485 +{
19486 + uint32 status;
19487 +
19488 + W_REG(&di->d64rxregs->control, 0);
19489 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
19490 + 10000);
19491 +
19492 + if (status != D64_RS0_RS_DISABLED) {
19493 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
19494 + }
19495 +}
19496 +
19497 +static bool
19498 +dma64_txsuspendedidle(dma_info_t *di)
19499 +{
19500 +
19501 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
19502 + return 0;
19503 +
19504 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
19505 + return 1;
19506 +
19507 + return 0;
19508 +}
19509 +
19510 +/*
19511 + * supports full 32bit dma engine buffer addressing so
19512 + * dma buffers can cross 4 Kbyte page boundaries.
19513 + */
19514 +static int
19515 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
19516 +{
19517 + void *p, *next;
19518 + uchar *data;
19519 + uint len;
19520 + uint txout;
19521 + uint32 flags;
19522 + uint32 pa;
19523 +
19524 + DMA_TRACE(("%s: dma_txfast\n", di->name));
19525 +
19526 + txout = di->txout;
19527 + flags = 0;
19528 +
19529 + /*
19530 + * Walk the chain of packet buffers
19531 + * allocating and initializing transmit descriptor entries.
19532 + */
19533 + for (p = p0; p; p = next) {
19534 + data = PKTDATA(di->osh, p);
19535 + len = PKTLEN(di->osh, p);
19536 + next = PKTNEXT(di->osh, p);
19537 +
19538 + /* return nonzero if out of tx descriptors */
19539 + if (NEXTTXD(txout) == di->txin)
19540 + goto outoftxd;
19541 +
19542 + if (len == 0)
19543 + continue;
19544 +
19545 + /* get physical address of buffer start */
19546 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
19547 +
19548 + flags = coreflags;
19549 +
19550 + if (p == p0)
19551 + flags |= D64_CTRL1_SOF;
19552 + if (next == NULL)
19553 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
19554 + if (txout == (di->ntxd - 1))
19555 + flags |= D64_CTRL1_EOT;
19556 +
19557 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
19558 +
19559 + ASSERT(di->txp[txout] == NULL);
19560 +
19561 + txout = NEXTTXD(txout);
19562 + }
19563 +
19564 + /* if last txd eof not set, fix it */
19565 + if (!(flags & D64_CTRL1_EOF))
19566 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
19567 +
19568 + /* save the packet */
19569 + di->txp[PREVTXD(txout)] = p0;
19570 +
19571 + /* bump the tx descriptor index */
19572 + di->txout = txout;
19573 +
19574 + /* kick the chip */
19575 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
19576 +
19577 + /* tx flow control */
19578 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19579 +
19580 + return (0);
19581 +
19582 +outoftxd:
19583 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
19584 + PKTFREE(di->osh, p0, TRUE);
19585 + di->txavail = 0;
19586 + di->hnddma.txnobuf++;
19587 + return (-1);
19588 +}
19589 +
19590 +static void*
19591 +dma64_getnexttxp(dma_info_t *di, bool forceall)
19592 +{
19593 + uint start, end, i;
19594 + void *txp;
19595 +
19596 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
19597 +
19598 + txp = NULL;
19599 +
19600 + start = di->txin;
19601 + if (forceall)
19602 + end = di->txout;
19603 + else
19604 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
19605 +
19606 + if ((start == 0) && (end > di->txout))
19607 + goto bogus;
19608 +
19609 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
19610 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
19611 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
19612 +
19613 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
19614 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
19615 +
19616 + txp = di->txp[i];
19617 + di->txp[i] = NULL;
19618 + }
19619 +
19620 + di->txin = i;
19621 +
19622 + /* tx flow control */
19623 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19624 +
19625 + return (txp);
19626 +
19627 +bogus:
19628 +/*
19629 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
19630 + start, end, di->txout, forceall));
19631 +*/
19632 + return (NULL);
19633 +}
19634 +
19635 +static void *
19636 +dma64_getnextrxp(dma_info_t *di, bool forceall)
19637 +{
19638 + uint i;
19639 + void *rxp;
19640 +
19641 + /* if forcing, dma engine must be disabled */
19642 + ASSERT(!forceall || !dma_rxenabled(di));
19643 +
19644 + i = di->rxin;
19645 +
19646 + /* return if no packets posted */
19647 + if (i == di->rxout)
19648 + return (NULL);
19649 +
19650 + /* ignore curr if forceall */
19651 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
19652 + return (NULL);
19653 +
19654 + /* get the packet pointer that corresponds to the rx descriptor */
19655 + rxp = di->rxp[i];
19656 + ASSERT(rxp);
19657 + di->rxp[i] = NULL;
19658 +
19659 + /* clear this packet from the descriptor ring */
19660 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
19661 + di->rxbufsize, DMA_RX, rxp);
19662 +
19663 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
19664 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
19665 +
19666 + di->rxin = NEXTRXD(i);
19667 +
19668 + return (rxp);
19669 +}
19670 +
19671 +static void
19672 +dma64_txrotate(di_t *di)
19673 +{
19674 + uint ad;
19675 + uint nactive;
19676 + uint rot;
19677 + uint old, new;
19678 + uint32 w;
19679 + uint first, last;
19680 +
19681 + ASSERT(dma_txsuspendedidle(di));
19682 +
19683 + nactive = dma_txactive(di);
19684 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
19685 + rot = TXD(ad - di->txin);
19686 +
19687 + ASSERT(rot < di->ntxd);
19688 +
19689 + /* full-ring case is a lot harder - don't worry about this */
19690 + if (rot >= (di->ntxd - nactive)) {
19691 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
19692 + return;
19693 + }
19694 +
19695 + first = di->txin;
19696 + last = PREVTXD(di->txout);
19697 +
19698 + /* move entries starting at last and moving backwards to first */
19699 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
19700 + new = TXD(old + rot);
19701 +
19702 + /*
19703 + * Move the tx dma descriptor.
19704 + * EOT is set only in the last entry in the ring.
19705 + */
19706 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
19707 + if (new == (di->ntxd - 1))
19708 + w |= D64_CTRL1_EOT;
19709 + W_SM(&di->txd64[new].ctrl1, w);
19710 +
19711 + w = R_SM(&di->txd64[old].ctrl2);
19712 + W_SM(&di->txd64[new].ctrl2, w);
19713 +
19714 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
19715 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
19716 +
19717 + /* zap the old tx dma descriptor address field */
19718 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
19719 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
19720 +
19721 + /* move the corresponding txp[] entry */
19722 + ASSERT(di->txp[new] == NULL);
19723 + di->txp[new] = di->txp[old];
19724 + di->txp[old] = NULL;
19725 + }
19726 +
19727 + /* update txin and txout */
19728 + di->txin = ad;
19729 + di->txout = TXD(di->txout + rot);
19730 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
19731 +
19732 + /* kick the chip */
19733 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
19734 +}
19735 +
19736 +#endif
19737 +
19738 diff -Naur linux.old/drivers/net/wl2/hnddma.h linux.dev/drivers/net/wl2/hnddma.h
19739 --- linux.old/drivers/net/wl2/hnddma.h 1970-01-01 01:00:00.000000000 +0100
19740 +++ linux.dev/drivers/net/wl2/hnddma.h 2006-04-06 16:32:44.000000000 +0200
19741 @@ -0,0 +1,71 @@
19742 +/*
19743 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
19744 + * This supports the following chips: BCM42xx, 44xx, 47xx .
19745 + *
19746 + * Copyright 2005, Broadcom Corporation
19747 + * All Rights Reserved.
19748 + *
19749 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19750 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19751 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19752 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19753 + * $Id$
19754 + */
19755 +
19756 +#ifndef _hnddma_h_
19757 +#define _hnddma_h_
19758 +
19759 +/* export structure */
19760 +typedef volatile struct {
19761 + /* rx error counters */
19762 + uint rxgiants; /* rx giant frames */
19763 + uint rxnobuf; /* rx out of dma descriptors */
19764 + /* tx error counters */
19765 + uint txnobuf; /* tx out of dma descriptors */
19766 +} hnddma_t;
19767 +
19768 +#ifndef di_t
19769 +#define di_t void
19770 +#endif
19771 +
19772 +#ifndef osl_t
19773 +#define osl_t void
19774 +#endif
19775 +
19776 +/* externs */
19777 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
19778 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
19779 +extern void dma_detach(di_t *di);
19780 +extern void dma_txreset(di_t *di);
19781 +extern void dma_rxreset(di_t *di);
19782 +extern void dma_txinit(di_t *di);
19783 +extern bool dma_txenabled(di_t *di);
19784 +extern void dma_rxinit(di_t *di);
19785 +extern void dma_rxenable(di_t *di);
19786 +extern bool dma_rxenabled(di_t *di);
19787 +extern void dma_txsuspend(di_t *di);
19788 +extern void dma_txresume(di_t *di);
19789 +extern bool dma_txsuspended(di_t *di);
19790 +extern bool dma_txsuspendedidle(di_t *di);
19791 +extern bool dma_txstopped(di_t *di);
19792 +extern bool dma_rxstopped(di_t *di);
19793 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
19794 +extern void dma_fifoloopbackenable(di_t *di);
19795 +extern void *dma_rx(di_t *di);
19796 +extern void dma_rxfill(di_t *di);
19797 +extern void dma_txreclaim(di_t *di, bool forceall);
19798 +extern void dma_rxreclaim(di_t *di);
19799 +extern uintptr dma_getvar(di_t *di, char *name);
19800 +extern void *dma_getnexttxp(di_t *di, bool forceall);
19801 +extern void *dma_peeknexttxp(di_t *di);
19802 +extern void *dma_getnextrxp(di_t *di, bool forceall);
19803 +extern void dma_txblock(di_t *di);
19804 +extern void dma_txunblock(di_t *di);
19805 +extern uint dma_txactive(di_t *di);
19806 +extern void dma_txrotate(di_t *di);
19807 +
19808 +extern void dma_rxpiomode(dma32regs_t *);
19809 +extern void dma_txpioloopback(dma32regs_t *);
19810 +
19811 +
19812 +#endif /* _hnddma_h_ */
19813 diff -Naur linux.old/drivers/net/wl2/pktq.h linux.dev/drivers/net/wl2/pktq.h
19814 --- linux.old/drivers/net/wl2/pktq.h 1970-01-01 01:00:00.000000000 +0100
19815 +++ linux.dev/drivers/net/wl2/pktq.h 2006-04-06 17:33:02.000000000 +0200
19816 @@ -0,0 +1,83 @@
19817 +/*
19818 + * Misc useful os-independent macros and functions.
19819 + *
19820 + * Copyright 2005, Broadcom Corporation
19821 + * All Rights Reserved.
19822 + *
19823 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19824 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19825 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19826 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19827 + * $Id$
19828 + */
19829 +
19830 +#ifndef _pktq_h_
19831 +#define _pktq_h_
19832 +
19833 +/*** driver-only section ***/
19834 +#ifdef BCMDRIVER
19835 +
19836 +/* osl packet chain functions */
19837 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
19838 +extern uint pkttotlen(osl_t *osh, void *);
19839 +
19840 +#define pktenq(pq, p) pktq_penq((pq), 0, (p)) /* legacy */
19841 +#define pktdeq(pq) pktq_pdeq((pq), 0) /* legacy */
19842 +
19843 +/* osl multi-precedence packet queue */
19844 +
19845 +#define PKTQ_LEN_DEFAULT 128
19846 +#define PKTQ_MAX_PREC 8
19847 +struct pktq_prec {
19848 + void *head; /* first packet to dequeue */
19849 + void *tail; /* last packet to dequeue */
19850 + uint16 len; /* number of queued packets */
19851 + uint16 max; /* maximum number of queued packets */
19852 +};
19853 +
19854 +struct pktq {
19855 + struct pktq_prec q[PKTQ_MAX_PREC];
19856 + uint16 num_prec; /* number of precedences in use */
19857 + uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
19858 + uint16 max; /* total max packets */
19859 + uint16 len; /* total number of packets */
19860 +};
19861 +
19862 +/* operations on a specific precedence in packet queue */
19863 +
19864 +#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
19865 +#define pktq_plen(pq, prec) ((pq)->q[prec].len)
19866 +#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
19867 +#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
19868 +#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
19869 +
19870 +#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
19871 +#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
19872 +
19873 +extern void *pktq_penq(struct pktq *pq, int prec, void *p);
19874 +extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
19875 +extern void *pktq_pdeq(struct pktq *pq, int prec);
19876 +extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
19877 +
19878 +/* operations on packet queue as a whole */
19879 +
19880 +extern void pktq_init(struct pktq *pq, int num_prec, int max);
19881 +
19882 +#define pktq_len(pq) ((int)(pq)->len)
19883 +#define pktq_max(pq) ((int)(pq)->max)
19884 +#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
19885 +#define pktq_full(pq) ((pq)->len >= (pq)->max)
19886 +#define pktq_empty(pq) ((pq)->len == 0)
19887 +
19888 +extern void *pktq_deq(struct pktq *pq, int *prec_out);
19889 +extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
19890 +extern void *pktq_peek(struct pktq *pq, int *prec_out);
19891 +extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
19892 +
19893 +extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
19894 +extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
19895 +
19896 +#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
19897 +
19898 +#endif
19899 +#endif /* _pktq_h_ */
19900 diff -Naur linux.old/drivers/net/wl2/sbhnddma.h linux.dev/drivers/net/wl2/sbhnddma.h
19901 --- linux.old/drivers/net/wl2/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
19902 +++ linux.dev/drivers/net/wl2/sbhnddma.h 2006-04-06 16:32:44.000000000 +0200
19903 @@ -0,0 +1,312 @@
19904 +/*
19905 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
19906 + * This supports the following chips: BCM42xx, 44xx, 47xx .
19907 + *
19908 + * Copyright 2005, Broadcom Corporation
19909 + * All Rights Reserved.
19910 + *
19911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19915 + * $Id$
19916 + */
19917 +
19918 +#ifndef _sbhnddma_h_
19919 +#define _sbhnddma_h_
19920 +
19921 +
19922 +/* 2byte-wide pio register set per channel(xmt or rcv) */
19923 +typedef volatile struct {
19924 + uint16 fifocontrol;
19925 + uint16 fifodata;
19926 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
19927 + uint16 PAD;
19928 +} pio2regs_t;
19929 +
19930 +/* a pair of pio channels(tx and rx) */
19931 +typedef volatile struct {
19932 + pio2regs_t tx;
19933 + pio2regs_t rx;
19934 +} pio2regp_t;
19935 +
19936 +/* 4byte-wide pio register set per channel(xmt or rcv) */
19937 +typedef volatile struct {
19938 + uint32 fifocontrol;
19939 + uint32 fifodata;
19940 +} pio4regs_t;
19941 +
19942 +/* a pair of pio channels(tx and rx) */
19943 +typedef volatile struct {
19944 + pio4regs_t tx;
19945 + pio4regs_t rx;
19946 +} pio4regp_t;
19947 +
19948 +
19949 +
19950 +/* DMA structure:
19951 + * support two DMA engines: 32 bits address or 64 bit addressing
19952 + * basic DMA register set is per channel(transmit or receive)
19953 + * a pair of channels is defined for convenience
19954 + */
19955 +
19956 +
19957 +/*** 32 bits addressing ***/
19958 +
19959 +/* dma registers per channel(xmt or rcv) */
19960 +typedef volatile struct {
19961 + uint32 control; /* enable, et al */
19962 + uint32 addr; /* descriptor ring base address (4K aligned) */
19963 + uint32 ptr; /* last descriptor posted to chip */
19964 + uint32 status; /* current active descriptor, et al */
19965 +} dma32regs_t;
19966 +
19967 +typedef volatile struct {
19968 + dma32regs_t xmt; /* dma tx channel */
19969 + dma32regs_t rcv; /* dma rx channel */
19970 +} dma32regp_t;
19971 +
19972 +typedef volatile struct { /* diag access */
19973 + uint32 fifoaddr; /* diag address */
19974 + uint32 fifodatalow; /* low 32bits of data */
19975 + uint32 fifodatahigh; /* high 32bits of data */
19976 + uint32 pad; /* reserved */
19977 +} dma32diag_t;
19978 +
19979 +/*
19980 + * DMA Descriptor
19981 + * Descriptors are only read by the hardware, never written back.
19982 + */
19983 +typedef volatile struct {
19984 + uint32 ctrl; /* misc control bits & bufcount */
19985 + uint32 addr; /* data buffer address */
19986 +} dma32dd_t;
19987 +
19988 +/*
19989 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
19990 + */
19991 +#define D32MAXRINGSZ 4096
19992 +#define D32RINGALIGN 4096
19993 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
19994 +
19995 +/* transmit channel control */
19996 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
19997 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
19998 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
19999 +#define XC_FL ((uint32)1 << 4) /* flush request */
20000 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
20001 +#define XC_AE_SHIFT 16
20002 +
20003 +/* transmit descriptor table pointer */
20004 +#define XP_LD_MASK 0xfff /* last valid descriptor */
20005 +
20006 +/* transmit channel status */
20007 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
20008 +#define XS_XS_MASK 0xf000 /* transmit state */
20009 +#define XS_XS_SHIFT 12
20010 +#define XS_XS_DISABLED 0x0000 /* disabled */
20011 +#define XS_XS_ACTIVE 0x1000 /* active */
20012 +#define XS_XS_IDLE 0x2000 /* idle wait */
20013 +#define XS_XS_STOPPED 0x3000 /* stopped */
20014 +#define XS_XS_SUSP 0x4000 /* suspend pending */
20015 +#define XS_XE_MASK 0xf0000 /* transmit errors */
20016 +#define XS_XE_SHIFT 16
20017 +#define XS_XE_NOERR 0x00000 /* no error */
20018 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
20019 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
20020 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
20021 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
20022 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
20023 +#define XS_AD_SHIFT 20
20024 +
20025 +/* receive channel control */
20026 +#define RC_RE ((uint32)1 << 0) /* receive enable */
20027 +#define RC_RO_MASK 0xfe /* receive frame offset */
20028 +#define RC_RO_SHIFT 1
20029 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
20030 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
20031 +#define RC_AE_SHIFT 16
20032 +
20033 +/* receive descriptor table pointer */
20034 +#define RP_LD_MASK 0xfff /* last valid descriptor */
20035 +
20036 +/* receive channel status */
20037 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
20038 +#define RS_RS_MASK 0xf000 /* receive state */
20039 +#define RS_RS_SHIFT 12
20040 +#define RS_RS_DISABLED 0x0000 /* disabled */
20041 +#define RS_RS_ACTIVE 0x1000 /* active */
20042 +#define RS_RS_IDLE 0x2000 /* idle wait */
20043 +#define RS_RS_STOPPED 0x3000 /* reserved */
20044 +#define RS_RE_MASK 0xf0000 /* receive errors */
20045 +#define RS_RE_SHIFT 16
20046 +#define RS_RE_NOERR 0x00000 /* no error */
20047 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
20048 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
20049 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
20050 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
20051 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
20052 +#define RS_AD_SHIFT 20
20053 +
20054 +/* fifoaddr */
20055 +#define FA_OFF_MASK 0xffff /* offset */
20056 +#define FA_SEL_MASK 0xf0000 /* select */
20057 +#define FA_SEL_SHIFT 16
20058 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
20059 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
20060 +#define FA_SEL_RDD 0x40000 /* receive dma data */
20061 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
20062 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
20063 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
20064 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
20065 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
20066 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
20067 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
20068 +
20069 +/* descriptor control flags */
20070 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
20071 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
20072 +#define CTRL_AE_SHIFT 16
20073 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
20074 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
20075 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
20076 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
20077 +
20078 +/* control flags in the range [27:20] are core-specific and not defined here */
20079 +#define CTRL_CORE_MASK 0x0ff00000
20080 +
20081 +/*** 64 bits addressing ***/
20082 +
20083 +/* dma registers per channel(xmt or rcv) */
20084 +typedef volatile struct {
20085 + uint32 control; /* enable, et al */
20086 + uint32 ptr; /* last descriptor posted to chip */
20087 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
20088 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
20089 + uint32 status0; /* current descriptor, xmt state */
20090 + uint32 status1; /* active descriptor, xmt error */
20091 +} dma64regs_t;
20092 +
20093 +typedef volatile struct {
20094 + dma64regs_t tx; /* dma64 tx channel */
20095 + dma64regs_t rx; /* dma64 rx channel */
20096 +} dma64regp_t;
20097 +
20098 +typedef volatile struct { /* diag access */
20099 + uint32 fifoaddr; /* diag address */
20100 + uint32 fifodatalow; /* low 32bits of data */
20101 + uint32 fifodatahigh; /* high 32bits of data */
20102 + uint32 pad; /* reserved */
20103 +} dma64diag_t;
20104 +
20105 +/*
20106 + * DMA Descriptor
20107 + * Descriptors are only read by the hardware, never written back.
20108 + */
20109 +typedef volatile struct {
20110 + uint32 ctrl1; /* misc control bits & bufcount */
20111 + uint32 ctrl2; /* buffer count and address extension */
20112 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
20113 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
20114 +} dma64dd_t;
20115 +
20116 +/*
20117 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
20118 + */
20119 +#define D64MAXRINGSZ 8192
20120 +#define D64RINGALIGN 8192
20121 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
20122 +
20123 +/* transmit channel control */
20124 +#define D64_XC_XE 0x00000001 /* transmit enable */
20125 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
20126 +#define D64_XC_LE 0x00000004 /* loopback enable */
20127 +#define D64_XC_FL 0x00000010 /* flush request */
20128 +#define D64_XC_AE 0x00110000 /* address extension bits */
20129 +#define D64_XC_AE_SHIFT 16
20130 +
20131 +/* transmit descriptor table pointer */
20132 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
20133 +
20134 +/* transmit channel status */
20135 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
20136 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
20137 +#define D64_XS0_XS_SHIFT 28
20138 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
20139 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
20140 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
20141 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
20142 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
20143 +
20144 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
20145 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
20146 +#define D64_XS1_XE_SHIFT 28
20147 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
20148 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
20149 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
20150 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
20151 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
20152 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
20153 +
20154 +/* receive channel control */
20155 +#define D64_RC_RE 0x00000001 /* receive enable */
20156 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
20157 +#define D64_RC_RO_SHIFT 1
20158 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
20159 +#define D64_RC_AE 0x00110000 /* address extension bits */
20160 +#define D64_RC_AE_SHIFT 16
20161 +
20162 +/* receive descriptor table pointer */
20163 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
20164 +
20165 +/* receive channel status */
20166 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
20167 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
20168 +#define D64_RS0_RS_SHIFT 28
20169 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
20170 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
20171 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
20172 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
20173 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
20174 +
20175 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
20176 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
20177 +#define D64_RS1_RE_SHIFT 28
20178 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
20179 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
20180 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
20181 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
20182 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
20183 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
20184 +
20185 +/* fifoaddr */
20186 +#define D64_FA_OFF_MASK 0xffff /* offset */
20187 +#define D64_FA_SEL_MASK 0xf0000 /* select */
20188 +#define D64_FA_SEL_SHIFT 16
20189 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
20190 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
20191 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
20192 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
20193 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
20194 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
20195 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
20196 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
20197 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
20198 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
20199 +
20200 +/* descriptor control flags 1 */
20201 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
20202 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
20203 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
20204 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
20205 +
20206 +/* descriptor control flags 2 */
20207 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
20208 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
20209 +#define D64_CTRL2_AE_SHIFT 16
20210 +
20211 +/* control flags in the range [27:20] are core-specific and not defined here */
20212 +#define D64_CTRL_CORE_MASK 0x0ff00000
20213 +
20214 +
20215 +#endif /* _sbhnddma_h_ */
20216 diff -Naur linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
20217 --- linux.old/drivers/parport/Config.in 2006-04-06 15:38:09.000000000 +0200
20218 +++ linux.dev/drivers/parport/Config.in 2006-04-06 15:34:15.000000000 +0200
20219 @@ -11,6 +11,7 @@
20220 tristate 'Parallel port support' CONFIG_PARPORT
20221 if [ "$CONFIG_PARPORT" != "n" ]; then
20222 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
20223 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
20224 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
20225 if [ "$CONFIG_SERIAL" = "m" ]; then
20226 define_tristate CONFIG_PARPORT_PC_CML1 m
20227 diff -Naur linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
20228 --- linux.old/drivers/parport/Makefile 2006-04-06 15:38:09.000000000 +0200
20229 +++ linux.dev/drivers/parport/Makefile 2006-04-06 15:34:15.000000000 +0200
20230 @@ -22,6 +22,7 @@
20231
20232 obj-$(CONFIG_PARPORT) += parport.o
20233 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
20234 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
20235 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
20236 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
20237 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
20238 diff -Naur linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
20239 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
20240 +++ linux.dev/drivers/parport/parport_splink.c 2006-04-06 15:34:15.000000000 +0200
20241 @@ -0,0 +1,345 @@
20242 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
20243 + *
20244 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
20245 + * Based on parport_pc source
20246 + */
20247 +
20248 +#include <linux/config.h>
20249 +#include <linux/module.h>
20250 +#include <linux/init.h>
20251 +#include <linux/ioport.h>
20252 +#include <linux/kernel.h>
20253 +#include <linux/slab.h>
20254 +#include <linux/parport.h>
20255 +#include <linux/parport_pc.h>
20256 +
20257 +#define SPLINK_ADDRESS 0xBF800010
20258 +
20259 +#undef DEBUG
20260 +
20261 +#ifdef DEBUG
20262 +#define DPRINTK printk
20263 +#else
20264 +#define DPRINTK(stuff...)
20265 +#endif
20266 +
20267 +
20268 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
20269 + * it doesn't do any extra masking. */
20270 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
20271 + unsigned char mask,
20272 + unsigned char val)
20273 +{
20274 + struct parport_pc_private *priv = p->physport->private_data;
20275 + unsigned char *io = (unsigned char *) p->base;
20276 + unsigned char ctr = priv->ctr;
20277 +#ifdef DEBUG_PARPORT
20278 + printk (KERN_DEBUG
20279 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
20280 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
20281 +#endif
20282 + ctr = (ctr & ~mask) ^ val;
20283 + ctr &= priv->ctr_writable; /* only write writable bits. */
20284 + *(io+2) = ctr;
20285 + priv->ctr = ctr; /* Update soft copy */
20286 + return ctr;
20287 +}
20288 +
20289 +
20290 +
20291 +static void parport_splink_data_forward (struct parport *p)
20292 +{
20293 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
20294 + __parport_splink_frob_control (p, 0x20, 0);
20295 +}
20296 +
20297 +static void parport_splink_data_reverse (struct parport *p)
20298 +{
20299 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
20300 + __parport_splink_frob_control (p, 0x20, 0x20);
20301 +}
20302 +
20303 +/*
20304 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
20305 +{
20306 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
20307 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
20308 +}
20309 +*/
20310 +
20311 +static void parport_splink_enable_irq(struct parport *p)
20312 +{
20313 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
20314 + __parport_splink_frob_control (p, 0x10, 0x10);
20315 +}
20316 +
20317 +static void parport_splink_disable_irq(struct parport *p)
20318 +{
20319 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
20320 + __parport_splink_frob_control (p, 0x10, 0);
20321 +}
20322 +
20323 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
20324 +{
20325 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
20326 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
20327 + if (dev->irq_func &&
20328 + dev->port->irq != PARPORT_IRQ_NONE)
20329 + /* Set ackIntEn */
20330 + s->u.pc.ctr |= 0x10;
20331 +}
20332 +
20333 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
20334 +{
20335 + const struct parport_pc_private *priv = p->physport->private_data;
20336 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
20337 + s->u.pc.ctr = priv->ctr;
20338 +}
20339 +
20340 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
20341 +{
20342 + struct parport_pc_private *priv = p->physport->private_data;
20343 + unsigned char *io = (unsigned char *) p->base;
20344 + unsigned char ctr = s->u.pc.ctr;
20345 +
20346 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
20347 + *(io+2) = ctr;
20348 + priv->ctr = ctr;
20349 +}
20350 +
20351 +static void parport_splink_setup_interrupt(void) {
20352 + return;
20353 +}
20354 +
20355 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
20356 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
20357 + unsigned char *io = (unsigned char *) p->base;
20358 + *io = d;
20359 +}
20360 +
20361 +static unsigned char parport_splink_read_data(struct parport *p) {
20362 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
20363 + unsigned char *io = (unsigned char *) p->base;
20364 + return *io;
20365 +}
20366 +
20367 +static void parport_splink_write_control(struct parport *p, unsigned char d)
20368 +{
20369 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
20370 + PARPORT_CONTROL_AUTOFD |
20371 + PARPORT_CONTROL_INIT |
20372 + PARPORT_CONTROL_SELECT);
20373 +
20374 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
20375 + /* Take this out when drivers have adapted to the newer interface. */
20376 + if (d & 0x20) {
20377 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
20378 + p->name, p->cad->name);
20379 + parport_splink_data_reverse (p);
20380 + }
20381 +
20382 + __parport_splink_frob_control (p, wm, d & wm);
20383 +}
20384 +
20385 +static unsigned char parport_splink_read_control(struct parport *p)
20386 +{
20387 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
20388 + PARPORT_CONTROL_AUTOFD |
20389 + PARPORT_CONTROL_INIT |
20390 + PARPORT_CONTROL_SELECT);
20391 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
20392 + const struct parport_pc_private *priv = p->physport->private_data;
20393 + return priv->ctr & wm; /* Use soft copy */
20394 +}
20395 +
20396 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
20397 + unsigned char val)
20398 +{
20399 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
20400 + PARPORT_CONTROL_AUTOFD |
20401 + PARPORT_CONTROL_INIT |
20402 + PARPORT_CONTROL_SELECT);
20403 +
20404 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
20405 + /* Take this out when drivers have adapted to the newer interface. */
20406 + if (mask & 0x20) {
20407 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
20408 + p->name, p->cad->name,
20409 + (val & 0x20) ? "reverse" : "forward");
20410 + if (val & 0x20)
20411 + parport_splink_data_reverse (p);
20412 + else
20413 + parport_splink_data_forward (p);
20414 + }
20415 +
20416 + /* Restrict mask and val to control lines. */
20417 + mask &= wm;
20418 + val &= wm;
20419 +
20420 + return __parport_splink_frob_control (p, mask, val);
20421 +}
20422 +
20423 +static unsigned char parport_splink_read_status(struct parport *p)
20424 +{
20425 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
20426 + unsigned char *io = (unsigned char *) p->base;
20427 + return *(io+1);
20428 +}
20429 +
20430 +static void parport_splink_inc_use_count(void)
20431 +{
20432 +#ifdef MODULE
20433 + MOD_INC_USE_COUNT;
20434 +#endif
20435 +}
20436 +
20437 +static void parport_splink_dec_use_count(void)
20438 +{
20439 +#ifdef MODULE
20440 + MOD_DEC_USE_COUNT;
20441 +#endif
20442 +}
20443 +
20444 +static struct parport_operations parport_splink_ops =
20445 +{
20446 + parport_splink_write_data,
20447 + parport_splink_read_data,
20448 +
20449 + parport_splink_write_control,
20450 + parport_splink_read_control,
20451 + parport_splink_frob_control,
20452 +
20453 + parport_splink_read_status,
20454 +
20455 + parport_splink_enable_irq,
20456 + parport_splink_disable_irq,
20457 +
20458 + parport_splink_data_forward,
20459 + parport_splink_data_reverse,
20460 +
20461 + parport_splink_init_state,
20462 + parport_splink_save_state,
20463 + parport_splink_restore_state,
20464 +
20465 + parport_splink_inc_use_count,
20466 + parport_splink_dec_use_count,
20467 +
20468 + parport_ieee1284_epp_write_data,
20469 + parport_ieee1284_epp_read_data,
20470 + parport_ieee1284_epp_write_addr,
20471 + parport_ieee1284_epp_read_addr,
20472 +
20473 + parport_ieee1284_ecp_write_data,
20474 + parport_ieee1284_ecp_read_data,
20475 + parport_ieee1284_ecp_write_addr,
20476 +
20477 + parport_ieee1284_write_compat,
20478 + parport_ieee1284_read_nibble,
20479 + parport_ieee1284_read_byte,
20480 +};
20481 +
20482 +/* --- Initialisation code -------------------------------- */
20483 +
20484 +static struct parport *parport_splink_probe_port (unsigned long int base)
20485 +{
20486 + struct parport_pc_private *priv;
20487 + struct parport_operations *ops;
20488 + struct parport *p;
20489 +
20490 + if (check_mem_region(base, 3)) {
20491 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
20492 + return NULL;
20493 + }
20494 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
20495 + if (!priv) {
20496 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
20497 + return NULL;
20498 + }
20499 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
20500 + if (!ops) {
20501 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
20502 + base);
20503 + kfree (priv);
20504 + return NULL;
20505 + }
20506 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
20507 + priv->ctr = 0xc;
20508 + priv->ctr_writable = 0xff;
20509 +
20510 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
20511 + PARPORT_DMA_NONE, ops))) {
20512 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
20513 + base);
20514 + kfree (priv);
20515 + kfree (ops);
20516 + return NULL;
20517 + }
20518 +
20519 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
20520 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
20521 + p->private_data = priv;
20522 +
20523 + parport_proc_register(p);
20524 + request_mem_region (p->base, 3, p->name);
20525 +
20526 + /* Done probing. Now put the port into a sensible start-up state. */
20527 + parport_splink_write_data(p, 0);
20528 + parport_splink_data_forward (p);
20529 +
20530 + /* Now that we've told the sharing engine about the port, and
20531 + found out its characteristics, let the high-level drivers
20532 + know about it. */
20533 + parport_announce_port (p);
20534 +
20535 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
20536 + base);
20537 + return p;
20538 +}
20539 +
20540 +static void parport_splink_unregister_port(struct parport *p) {
20541 + struct parport_pc_private *priv = p->private_data;
20542 + struct parport_operations *ops = p->ops;
20543 +
20544 + if (p->irq != PARPORT_IRQ_NONE)
20545 + free_irq(p->irq, p);
20546 + release_mem_region(p->base, 3);
20547 + parport_proc_unregister(p);
20548 + kfree (priv);
20549 + parport_unregister_port(p);
20550 + kfree (ops);
20551 +}
20552 +
20553 +
20554 +int parport_splink_init(void)
20555 +{
20556 + int ret;
20557 +
20558 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
20559 + parport_splink_setup_interrupt();
20560 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
20561 +
20562 + return ret;
20563 +}
20564 +
20565 +void parport_splink_cleanup(void) {
20566 + struct parport *p = parport_enumerate(), *tmp;
20567 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
20568 + if (p->size) {
20569 + if (p->modes & PARPORT_MODE_PCSPP) {
20570 + while(p) {
20571 + tmp = p->next;
20572 + parport_splink_unregister_port(p);
20573 + p = tmp;
20574 + }
20575 + }
20576 + }
20577 +}
20578 +
20579 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
20580 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
20581 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
20582 +MODULE_LICENSE("GPL");
20583 +
20584 +module_init(parport_splink_init)
20585 +module_exit(parport_splink_cleanup)
20586 +
20587 diff -Naur linux.old/drivers/pcmcia/Makefile linux.dev/drivers/pcmcia/Makefile
20588 --- linux.old/drivers/pcmcia/Makefile 2006-04-06 15:38:09.000000000 +0200
20589 +++ linux.dev/drivers/pcmcia/Makefile 2006-04-06 15:34:15.000000000 +0200
20590 @@ -74,6 +74,10 @@
20591 au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o
20592 au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
20593
20594 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
20595 +bcm4710_ss-objs := bcm4710_generic.o
20596 +bcm4710_ss-objs += bcm4710_pcmcia.o
20597 +
20598 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
20599 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
20600 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
20601 @@ -112,5 +116,8 @@
20602 au1x00_ss.o: $(au1000_ss-objs-y)
20603 $(LD) -r -o $@ $(au1000_ss-objs-y)
20604
20605 +bcm4710_ss.o: $(bcm4710_ss-objs)
20606 + $(LD) -r -o $@ $(bcm4710_ss-objs)
20607 +
20608 yenta_socket.o: $(yenta_socket-objs)
20609 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
20610 diff -Naur linux.old/drivers/pcmcia/bcm4710_generic.c linux.dev/drivers/pcmcia/bcm4710_generic.c
20611 --- linux.old/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
20612 +++ linux.dev/drivers/pcmcia/bcm4710_generic.c 2006-04-06 15:34:15.000000000 +0200
20613 @@ -0,0 +1,912 @@
20614 +/*
20615 + *
20616 + * bcm47xx pcmcia driver
20617 + *
20618 + * Copyright 2004, Broadcom Corporation
20619 + * All Rights Reserved.
20620 + *
20621 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
20622 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
20623 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
20624 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
20625 + *
20626 + * Based on sa1100_generic.c from www.handhelds.org,
20627 + * and au1000_generic.c from oss.sgi.com.
20628 + *
20629 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
20630 + */
20631 +#include <linux/module.h>
20632 +#include <linux/init.h>
20633 +#include <linux/config.h>
20634 +#include <linux/delay.h>
20635 +#include <linux/ioport.h>
20636 +#include <linux/kernel.h>
20637 +#include <linux/tqueue.h>
20638 +#include <linux/timer.h>
20639 +#include <linux/mm.h>
20640 +#include <linux/proc_fs.h>
20641 +#include <linux/version.h>
20642 +#include <linux/types.h>
20643 +#include <linux/vmalloc.h>
20644 +
20645 +#include <pcmcia/version.h>
20646 +#include <pcmcia/cs_types.h>
20647 +#include <pcmcia/cs.h>
20648 +#include <pcmcia/ss.h>
20649 +#include <pcmcia/bulkmem.h>
20650 +#include <pcmcia/cistpl.h>
20651 +#include <pcmcia/bus_ops.h>
20652 +#include "cs_internal.h"
20653 +
20654 +#include <asm/io.h>
20655 +#include <asm/irq.h>
20656 +#include <asm/system.h>
20657 +
20658 +#include <typedefs.h>
20659 +#include <bcm4710.h>
20660 +#include <sbextif.h>
20661 +
20662 +#include "bcm4710pcmcia.h"
20663 +
20664 +#ifdef PCMCIA_DEBUG
20665 +static int pc_debug = PCMCIA_DEBUG;
20666 +#endif
20667 +
20668 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
20669 +
20670 +/* This structure maintains housekeeping state for each socket, such
20671 + * as the last known values of the card detect pins, or the Card Services
20672 + * callback value associated with the socket:
20673 + */
20674 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
20675 +static int socket_count;
20676 +
20677 +
20678 +/* Returned by the low-level PCMCIA interface: */
20679 +static struct pcmcia_low_level *pcmcia_low_level;
20680 +
20681 +/* Event poll timer structure */
20682 +static struct timer_list poll_timer;
20683 +
20684 +
20685 +/* Prototypes for routines which are used internally: */
20686 +
20687 +static int bcm47xx_pcmcia_driver_init(void);
20688 +static void bcm47xx_pcmcia_driver_shutdown(void);
20689 +static void bcm47xx_pcmcia_task_handler(void *data);
20690 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
20691 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
20692 +static struct tq_struct bcm47xx_pcmcia_task;
20693 +
20694 +#ifdef CONFIG_PROC_FS
20695 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
20696 + off_t pos, int count, int *eof, void *data);
20697 +#endif
20698 +
20699 +
20700 +/* Prototypes for operations which are exported to the
20701 + * in-kernel PCMCIA core:
20702 + */
20703 +
20704 +static int bcm47xx_pcmcia_init(unsigned int sock);
20705 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
20706 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
20707 + void (*handler)(void *, unsigned int), void *info);
20708 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
20709 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
20710 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
20711 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
20712 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
20713 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
20714 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
20715 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
20716 +#ifdef CONFIG_PROC_FS
20717 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
20718 +#endif
20719 +
20720 +static struct pccard_operations bcm47xx_pcmcia_operations = {
20721 + bcm47xx_pcmcia_init,
20722 + bcm47xx_pcmcia_suspend,
20723 + bcm47xx_pcmcia_register_callback,
20724 + bcm47xx_pcmcia_inquire_socket,
20725 + bcm47xx_pcmcia_get_status,
20726 + bcm47xx_pcmcia_get_socket,
20727 + bcm47xx_pcmcia_set_socket,
20728 + bcm47xx_pcmcia_get_io_map,
20729 + bcm47xx_pcmcia_set_io_map,
20730 + bcm47xx_pcmcia_get_mem_map,
20731 + bcm47xx_pcmcia_set_mem_map,
20732 +#ifdef CONFIG_PROC_FS
20733 + bcm47xx_pcmcia_proc_setup
20734 +#endif
20735 +};
20736 +
20737 +
20738 +/*
20739 + * bcm47xx_pcmcia_driver_init()
20740 + *
20741 + * This routine performs a basic sanity check to ensure that this
20742 + * kernel has been built with the appropriate board-specific low-level
20743 + * PCMCIA support, performs low-level PCMCIA initialization, registers
20744 + * this socket driver with Card Services, and then spawns the daemon
20745 + * thread which is the real workhorse of the socket driver.
20746 + *
20747 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
20748 + * on the low-level kernel interface.
20749 + *
20750 + * Returns: 0 on success, -1 on error
20751 + */
20752 +static int __init bcm47xx_pcmcia_driver_init(void)
20753 +{
20754 + servinfo_t info;
20755 + struct pcmcia_init pcmcia_init;
20756 + struct pcmcia_state state;
20757 + unsigned int i;
20758 + unsigned long tmp;
20759 +
20760 +
20761 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
20762 +
20763 + CardServices(GetCardServicesInfo, &info);
20764 +
20765 + if (info.Revision != CS_RELEASE_CODE) {
20766 + printk(KERN_ERR "Card Services release codes do not match\n");
20767 + return -1;
20768 + }
20769 +
20770 +#ifdef CONFIG_BCM4710
20771 + pcmcia_low_level=&bcm4710_pcmcia_ops;
20772 +#else
20773 +#error Unsupported Broadcom BCM47XX board.
20774 +#endif
20775 +
20776 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
20777 +
20778 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
20779 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
20780 + return -EIO;
20781 + } else {
20782 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
20783 + }
20784 +
20785 + pcmcia_socket =
20786 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
20787 + GFP_KERNEL);
20788 + memset(pcmcia_socket, 0,
20789 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
20790 + if (!pcmcia_socket) {
20791 + printk(KERN_ERR "Card Services can't get memory \n");
20792 + return -1;
20793 + }
20794 +
20795 + for (i = 0; i < socket_count; i++) {
20796 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
20797 + printk(KERN_ERR "Unable to get PCMCIA status\n");
20798 + return -EIO;
20799 + }
20800 + pcmcia_socket[i].k_state = state;
20801 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
20802 +
20803 + if (i == 0) {
20804 + pcmcia_socket[i].virt_io =
20805 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
20806 + /* Substract ioport base which gets added by in/out */
20807 + pcmcia_socket[i].virt_io -= mips_io_port_base;
20808 + pcmcia_socket[i].phys_attr =
20809 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
20810 + pcmcia_socket[i].phys_mem =
20811 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
20812 + } else {
20813 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
20814 + return 1;
20815 + }
20816 + }
20817 +
20818 + /* Only advertise as many sockets as we can detect: */
20819 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
20820 + printk(KERN_ERR "Unable to register socket service routine\n");
20821 + return -ENXIO;
20822 + }
20823 +
20824 + /* Start the event poll timer.
20825 + * It will reschedule by itself afterwards.
20826 + */
20827 + bcm47xx_pcmcia_poll_event(0);
20828 +
20829 + DEBUG(1, "bcm4710: initialization complete\n");
20830 + return 0;
20831 +
20832 +}
20833 +
20834 +module_init(bcm47xx_pcmcia_driver_init);
20835 +
20836 +
20837 +/*
20838 + * bcm47xx_pcmcia_driver_shutdown()
20839 + *
20840 + * Invokes the low-level kernel service to free IRQs associated with this
20841 + * socket controller and reset GPIO edge detection.
20842 + */
20843 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
20844 +{
20845 + int i;
20846 +
20847 + del_timer_sync(&poll_timer);
20848 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
20849 + pcmcia_low_level->shutdown();
20850 + flush_scheduled_tasks();
20851 + for (i = 0; i < socket_count; i++) {
20852 + if (pcmcia_socket[i].virt_io)
20853 + iounmap((void *)pcmcia_socket[i].virt_io);
20854 + if (pcmcia_socket[i].phys_attr)
20855 + iounmap((void *)pcmcia_socket[i].phys_attr);
20856 + if (pcmcia_socket[i].phys_mem)
20857 + iounmap((void *)pcmcia_socket[i].phys_mem);
20858 + }
20859 + DEBUG(1, "bcm4710: shutdown complete\n");
20860 +}
20861 +
20862 +module_exit(bcm47xx_pcmcia_driver_shutdown);
20863 +
20864 +/*
20865 + * bcm47xx_pcmcia_init()
20866 + * We perform all of the interesting initialization tasks in
20867 + * bcm47xx_pcmcia_driver_init().
20868 + *
20869 + * Returns: 0
20870 + */
20871 +static int bcm47xx_pcmcia_init(unsigned int sock)
20872 +{
20873 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
20874 +
20875 + return 0;
20876 +}
20877 +
20878 +/*
20879 + * bcm47xx_pcmcia_suspend()
20880 + *
20881 + * We don't currently perform any actions on a suspend.
20882 + *
20883 + * Returns: 0
20884 + */
20885 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
20886 +{
20887 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
20888 +
20889 + return 0;
20890 +}
20891 +
20892 +
20893 +/*
20894 + * bcm47xx_pcmcia_events()
20895 + *
20896 + * Helper routine to generate a Card Services event mask based on
20897 + * state information obtained from the kernel low-level PCMCIA layer
20898 + * in a recent (and previous) sampling. Updates `prev_state'.
20899 + *
20900 + * Returns: an event mask for the given socket state.
20901 + */
20902 +static inline unsigned
20903 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
20904 + struct pcmcia_state *prev_state,
20905 + unsigned int mask, unsigned int flags)
20906 +{
20907 + unsigned int events=0;
20908 +
20909 + if (state->bvd1 != prev_state->bvd1) {
20910 +
20911 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
20912 +
20913 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
20914 + }
20915 +
20916 + if (state->bvd2 != prev_state->bvd2) {
20917 +
20918 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
20919 +
20920 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
20921 + }
20922 +
20923 + if (state->detect != prev_state->detect) {
20924 +
20925 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
20926 +
20927 + events |= mask & SS_DETECT;
20928 + }
20929 +
20930 +
20931 + if (state->ready != prev_state->ready) {
20932 +
20933 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
20934 +
20935 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
20936 + }
20937 +
20938 + if (events != 0) {
20939 + DEBUG(2, "events: %s%s%s%s%s\n",
20940 + (events & SS_DETECT) ? "DETECT " : "",
20941 + (events & SS_READY) ? "READY " : "",
20942 + (events & SS_BATDEAD) ? "BATDEAD " : "",
20943 + (events & SS_BATWARN) ? "BATWARN " : "",
20944 + (events & SS_STSCHG) ? "STSCHG " : "");
20945 + }
20946 +
20947 + *prev_state=*state;
20948 + return events;
20949 +}
20950 +
20951 +
20952 +/*
20953 + * bcm47xx_pcmcia_task_handler()
20954 + *
20955 + * Processes serviceable socket events using the "eventd" thread context.
20956 + *
20957 + * Event processing (specifically, the invocation of the Card Services event
20958 + * callback) occurs in this thread rather than in the actual interrupt
20959 + * handler due to the use of scheduling operations in the PCMCIA core.
20960 + */
20961 +static void bcm47xx_pcmcia_task_handler(void *data)
20962 +{
20963 + struct pcmcia_state state;
20964 + int i, events, irq_status;
20965 +
20966 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
20967 +
20968 + for (i = 0; i < socket_count; i++) {
20969 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
20970 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
20971 +
20972 + events = bcm47xx_pcmcia_events(&state,
20973 + &pcmcia_socket[i].k_state,
20974 + pcmcia_socket[i].cs_state.csc_mask,
20975 + pcmcia_socket[i].cs_state.flags);
20976 +
20977 + if (pcmcia_socket[i].handler != NULL) {
20978 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
20979 + events);
20980 + }
20981 + }
20982 +}
20983 +
20984 +static struct tq_struct bcm47xx_pcmcia_task = {
20985 + routine: bcm47xx_pcmcia_task_handler
20986 +};
20987 +
20988 +
20989 +/*
20990 + * bcm47xx_pcmcia_poll_event()
20991 + *
20992 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
20993 + */
20994 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
20995 +{
20996 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
20997 +
20998 + poll_timer.function = bcm47xx_pcmcia_poll_event;
20999 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
21000 + add_timer(&poll_timer);
21001 + schedule_task(&bcm47xx_pcmcia_task);
21002 +}
21003 +
21004 +
21005 +/*
21006 + * bcm47xx_pcmcia_interrupt()
21007 + *
21008 + * Service routine for socket driver interrupts (requested by the
21009 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
21010 + *
21011 + * The actual interrupt-servicing work is performed by
21012 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
21013 + * handling code performs scheduling operations which cannot be
21014 + * executed from within an interrupt context.
21015 + */
21016 +static void
21017 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
21018 +{
21019 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
21020 + schedule_task(&bcm47xx_pcmcia_task);
21021 +}
21022 +
21023 +
21024 +/*
21025 + * bcm47xx_pcmcia_register_callback()
21026 + *
21027 + * Implements the register_callback() operation for the in-kernel
21028 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
21029 + * the function pointer `handler' is not NULL, remember the callback
21030 + * location in the state for `sock', and increment the usage counter
21031 + * for the driver module. (The callback is invoked from the interrupt
21032 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
21033 + * of interesting events.) Otherwise, clear the callback pointer in the
21034 + * socket state and decrement the module usage count.
21035 + *
21036 + * Returns: 0
21037 + */
21038 +static int
21039 +bcm47xx_pcmcia_register_callback(unsigned int sock,
21040 + void (*handler)(void *, unsigned int), void *info)
21041 +{
21042 + if (handler == NULL) {
21043 + pcmcia_socket[sock].handler = NULL;
21044 + MOD_DEC_USE_COUNT;
21045 + } else {
21046 + MOD_INC_USE_COUNT;
21047 + pcmcia_socket[sock].handler = handler;
21048 + pcmcia_socket[sock].handler_info = info;
21049 + }
21050 + return 0;
21051 +}
21052 +
21053 +
21054 +/*
21055 + * bcm47xx_pcmcia_inquire_socket()
21056 + *
21057 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
21058 + * service (formerly SS_InquireSocket in Card Services). Of note is
21059 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
21060 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
21061 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
21062 + * resource database check. (Mapped memory is set up within the socket
21063 + * driver itself.)
21064 + *
21065 + * In conjunction with the STATIC_MAP capability is a new field,
21066 + * `io_offset', recommended by David Hinds. Rather than go through
21067 + * the SetIOMap interface (which is not quite suited for communicating
21068 + * window locations up from the socket driver), we just pass up
21069 + * an offset which is applied to client-requested base I/O addresses
21070 + * in alloc_io_space().
21071 + *
21072 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
21073 + */
21074 +static int
21075 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
21076 +{
21077 + struct pcmcia_irq_info irq_info;
21078 +
21079 + if (sock >= socket_count) {
21080 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
21081 + return -1;
21082 + }
21083 +
21084 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
21085 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
21086 + * general, the mapped * addresses of the PCMCIA memory regions
21087 + * will not be within 0xffff, setting force_low would be
21088 + * undesirable.
21089 + *
21090 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
21091 + * resource database; we instead pass up physical address ranges
21092 + * and allow other parts of Card Services to deal with remapping.
21093 + *
21094 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
21095 + * not 32-bit CardBus devices.
21096 + */
21097 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
21098 +
21099 + irq_info.sock = sock;
21100 + irq_info.irq = -1;
21101 +
21102 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
21103 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
21104 + return -1;
21105 + }
21106 +
21107 + cap->irq_mask = 0;
21108 + cap->map_size = PAGE_SIZE;
21109 + cap->pci_irq = irq_info.irq;
21110 + cap->io_offset = pcmcia_socket[sock].virt_io;
21111 +
21112 + return 0;
21113 +}
21114 +
21115 +
21116 +/*
21117 + * bcm47xx_pcmcia_get_status()
21118 + *
21119 + * Implements the get_status() operation for the in-kernel PCMCIA
21120 + * service (formerly SS_GetStatus in Card Services). Essentially just
21121 + * fills in bits in `status' according to internal driver state or
21122 + * the value of the voltage detect chipselect register.
21123 + *
21124 + * As a debugging note, during card startup, the PCMCIA core issues
21125 + * three set_socket() commands in a row the first with RESET deasserted,
21126 + * the second with RESET asserted, and the last with RESET deasserted
21127 + * again. Following the third set_socket(), a get_status() command will
21128 + * be issued. The kernel is looking for the SS_READY flag (see
21129 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
21130 + *
21131 + * Returns: 0
21132 + */
21133 +static int
21134 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
21135 +{
21136 + struct pcmcia_state state;
21137 +
21138 +
21139 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
21140 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
21141 + return -1;
21142 + }
21143 +
21144 + pcmcia_socket[sock].k_state = state;
21145 +
21146 + *status = state.detect ? SS_DETECT : 0;
21147 +
21148 + *status |= state.ready ? SS_READY : 0;
21149 +
21150 + /* The power status of individual sockets is not available
21151 + * explicitly from the hardware, so we just remember the state
21152 + * and regurgitate it upon request:
21153 + */
21154 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
21155 +
21156 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
21157 + *status |= state.bvd1 ? SS_STSCHG : 0;
21158 + else {
21159 + if (state.bvd1 == 0)
21160 + *status |= SS_BATDEAD;
21161 + else if (state.bvd2 == 0)
21162 + *status |= SS_BATWARN;
21163 + }
21164 +
21165 + *status |= state.vs_3v ? SS_3VCARD : 0;
21166 +
21167 + *status |= state.vs_Xv ? SS_XVCARD : 0;
21168 +
21169 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
21170 + (*status&SS_DETECT)?"DETECT ":"",
21171 + (*status&SS_READY)?"READY ":"",
21172 + (*status&SS_BATDEAD)?"BATDEAD ":"",
21173 + (*status&SS_BATWARN)?"BATWARN ":"",
21174 + (*status&SS_POWERON)?"POWERON ":"",
21175 + (*status&SS_STSCHG)?"STSCHG ":"",
21176 + (*status&SS_3VCARD)?"3VCARD ":"",
21177 + (*status&SS_XVCARD)?"XVCARD ":"");
21178 +
21179 + return 0;
21180 +}
21181 +
21182 +
21183 +/*
21184 + * bcm47xx_pcmcia_get_socket()
21185 + *
21186 + * Implements the get_socket() operation for the in-kernel PCMCIA
21187 + * service (formerly SS_GetSocket in Card Services). Not a very
21188 + * exciting routine.
21189 + *
21190 + * Returns: 0
21191 + */
21192 +static int
21193 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
21194 +{
21195 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
21196 +
21197 + /* This information was given to us in an earlier call to set_socket(),
21198 + * so we're just regurgitating it here:
21199 + */
21200 + *state = pcmcia_socket[sock].cs_state;
21201 + return 0;
21202 +}
21203 +
21204 +
21205 +/*
21206 + * bcm47xx_pcmcia_set_socket()
21207 + *
21208 + * Implements the set_socket() operation for the in-kernel PCMCIA
21209 + * service (formerly SS_SetSocket in Card Services). We more or
21210 + * less punt all of this work and let the kernel handle the details
21211 + * of power configuration, reset, &c. We also record the value of
21212 + * `state' in order to regurgitate it to the PCMCIA core later.
21213 + *
21214 + * Returns: 0
21215 + */
21216 +static int
21217 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
21218 +{
21219 + struct pcmcia_configure configure;
21220 +
21221 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
21222 + "\tVcc %d Vpp %d irq %d\n",
21223 + (state->csc_mask == 0) ? "<NONE>" : "",
21224 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
21225 + (state->csc_mask & SS_READY) ? "READY " : "",
21226 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
21227 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
21228 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
21229 + (state->flags == 0) ? "<NONE>" : "",
21230 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
21231 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
21232 + (state->flags & SS_RESET) ? "RESET " : "",
21233 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
21234 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
21235 + state->Vcc, state->Vpp, state->io_irq);
21236 +
21237 + configure.sock = sock;
21238 + configure.vcc = state->Vcc;
21239 + configure.vpp = state->Vpp;
21240 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
21241 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
21242 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
21243 +
21244 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
21245 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
21246 + return -1;
21247 + }
21248 +
21249 + pcmcia_socket[sock].cs_state = *state;
21250 + return 0;
21251 +}
21252 +
21253 +
21254 +/*
21255 + * bcm47xx_pcmcia_get_io_map()
21256 + *
21257 + * Implements the get_io_map() operation for the in-kernel PCMCIA
21258 + * service (formerly SS_GetIOMap in Card Services). Just returns an
21259 + * I/O map descriptor which was assigned earlier by a set_io_map().
21260 + *
21261 + * Returns: 0 on success, -1 if the map index was out of range
21262 + */
21263 +static int
21264 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
21265 +{
21266 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
21267 +
21268 + if (map->map >= MAX_IO_WIN) {
21269 + printk(KERN_ERR "%s(): map (%d) out of range\n",
21270 + __FUNCTION__, map->map);
21271 + return -1;
21272 + }
21273 +
21274 + *map = pcmcia_socket[sock].io_map[map->map];
21275 + return 0;
21276 +}
21277 +
21278 +
21279 +/*
21280 + * bcm47xx_pcmcia_set_io_map()
21281 + *
21282 + * Implements the set_io_map() operation for the in-kernel PCMCIA
21283 + * service (formerly SS_SetIOMap in Card Services). We configure
21284 + * the map speed as requested, but override the address ranges
21285 + * supplied by Card Services.
21286 + *
21287 + * Returns: 0 on success, -1 on error
21288 + */
21289 +int
21290 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
21291 +{
21292 + unsigned int speed;
21293 + unsigned long start;
21294 +
21295 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
21296 + "\tflags: %s%s%s%s%s%s%s%s\n",
21297 + map->map, map->speed, map->start, map->stop,
21298 + (map->flags == 0) ? "<NONE>" : "",
21299 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
21300 + (map->flags & MAP_16BIT) ? "16BIT " : "",
21301 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
21302 + (map->flags & MAP_0WS) ? "0WS " : "",
21303 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
21304 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
21305 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
21306 +
21307 + if (map->map >= MAX_IO_WIN) {
21308 + printk(KERN_ERR "%s(): map (%d) out of range\n",
21309 + __FUNCTION__, map->map);
21310 + return -1;
21311 + }
21312 +
21313 + if (map->flags & MAP_ACTIVE) {
21314 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
21315 + pcmcia_socket[sock].speed_io = speed;
21316 + }
21317 +
21318 + start = map->start;
21319 +
21320 + if (map->stop == 1) {
21321 + map->stop = PAGE_SIZE - 1;
21322 + }
21323 +
21324 + map->start = pcmcia_socket[sock].virt_io;
21325 + map->stop = map->start + (map->stop - start);
21326 + pcmcia_socket[sock].io_map[map->map] = *map;
21327 + DEBUG(2, "set_io_map %d start %x stop %x\n",
21328 + map->map, map->start, map->stop);
21329 + return 0;
21330 +}
21331 +
21332 +
21333 +/*
21334 + * bcm47xx_pcmcia_get_mem_map()
21335 + *
21336 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
21337 + * service (formerly SS_GetMemMap in Card Services). Just returns a
21338 + * memory map descriptor which was assigned earlier by a
21339 + * set_mem_map() request.
21340 + *
21341 + * Returns: 0 on success, -1 if the map index was out of range
21342 + */
21343 +static int
21344 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
21345 +{
21346 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
21347 +
21348 + if (map->map >= MAX_WIN) {
21349 + printk(KERN_ERR "%s(): map (%d) out of range\n",
21350 + __FUNCTION__, map->map);
21351 + return -1;
21352 + }
21353 +
21354 + *map = pcmcia_socket[sock].mem_map[map->map];
21355 + return 0;
21356 +}
21357 +
21358 +
21359 +/*
21360 + * bcm47xx_pcmcia_set_mem_map()
21361 + *
21362 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
21363 + * service (formerly SS_SetMemMap in Card Services). We configure
21364 + * the map speed as requested, but override the address ranges
21365 + * supplied by Card Services.
21366 + *
21367 + * Returns: 0 on success, -1 on error
21368 + */
21369 +static int
21370 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
21371 +{
21372 + unsigned int speed;
21373 + unsigned long start;
21374 + u_long flags;
21375 +
21376 + if (map->map >= MAX_WIN) {
21377 + printk(KERN_ERR "%s(): map (%d) out of range\n",
21378 + __FUNCTION__, map->map);
21379 + return -1;
21380 + }
21381 +
21382 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
21383 + "\tsys_stop %#lx\n\tcard_start %#x\n"
21384 + "\tflags: %s%s%s%s%s%s%s%s\n",
21385 + map->map, map->speed, map->sys_start, map->sys_stop,
21386 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
21387 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
21388 + (map->flags & MAP_16BIT) ? "16BIT " : "",
21389 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
21390 + (map->flags & MAP_0WS) ? "0WS " : "",
21391 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
21392 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
21393 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
21394 +
21395 + if (map->flags & MAP_ACTIVE) {
21396 + /* When clients issue RequestMap, the access speed is not always
21397 + * properly configured:
21398 + */
21399 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
21400 +
21401 + /* TBD */
21402 + if (map->flags & MAP_ATTRIB) {
21403 + pcmcia_socket[sock].speed_attr = speed;
21404 + } else {
21405 + pcmcia_socket[sock].speed_mem = speed;
21406 + }
21407 + }
21408 +
21409 + save_flags(flags);
21410 + cli();
21411 + start = map->sys_start;
21412 +
21413 + if (map->sys_stop == 0)
21414 + map->sys_stop = PAGE_SIZE - 1;
21415 +
21416 + if (map->flags & MAP_ATTRIB) {
21417 + map->sys_start = pcmcia_socket[sock].phys_attr +
21418 + map->card_start;
21419 + } else {
21420 + map->sys_start = pcmcia_socket[sock].phys_mem +
21421 + map->card_start;
21422 + }
21423 +
21424 + map->sys_stop = map->sys_start + (map->sys_stop - start);
21425 + pcmcia_socket[sock].mem_map[map->map] = *map;
21426 + restore_flags(flags);
21427 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
21428 + map->map, map->sys_start, map->sys_stop,
21429 + map->card_start);
21430 + return 0;
21431 +}
21432 +
21433 +
21434 +#if defined(CONFIG_PROC_FS)
21435 +
21436 +/*
21437 + * bcm47xx_pcmcia_proc_setup()
21438 + *
21439 + * Implements the proc_setup() operation for the in-kernel PCMCIA
21440 + * service (formerly SS_ProcSetup in Card Services).
21441 + *
21442 + * Returns: 0 on success, -1 on error
21443 + */
21444 +static void
21445 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
21446 +{
21447 + struct proc_dir_entry *entry;
21448 +
21449 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
21450 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
21451 + return;
21452 + }
21453 +
21454 + entry->read_proc = bcm47xx_pcmcia_proc_status;
21455 + entry->data = (void *)sock;
21456 +}
21457 +
21458 +
21459 +/*
21460 + * bcm47xx_pcmcia_proc_status()
21461 + *
21462 + * Implements the /proc/bus/pccard/??/status file.
21463 + *
21464 + * Returns: the number of characters added to the buffer
21465 + */
21466 +static int
21467 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
21468 + int count, int *eof, void *data)
21469 +{
21470 + char *p = buf;
21471 + unsigned int sock = (unsigned int)data;
21472 +
21473 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
21474 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
21475 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
21476 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
21477 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
21478 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
21479 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
21480 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
21481 +
21482 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
21483 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
21484 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
21485 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
21486 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
21487 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
21488 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
21489 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
21490 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
21491 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
21492 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
21493 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
21494 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
21495 +
21496 + p += sprintf(p, "mask : %s%s%s%s%s\n",
21497 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
21498 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
21499 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
21500 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
21501 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
21502 +
21503 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
21504 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
21505 + "SS_PWR_AUTO " : "",
21506 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
21507 + "SS_IOCARD " : "",
21508 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
21509 + "SS_RESET " : "",
21510 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
21511 + "SS_SPKR_ENA " : "",
21512 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
21513 + "SS_OUTPUT_ENA " : "");
21514 +
21515 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
21516 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
21517 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
21518 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
21519 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
21520 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
21521 + return p-buf;
21522 +}
21523 +
21524 +
21525 +#endif /* defined(CONFIG_PROC_FS) */
21526 diff -Naur linux.old/drivers/pcmcia/bcm4710_pcmcia.c linux.dev/drivers/pcmcia/bcm4710_pcmcia.c
21527 --- linux.old/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
21528 +++ linux.dev/drivers/pcmcia/bcm4710_pcmcia.c 2006-04-06 15:34:15.000000000 +0200
21529 @@ -0,0 +1,266 @@
21530 +/*
21531 + * BCM4710 specific pcmcia routines.
21532 + *
21533 + * Copyright 2004, Broadcom Corporation
21534 + * All Rights Reserved.
21535 + *
21536 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21537 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21538 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21539 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21540 + *
21541 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
21542 + */
21543 +#include <linux/module.h>
21544 +#include <linux/init.h>
21545 +#include <linux/config.h>
21546 +#include <linux/delay.h>
21547 +#include <linux/ioport.h>
21548 +#include <linux/kernel.h>
21549 +#include <linux/tqueue.h>
21550 +#include <linux/timer.h>
21551 +#include <linux/mm.h>
21552 +#include <linux/proc_fs.h>
21553 +#include <linux/version.h>
21554 +#include <linux/types.h>
21555 +#include <linux/pci.h>
21556 +
21557 +#include <pcmcia/version.h>
21558 +#include <pcmcia/cs_types.h>
21559 +#include <pcmcia/cs.h>
21560 +#include <pcmcia/ss.h>
21561 +#include <pcmcia/bulkmem.h>
21562 +#include <pcmcia/cistpl.h>
21563 +#include <pcmcia/bus_ops.h>
21564 +#include "cs_internal.h"
21565 +
21566 +#include <asm/io.h>
21567 +#include <asm/irq.h>
21568 +#include <asm/system.h>
21569 +
21570 +
21571 +#include <typedefs.h>
21572 +#include <bcmdevs.h>
21573 +#include <bcm4710.h>
21574 +#include <sbconfig.h>
21575 +#include <sbextif.h>
21576 +
21577 +#include "bcm4710pcmcia.h"
21578 +
21579 +/* Use a static var for irq dev_id */
21580 +static int bcm47xx_pcmcia_dev_id;
21581 +
21582 +/* Do we think we have a card or not? */
21583 +static int bcm47xx_pcmcia_present = 0;
21584 +
21585 +
21586 +static void bcm4710_pcmcia_reset(void)
21587 +{
21588 + extifregs_t *eir;
21589 + unsigned long s;
21590 + uint32 out0, out1, outen;
21591 +
21592 +
21593 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
21594 +
21595 + save_and_cli(s);
21596 +
21597 + /* Use gpio7 to reset the pcmcia slot */
21598 + outen = readl(&eir->gpio[0].outen);
21599 + outen |= BCM47XX_PCMCIA_RESET;
21600 + out0 = readl(&eir->gpio[0].out);
21601 + out0 &= ~(BCM47XX_PCMCIA_RESET);
21602 + out1 = out0 | BCM47XX_PCMCIA_RESET;
21603 +
21604 + writel(out0, &eir->gpio[0].out);
21605 + writel(outen, &eir->gpio[0].outen);
21606 + mdelay(1);
21607 + writel(out1, &eir->gpio[0].out);
21608 + mdelay(1);
21609 + writel(out0, &eir->gpio[0].out);
21610 +
21611 + restore_flags(s);
21612 +}
21613 +
21614 +
21615 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
21616 +{
21617 + struct pci_dev *pdev;
21618 + extifregs_t *eir;
21619 + uint32 outen, intp, intm, tmp;
21620 + uint16 *attrsp;
21621 + int rc = 0, i;
21622 + extern unsigned long bcm4710_cpu_cycle;
21623 +
21624 +
21625 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
21626 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
21627 + return -ENODEV;
21628 + }
21629 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
21630 +
21631 + /* Initialize the pcmcia i/f: 16bit no swap */
21632 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
21633 +
21634 +#ifdef notYet
21635 +
21636 + /* Set the timing for memory accesses */
21637 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
21638 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
21639 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
21640 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
21641 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
21642 +
21643 + /* Set the timing for I/O accesses */
21644 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
21645 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
21646 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
21647 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
21648 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
21649 +
21650 + /* Set the timing for attribute accesses */
21651 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
21652 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
21653 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
21654 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
21655 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
21656 +
21657 +#endif
21658 + /* Make sure gpio0 and gpio5 are inputs */
21659 + outen = readl(&eir->gpio[0].outen);
21660 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
21661 + writel(outen, &eir->gpio[0].outen);
21662 +
21663 + /* Issue a reset to the pcmcia socket */
21664 + bcm4710_pcmcia_reset();
21665 +
21666 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
21667 + /* Setup gpio5 to be the STSCHG interrupt */
21668 + intp = readl(&eir->gpiointpolarity);
21669 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
21670 + intm = readl(&eir->gpiointmask);
21671 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
21672 +#endif
21673 +
21674 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
21675 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
21676 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
21677 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
21678 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
21679 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
21680 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
21681 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
21682 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
21683 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
21684 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
21685 +
21686 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
21687 + /* Request pcmcia interrupt */
21688 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
21689 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
21690 +#endif
21691 +
21692 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
21693 + tmp = readw(&attrsp[0]);
21694 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
21695 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
21696 + bcm47xx_pcmcia_present = 0;
21697 + } else {
21698 + bcm47xx_pcmcia_present = 1;
21699 + }
21700 +
21701 + /* There's only one socket */
21702 + return 1;
21703 +}
21704 +
21705 +static int bcm4710_pcmcia_shutdown(void)
21706 +{
21707 + extifregs_t *eir;
21708 + uint32 intm;
21709 +
21710 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
21711 +
21712 + /* Disable the pcmcia i/f */
21713 + writel(0, &eir->pcmcia_config);
21714 +
21715 + /* Reset gpio's */
21716 + intm = readl(&eir->gpiointmask);
21717 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
21718 +
21719 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
21720 +
21721 + return 0;
21722 +}
21723 +
21724 +static int
21725 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
21726 +{
21727 + extifregs_t *eir;
21728 +
21729 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
21730 +
21731 +
21732 + if (sock != 0) {
21733 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
21734 + return -1;
21735 + }
21736 +
21737 + if (bcm47xx_pcmcia_present) {
21738 + state->detect = 1;
21739 + state->ready = 1;
21740 + state->bvd1 = 1;
21741 + state->bvd2 = 1;
21742 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
21743 + state->vs_3v = 0;
21744 + state->vs_Xv = 0;
21745 + } else {
21746 + state->detect = 0;
21747 + state->ready = 0;
21748 + }
21749 +
21750 + return 1;
21751 +}
21752 +
21753 +
21754 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
21755 +{
21756 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
21757 +
21758 + info->irq = BCM47XX_PCMCIA_IRQ;
21759 +
21760 + return 0;
21761 +}
21762 +
21763 +
21764 +static int
21765 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
21766 +{
21767 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
21768 +
21769 +
21770 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
21771 + configure->vpp, configure->output, configure->speaker, configure->reset);
21772 +
21773 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
21774 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
21775 + configure->vpp);
21776 + }
21777 +
21778 + if (configure->reset) {
21779 + /* Issue a reset to the pcmcia socket */
21780 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
21781 + bcm4710_pcmcia_reset();
21782 + }
21783 +
21784 +
21785 + return 0;
21786 +}
21787 +
21788 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
21789 + bcm4710_pcmcia_init,
21790 + bcm4710_pcmcia_shutdown,
21791 + bcm4710_pcmcia_socket_state,
21792 + bcm4710_pcmcia_get_irq_info,
21793 + bcm4710_pcmcia_configure_socket
21794 +};
21795 +
21796 diff -Naur linux.old/drivers/pcmcia/bcm4710pcmcia.h linux.dev/drivers/pcmcia/bcm4710pcmcia.h
21797 --- linux.old/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
21798 +++ linux.dev/drivers/pcmcia/bcm4710pcmcia.h 2006-04-06 15:34:15.000000000 +0200
21799 @@ -0,0 +1,118 @@
21800 +/*
21801 + *
21802 + * bcm47xx pcmcia driver
21803 + *
21804 + * Copyright 2004, Broadcom Corporation
21805 + * All Rights Reserved.
21806 + *
21807 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21808 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21809 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21810 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21811 + *
21812 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
21813 + * from www.handhelds.org,
21814 + * and au1000_generic.c from oss.sgi.com.
21815 + *
21816 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
21817 + */
21818 +
21819 +#if !defined(_BCM4710PCMCIA_H)
21820 +#define _BCM4710PCMCIA_H
21821 +
21822 +#include <pcmcia/cs_types.h>
21823 +#include <pcmcia/ss.h>
21824 +#include <pcmcia/bulkmem.h>
21825 +#include <pcmcia/cistpl.h>
21826 +#include "cs_internal.h"
21827 +
21828 +
21829 +/* The 47xx can only support one socket */
21830 +#define BCM47XX_PCMCIA_MAX_SOCK 1
21831 +
21832 +/* In the bcm947xx gpio's are used for some pcmcia functions */
21833 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
21834 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
21835 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
21836 +
21837 +#define BCM47XX_PCMCIA_IRQ 2
21838 +
21839 +/* The socket driver actually works nicely in interrupt-driven form,
21840 + * so the (relatively infrequent) polling is "just to be sure."
21841 + */
21842 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
21843 +
21844 +#define BCM47XX_PCMCIA_IO_SPEED (255)
21845 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
21846 +
21847 +
21848 +struct pcmcia_state {
21849 + unsigned detect: 1,
21850 + ready: 1,
21851 + bvd1: 1,
21852 + bvd2: 1,
21853 + wrprot: 1,
21854 + vs_3v: 1,
21855 + vs_Xv: 1;
21856 +};
21857 +
21858 +
21859 +struct pcmcia_configure {
21860 + unsigned sock: 8,
21861 + vcc: 8,
21862 + vpp: 8,
21863 + output: 1,
21864 + speaker: 1,
21865 + reset: 1;
21866 +};
21867 +
21868 +struct pcmcia_irq_info {
21869 + unsigned int sock;
21870 + unsigned int irq;
21871 +};
21872 +
21873 +/* This structure encapsulates per-socket state which we might need to
21874 + * use when responding to a Card Services query of some kind.
21875 + */
21876 +struct bcm47xx_pcmcia_socket {
21877 + socket_state_t cs_state;
21878 + struct pcmcia_state k_state;
21879 + unsigned int irq;
21880 + void (*handler)(void *, unsigned int);
21881 + void *handler_info;
21882 + pccard_io_map io_map[MAX_IO_WIN];
21883 + pccard_mem_map mem_map[MAX_WIN];
21884 + ioaddr_t virt_io, phys_attr, phys_mem;
21885 + unsigned short speed_io, speed_attr, speed_mem;
21886 +};
21887 +
21888 +struct pcmcia_init {
21889 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
21890 +};
21891 +
21892 +struct pcmcia_low_level {
21893 + int (*init)(struct pcmcia_init *);
21894 + int (*shutdown)(void);
21895 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
21896 + int (*get_irq_info)(struct pcmcia_irq_info *);
21897 + int (*configure_socket)(const struct pcmcia_configure *);
21898 +};
21899 +
21900 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
21901 +
21902 +/* I/O pins replacing memory pins
21903 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
21904 + *
21905 + * These signals change meaning when going from memory-only to
21906 + * memory-or-I/O interface:
21907 + */
21908 +#define iostschg bvd1
21909 +#define iospkr bvd2
21910 +
21911 +
21912 +/*
21913 + * Declaration for implementation specific low_level operations.
21914 + */
21915 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
21916 +
21917 +#endif /* !defined(_BCM4710PCMCIA_H) */
21918 diff -Naur linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
21919 --- linux.old/include/asm-mips/bootinfo.h 2006-04-06 15:38:09.000000000 +0200
21920 +++ linux.dev/include/asm-mips/bootinfo.h 2006-04-06 15:34:15.000000000 +0200
21921 @@ -37,6 +37,7 @@
21922 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
21923 #define MACH_GROUP_LASAT 21
21924 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
21925 +#define MACH_GROUP_BRCM 23 /* Broadcom */
21926
21927 /*
21928 * Valid machtype values for group unknown (low order halfword of mips_machtype)
21929 @@ -197,6 +198,15 @@
21930 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
21931
21932 /*
21933 + * Valid machtypes for group Broadcom
21934 + */
21935 +#define MACH_BCM93725 0
21936 +#define MACH_BCM93725_VJ 1
21937 +#define MACH_BCM93730 2
21938 +#define MACH_BCM947XX 3
21939 +#define MACH_BCM933XX 4
21940 +
21941 +/*
21942 * Valid machtype for group TITAN
21943 */
21944 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
21945 diff -Naur linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
21946 --- linux.old/include/asm-mips/cpu.h 2006-04-06 15:38:09.000000000 +0200
21947 +++ linux.dev/include/asm-mips/cpu.h 2006-04-06 15:34:15.000000000 +0200
21948 @@ -22,6 +22,11 @@
21949 spec.
21950 */
21951
21952 +#define PRID_COPT_MASK 0xff000000
21953 +#define PRID_COMP_MASK 0x00ff0000
21954 +#define PRID_IMP_MASK 0x0000ff00
21955 +#define PRID_REV_MASK 0x000000ff
21956 +
21957 #define PRID_COMP_LEGACY 0x000000
21958 #define PRID_COMP_MIPS 0x010000
21959 #define PRID_COMP_BROADCOM 0x020000
21960 @@ -58,6 +63,7 @@
21961 #define PRID_IMP_RM7000 0x2700
21962 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
21963 #define PRID_IMP_RM9000 0x3400
21964 +#define PRID_IMP_BCM4710 0x4000
21965 #define PRID_IMP_R5432 0x5400
21966 #define PRID_IMP_R5500 0x5500
21967 #define PRID_IMP_4KC 0x8000
21968 @@ -66,10 +72,16 @@
21969 #define PRID_IMP_4KEC 0x8400
21970 #define PRID_IMP_4KSC 0x8600
21971 #define PRID_IMP_25KF 0x8800
21972 +#define PRID_IMP_BCM3302 0x9000
21973 +#define PRID_IMP_BCM3303 0x9100
21974 #define PRID_IMP_24K 0x9300
21975
21976 #define PRID_IMP_UNKNOWN 0xff00
21977
21978 +#define BCM330X(id) \
21979 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
21980 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
21981 +
21982 /*
21983 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
21984 */
21985 @@ -174,7 +186,9 @@
21986 #define CPU_AU1550 57
21987 #define CPU_24K 58
21988 #define CPU_AU1200 59
21989 -#define CPU_LAST 59
21990 +#define CPU_BCM4710 60
21991 +#define CPU_BCM3302 61
21992 +#define CPU_LAST 61
21993
21994 /*
21995 * ISA Level encodings
21996 diff -Naur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
21997 --- linux.old/include/asm-mips/r4kcache.h 2006-04-06 15:38:09.000000000 +0200
21998 +++ linux.dev/include/asm-mips/r4kcache.h 2006-04-06 15:34:15.000000000 +0200
21999 @@ -658,4 +658,17 @@
22000 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
22001 }
22002
22003 +extern inline void fill_icache_line(unsigned long addr)
22004 +{
22005 + __asm__ __volatile__(
22006 + ".set noreorder\n\t"
22007 + ".set mips3\n\t"
22008 + "cache %1, (%0)\n\t"
22009 + ".set mips0\n\t"
22010 + ".set reorder"
22011 + :
22012 + : "r" (addr),
22013 + "i" (Fill));
22014 +}
22015 +
22016 #endif /* __ASM_R4KCACHE_H */
22017 diff -Naur linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
22018 --- linux.old/include/asm-mips/serial.h 2006-04-06 15:38:09.000000000 +0200
22019 +++ linux.dev/include/asm-mips/serial.h 2006-04-06 15:34:15.000000000 +0200
22020 @@ -223,6 +223,13 @@
22021 #define TXX927_SERIAL_PORT_DEFNS
22022 #endif
22023
22024 +#ifdef CONFIG_BCM947XX
22025 +/* reserve 4 ports to be configured at runtime */
22026 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
22027 +#else
22028 +#define BCM947XX_SERIAL_PORT_DEFNS
22029 +#endif
22030 +
22031 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
22032 #define STD_SERIAL_PORT_DEFNS \
22033 /* UART CLK PORT IRQ FLAGS */ \
22034 @@ -470,6 +477,7 @@
22035 #define SERIAL_PORT_DFNS \
22036 ATLAS_SERIAL_PORT_DEFNS \
22037 AU1000_SERIAL_PORT_DEFNS \
22038 + BCM947XX_SERIAL_PORT_DEFNS \
22039 COBALT_SERIAL_PORT_DEFNS \
22040 DDB5477_SERIAL_PORT_DEFNS \
22041 EV96100_SERIAL_PORT_DEFNS \
22042 diff -Naur linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
22043 --- linux.old/init/do_mounts.c 2006-04-06 15:38:09.000000000 +0200
22044 +++ linux.dev/init/do_mounts.c 2006-04-06 15:34:15.000000000 +0200
22045 @@ -254,7 +254,13 @@
22046 { "ftlb", 0x2c08 },
22047 { "ftlc", 0x2c10 },
22048 { "ftld", 0x2c18 },
22049 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
22050 { "mtdblock", 0x1f00 },
22051 + { "mtdblock0",0x1f00 },
22052 + { "mtdblock1",0x1f01 },
22053 + { "mtdblock2",0x1f02 },
22054 + { "mtdblock3",0x1f03 },
22055 +#endif
22056 { "nb", 0x2b00 },
22057 { NULL, 0 }
22058 };
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