ath79: add support for D-Link DIR-842 C2
[openwrt/staging/dedeckeh.git] / target / linux / ath79 / dts / qca9563_dlink_dir-842-c2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "qca956x.dtsi"
8
9 / {
10 model = "D-Link DIR-842 C2";
11 compatible = "dlink,dir-842-c2", "qca,qca9563";
12
13 aliases {
14 led-boot = &power;
15 led-failsafe = &power;
16 led-running = &power;
17 led-upgrade = &power;
18 };
19
20 chosen {
21 bootargs = "console=ttyS0,115200n8";
22 };
23
24 leds {
25 compatible = "gpio-leds";
26
27 wps {
28 label = "dir-842-c2:green:wps";
29 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
30 };
31
32 power: power {
33 label = "dir-842-c2:green:power";
34 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
35 };
36
37 internet {
38 label = "dir-842-c2:green:internet";
39 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
40 };
41
42 wlan {
43 label = "dir-842-c2:green:wlan";
44 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
45 linux,default-trigger = "phy0tpt";
46 };
47 };
48
49 keys {
50 compatible = "gpio-keys";
51
52 wps {
53 linux,code = <KEY_WPS_BUTTON>;
54 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
55 debounce-interval = <60>;
56 };
57
58 reset {
59 linux,code = <KEY_RESTART>;
60 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
61 debounce-interval = <60>;
62 };
63 };
64
65 // Pull up on boot - otherwise the reset button won't work
66 reset-button {
67 gpio-hog;
68 output-high;
69 gpios = <11 GPIO_ACTIVE_LOW>;
70 line-name = "reset-button";
71 };
72 };
73
74 &uart {
75 status = "okay";
76 };
77
78 &pcie {
79 status = "okay";
80 };
81
82 &spi {
83 status = "okay";
84 num-cs = <1>;
85
86 flash@0 {
87 compatible = "jedec,spi-nor";
88 reg = <0>;
89 spi-max-frequency = <30000000>;
90
91 partitions {
92 compatible = "fixed-partitions";
93 #address-cells = <1>;
94 #size-cells = <1>;
95
96 partition@0 {
97 label = "u-boot";
98 reg = <0x000000 0x40000>;
99 read-only;
100 };
101
102 partition@40000 {
103 label = "u-boot-env";
104 reg = <0x040000 0x10000>;
105 read-only;
106 };
107
108 partition@50000 {
109 label = "devdata";
110 reg = <0x050000 0x10000>;
111 read-only;
112 };
113
114 partition@60000 {
115 label = "devconf";
116 reg = <0x060000 0x10000>;
117 read-only;
118 };
119
120 partition@70000 {
121 label = "misc";
122 reg = <0x070000 0x10000>;
123 read-only;
124 };
125
126 partition@80000 {
127 compatible = "seama";
128 label = "firmware";
129 reg = <0x080000 0xf50000>;
130 };
131
132 art: partition@fd0000 {
133 label = "art";
134 reg = <0xfd0000 0x010000>;
135 read-only;
136 };
137
138 partition@fe0000 {
139 label = "reserved";
140 reg = <0xfe0000 0x20000>;
141 read-only;
142 };
143 };
144 };
145 };
146
147 &mdio0 {
148 status = "okay";
149
150 phy-mask = <0>;
151
152 phy0: ethernet-phy@0 {
153 reg = <0>;
154 qca,mib-poll-interval = <500>;
155
156 qca,ar8327-initvals = <
157 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
158 0x10 0x81000080 /* POWER_ON_STRIP */
159 0x50 0xcc35cc35 /* LED_CTRL0 */
160 0x54 0xcb37cb37 /* LED_CTRL1 */
161 0x58 0x00000000 /* LED_CTRL2 */
162 0x5c 0x00f3cf00 /* LED_CTRL3 */
163 0x7c 0x0000007e /* PORT0_STATUS */
164 >;
165 };
166 };
167
168 &eth0 {
169 status = "okay";
170
171 pll-data = <0x03000101 0x00000101 0x00001919>;
172
173 phy-mode = "sgmii";
174 phy-handle = <&phy0>;
175 };
176
177 &wmac {
178 status = "okay";
179 qca,no-eeprom;
180 };
181
182 &usb_phy0 {
183 status = "okay";
184 };
185
186 &usb0 {
187 status = "okay";
188 };