target/linux/brcm2708/patches-4.4/0289-drm-vc4-Initialize-scaler-DISPBKGND-on-modeset.patch

   1 From bf75b498fa8699b0b3230c33cc16a0633ff0e65c Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Tue, 16 Feb 2016 10:24:08 -0800
   4 Subject: [PATCH 289/423] drm/vc4: Initialize scaler DISPBKGND on modeset.
   5
   6 We weren't updating the interlaced bit, so we'd scan out incorrectly
   7 if the firmware had brought up the TV encoder and we were switching to
   8 HDMI.
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 (cherry picked from commit 6a609209865247cc748e90158c99f374f79b494c)
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c |  6 ++++++
  14  drivers/gpu/drm/vc4/vc4_regs.h | 14 ++++++++++++++
  15  2 files changed, 20 insertions(+)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  19 @@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct d
  20
  21  static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
  22  {
  23 +       struct drm_device *dev = crtc->dev;
  24 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
  25         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  26         struct drm_crtc_state *state = crtc->state;
  27         struct drm_display_mode *mode = &state->adjusted_mode;
  28 @@ -256,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struc
  29                    PV_CONTROL_FIFO_CLR |
  30                    PV_CONTROL_EN);
  31
  32 +       HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
  33 +                 SCALER_DISPBKGND_AUTOHS |
  34 +                 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
  35 +
  36         if (debug_dump_regs) {
  37                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
  38                 vc4_crtc_dump_regs(vc4_crtc);
  39 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  40 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  41 @@ -350,6 +350,17 @@
  42  # define SCALER_DISPCTRLX_HEIGHT_SHIFT         0
  43
  44  #define SCALER_DISPBKGND0                       0x00000044
  45 +# define SCALER_DISPBKGND_AUTOHS               BIT(31)
  46 +# define SCALER_DISPBKGND_INTERLACE            BIT(30)
  47 +# define SCALER_DISPBKGND_GAMMA                        BIT(29)
  48 +# define SCALER_DISPBKGND_TESTMODE_MASK                VC4_MASK(28, 25)
  49 +# define SCALER_DISPBKGND_TESTMODE_SHIFT       25
  50 +/* Enables filling the scaler line with the RGB value in the low 24
  51 + * bits before compositing.  Costs cycles, so should be skipped if
  52 + * opaque display planes will cover everything.
  53 + */
  54 +# define SCALER_DISPBKGND_FILL                 BIT(24)
  55 +
  56  #define SCALER_DISPSTAT0                        0x00000048
  57  #define SCALER_DISPBASE0                        0x0000004c
  58  # define SCALER_DISPSTATX_MODE_MASK            VC4_MASK(31, 30)
  59 @@ -362,6 +373,9 @@
  60  # define SCALER_DISPSTATX_EMPTY                        BIT(28)
  61  #define SCALER_DISPCTRL1                        0x00000050
  62  #define SCALER_DISPBKGND1                       0x00000054
  63 +#define SCALER_DISPBKGNDX(x)                   (SCALER_DISPBKGND0 +        \
  64 +                                                (x) * (SCALER_DISPBKGND1 - \
  65 +                                                       SCALER_DISPBKGND0))
  66  #define SCALER_DISPSTAT1                        0x00000058
  67  #define SCALER_DISPSTATX(x)                    (SCALER_DISPSTAT0 +        \
  68                                                  (x) * (SCALER_DISPSTAT1 - \