target/linux/brcm2708/patches-4.4/0395-dmaengine-bcm2835-add-additional-defines-for-DMA-reg.patch

   1 From b1f4d42406261ed1ddffbbf0582ebbfaf6c0a73b Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Wed, 16 Mar 2016 12:24:57 -0700
   4 Subject: [PATCH 395/423] dmaengine: bcm2835: add additional defines for
   5  DMA-registers
   6
   7 Add additional defines describing the DMA registers
   8 as well as adding some more documentation to those registers.
   9
  10 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  11 Reviewed-by: Eric Anholt <eric@anholt.net>
  12 Signed-off-by: Eric Anholt <eric@anholt.net>
  13 Signed-off-by: Vinod Koul <vinod.koul@intel.com>
  14 ---
  15  drivers/dma/bcm2835-dma.c | 57 ++++++++++++++++++++++++++++++++++++++++-------
  16  1 file changed, 49 insertions(+), 8 deletions(-)
  17
  18 --- a/drivers/dma/bcm2835-dma.c
  19 +++ b/drivers/dma/bcm2835-dma.c
  20 @@ -97,26 +97,67 @@ struct bcm2835_desc {
  21
  22  #define BCM2835_DMA_CS         0x00
  23  #define BCM2835_DMA_ADDR       0x04
  24 +#define BCM2835_DMA_TI         0x08
  25  #define BCM2835_DMA_SOURCE_AD  0x0c
  26  #define BCM2835_DMA_DEST_AD    0x10
  27 -#define BCM2835_DMA_NEXTCB     0x1C
  28 +#define BCM2835_DMA_LEN                0x14
  29 +#define BCM2835_DMA_STRIDE     0x18
  30 +#define BCM2835_DMA_NEXTCB     0x1c
  31 +#define BCM2835_DMA_DEBUG      0x20
  32
  33  /* DMA CS Control and Status bits */
  34 -#define BCM2835_DMA_ACTIVE     BIT(0)
  35 -#define BCM2835_DMA_INT        BIT(2)
  36 +#define BCM2835_DMA_ACTIVE     BIT(0)  /* activate the DMA */
  37 +#define BCM2835_DMA_END                BIT(1)  /* current CB has ended */
  38 +#define BCM2835_DMA_INT                BIT(2)  /* interrupt status */
  39 +#define BCM2835_DMA_DREQ       BIT(3)  /* DREQ state */
  40  #define BCM2835_DMA_ISPAUSED   BIT(4)  /* Pause requested or not active */
  41  #define BCM2835_DMA_ISHELD     BIT(5)  /* Is held by DREQ flow control */
  42 -#define BCM2835_DMA_ERR        BIT(8)
  43 +#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
  44 +                                              * AXI-write to ack
  45 +                                              */
  46 +#define BCM2835_DMA_ERR                BIT(8)
  47 +#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
  48 +#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
  49 +/* current value of TI.BCM2835_DMA_WAIT_RESP */
  50 +#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
  51 +#define BCM2835_DMA_DIS_DEBUG  BIT(29) /* disable debug pause signal */
  52  #define BCM2835_DMA_ABORT      BIT(30) /* Stop current CB, go to next, WO */
  53  #define BCM2835_DMA_RESET      BIT(31) /* WO, self clearing */
  54
  55 +/* Transfer information bits - also bcm2835_cb.info field */
  56  #define BCM2835_DMA_INT_EN     BIT(0)
  57 +#define BCM2835_DMA_TDMODE     BIT(1) /* 2D-Mode */
  58 +#define BCM2835_DMA_WAIT_RESP  BIT(3) /* wait for AXI-write to be acked */
  59  #define BCM2835_DMA_D_INC      BIT(4)
  60 -#define BCM2835_DMA_D_DREQ     BIT(6)
  61 +#define BCM2835_DMA_D_WIDTH    BIT(5) /* 128bit writes if set */
  62 +#define BCM2835_DMA_D_DREQ     BIT(6) /* enable DREQ for destination */
  63 +#define BCM2835_DMA_D_IGNORE   BIT(7) /* ignore destination writes */
  64  #define BCM2835_DMA_S_INC      BIT(8)
  65 -#define BCM2835_DMA_S_DREQ     BIT(10)
  66 +#define BCM2835_DMA_S_WIDTH    BIT(9) /* 128bit writes if set */
  67 +#define BCM2835_DMA_S_DREQ     BIT(10) /* enable SREQ for source */
  68 +#define BCM2835_DMA_S_IGNORE   BIT(11) /* ignore source reads - read 0 */
  69 +#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
  70 +#define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
  71 +#define BCM2835_DMA_WAIT(x)    ((x & 31) << 21) /* add DMA-wait cycles */
  72 +#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
  73
  74 -#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
  75 +/* debug register bits */
  76 +#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR     BIT(0)
  77 +#define BCM2835_DMA_DEBUG_FIFO_ERR             BIT(1)
  78 +#define BCM2835_DMA_DEBUG_READ_ERR             BIT(2)
  79 +#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
  80 +#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
  81 +#define BCM2835_DMA_DEBUG_ID_SHIFT             16
  82 +#define BCM2835_DMA_DEBUG_ID_BITS              9
  83 +#define BCM2835_DMA_DEBUG_STATE_SHIFT          16
  84 +#define BCM2835_DMA_DEBUG_STATE_BITS           9
  85 +#define BCM2835_DMA_DEBUG_VERSION_SHIFT                25
  86 +#define BCM2835_DMA_DEBUG_VERSION_BITS         3
  87 +#define BCM2835_DMA_DEBUG_LITE                 BIT(28)
  88 +
  89 +/* shared registers for all dma channels */
  90 +#define BCM2835_DMA_INT_STATUS         0xfe0
  91 +#define BCM2835_DMA_ENABLE             0xff0
  92
  93  #define BCM2835_DMA_DATA_TYPE_S8       1
  94  #define BCM2835_DMA_DATA_TYPE_S16      2