target/linux/brcm2708/patches-4.4/0396-dmaengine-bcm2835-move-controlblock-chain-generation.patch

   1 From a41b5c7005c6880ac91b9e08062c6b6813df758e Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Wed, 16 Mar 2016 12:24:59 -0700
   4 Subject: [PATCH] dmaengine: bcm2835: move controlblock chain generation into
   5  separate method
   6
   7 In preparation of adding slave_sg functionality this patch moves the
   8 generation/allocation of bcm2835_desc and the building of
   9 the corresponding DMA-control-block chain from bcm2835_dma_prep_dma_cyclic
  10 into the newly created method bcm2835_dma_create_cb_chain.
  11
  12 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  13 Reviewed-by: Eric Anholt <eric@anholt.net>
  14 Signed-off-by: Eric Anholt <eric@anholt.net>
  15 Signed-off-by: Vinod Koul <vinod.koul@intel.com>
  16 ---
  17  drivers/dma/bcm2835-dma.c | 294 +++++++++++++++++++++++++++++++---------------
  18  1 file changed, 198 insertions(+), 96 deletions(-)
  19
  20 --- a/drivers/dma/bcm2835-dma.c
  21 +++ b/drivers/dma/bcm2835-dma.c
  22 @@ -88,12 +88,12 @@ struct bcm2835_desc {
  23         struct virt_dma_desc vd;
  24         enum dma_transfer_direction dir;
  25
  26 -       struct bcm2835_cb_entry *cb_list;
  27 -
  28         unsigned int frames;
  29         size_t size;
  30
  31         bool cyclic;
  32 +
  33 +       struct bcm2835_cb_entry cb_list[];
  34  };
  35
  36  #define BCM2835_DMA_CS         0x00
  37 @@ -169,6 +169,13 @@ struct bcm2835_desc {
  38  #define BCM2835_DMA_CHAN(n)    ((n) << 8) /* Base address */
  39  #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
  40
  41 +/* how many frames of max_len size do we need to transfer len bytes */
  42 +static inline size_t bcm2835_dma_frames_for_length(size_t len,
  43 +                                                  size_t max_len)
  44 +{
  45 +       return DIV_ROUND_UP(len, max_len);
  46 +}
  47 +
  48  static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
  49  {
  50         return container_of(d, struct bcm2835_dmadev, ddev);
  51 @@ -185,19 +192,161 @@ static inline struct bcm2835_desc *to_bc
  52         return container_of(t, struct bcm2835_desc, vd.tx);
  53  }
  54
  55 -static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
  56 +static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
  57  {
  58 -       struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
  59 -       int i;
  60 +       size_t i;
  61
  62         for (i = 0; i < desc->frames; i++)
  63                 dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
  64                               desc->cb_list[i].paddr);
  65
  66 -       kfree(desc->cb_list);
  67         kfree(desc);
  68  }
  69
  70 +static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
  71 +{
  72 +       bcm2835_dma_free_cb_chain(
  73 +               container_of(vd, struct bcm2835_desc, vd));
  74 +}
  75 +
  76 +static void bcm2835_dma_create_cb_set_length(
  77 +       struct bcm2835_chan *chan,
  78 +       struct bcm2835_dma_cb *control_block,
  79 +       size_t len,
  80 +       size_t period_len,
  81 +       size_t *total_len,
  82 +       u32 finalextrainfo)
  83 +{
  84 +       /* set the length */
  85 +       control_block->length = len;
  86 +
  87 +       /* finished if we have no period_length */
  88 +       if (!period_len)
  89 +               return;
  90 +
  91 +       /*
  92 +        * period_len means: that we need to generate
  93 +        * transfers that are terminating at every
  94 +        * multiple of period_len - this is typically
  95 +        * used to set the interrupt flag in info
  96 +        * which is required during cyclic transfers
  97 +        */
  98 +
  99 +       /* have we filled in period_length yet? */
 100 +       if (*total_len + control_block->length < period_len)
 101 +               return;
 102 +
 103 +       /* calculate the length that remains to reach period_length */
 104 +       control_block->length = period_len - *total_len;
 105 +
 106 +       /* reset total_length for next period */
 107 +       *total_len = 0;
 108 +
 109 +       /* add extrainfo bits in info */
 110 +       control_block->info |= finalextrainfo;
 111 +}
 112 +
 113 +/**
 114 + * bcm2835_dma_create_cb_chain - create a control block and fills data in
 115 + *
 116 + * @chan:           the @dma_chan for which we run this
 117 + * @direction:      the direction in which we transfer
 118 + * @cyclic:         it is a cyclic transfer
 119 + * @info:           the default info bits to apply per controlblock
 120 + * @frames:         number of controlblocks to allocate
 121 + * @src:            the src address to assign (if the S_INC bit is set
 122 + *                  in @info, then it gets incremented)
 123 + * @dst:            the dst address to assign (if the D_INC bit is set
 124 + *                  in @info, then it gets incremented)
 125 + * @buf_len:        the full buffer length (may also be 0)
 126 + * @period_len:     the period length when to apply @finalextrainfo
 127 + *                  in addition to the last transfer
 128 + *                  this will also break some control-blocks early
 129 + * @finalextrainfo: additional bits in last controlblock
 130 + *                  (or when period_len is reached in case of cyclic)
 131 + * @gfp:            the GFP flag to use for allocation
 132 + */
 133 +static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
 134 +       struct dma_chan *chan, enum dma_transfer_direction direction,
 135 +       bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
 136 +       dma_addr_t src, dma_addr_t dst, size_t buf_len,
 137 +       size_t period_len, gfp_t gfp)
 138 +{
 139 +       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 140 +       size_t len = buf_len, total_len;
 141 +       size_t frame;
 142 +       struct bcm2835_desc *d;
 143 +       struct bcm2835_cb_entry *cb_entry;
 144 +       struct bcm2835_dma_cb *control_block;
 145 +
 146 +       /* allocate and setup the descriptor. */
 147 +       d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
 148 +                   gfp);
 149 +       if (!d)
 150 +               return NULL;
 151 +
 152 +       d->c = c;
 153 +       d->dir = direction;
 154 +       d->cyclic = cyclic;
 155 +
 156 +       /*
 157 +        * Iterate over all frames, create a control block
 158 +        * for each frame and link them together.
 159 +        */
 160 +       for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
 161 +               cb_entry = &d->cb_list[frame];
 162 +               cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
 163 +                                             &cb_entry->paddr);
 164 +               if (!cb_entry->cb)
 165 +                       goto error_cb;
 166 +
 167 +               /* fill in the control block */
 168 +               control_block = cb_entry->cb;
 169 +               control_block->info = info;
 170 +               control_block->src = src;
 171 +               control_block->dst = dst;
 172 +               control_block->stride = 0;
 173 +               control_block->next = 0;
 174 +               /* set up length in control_block if requested */
 175 +               if (buf_len) {
 176 +                       /* calculate length honoring period_length */
 177 +                       bcm2835_dma_create_cb_set_length(
 178 +                               c, control_block,
 179 +                               len, period_len, &total_len,
 180 +                               cyclic ? finalextrainfo : 0);
 181 +
 182 +                       /* calculate new remaining length */
 183 +                       len -= control_block->length;
 184 +               }
 185 +
 186 +               /* link this the last controlblock */
 187 +               if (frame)
 188 +                       d->cb_list[frame - 1].cb->next = cb_entry->paddr;
 189 +
 190 +               /* update src and dst and length */
 191 +               if (src && (info & BCM2835_DMA_S_INC))
 192 +                       src += control_block->length;
 193 +               if (dst && (info & BCM2835_DMA_D_INC))
 194 +                       dst += control_block->length;
 195 +
 196 +               /* Length of total transfer */
 197 +               d->size += control_block->length;
 198 +       }
 199 +
 200 +       /* the last frame requires extra flags */
 201 +       d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
 202 +
 203 +       /* detect a size missmatch */
 204 +       if (buf_len && (d->size != buf_len))
 205 +               goto error_cb;
 206 +
 207 +       return d;
 208 +error_cb:
 209 +       bcm2835_dma_free_cb_chain(d);
 210 +
 211 +       return NULL;
 212 +}
 213 +
 214  static int bcm2835_dma_abort(void __iomem *chan_base)
 215  {
 216         unsigned long cs;
 217 @@ -391,12 +540,11 @@ static struct dma_async_tx_descriptor *b
 218         unsigned long flags)
 219  {
 220         struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 221 -       enum dma_slave_buswidth dev_width;
 222         struct bcm2835_desc *d;
 223 -       dma_addr_t dev_addr;
 224 -       unsigned int es, sync_type;
 225 -       unsigned int frame;
 226 -       int i;
 227 +       dma_addr_t src, dst;
 228 +       u32 info = BCM2835_DMA_WAIT_RESP;
 229 +       u32 extra = BCM2835_DMA_INT_EN;
 230 +       size_t frames;
 231
 232         /* Grab configuration */
 233         if (!is_slave_direction(direction)) {
 234 @@ -404,104 +552,58 @@ static struct dma_async_tx_descriptor *b
 235                 return NULL;
 236         }
 237
 238 -       if (direction == DMA_DEV_TO_MEM) {
 239 -               dev_addr = c->cfg.src_addr;
 240 -               dev_width = c->cfg.src_addr_width;
 241 -               sync_type = BCM2835_DMA_S_DREQ;
 242 -       } else {
 243 -               dev_addr = c->cfg.dst_addr;
 244 -               dev_width = c->cfg.dst_addr_width;
 245 -               sync_type = BCM2835_DMA_D_DREQ;
 246 -       }
 247 -
 248 -       /* Bus width translates to the element size (ES) */
 249 -       switch (dev_width) {
 250 -       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 251 -               es = BCM2835_DMA_DATA_TYPE_S32;
 252 -               break;
 253 -       default:
 254 +       if (!buf_len) {
 255 +               dev_err(chan->device->dev,
 256 +                       "%s: bad buffer length (= 0)\n", __func__);
 257                 return NULL;
 258         }
 259
 260 -       /* Now allocate and setup the descriptor. */
 261 -       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 262 -       if (!d)
 263 -               return NULL;
 264 -
 265 -       d->c = c;
 266 -       d->dir = direction;
 267 -       d->frames = buf_len / period_len;
 268 -       d->cyclic = true;
 269 +       /*
 270 +        * warn if buf_len is not a multiple of period_len - this may leed
 271 +        * to unexpected latencies for interrupts and thus audiable clicks
 272 +        */
 273 +       if (buf_len % period_len)
 274 +               dev_warn_once(chan->device->dev,
 275 +                             "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
 276 +                             __func__, buf_len, period_len);
 277 +
 278 +       /* Setup DREQ channel */
 279 +       if (c->dreq != 0)
 280 +               info |= BCM2835_DMA_PER_MAP(c->dreq);
 281
 282 -       d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
 283 -       if (!d->cb_list) {
 284 -               kfree(d);
 285 -               return NULL;
 286 +       if (direction == DMA_DEV_TO_MEM) {
 287 +               if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
 288 +                       return NULL;
 289 +               src = c->cfg.src_addr;
 290 +               dst = buf_addr;
 291 +               info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
 292 +       } else {
 293 +               if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
 294 +                       return NULL;
 295 +               dst = c->cfg.dst_addr;
 296 +               src = buf_addr;
 297 +               info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
 298         }
 299 -       /* Allocate memory for control blocks */
 300 -       for (i = 0; i < d->frames; i++) {
 301 -               struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
 302
 303 -               cb_entry->cb = dma_pool_zalloc(c->cb_pool, GFP_ATOMIC,
 304 -                                              &cb_entry->paddr);
 305 -               if (!cb_entry->cb)
 306 -                       goto error_cb;
 307 -       }
 308 +       /* calculate number of frames */
 309 +       frames = DIV_ROUND_UP(buf_len, period_len);
 310
 311         /*
 312 -        * Iterate over all frames, create a control block
 313 -        * for each frame and link them together.
 314 +        * allocate the CB chain
 315 +        * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
 316 +        * implementation calls prep_dma_cyclic with interrupts disabled.
 317          */
 318 -       for (frame = 0; frame < d->frames; frame++) {
 319 -               struct bcm2835_dma_cb *control_block = d->cb_list[frame].cb;
 320 -
 321 -               /* Setup adresses */
 322 -               if (d->dir == DMA_DEV_TO_MEM) {
 323 -                       control_block->info = BCM2835_DMA_D_INC;
 324 -                       control_block->src = dev_addr;
 325 -                       control_block->dst = buf_addr + frame * period_len;
 326 -               } else {
 327 -                       control_block->info = BCM2835_DMA_S_INC;
 328 -                       control_block->src = buf_addr + frame * period_len;
 329 -                       control_block->dst = dev_addr;
 330 -               }
 331 -
 332 -               /* Enable interrupt */
 333 -               control_block->info |= BCM2835_DMA_INT_EN;
 334 -
 335 -               /* Setup synchronization */
 336 -               if (sync_type != 0)
 337 -                       control_block->info |= sync_type;
 338 -
 339 -               /* Setup DREQ channel */
 340 -               if (c->dreq != 0)
 341 -                       control_block->info |=
 342 -                               BCM2835_DMA_PER_MAP(c->dreq);
 343 -
 344 -               /* Length of a frame */
 345 -               control_block->length = period_len;
 346 -               d->size += control_block->length;
 347 +       d = bcm2835_dma_create_cb_chain(chan, direction, true,
 348 +                                       info, extra,
 349 +                                       frames, src, dst, buf_len,
 350 +                                       period_len, GFP_NOWAIT);
 351 +       if (!d)
 352 +               return NULL;
 353
 354 -               /*
 355 -                * Next block is the next frame.
 356 -                * This DMA engine driver currently only supports cyclic DMA.
 357 -                * Therefore, wrap around at number of frames.
 358 -                */
 359 -               control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr;
 360 -       }
 361 +       /* wrap around into a loop */
 362 +       d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
 363
 364         return vchan_tx_prep(&c->vc, &d->vd, flags);
 365 -error_cb:
 366 -       i--;
 367 -       for (; i >= 0; i--) {
 368 -               struct bcm2835_cb_entry *cb_entry = &d->cb_list[i];
 369 -
 370 -               dma_pool_free(c->cb_pool, cb_entry->cb, cb_entry->paddr);
 371 -       }
 372 -
 373 -       kfree(d->cb_list);
 374 -       kfree(d);
 375 -       return NULL;
 376  }
 377
 378  static int bcm2835_dma_slave_config(struct dma_chan *chan,