target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch

   1 From c08886564938df6796a7d98495cf5cc3f7a09337 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Wed, 18 Jan 2017 07:31:55 +1100
   4 Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL
   5  dividers (v2).
   6
   7 Our core PLLs are intended to be configured once and left alone.  With
   8 the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
   9 change PLLD just to get closer to the requested DSI clock, thus
  10 changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
  11 it, and breaking ethernet.
  12
  13 We *do* want PLLH to change so that PLLH_AUX can be exactly the value
  14 we want, though.  Thus, we need to have a per-divider policy of
  15 whether to pass rate changes up.
  16
  17 Signed-off-by: Eric Anholt <eric@anholt.net>
  18 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  19 (cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5)
  20 ---
  21  drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++--------------
  22  1 file changed, 28 insertions(+), 14 deletions(-)
  23
  24 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
  25 index 89dad97..54cb4e1 100644
  26 --- a/drivers/clk/bcm/clk-bcm2835.c
  27 +++ b/drivers/clk/bcm/clk-bcm2835.c
  28 @@ -449,6 +449,7 @@ struct bcm2835_pll_divider_data {
  29         u32 load_mask;
  30         u32 hold_mask;
  31         u32 fixed_divider;
  32 +       u32 flags;
  33  };
  34
  35  struct bcm2835_clock_data {
  36 @@ -1286,7 +1287,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
  37         init.num_parents = 1;
  38         init.name = divider_name;
  39         init.ops = &bcm2835_pll_divider_clk_ops;
  40 -       init.flags = CLK_IGNORE_UNUSED;
  41 +       init.flags = data->flags | CLK_IGNORE_UNUSED;
  42
  43         divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
  44         if (!divider)
  45 @@ -1525,7 +1526,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  46                 .a2w_reg = A2W_PLLA_CORE,
  47                 .load_mask = CM_PLLA_LOADCORE,
  48                 .hold_mask = CM_PLLA_HOLDCORE,
  49 -               .fixed_divider = 1),
  50 +               .fixed_divider = 1,
  51 +               .flags = CLK_SET_RATE_PARENT),
  52         [BCM2835_PLLA_PER]      = REGISTER_PLL_DIV(
  53                 .name = "plla_per",
  54                 .source_pll = "plla",
  55 @@ -1533,7 +1535,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  56                 .a2w_reg = A2W_PLLA_PER,
  57                 .load_mask = CM_PLLA_LOADPER,
  58                 .hold_mask = CM_PLLA_HOLDPER,
  59 -               .fixed_divider = 1),
  60 +               .fixed_divider = 1,
  61 +               .flags = CLK_SET_RATE_PARENT),
  62         [BCM2835_PLLA_DSI0]     = REGISTER_PLL_DIV(
  63                 .name = "plla_dsi0",
  64                 .source_pll = "plla",
  65 @@ -1549,7 +1552,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  66                 .a2w_reg = A2W_PLLA_CCP2,
  67                 .load_mask = CM_PLLA_LOADCCP2,
  68                 .hold_mask = CM_PLLA_HOLDCCP2,
  69 -               .fixed_divider = 1),
  70 +               .fixed_divider = 1,
  71 +               .flags = CLK_SET_RATE_PARENT),
  72
  73         /* PLLB is used for the ARM's clock. */
  74         [BCM2835_PLLB]          = REGISTER_PLL(
  75 @@ -1573,7 +1577,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  76                 .a2w_reg = A2W_PLLB_ARM,
  77                 .load_mask = CM_PLLB_LOADARM,
  78                 .hold_mask = CM_PLLB_HOLDARM,
  79 -               .fixed_divider = 1),
  80 +               .fixed_divider = 1,
  81 +               .flags = CLK_SET_RATE_PARENT),
  82
  83         /*
  84          * PLLC is the core PLL, used to drive the core VPU clock.
  85 @@ -1602,7 +1607,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  86                 .a2w_reg = A2W_PLLC_CORE0,
  87                 .load_mask = CM_PLLC_LOADCORE0,
  88                 .hold_mask = CM_PLLC_HOLDCORE0,
  89 -               .fixed_divider = 1),
  90 +               .fixed_divider = 1,
  91 +               .flags = CLK_SET_RATE_PARENT),
  92         [BCM2835_PLLC_CORE1]    = REGISTER_PLL_DIV(
  93                 .name = "pllc_core1",
  94                 .source_pll = "pllc",
  95 @@ -1610,7 +1616,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
  96                 .a2w_reg = A2W_PLLC_CORE1,
  97                 .load_mask = CM_PLLC_LOADCORE1,
  98                 .hold_mask = CM_PLLC_HOLDCORE1,
  99 -               .fixed_divider = 1),
 100 +               .fixed_divider = 1,
 101 +               .flags = CLK_SET_RATE_PARENT),
 102         [BCM2835_PLLC_CORE2]    = REGISTER_PLL_DIV(
 103                 .name = "pllc_core2",
 104                 .source_pll = "pllc",
 105 @@ -1618,7 +1625,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 106                 .a2w_reg = A2W_PLLC_CORE2,
 107                 .load_mask = CM_PLLC_LOADCORE2,
 108                 .hold_mask = CM_PLLC_HOLDCORE2,
 109 -               .fixed_divider = 1),
 110 +               .fixed_divider = 1,
 111 +               .flags = CLK_SET_RATE_PARENT),
 112         [BCM2835_PLLC_PER]      = REGISTER_PLL_DIV(
 113                 .name = "pllc_per",
 114                 .source_pll = "pllc",
 115 @@ -1626,7 +1634,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 116                 .a2w_reg = A2W_PLLC_PER,
 117                 .load_mask = CM_PLLC_LOADPER,
 118                 .hold_mask = CM_PLLC_HOLDPER,
 119 -               .fixed_divider = 1),
 120 +               .fixed_divider = 1,
 121 +               .flags = CLK_SET_RATE_PARENT),
 122
 123         /*
 124          * PLLD is the display PLL, used to drive DSI display panels.
 125 @@ -1655,7 +1664,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 126                 .a2w_reg = A2W_PLLD_CORE,
 127                 .load_mask = CM_PLLD_LOADCORE,
 128                 .hold_mask = CM_PLLD_HOLDCORE,
 129 -               .fixed_divider = 1),
 130 +               .fixed_divider = 1,
 131 +               .flags = CLK_SET_RATE_PARENT),
 132         [BCM2835_PLLD_PER]      = REGISTER_PLL_DIV(
 133                 .name = "plld_per",
 134                 .source_pll = "plld",
 135 @@ -1663,7 +1673,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 136                 .a2w_reg = A2W_PLLD_PER,
 137                 .load_mask = CM_PLLD_LOADPER,
 138                 .hold_mask = CM_PLLD_HOLDPER,
 139 -               .fixed_divider = 1),
 140 +               .fixed_divider = 1,
 141 +               .flags = CLK_SET_RATE_PARENT),
 142         [BCM2835_PLLD_DSI0]     = REGISTER_PLL_DIV(
 143                 .name = "plld_dsi0",
 144                 .source_pll = "plld",
 145 @@ -1708,7 +1719,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 146                 .a2w_reg = A2W_PLLH_RCAL,
 147                 .load_mask = CM_PLLH_LOADRCAL,
 148                 .hold_mask = 0,
 149 -               .fixed_divider = 10),
 150 +               .fixed_divider = 10,
 151 +               .flags = CLK_SET_RATE_PARENT),
 152         [BCM2835_PLLH_AUX]      = REGISTER_PLL_DIV(
 153                 .name = "pllh_aux",
 154                 .source_pll = "pllh",
 155 @@ -1716,7 +1728,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 156                 .a2w_reg = A2W_PLLH_AUX,
 157                 .load_mask = CM_PLLH_LOADAUX,
 158                 .hold_mask = 0,
 159 -               .fixed_divider = 1),
 160 +               .fixed_divider = 1,
 161 +               .flags = CLK_SET_RATE_PARENT),
 162         [BCM2835_PLLH_PIX]      = REGISTER_PLL_DIV(
 163                 .name = "pllh_pix",
 164                 .source_pll = "pllh",
 165 @@ -1724,7 +1737,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 166                 .a2w_reg = A2W_PLLH_PIX,
 167                 .load_mask = CM_PLLH_LOADPIX,
 168                 .hold_mask = 0,
 169 -               .fixed_divider = 10),
 170 +               .fixed_divider = 10,
 171 +               .flags = CLK_SET_RATE_PARENT),
 172
 173         /* the clocks */
 174
 175 --
 176 2.1.4
 177