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add initial support for the crisarchitecture used on foxboards to openwrt
[openwrt/staging/dedeckeh.git] / target / linux / etrax-2.6 / image / e100boot / src / cbl / src / hwregs_int.h
1 /*!**********************************************************************
2 *!
3 *! FILE NAME: hwregs_int.h
4 *!
5 *! DESCRIPTION: Internal shadow register implementation.
6 *! Not intended for general use.
7 *! This file is include in hwregs.h
8 *!
9 *! FUNCTIONS: none
10 *!
11 *! NOTE: This file is automatically generated, do _not_ edit.
12 *! Created: Thu Oct 3 01:21:27 2002
13 *! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
14 *! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
15 *! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
16 *!
17 *! MACROS: REG_INITIATED
18 *! REG_CHECK_INIT
19 *! REG_ICHECK_INIT
20 *! REG_CHECK_INR
21 *! REG_VAL_VAL
22 *! REG_SVAL
23 *! REG_SVAL_ZERO
24 *! REG_SVAL_SHADOW
25 *! REG_SVAL_I
26 *! REG_SVAL_I_ZERO
27 *! REG_SVAL_I_SHADOW
28 *!
29 *! REG_IMASK
30 *! REG_ADDR_I
31 *! REG_SADDR_I
32 *! REG_IADDR_I
33 *! REG_VAL_ENUM
34 *! REG_GET_WO
35 *! REG_GET_RO
36 *! REG_GET_RW
37 *! REG_IGET_WO
38 *! REG_IGET_RO
39 *! REG_IGET_RW
40 *! REG_SET_WO
41 *! REG_ISET_WO
42 *! REG_SET_VAL_WO
43 *! REG_SET_RW
44 *! REG_ISET_RW
45 *! REG_SET_VAL_RW
46 *! REG_EQL_WO
47 *! REG_EQL_RO
48 *! REG_EQL_RW
49 *! REG_IEQL_WO
50 *! REG_IEQL_RO
51 *! REG_IEQL_RW
52 *! REG_RD_WO
53 *! REG_RD_RO
54 *! REG_RD_RW
55 *! REG_IRD_WO
56 *! REG_IRD_RO
57 *! REG_IRD_RW
58 *! REG_WR_WO
59 *! REG_WR_RW
60 *! REG_IWR_WO
61 *! REG_IWR_RW
62 *!
63 *!----------------------------------------------------------------------
64 *! HISTORY
65 *!
66 *! DATE NAME CHANGES
67 *! ---- ---- -------
68 *! Apr 01 1998 Jan Bengtsson Initial version
69 *! Oct 01 2002 Hans-Peter Nilsson Large mechanical changes to correct
70 *! use of the ## operator.
71 *!----------------------------------------------------------------------
72 *!
73 *! (C) Copyright 1998, 2002 Axis Communications AB, LUND, SWEDEN
74 *!
75 *!**********************************************************************/
76 /* %Z% %M% %I% %G% */
77
78 #ifndef __HWREGS_INT_H__
79 #define __HWREGS_INT_H__
80
81 /********************** INCLUDE FILES SECTION **************************/
82
83 /********************** CONSTANT AND MACRO SECTION *********************/
84 #ifndef __REG_GENERAL_INT_H__
85 #define __REG_GENERAL_INT_H__
86
87 /*
88 ** The first part of hwregs_int.h is common to all shadow
89 ** register modules, and should therefore only be included once to
90 ** avoid macro redefinitions.
91 */
92
93 #if REG_DEBUG && !defined(__ASSEMBLER__)
94
95 #ifndef REG_SERROR
96 #define REG_SERROR(ok,reg) \
97 assert( ok ),
98 #endif
99
100 #ifndef REG_VERROR
101 #define REG_VERROR(ok,val) \
102 assert( ok ),
103 #endif
104
105 #ifndef REG_IERROR
106 #define REG_IERROR(ok,i,reg) \
107 assert( ok ),
108 #endif
109
110 /*#**********************************************************************
111 *#
112 *# MACRO NAME : REG_INITIATED
113 *#
114 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
115 *#
116 *# RETURNS : 0
117 *#
118 *# SIDE EFFECTS: Clears initiated flag in reg_initiated_type struct.
119 *#
120 *# DESCRIPTION : Clears initiated flag in reg_initiated_type struct.
121 *#
122 *#----------------------------------------------------------------------
123 *# HISTORY
124 *#
125 *# DATE NAME CHANGES
126 *# ---- ---- -------
127 *# Apr 01 1998 Jan Bengtsson Initial version
128 *# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended.
129 *#**********************************************************************/
130
131 #define REG_INITIATED(reg_) \
132 *reg_##_IADDR = 0,
133
134 /*#**********************************************************************
135 *#
136 *# MACRO NAME : REG_CHECK_INIT
137 *#
138 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
139 *#
140 *# RETURNS : Value of REG_SERROR macro.
141 *#
142 *# SIDE EFFECTS: Evaluates REG_SERROR macro.
143 *#
144 *# DESCRIPTION : Check that shadow is initiated, by
145 *# evaluating REG_SERROR macro.
146 *#
147 *#----------------------------------------------------------------------
148 *# HISTORY
149 *#
150 *# DATE NAME CHANGES
151 *# ---- ---- -------
152 *# Apr 01 1998 Jan Bengtsson Initial version
153 *# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended.
154 *# Correct stringization.
155 *#**********************************************************************/
156
157 #define REG_CHECK_INIT(reg_) \
158 REG_SERROR(*reg_##_IADDR == 0, #reg_)
159
160 /*#**********************************************************************
161 *#
162 *# MACRO NAME : REG_ICHECK_INIT
163 *#
164 *# PARAMETERS : i : Interface number.
165 *# reg_: Name of a register, with "_" appended.
166 *#
167 *# RETURNS : Value of REG_SERROR macro.
168 *#
169 *# SIDE EFFECTS: Evaluates REG_SERROR macro.
170 *#
171 *# DESCRIPTION : Check that shadow is initiated, by
172 *# evaluating REG_SERROR macro.
173 *#
174 *#----------------------------------------------------------------------
175 *# HISTORY
176 *#
177 *# DATE NAME CHANGES
178 *# ---- ---- -------
179 *# Apr 01 1998 Jan Bengtsson Initial version
180 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
181 *# Correct stringization.
182 *#**********************************************************************/
183
184 #define REG_ICHECK_INIT(i, reg_) \
185 REG_SERROR(*REG_IADDR_I(i, reg_) == 0, #reg_)
186
187 /*#**********************************************************************
188 *#
189 *# MACRO NAME : REG_CHECK_INR
190 *#
191 *# PARAMETERS : i : Interface number.
192 *# reg_: Name of a register, with "_" appended.
193 *#
194 *# RETURNS : Value of REG_IERROR macro.
195 *#
196 *# SIDE EFFECTS: Evaluates REG_IERROR macro.
197 *#
198 *# DESCRIPTION : Check that interface number is valid.
199 *# If an invalid interface number is found at compile
200 *# time gcc report the following warning:
201 *# 'warning: right shift count >= width of type'
202 *# If an invalid interface number is found at run time
203 *# the REG_IERROR macro is evaluated.
204 *#----------------------------------------------------------------------
205 *# HISTORY
206 *#
207 *# DATE NAME CHANGES
208 *# ---- ---- -------
209 *# Apr 01 1998 Jan Bengtsson Initial version
210 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
211 *# Correct stringization.
212 *#**********************************************************************/
213
214 #define REG_CHECK_INR(i, reg_) \
215 REG_IERROR( \
216 1 >> ( \
217 ( \
218 (udword)(~(i)) > (udword)(~(reg_##_FIRST)) || \
219 (udword)(i) > (udword)(reg_##_LAST) \
220 ) ? 32 : 0 \
221 ), \
222 i, #reg_ \
223 )
224
225 /*#**********************************************************************
226 *#
227 *# MACRO NAME : REG_VAL_VAL
228 *#
229 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
230 *# field_: Name of a field, with "_" appended.
231 *# val : Integer value
232 *#
233 *# RETURNS : val
234 *#
235 *# SIDE EFFECTS: Evaluate REG_VERROR macro.
236 *#
237 *# DESCRIPTION : Check that an integer value is within field range.
238 *# If val parameter is found to be out of range at compile
239 *# time gcc report the following warning:
240 *# 'left shift count >= width of type'
241 *# If an invalid integer value is found at run time
242 *# the REG_VERROR macro is evaluated.
243 *#----------------------------------------------------------------------
244 *# HISTORY
245 *#
246 *# DATE NAME CHANGES
247 *# ---- ---- -------
248 *# Apr 01 1998 Jan Bengtsson Initial version
249 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
250 *# have "_" appended.
251 *#**********************************************************************/
252
253 #define REG_VAL_VAL(reg_, field_, val) ( \
254 REG_VERROR( \
255 1 << ( \
256 ( \
257 (udword)(~(val)) > (udword)(~(reg_##_##field_##_MIN)) || \
258 (udword)(val) > (udword)(reg_##_##field_##_MAX) \
259 ) ? 32 : 0 \
260 ), \
261 val \
262 ) \
263 val \
264 )
265
266 #else /* ! REG_DEBUG || __ASSEMBER__ */
267
268 /* Checks only done in debug mode. */
269 /* No need for REG_VERROR, REG_SERROR, and REG_IERROR. */
270
271 #define REG_INITIATED(reg)
272 #define REG_CHECK_INIT(reg)
273 #define REG_ICHECK_INIT(i,reg)
274 #define REG_CHECK_INR(i,reg)
275 #define REG_VAL_VAL(reg,field,val) (val)
276
277 #endif
278
279 /*#**********************************************************************
280 *#
281 *# MACRO NAME : REG_SVAL
282 *#
283 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
284 *#
285 *# RETURNS : Value of shadow register associated with a WO register,
286 *# or 0.
287 *#
288 *# SIDE EFFECTS: None
289 *#
290 *# DESCRIPTION : Read contents of a shadow register. By using this macro
291 *# it's possible to force special values for some registers,
292 *# e.g. zero for set/clr registers.
293 *#
294 *#----------------------------------------------------------------------
295 *# HISTORY
296 *#
297 *# DATE NAME CHANGES
298 *# ---- ---- -------
299 *# Apr 01 1998 Jan Bengtsson Initial version
300 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
301 *#**********************************************************************/
302 #define REG_SVAL(reg_) ( \
303 reg_##_SVAL(reg_) \
304 )
305
306 /*#**********************************************************************
307 *#
308 *# MACRO NAME : REG_SVAL_ZERO
309 *#
310 *# PARAMETERS : reg : Name of a register.
311 *#
312 *# RETURNS : Zero.
313 *#
314 *# SIDE EFFECTS: None
315 *#
316 *# DESCRIPTION : Force contents of shadow register to zero, used by
317 *# the set/clr registers.
318 *#
319 *#----------------------------------------------------------------------
320 *# HISTORY
321 *#
322 *# DATE NAME CHANGES
323 *# ---- ---- -------
324 *# Apr 01 1998 Jan Bengtsson Initial version
325 *#**********************************************************************/
326 #define REG_SVAL_ZERO(reg) ( \
327 0 \
328 )
329
330 /*#**********************************************************************
331 *#
332 *# MACRO NAME : REG_SVAL_SHADOW
333 *#
334 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
335 *#
336 *# RETURNS : Value of shadow register associated with a WO register.
337 *#
338 *# SIDE EFFECTS: None
339 *#
340 *# DESCRIPTION : Read shadow register contents.
341 *#
342 *#----------------------------------------------------------------------
343 *# HISTORY
344 *#
345 *# DATE NAME CHANGES
346 *# ---- ---- -------
347 *# Apr 01 1998 Jan Bengtsson Initial version
348 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
349 *#**********************************************************************/
350 #define REG_SVAL_SHADOW(reg_) ( \
351 *reg_##_SADDR \
352 )
353
354 /*#**********************************************************************
355 *#
356 *# MACRO NAME : REG_SVAL_I
357 *#
358 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
359 *# i : Interface number.
360 *#
361 *# RETURNS : Value of shadow register associated with a WO register,
362 *# or 0, for interface i.
363 *#
364 *# SIDE EFFECTS: None
365 *#
366 *# DESCRIPTION : Read contents of a shadow register. By using this macro
367 *# it's possible to force special values for some registers,
368 *# e.g. zero for set/clr registers.
369 *#
370 *#----------------------------------------------------------------------
371 *# HISTORY
372 *#
373 *# DATE NAME CHANGES
374 *# ---- ---- -------
375 *# Apr 01 1998 Jan Bengtsson Initial version
376 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
377 *#**********************************************************************/
378 #define REG_SVAL_I(i, reg_) ( \
379 reg_##_SVAL_I(i, reg_) \
380 )
381
382 /*#**********************************************************************
383 *#
384 *# MACRO NAME : REG_SVAL_I_ZERO
385 *#
386 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
387 *# i : Interface number.
388 *#
389 *# RETURNS : Zero.
390 *#
391 *# SIDE EFFECTS: None
392 *#
393 *# DESCRIPTION : Force contents of shadow register to zero, used by
394 *# the set/clr registers, for interface i.
395 *#
396 *#----------------------------------------------------------------------
397 *# HISTORY
398 *#
399 *# DATE NAME CHANGES
400 *# ---- ---- -------
401 *# Apr 01 1998 Jan Bengtsson Initial version
402 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
403 *#**********************************************************************/
404 #define REG_SVAL_I_ZERO(i,reg) ( \
405 0 \
406 )
407
408 /*#**********************************************************************
409 *#
410 *# MACRO NAME : REG_SVAL_I_SHADOW
411 *#
412 *# PARAMETERS : reg_ : Name of a register.
413 *# i : Interface number.
414 *#
415 *# RETURNS : Value of shadow register associated with a WO register,
416 *# for interface i.
417 *#
418 *# SIDE EFFECTS: None
419 *#
420 *# DESCRIPTION : Read shadow register contents, of interface i.
421 *#
422 *#----------------------------------------------------------------------
423 *# HISTORY
424 *#
425 *# DATE NAME CHANGES
426 *# ---- ---- -------
427 *# Apr 01 1998 Jan Bengtsson Initial version
428 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
429 *#**********************************************************************/
430 #define REG_SVAL_I_SHADOW(i, reg_) ( \
431 *REG_SADDR_I(i, reg_) \
432 )
433
434 /*#**********************************************************************
435 *#
436 *# MACRO NAME : REG_IMASK
437 *#
438 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
439 *# field_ : Name of a field, with "_" appended.
440 *#
441 *# RETURNS : Inverse of field mask.
442 *#
443 *# SIDE EFFECTS: none
444 *#
445 *# DESCRIPTION : Create a mask with zeros matching the field,
446 *# and ones matching the rest.
447 *#----------------------------------------------------------------------
448 *# HISTORY
449 *#
450 *# DATE NAME CHANGES
451 *# ---- ---- -------
452 *# Apr 01 1998 Jan Bengtsson Initial version
453 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
454 *# have "_" appended.
455 *#**********************************************************************/
456
457 #define REG_IMASK(reg_, field_) ( \
458 ~reg_##_##field_##_##field_##_MASK \
459 )
460
461 /*#**********************************************************************
462 *#
463 *# MACRO NAME : REG_ADDR_I
464 *#
465 *# PARAMETERS : i : interface number.
466 *# reg_ : Name of a register, with "_" appended.
467 *#
468 *# RETURNS : Address to reg for interface i.
469 *#
470 *# SIDE EFFECTS: May evaluate REG_IERROR.
471 *#
472 *# DESCRIPTION : Calculate address to reg for interface i.
473 *#
474 *#----------------------------------------------------------------------
475 *# HISTORY
476 *#
477 *# DATE NAME CHANGES
478 *# ---- ---- -------
479 *# Apr 01 1998 Jan Bengtsson Initial version
480 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
481 *#**********************************************************************/
482
483 #define REG_ADDR_I(i, reg_) ( \
484 reg_##_TYPECAST ( \
485 REG_CHECK_INR(i, reg_) \
486 ((udword) reg_##_ADDR) + reg_##_OFFSET * (i) \
487 ) \
488 )
489
490 /*#**********************************************************************
491 *#
492 *# MACRO NAME : REG_SADDR_I
493 *#
494 *# PARAMETERS : i : interface number.
495 *# reg_ : Name of a register, with "_" appended.
496 *#
497 *# RETURNS : Address to shadow register for interface i.
498 *#
499 *# SIDE EFFECTS: May evaluate REG_IERROR.
500 *#
501 *# DESCRIPTION : Calculate address to shadow register for interface i.
502 *#
503 *#----------------------------------------------------------------------
504 *# HISTORY
505 *#
506 *# DATE NAME CHANGES
507 *# ---- ---- -------
508 *# Apr 01 1998 Jan Bengtsson Initial version
509 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
510 *#**********************************************************************/
511
512 #define REG_SADDR_I(i, reg_) ( \
513 reg_##_STYPECAST ( \
514 REG_CHECK_INR(i, reg_) \
515 ((udword) reg_##_SADDR) + reg_##_SOFFSET * (i) \
516 ) \
517 )
518
519 /*#**********************************************************************
520 *#
521 *# MACRO NAME : REG_IADDR_I
522 *#
523 *# PARAMETERS : i : interface number.
524 *# reg_ : Name of a register, with "_" appended.
525 *#
526 *# RETURNS : Address to initiated flag for interface i.
527 *#
528 *# SIDE EFFECTS: May evaluate REG_IERROR.
529 *#
530 *# DESCRIPTION : Calculate address to initiated flag for interface i.
531 *# The reg_initiated_type struct has the same layout as
532 *# the reg_shadow_type struct, i.e. it's possible to use
533 *# <reg>__SOFFSET here to.
534 *#
535 *#----------------------------------------------------------------------
536 *# HISTORY
537 *#
538 *# DATE NAME CHANGES
539 *# ---- ---- -------
540 *# Apr 01 1998 Jan Bengtsson Initial version
541 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
542 *#**********************************************************************/
543
544 #define REG_IADDR_I(i, reg_) ( \
545 reg_##_STYPECAST ( \
546 REG_CHECK_INR(i, reg_) \
547 ((udword) reg_##_IADDR) + reg_##_SOFFSET * (i) \
548 ) \
549 )
550
551 /*#**********************************************************************
552 *#
553 *# MACRO NAME : REG_VAL_ENUM
554 *#
555 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
556 *# field_: Name of a field, with "_" appended.
557 *# sym : Symbolic value.
558 *#
559 *# RETURNS : Integer value for sym.
560 *#
561 *# SIDE EFFECTS: none
562 *#
563 *# DESCRIPTION : Convert symbolic value to an integer value.
564 *#
565 *#----------------------------------------------------------------------
566 *# HISTORY
567 *#
568 *# DATE NAME CHANGES
569 *# ---- ---- -------
570 *# Apr 01 1998 Jan Bengtsson Initial version
571 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
572 *# have "_" appended.
573 *#**********************************************************************/
574
575 #define REG_VAL_ENUM(reg_, field_, sym) ( \
576 reg_##_##field_##_##field_##_##sym \
577 )
578
579 /*#**********************************************************************
580 *#
581 *# MACRO NAME : REG_GET_WO
582 *#
583 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
584 *# field_ : Name of a field, with "_" appended.
585 *#
586 *# RETURNS : Value of field field in register reg.
587 *#
588 *# SIDE EFFECTS: May evaluate REG_SERROR.
589 *#
590 *# DESCRIPTION : Read a field in a write only shadow register,
591 *# i.e. from the shadow register. If the shadow register
592 *# isn't initiated the REG_SERROR macro is evaluated.
593 *#
594 *#----------------------------------------------------------------------
595 *# HISTORY
596 *#
597 *# DATE NAME CHANGES
598 *# ---- ---- -------
599 *# Apr 01 1998 Jan Bengtsson Initial version
600 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
601 *# have "_" appended.
602 *#**********************************************************************/
603
604 #define REG_GET_WO(reg_, field_) ( \
605 REG_CHECK_INIT(reg_) \
606 (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \
607 reg_##_##field_##_BITNR \
608 )
609
610 /*#**********************************************************************
611 *#
612 *# MACRO NAME : REG_GET_RO, REG_GET_RW
613 *#
614 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
615 *# field_ : Name of a field, with "_" appended.
616 *#
617 *# RETURNS : Value of field field in register reg.
618 *#
619 *# SIDE EFFECTS: none
620 *#
621 *# DESCRIPTION : Read a field in a read only or read write shadow register.
622 *#
623 *#----------------------------------------------------------------------
624 *# HISTORY
625 *#
626 *# DATE NAME CHANGES
627 *# ---- ---- -------
628 *# Apr 01 1998 Jan Bengtsson Initial version
629 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
630 *# have "_" appended.
631 *#**********************************************************************/
632
633 #define REG_GET_RO(reg_, field_) ( \
634 (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \
635 reg_##_##field_##_BITNR \
636 )
637
638 #define REG_GET_RW REG_GET_RO
639
640 /*#**********************************************************************
641 *#
642 *# MACRO NAME : REG_IGET_WO
643 *#
644 *# PARAMETERS : i : Interface number.
645 *# reg_ : Name of a register, with "_" appended.
646 *# field_: Name of a field, with "_" appended.
647 *#
648 *# RETURNS : Value of field field in register reg.
649 *#
650 *# SIDE EFFECTS: May evaluate REG_SERROR, and REG_IERROR.
651 *#
652 *# DESCRIPTION : Read a field in a write only register for interface i,
653 *# i.e. from the shadow register. If the shadow register
654 *# isn't initiated the REG_SERROR macro is evaluated,
655 *# and if i is out of range REG_IERROR is evaluated.
656 *#
657 *#----------------------------------------------------------------------
658 *# HISTORY
659 *#
660 *# DATE NAME CHANGES
661 *# ---- ---- -------
662 *# Apr 01 1998 Jan Bengtsson Initial version
663 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
664 *# have "_" appended.
665 *#**********************************************************************/
666
667 #define REG_IGET_WO(i, reg_, field_) ( \
668 REG_ICHECK_INIT(i, reg_) \
669 (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \
670 reg_##_##field_##_BITNR \
671 )
672
673 /*#**********************************************************************
674 *#
675 *# MACRO NAME : REG_IGET_RO, REG_IGET_RW
676 *#
677 *# PARAMETERS : i : Interface number.
678 *# reg_ : Name of a register, with "_" appended.
679 *# field_: Name of a field, with "_" appended.
680 *#
681 *# RETURNS : Value of field field in register reg.
682 *#
683 *# SIDE EFFECTS: May evaluate REG_IERROR.
684 *#
685 *# DESCRIPTION : Read a field in a read only or read write register for
686 *# interface i. If i is out of range REG_IERROR is evaluated.
687 *#
688 *#----------------------------------------------------------------------
689 *# HISTORY
690 *#
691 *# DATE NAME CHANGES
692 *# ---- ---- -------
693 *# Apr 01 1998 Jan Bengtsson Initial version
694 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
695 *# have "_" appended.
696 *#**********************************************************************/
697
698 #define REG_IGET_RO(i, reg_, field_) ( \
699 (reg_##_READ(REG_ADDR_I(i, reg_) ) & \
700 reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \
701 )
702
703 #define REG_IGET_RW REG_IGET_RO
704
705 /*#**********************************************************************
706 *#
707 *# MACRO NAME : REG_SET_WO
708 *#
709 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
710 *# field_: Name of a field, with "_" appended.
711 *# val : Value to write to field.
712 *#
713 *# RETURNS : Integer value written to complete register.
714 *#
715 *# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
716 *#
717 *# DESCRIPTION : Write val parameter to field field in write only register
718 *# reg and in the shadow register. If the shadow register
719 *# isn't initiated REG_SERROR is evaluated, and if the
720 *# val parameter is out of range REG_VERROR is evaluated.
721 *#
722 *#----------------------------------------------------------------------
723 *# HISTORY
724 *#
725 *# DATE NAME CHANGES
726 *# ---- ---- -------
727 *# Apr 01 1998 Jan Bengtsson Initial version
728 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
729 *# have "_" appended.
730 *#**********************************************************************/
731
732 #define REG_SET_WO(reg_, field_, val) ( \
733 *reg_##_SADDR = ( \
734 REG_CHECK_INIT(reg_) \
735 (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \
736 (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
737 reg_##_##field_##_BITNR) \
738 ), \
739 reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
740 )
741
742 /*#**********************************************************************
743 *#
744 *# MACRO NAME : REG_ISET_WO
745 *#
746 *# PARAMETERS : i : Interface number.
747 *# reg_ : Name of a register, with "_" appended.
748 *# field_: Name of a field, with "_" appended.
749 *# val : Value to write to field.
750 *#
751 *# RETURNS : Integer value written to complete register.
752 *#
753 *# SIDE EFFECTS: May evaluate REG_IERROR, REG_SERROR, and REG_VERROR.
754 *#
755 *# DESCRIPTION : Write val parameter to field field in write only register
756 *# reg of interface i and in the shadow register. If the
757 *# shadow register isn't initiated REG_SERROR is evaluated,
758 *# and if the val parameter is out of range REG_VERROR is
759 *# evaluated, and if the interface number is out of range
760 *# REG_IERROR is evaluated.
761 *#
762 *#----------------------------------------------------------------------
763 *# HISTORY
764 *#
765 *# DATE NAME CHANGES
766 *# ---- ---- -------
767 *# Apr 01 1998 Jan Bengtsson Initial version
768 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
769 *# have "_" appended.
770 *#**********************************************************************/
771
772 #define REG_ISET_WO(i, reg_, field_, val) ( \
773 *REG_SADDR_I(i, reg_) = ( \
774 REG_ICHECK_INIT(i, reg_) \
775 (REG_SVAL_I(i, reg_) & REG_IMASK(reg_, field_)) | \
776 (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
777 reg_##_##field_##_BITNR) \
778 ), \
779 reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \
780 )
781
782 /*#**********************************************************************
783 *#
784 *# MACRO NAME : REG_SET_VAL_WO
785 *#
786 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
787 *# field_: Name of a field, with "_" appended.
788 *# val : Integer value to write to symbolic field.
789 *#
790 *# RETURNS : Integer value written to complete register.
791 *#
792 *# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
793 *#
794 *# DESCRIPTION : Write val parameter to field field in write only register
795 *# reg and in the shadow register. If the shadow register
796 *# isn't initiated REG_SERROR is evaluated, and if the
797 *# val parameter is out of range REG_VERROR is evaluated.
798 *#
799 *#----------------------------------------------------------------------
800 *# HISTORY
801 *#
802 *# DATE NAME CHANGES
803 *# ---- ---- -------
804 *# Apr 01 1998 Jan Bengtsson Initial version
805 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
806 *# have "_" appended.
807 *#**********************************************************************/
808
809 #define REG_SET_VAL_WO(reg_, field_, val) ( \
810 *reg_##_SADDR = ( \
811 REG_CHECK_INIT(reg_) \
812 (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \
813 (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) \
814 ), \
815 reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
816 )
817
818 /*#**********************************************************************
819 *# Can't write to a read only register, i.e. NO REG_SET_RO, REG_ISET_RO,
820 *# and REG_SET_VAL_RO macros.
821 *#**********************************************************************/
822
823
824 /*#**********************************************************************
825 *#
826 *# MACRO NAME : REG_SET_RW
827 *#
828 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
829 *# field_: Name of a field, with "_" appended.
830 *# val : Value to write to field.
831 *#
832 *# RETURNS : Integer value written to complete register.
833 *#
834 *# SIDE EFFECTS: May evaluate REG_VERROR.
835 *#
836 *# DESCRIPTION : Write val parameter to field field in read write register
837 *# reg. If the val parameter is out of range REG_VERROR is
838 *# evaluated.
839 *#
840 *#----------------------------------------------------------------------
841 *# HISTORY
842 *#
843 *# DATE NAME CHANGES
844 *# ---- ---- -------
845 *# Apr 01 1998 Jan Bengtsson Initial version
846 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
847 *# have "_" appended.
848 *#**********************************************************************/
849
850 #define REG_SET_RW(reg_, field_, val) ( \
851 reg_##_WRITE(reg_##_ADDR, ( \
852 (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \
853 (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
854 reg_##_##field_##_BITNR) ) \
855 ) \
856 )
857
858 /*#**********************************************************************
859 *#
860 *# MACRO NAME : REG_ISET_RW
861 *#
862 *# PARAMETERS : i : Interface number.
863 *# reg_ : Name of a register, with "_" appended.
864 *# field_: Name of a field, with "_" appended.
865 *# val : Value to write to field.
866 *#
867 *# RETURNS : Integer value written to complete register.
868 *#
869 *# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR.
870 *#
871 *# DESCRIPTION : Write val parameter to field field in read write register
872 *# reg of interface i. If the val parameter is out of range
873 *# REG_VERROR is evaluated, and if the interface number is
874 *# out of range REG_IERROR is evaluated.
875 *#
876 *#----------------------------------------------------------------------
877 *# HISTORY
878 *#
879 *# DATE NAME CHANGES
880 *# ---- ---- -------
881 *# Apr 01 1998 Jan Bengtsson Initial version
882 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
883 *# have "_" appended.
884 *#**********************************************************************/
885
886 #define REG_ISET_RW(i, reg_, field_, val) ( \
887 reg_##_WRITE(REG_ADDR_I(i, reg_), ( \
888 (reg_##_READ(REG_ADDR_I(i, reg_)) & REG_IMASK(reg_, field_))\
889 | (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
890 reg_##_##field_##_BITNR) ) \
891 ) \
892 )
893
894 /*#**********************************************************************
895 *#
896 *# MACRO NAME : REG_SET_VAL_RW
897 *#
898 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
899 *# field_: Name of a field, with "_" appended.
900 *# val : Integer value to write to symbolic field.
901 *#
902 *# RETURNS : Integer value written to complete register.
903 *#
904 *# SIDE EFFECTS: May evaluate REG_VERROR.
905 *#
906 *# DESCRIPTION : Write val parameter to field field in read write register
907 *# reg. If the val parameter is out of range REG_VERROR is
908 *# evaluated.
909 *#
910 *#----------------------------------------------------------------------
911 *# HISTORY
912 *#
913 *# DATE NAME CHANGES
914 *# ---- ---- -------
915 *# Apr 01 1998 Jan Bengtsson Initial version
916 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
917 *# have "_" appended.
918 *#**********************************************************************/
919
920 #define REG_SET_VAL_RW(reg_, field_, val) ( \
921 reg_##_WRITE(reg_##_ADDR, ( \
922 (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \
923 (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) ) \
924 ) \
925 )
926
927 /*#**********************************************************************
928 *#
929 *# MACRO NAME : REG_EQL_WO
930 *#
931 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
932 *# field_: Name of a field, with "_" appended.
933 *# val : Value to compare with field.
934 *#
935 *# RETURNS : TRUE, FALSE
936 *#
937 *# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
938 *#
939 *# DESCRIPTION : Compare val parameter with field field in write only
940 *# register reg. If the val parameter is out of range
941 *# REG_VERROR is evaluated, and if the shadow register
942 *# isn't initiated REG_SERROR is evaluated.
943 *#
944 *#----------------------------------------------------------------------
945 *# HISTORY
946 *#
947 *# DATE NAME CHANGES
948 *# ---- ---- -------
949 *# Apr 01 1998 Jan Bengtsson Initial version
950 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
951 *# have "_" appended.
952 *#**********************************************************************/
953
954 #define REG_EQL_WO(reg_, field_, val) ( \
955 REG_CHECK_INIT(reg_) \
956 ( (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \
957 reg_##_##field_##_BITNR \
958 ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
959 )
960
961 /*#**********************************************************************
962 *#
963 *# MACRO NAME : REG_EQL_RO, REG_EQL_RW
964 *#
965 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
966 *# field_: Name of a field, with "_" appended.
967 *# val : Value to compare with field.
968 *#
969 *# RETURNS : TRUE, FALSE
970 *#
971 *# SIDE EFFECTS: May evaluate REG_VERROR.
972 *#
973 *# DESCRIPTION : Compare val parameter with field field in read only
974 *# or read write register reg. If the val parameter is
975 *# out of range REG_VERROR is evaluated.
976 *#
977 *#----------------------------------------------------------------------
978 *# HISTORY
979 *#
980 *# DATE NAME CHANGES
981 *# ---- ---- -------
982 *# Apr 01 1998 Jan Bengtsson Initial version
983 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
984 *# have "_" appended.
985 *#**********************************************************************/
986
987 #define REG_EQL_RO(reg_, field_, val) ( \
988 ( (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \
989 reg_##_##field_##_BITNR \
990 ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
991 )
992
993 #define REG_EQL_RW REG_EQL_RO
994
995 /*#**********************************************************************
996 *#
997 *# MACRO NAME : REG_IEQL_WO
998 *#
999 *# PARAMETERS : i : Interface number.
1000 *# reg_ : Name of a register, with "_" appended.
1001 *# field_: Name of a field, with "_" appended.
1002 *# val : Value to compare with field.
1003 *#
1004 *# RETURNS : TRUE, FALSE
1005 *#
1006 *# SIDE EFFECTS: May evaluate REG_VERROR, REG_IERROR, and REG_SERROR.
1007 *#
1008 *# DESCRIPTION : Compare val parameter with field field in write only
1009 *# register reg of interface i. If the val parameter is
1010 *# out of range REG_VERROR is evaluated, and if the
1011 *# interface number is out of range REG_IERROR is evaluated,
1012 *# and if the shadow register isn't initiated REG_SERROR
1013 *# is evaluated.
1014 *#
1015 *#----------------------------------------------------------------------
1016 *# HISTORY
1017 *#
1018 *# DATE NAME CHANGES
1019 *# ---- ---- -------
1020 *# Apr 01 1998 Jan Bengtsson Initial version
1021 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
1022 *# have "_" appended.
1023 *#**********************************************************************/
1024
1025 #define REG_IEQL_WO(i, reg_, field_, val) ( \
1026 REG_ICHECK_INIT(i, reg_) \
1027 ( (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \
1028 reg_##_##field_##_BITNR \
1029 ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
1030 )
1031
1032 /*#**********************************************************************
1033 *#
1034 *# MACRO NAME : REG_IEQL_RO, REG_IEQL_RW
1035 *#
1036 *# PARAMETERS : i : Interface number.
1037 *# reg_ : Name of a register.
1038 *# field_: Name of a field.
1039 *# val : Value to compare with field.
1040 *#
1041 *# RETURNS : TRUE, FALSE
1042 *#
1043 *# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR.
1044 *#
1045 *# DESCRIPTION : Compare val parameter with field field in read only
1046 *# or read write register reg of interface i. If the val
1047 *# parameter is out of range REG_VERROR is evaluated, and
1048 *# if the interface number is out of range REG_IERROR is
1049 *# evaluated.
1050 *#
1051 *#----------------------------------------------------------------------
1052 *# HISTORY
1053 *#
1054 *# DATE NAME CHANGES
1055 *# ---- ---- -------
1056 *# Apr 01 1998 Jan Bengtsson Initial version
1057 *# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
1058 *# have "_" appended.
1059 *#**********************************************************************/
1060
1061 #define REG_IEQL_RO(i, reg_, field_, val) ( \
1062 ( (reg_##_READ(REG_ADDR_I(i, reg_)) & \
1063 reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \
1064 ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
1065 )
1066
1067 #define REG_IEQL_RW REG_IEQL_RO
1068
1069 /*#**********************************************************************
1070 *#
1071 *# MACRO NAME : REG_RD_WO
1072 *#
1073 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
1074 *#
1075 *# RETURNS : Contents of register reg.
1076 *#
1077 *# SIDE EFFECTS: May evaluate REG_SERROR.
1078 *#
1079 *# DESCRIPTION : Read contents of write only register reg, i.e. read
1080 *# the shadow register. If the shadow register isn't
1081 *# initiated REG_SERROR is evaluated.
1082 *#
1083 *#----------------------------------------------------------------------
1084 *# HISTORY
1085 *#
1086 *# DATE NAME CHANGES
1087 *# ---- ---- -------
1088 *# Apr 01 1998 Jan Bengtsson Initial version
1089 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1090 *#**********************************************************************/
1091
1092 #define REG_RD_WO(reg_) ( \
1093 REG_CHECK_INIT(reg_) \
1094 REG_SVAL(reg_) \
1095 )
1096
1097 /*#**********************************************************************
1098 *#
1099 *# MACRO NAME : REG_RD_RO, REG_RD_RW
1100 *#
1101 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
1102 *#
1103 *# RETURNS : Contents of register reg.
1104 *#
1105 *# SIDE EFFECTS: none
1106 *#
1107 *# DESCRIPTION : Read contents of read only or read write register reg.
1108 *#
1109 *#----------------------------------------------------------------------
1110 *# HISTORY
1111 *#
1112 *# DATE NAME CHANGES
1113 *# ---- ---- -------
1114 *# Apr 01 1998 Jan Bengtsson Initial version
1115 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1116 *#**********************************************************************/
1117
1118 #define REG_RD_RO(reg_) ( \
1119 reg_##_READ(reg_##_ADDR) \
1120 )
1121
1122 #define REG_RD_RW REG_RD_RO
1123
1124 /*#**********************************************************************
1125 *#
1126 *# MACRO NAME : REG_IRD_WO
1127 *#
1128 *# PARAMETERS : i : Interface number.
1129 *# reg_ : Name of a register, with "_" appended.
1130 *#
1131 *# RETURNS : Contents of register reg.
1132 *#
1133 *# SIDE EFFECTS: May evaluate REG_SERROR and REG_IERROR.
1134 *#
1135 *# DESCRIPTION : Read contents of write only register reg, i.e. read
1136 *# the shadow register of interface i. If the shadow register
1137 *# isn't initiated REG_SERROR is evaluated, and if the
1138 *# interface number is out of range REG_IERROR is evaluated.
1139 *#
1140 *#----------------------------------------------------------------------
1141 *# HISTORY
1142 *#
1143 *# DATE NAME CHANGES
1144 *# ---- ---- -------
1145 *# Apr 01 1998 Jan Bengtsson Initial version
1146 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1147 *#**********************************************************************/
1148
1149 #define REG_IRD_WO(i, reg_) ( \
1150 REG_ICHECK_INIT(i, reg_) \
1151 REG_SVAL_I(i, reg_) \
1152 )
1153
1154 /*#**********************************************************************
1155 *#
1156 *# MACRO NAME : REG_IRD_RO, REG_IRD_RW
1157 *#
1158 *# PARAMETERS : i : Interface number.
1159 *# reg_ : Name of a register.
1160 *#
1161 *# RETURNS : Contents of register reg.
1162 *#
1163 *# SIDE EFFECTS: none
1164 *#
1165 *# DESCRIPTION : Read contents of read only or read write register reg
1166 *# of interface i.
1167 *#
1168 *#----------------------------------------------------------------------
1169 *# HISTORY
1170 *#
1171 *# DATE NAME CHANGES
1172 *# ---- ---- -------
1173 *# Apr 01 1998 Jan Bengtsson Initial version
1174 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1175 *#**********************************************************************/
1176
1177 #define REG_IRD_RO(i, reg_) ( \
1178 reg_##_READ(REG_ADDR_I(i, reg_)) \
1179 )
1180
1181 #define REG_IRD_RW REG_IRD_RO
1182
1183 /*#**********************************************************************
1184 *#
1185 *# MACRO NAME : REG_WR_WO
1186 *#
1187 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
1188 *# var : Variable (or value) to write to reg.
1189 *#
1190 *# RETURNS : integer value written to register reg.
1191 *#
1192 *# SIDE EFFECTS: May evaluate REG_SERROR.
1193 *#
1194 *# DESCRIPTION : Write value of var parameter to register reg and to
1195 *# the shadow register. If the shadow register
1196 *# isn't initiated REG_SERROR is evaluated.
1197 *#
1198 *#----------------------------------------------------------------------
1199 *# HISTORY
1200 *#
1201 *# DATE NAME CHANGES
1202 *# ---- ---- -------
1203 *# Apr 01 1998 Jan Bengtsson Initial version
1204 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1205 *#**********************************************************************/
1206
1207 #define REG_WR_WO(reg_, var) ( \
1208 *reg_##_SADDR = ( \
1209 REG_CHECK_INIT(reg_) \
1210 (reg_##_TYPE var) \
1211 ), \
1212 reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
1213 )
1214
1215 /*#**********************************************************************
1216 *#
1217 *# MACRO NAME : REG_WR_RW
1218 *#
1219 *# PARAMETERS : reg_ : Name of a register, with "_" appended.
1220 *# var : Variable (or value) to write to reg.
1221 *#
1222 *# RETURNS : integer value written to register reg.
1223 *#
1224 *# SIDE EFFECTS: None.
1225 *#
1226 *# DESCRIPTION : Write value of var parameter to register reg.
1227 *#
1228 *#----------------------------------------------------------------------
1229 *# HISTORY
1230 *#
1231 *# DATE NAME CHANGES
1232 *# ---- ---- -------
1233 *# Apr 01 1998 Jan Bengtsson Initial version
1234 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1235 *#**********************************************************************/
1236
1237 #define REG_WR_RW(reg_, var) ( \
1238 reg_##_WRITE(reg_##_ADDR, (reg_##_TYPE (var))) \
1239 )
1240
1241 /*#**********************************************************************
1242 *#
1243 *# MACRO NAME : REG_IWR_WO
1244 *#
1245 *# PARAMETERS : i : Interface number.
1246 *# reg_ : Name of a register, with "_" appended.
1247 *# var : Variable (or value) to write to reg.
1248 *#
1249 *# RETURNS : integer value written to register reg.
1250 *#
1251 *# SIDE EFFECTS: May evaluate REG_SERROR.
1252 *#
1253 *# DESCRIPTION : Write value of var parameter to register reg and to
1254 *# the shadow register of interface i. If the shadow
1255 *# register isn't initiated REG_SERROR is evaluated.
1256 *#
1257 *#----------------------------------------------------------------------
1258 *# HISTORY
1259 *#
1260 *# DATE NAME CHANGES
1261 *# ---- ---- -------
1262 *# Apr 01 1998 Jan Bengtsson Initial version
1263 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1264 *#**********************************************************************/
1265
1266 #define REG_IWR_WO(i, reg_, var) ( \
1267 *REG_SADDR_I(i, reg_) = ( \
1268 REG_ICHECK_INIT(i, reg_) \
1269 reg_##_TYPE (var) \
1270 ), \
1271 reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \
1272 )
1273
1274 /*#**********************************************************************
1275 *#
1276 *# MACRO NAME : REG_IWR_RW
1277 *#
1278 *# PARAMETERS : i : Interface number.
1279 *# reg_ : Name of a register.
1280 *# var : Variable (or value) to write to reg.
1281 *#
1282 *# RETURNS : integer value written to register reg.
1283 *#
1284 *# SIDE EFFECTS: None.
1285 *#
1286 *# DESCRIPTION : Write value of var parameter to register reg of
1287 *# interface i.
1288 *#
1289 *#----------------------------------------------------------------------
1290 *# HISTORY
1291 *#
1292 *# DATE NAME CHANGES
1293 *# ---- ---- -------
1294 *# Apr 01 1998 Jan Bengtsson Initial version
1295 *# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
1296 *#**********************************************************************/
1297
1298 #define REG_IWR_RW(i, reg_, var) ( \
1299 reg_##_WRITE(REG_ADDR_I(i, reg_), (reg_##_TYPE (var))) \
1300 )
1301
1302 /*
1303 * Can't write to a read only register, i.e. NO REG_WR_RO, REG_IWR_RO
1304 * macros.
1305 */
1306
1307 #endif /* __REG_GENERAL_INT_H__ */
1308
1309 /*
1310 * R_ALT_SER_BAUDRATE
1311 * - type: WO
1312 * - addr: 0xb000005c
1313 * - group: Serial port registers
1314 */
1315
1316 #if USE_GROUP__Serial_port_registers
1317
1318 #define R_ALT_SER_BAUDRATE__ADDR (REG_TYPECAST_UDWORD 0xb000005c)
1319
1320 #ifndef REG_NO_SHADOW
1321 #define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ALT_SER_BAUDRATE + 0))
1322 #define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ALT_SER_BAUDRATE + 0))
1323 #else /* REG_NO_SHADOW */
1324 #define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
1325 #define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
1326 #endif /* REG_NO_SHADOW */
1327
1328 #define R_ALT_SER_BAUDRATE__STYPECAST REG_STYPECAST_UDWORD
1329 #define R_ALT_SER_BAUDRATE__SVAL REG_SVAL_SHADOW
1330 #define R_ALT_SER_BAUDRATE__SVAL_I REG_SVAL_I_SHADOW
1331 #define R_ALT_SER_BAUDRATE__TYPECAST REG_TYPECAST_UDWORD
1332 #define R_ALT_SER_BAUDRATE__TYPE (REG_UDWORD)
1333 #define R_ALT_SER_BAUDRATE__GET REG_GET_WO
1334 #define R_ALT_SER_BAUDRATE__IGET REG_IGET_WO
1335 #define R_ALT_SER_BAUDRATE__SET REG_SET_WO
1336 #define R_ALT_SER_BAUDRATE__ISET REG_ISET_WO
1337 #define R_ALT_SER_BAUDRATE__SET_VAL REG_SET_VAL_WO
1338 #define R_ALT_SER_BAUDRATE__EQL REG_EQL_WO
1339 #define R_ALT_SER_BAUDRATE__IEQL REG_IEQL_WO
1340 #define R_ALT_SER_BAUDRATE__RD REG_RD_WO
1341 #define R_ALT_SER_BAUDRATE__IRD REG_IRD_WO
1342 #define R_ALT_SER_BAUDRATE__WR REG_WR_WO
1343 #define R_ALT_SER_BAUDRATE__IWR REG_IWR_WO
1344
1345 #define R_ALT_SER_BAUDRATE__WRITE(addr,value) \
1346 (*(addr) = (value))
1347
1348 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__MASK 0x30000000U
1349 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__MASK 0x03000000U
1350 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__MASK 0x00300000U
1351 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__MASK 0x00030000U
1352 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__MASK 0x00003000U
1353 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__MASK 0x00000300U
1354 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__MASK 0x00000030U
1355 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__MASK 0x00000003U
1356
1357 #define R_ALT_SER_BAUDRATE__ser3_tr__MAX 0x3
1358 #define R_ALT_SER_BAUDRATE__ser3_rec__MAX 0x3
1359 #define R_ALT_SER_BAUDRATE__ser2_tr__MAX 0x3
1360 #define R_ALT_SER_BAUDRATE__ser2_rec__MAX 0x3
1361 #define R_ALT_SER_BAUDRATE__ser1_tr__MAX 0x3
1362 #define R_ALT_SER_BAUDRATE__ser1_rec__MAX 0x3
1363 #define R_ALT_SER_BAUDRATE__ser0_tr__MAX 0x3
1364 #define R_ALT_SER_BAUDRATE__ser0_rec__MAX 0x3
1365
1366 #define R_ALT_SER_BAUDRATE__ser3_tr__MIN 0
1367 #define R_ALT_SER_BAUDRATE__ser3_rec__MIN 0
1368 #define R_ALT_SER_BAUDRATE__ser2_tr__MIN 0
1369 #define R_ALT_SER_BAUDRATE__ser2_rec__MIN 0
1370 #define R_ALT_SER_BAUDRATE__ser1_tr__MIN 0
1371 #define R_ALT_SER_BAUDRATE__ser1_rec__MIN 0
1372 #define R_ALT_SER_BAUDRATE__ser0_tr__MIN 0
1373 #define R_ALT_SER_BAUDRATE__ser0_rec__MIN 0
1374
1375 #define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
1376 #define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
1377 #define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
1378 #define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
1379 #define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
1380 #define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
1381 #define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
1382 #define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
1383
1384 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__VAL REG_VAL_ENUM
1385 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__VAL REG_VAL_ENUM
1386 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__VAL REG_VAL_ENUM
1387 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__VAL REG_VAL_ENUM
1388 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__VAL REG_VAL_ENUM
1389 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__VAL REG_VAL_ENUM
1390 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__VAL REG_VAL_ENUM
1391 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__VAL REG_VAL_ENUM
1392
1393 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__extern 2
1394 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__normal 0
1395 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__prescale 1
1396 #define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__timer 3
1397 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__extern 2
1398 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__normal 0
1399 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__prescale 1
1400 #define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__timer 3
1401 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__extern 2
1402 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__normal 0
1403 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__prescale 1
1404 #define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__timer 3
1405 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__extern 2
1406 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__normal 0
1407 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__prescale 1
1408 #define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__timer 3
1409 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__extern 2
1410 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__normal 0
1411 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__prescale 1
1412 #define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__timer 3
1413 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__extern 2
1414 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__normal 0
1415 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__prescale 1
1416 #define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__timer 3
1417 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__extern 2
1418 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__normal 0
1419 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__prescale 1
1420 #define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__timer 3
1421 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__extern 2
1422 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__normal 0
1423 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__prescale 1
1424 #define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__timer 3
1425
1426 #endif
1427
1428 /*
1429 * R_ATA_CONFIG
1430 * - type: WO
1431 * - addr: 0xb0000044
1432 * - group: ATA interface registers
1433 */
1434
1435 #if USE_GROUP__ATA_interface_registers
1436
1437 #define R_ATA_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
1438
1439 #ifndef REG_NO_SHADOW
1440 #define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
1441 #define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
1442 #else /* REG_NO_SHADOW */
1443 #define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
1444 #define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
1445 #endif /* REG_NO_SHADOW */
1446
1447 #define R_ATA_CONFIG__STYPECAST REG_STYPECAST_UDWORD
1448 #define R_ATA_CONFIG__SVAL REG_SVAL_SHADOW
1449 #define R_ATA_CONFIG__SVAL_I REG_SVAL_I_SHADOW
1450 #define R_ATA_CONFIG__TYPECAST REG_TYPECAST_UDWORD
1451 #define R_ATA_CONFIG__TYPE (REG_UDWORD)
1452 #define R_ATA_CONFIG__GET REG_GET_WO
1453 #define R_ATA_CONFIG__IGET REG_IGET_WO
1454 #define R_ATA_CONFIG__SET REG_SET_WO
1455 #define R_ATA_CONFIG__ISET REG_ISET_WO
1456 #define R_ATA_CONFIG__SET_VAL REG_SET_VAL_WO
1457 #define R_ATA_CONFIG__EQL REG_EQL_WO
1458 #define R_ATA_CONFIG__IEQL REG_IEQL_WO
1459 #define R_ATA_CONFIG__RD REG_RD_WO
1460 #define R_ATA_CONFIG__IRD REG_IRD_WO
1461 #define R_ATA_CONFIG__WR REG_WR_WO
1462 #define R_ATA_CONFIG__IWR REG_IWR_WO
1463
1464 #define R_ATA_CONFIG__WRITE(addr,value) \
1465 (*(addr) = (value))
1466
1467 #define R_ATA_CONFIG__enable__enable__MASK 0x02000000U
1468 #define R_ATA_CONFIG__dma_strobe__dma_strobe__MASK 0x01f00000U
1469 #define R_ATA_CONFIG__dma_hold__dma_hold__MASK 0x000f8000U
1470 #define R_ATA_CONFIG__pio_setup__pio_setup__MASK 0x00007c00U
1471 #define R_ATA_CONFIG__pio_strobe__pio_strobe__MASK 0x000003e0U
1472 #define R_ATA_CONFIG__pio_hold__pio_hold__MASK 0x0000001fU
1473
1474 #define R_ATA_CONFIG__enable__MAX 0x1
1475 #define R_ATA_CONFIG__dma_strobe__MAX 31
1476 #define R_ATA_CONFIG__dma_hold__MAX 31
1477 #define R_ATA_CONFIG__pio_setup__MAX 31
1478 #define R_ATA_CONFIG__pio_strobe__MAX 31
1479 #define R_ATA_CONFIG__pio_hold__MAX 31
1480
1481 #define R_ATA_CONFIG__enable__MIN 0
1482 #define R_ATA_CONFIG__dma_strobe__MIN 0
1483 #define R_ATA_CONFIG__dma_hold__MIN 0
1484 #define R_ATA_CONFIG__pio_setup__MIN 0
1485 #define R_ATA_CONFIG__pio_strobe__MIN 0
1486 #define R_ATA_CONFIG__pio_hold__MIN 0
1487
1488 #define R_ATA_CONFIG__enable__BITNR 25
1489 #define R_ATA_CONFIG__dma_strobe__BITNR 20
1490 #define R_ATA_CONFIG__dma_hold__BITNR 15
1491 #define R_ATA_CONFIG__pio_setup__BITNR 10
1492 #define R_ATA_CONFIG__pio_strobe__BITNR 5
1493 #define R_ATA_CONFIG__pio_hold__BITNR 0
1494
1495 #define R_ATA_CONFIG__enable__enable__VAL REG_VAL_ENUM
1496 #define R_ATA_CONFIG__dma_strobe__dma_strobe__VAL REG_VAL_VAL
1497 #define R_ATA_CONFIG__dma_hold__dma_hold__VAL REG_VAL_VAL
1498 #define R_ATA_CONFIG__pio_setup__pio_setup__VAL REG_VAL_VAL
1499 #define R_ATA_CONFIG__pio_strobe__pio_strobe__VAL REG_VAL_VAL
1500 #define R_ATA_CONFIG__pio_hold__pio_hold__VAL REG_VAL_VAL
1501
1502 #define R_ATA_CONFIG__enable__enable__off 0
1503 #define R_ATA_CONFIG__enable__enable__on 1
1504
1505 #endif
1506
1507 /*
1508 * R_ATA_CTRL_DATA
1509 * - type: WO
1510 * - addr: 0xb0000040
1511 * - group: ATA interface registers
1512 */
1513
1514 #if USE_GROUP__ATA_interface_registers
1515
1516 #define R_ATA_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
1517
1518 #ifndef REG_NO_SHADOW
1519 #define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
1520 #define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
1521 #else /* REG_NO_SHADOW */
1522 #define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
1523 #define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
1524 #endif /* REG_NO_SHADOW */
1525
1526 #define R_ATA_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
1527 #define R_ATA_CTRL_DATA__SVAL REG_SVAL_SHADOW
1528 #define R_ATA_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
1529 #define R_ATA_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
1530 #define R_ATA_CTRL_DATA__TYPE (REG_UDWORD)
1531 #define R_ATA_CTRL_DATA__GET REG_GET_WO
1532 #define R_ATA_CTRL_DATA__IGET REG_IGET_WO
1533 #define R_ATA_CTRL_DATA__SET REG_SET_WO
1534 #define R_ATA_CTRL_DATA__ISET REG_ISET_WO
1535 #define R_ATA_CTRL_DATA__SET_VAL REG_SET_VAL_WO
1536 #define R_ATA_CTRL_DATA__EQL REG_EQL_WO
1537 #define R_ATA_CTRL_DATA__IEQL REG_IEQL_WO
1538 #define R_ATA_CTRL_DATA__RD REG_RD_WO
1539 #define R_ATA_CTRL_DATA__IRD REG_IRD_WO
1540 #define R_ATA_CTRL_DATA__WR REG_WR_WO
1541 #define R_ATA_CTRL_DATA__IWR REG_IWR_WO
1542
1543 #define R_ATA_CTRL_DATA__WRITE(addr,value) \
1544 (*(addr) = (value))
1545
1546 #define R_ATA_CTRL_DATA__sel__sel__MASK 0xc0000000U
1547 #define R_ATA_CTRL_DATA__cs1__cs1__MASK 0x20000000U
1548 #define R_ATA_CTRL_DATA__cs0__cs0__MASK 0x10000000U
1549 #define R_ATA_CTRL_DATA__addr__addr__MASK 0x0e000000U
1550 #define R_ATA_CTRL_DATA__rw__rw__MASK 0x01000000U
1551 #define R_ATA_CTRL_DATA__src_dst__src_dst__MASK 0x00800000U
1552 #define R_ATA_CTRL_DATA__handsh__handsh__MASK 0x00400000U
1553 #define R_ATA_CTRL_DATA__multi__multi__MASK 0x00200000U
1554 #define R_ATA_CTRL_DATA__dma_size__dma_size__MASK 0x00100000U
1555 #define R_ATA_CTRL_DATA__data__data__MASK 0x0000ffffU
1556
1557 #define R_ATA_CTRL_DATA__sel__MAX 3
1558 #define R_ATA_CTRL_DATA__cs1__MAX 0x1
1559 #define R_ATA_CTRL_DATA__cs0__MAX 0x1
1560 #define R_ATA_CTRL_DATA__addr__MAX 7
1561 #define R_ATA_CTRL_DATA__rw__MAX 0x1
1562 #define R_ATA_CTRL_DATA__src_dst__MAX 0x1
1563 #define R_ATA_CTRL_DATA__handsh__MAX 0x1
1564 #define R_ATA_CTRL_DATA__multi__MAX 0x1
1565 #define R_ATA_CTRL_DATA__dma_size__MAX 0x1
1566 #define R_ATA_CTRL_DATA__data__MAX 0xffff
1567
1568 #define R_ATA_CTRL_DATA__sel__MIN 0
1569 #define R_ATA_CTRL_DATA__cs1__MIN 0
1570 #define R_ATA_CTRL_DATA__cs0__MIN 0
1571 #define R_ATA_CTRL_DATA__addr__MIN 0
1572 #define R_ATA_CTRL_DATA__rw__MIN 0
1573 #define R_ATA_CTRL_DATA__src_dst__MIN 0
1574 #define R_ATA_CTRL_DATA__handsh__MIN 0
1575 #define R_ATA_CTRL_DATA__multi__MIN 0
1576 #define R_ATA_CTRL_DATA__dma_size__MIN 0
1577 #define R_ATA_CTRL_DATA__data__MIN 0
1578
1579 #define R_ATA_CTRL_DATA__sel__BITNR 30
1580 #define R_ATA_CTRL_DATA__cs1__BITNR 29
1581 #define R_ATA_CTRL_DATA__cs0__BITNR 28
1582 #define R_ATA_CTRL_DATA__addr__BITNR 25
1583 #define R_ATA_CTRL_DATA__rw__BITNR 24
1584 #define R_ATA_CTRL_DATA__src_dst__BITNR 23
1585 #define R_ATA_CTRL_DATA__handsh__BITNR 22
1586 #define R_ATA_CTRL_DATA__multi__BITNR 21
1587 #define R_ATA_CTRL_DATA__dma_size__BITNR 20
1588 #define R_ATA_CTRL_DATA__data__BITNR 0
1589
1590 #define R_ATA_CTRL_DATA__sel__sel__VAL REG_VAL_VAL
1591 #define R_ATA_CTRL_DATA__cs1__cs1__VAL REG_VAL_ENUM
1592 #define R_ATA_CTRL_DATA__cs0__cs0__VAL REG_VAL_ENUM
1593 #define R_ATA_CTRL_DATA__addr__addr__VAL REG_VAL_VAL
1594 #define R_ATA_CTRL_DATA__rw__rw__VAL REG_VAL_ENUM
1595 #define R_ATA_CTRL_DATA__src_dst__src_dst__VAL REG_VAL_ENUM
1596 #define R_ATA_CTRL_DATA__handsh__handsh__VAL REG_VAL_ENUM
1597 #define R_ATA_CTRL_DATA__multi__multi__VAL REG_VAL_ENUM
1598 #define R_ATA_CTRL_DATA__dma_size__dma_size__VAL REG_VAL_ENUM
1599 #define R_ATA_CTRL_DATA__data__data__VAL REG_VAL_VAL
1600
1601 #define R_ATA_CTRL_DATA__cs1__cs1__active 1
1602 #define R_ATA_CTRL_DATA__cs1__cs1__inactive 0
1603 #define R_ATA_CTRL_DATA__cs0__cs0__active 1
1604 #define R_ATA_CTRL_DATA__cs0__cs0__inactive 0
1605 #define R_ATA_CTRL_DATA__rw__rw__read 1
1606 #define R_ATA_CTRL_DATA__rw__rw__write 0
1607 #define R_ATA_CTRL_DATA__src_dst__src_dst__dma 1
1608 #define R_ATA_CTRL_DATA__src_dst__src_dst__register 0
1609 #define R_ATA_CTRL_DATA__handsh__handsh__dma 1
1610 #define R_ATA_CTRL_DATA__handsh__handsh__pio 0
1611 #define R_ATA_CTRL_DATA__multi__multi__off 0
1612 #define R_ATA_CTRL_DATA__multi__multi__on 1
1613 #define R_ATA_CTRL_DATA__dma_size__dma_size__byte 1
1614 #define R_ATA_CTRL_DATA__dma_size__dma_size__word 0
1615
1616 #endif
1617
1618 /*
1619 * R_ATA_STATUS_DATA
1620 * - type: RO
1621 * - addr: 0xb0000040
1622 * - group: ATA interface registers
1623 */
1624
1625 #if USE_GROUP__ATA_interface_registers
1626
1627 #define R_ATA_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
1628 #define R_ATA_STATUS_DATA__SVAL REG_SVAL_SHADOW
1629 #define R_ATA_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
1630 #define R_ATA_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
1631 #define R_ATA_STATUS_DATA__TYPE (REG_UDWORD)
1632 #define R_ATA_STATUS_DATA__GET REG_GET_RO
1633 #define R_ATA_STATUS_DATA__IGET REG_IGET_RO
1634 #define R_ATA_STATUS_DATA__SET REG_SET_RO
1635 #define R_ATA_STATUS_DATA__ISET REG_ISET_RO
1636 #define R_ATA_STATUS_DATA__SET_VAL REG_SET_VAL_RO
1637 #define R_ATA_STATUS_DATA__EQL REG_EQL_RO
1638 #define R_ATA_STATUS_DATA__IEQL REG_IEQL_RO
1639 #define R_ATA_STATUS_DATA__RD REG_RD_RO
1640 #define R_ATA_STATUS_DATA__IRD REG_IRD_RO
1641 #define R_ATA_STATUS_DATA__WR REG_WR_RO
1642 #define R_ATA_STATUS_DATA__IWR REG_IWR_RO
1643
1644 #define R_ATA_STATUS_DATA__READ(addr) \
1645 (*(addr))
1646
1647 #define R_ATA_STATUS_DATA__busy__busy__MASK 0x00040000U
1648 #define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
1649 #define R_ATA_STATUS_DATA__dav__dav__MASK 0x00010000U
1650 #define R_ATA_STATUS_DATA__data__data__MASK 0x0000ffffU
1651
1652 #define R_ATA_STATUS_DATA__busy__MAX 0x1
1653 #define R_ATA_STATUS_DATA__tr_rdy__MAX 0x1
1654 #define R_ATA_STATUS_DATA__dav__MAX 0x1
1655 #define R_ATA_STATUS_DATA__data__MAX 0xffff
1656
1657 #define R_ATA_STATUS_DATA__busy__MIN 0
1658 #define R_ATA_STATUS_DATA__tr_rdy__MIN 0
1659 #define R_ATA_STATUS_DATA__dav__MIN 0
1660 #define R_ATA_STATUS_DATA__data__MIN 0
1661
1662 #define R_ATA_STATUS_DATA__busy__BITNR 18
1663 #define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
1664 #define R_ATA_STATUS_DATA__dav__BITNR 16
1665 #define R_ATA_STATUS_DATA__data__BITNR 0
1666
1667 #define R_ATA_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
1668 #define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
1669 #define R_ATA_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
1670 #define R_ATA_STATUS_DATA__data__data__VAL REG_VAL_VAL
1671
1672 #define R_ATA_STATUS_DATA__busy__busy__no 0
1673 #define R_ATA_STATUS_DATA__busy__busy__yes 1
1674 #define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__busy 0
1675 #define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__ready 1
1676 #define R_ATA_STATUS_DATA__dav__dav__data 1
1677 #define R_ATA_STATUS_DATA__dav__dav__nodata 0
1678
1679 #endif
1680
1681 /*
1682 * R_ATA_TRANSFER_CNT
1683 * - type: RW
1684 * - addr: 0xb0000048
1685 * - group: ATA interface registers
1686 */
1687
1688 #if USE_GROUP__ATA_interface_registers
1689
1690 #define R_ATA_TRANSFER_CNT__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
1691 #define R_ATA_TRANSFER_CNT__SVAL REG_SVAL_SHADOW
1692 #define R_ATA_TRANSFER_CNT__SVAL_I REG_SVAL_I_SHADOW
1693 #define R_ATA_TRANSFER_CNT__TYPECAST REG_TYPECAST_UDWORD
1694 #define R_ATA_TRANSFER_CNT__TYPE (REG_UDWORD)
1695 #define R_ATA_TRANSFER_CNT__GET REG_GET_RW
1696 #define R_ATA_TRANSFER_CNT__IGET REG_IGET_RW
1697 #define R_ATA_TRANSFER_CNT__SET REG_SET_RW
1698 #define R_ATA_TRANSFER_CNT__ISET REG_ISET_RW
1699 #define R_ATA_TRANSFER_CNT__SET_VAL REG_SET_VAL_RW
1700 #define R_ATA_TRANSFER_CNT__EQL REG_EQL_RW
1701 #define R_ATA_TRANSFER_CNT__IEQL REG_IEQL_RW
1702 #define R_ATA_TRANSFER_CNT__RD REG_RD_RW
1703 #define R_ATA_TRANSFER_CNT__IRD REG_IRD_RW
1704 #define R_ATA_TRANSFER_CNT__WR REG_WR_RW
1705 #define R_ATA_TRANSFER_CNT__IWR REG_IWR_RW
1706
1707 #define R_ATA_TRANSFER_CNT__WRITE(addr,value) \
1708 (*(addr) = (value))
1709 #define R_ATA_TRANSFER_CNT__READ(addr) \
1710 (*(addr))
1711
1712 #define R_ATA_TRANSFER_CNT__count__count__MASK 0x0001ffffU
1713
1714 #define R_ATA_TRANSFER_CNT__count__MAX 0x1ffff
1715
1716 #define R_ATA_TRANSFER_CNT__count__MIN 0
1717
1718 #define R_ATA_TRANSFER_CNT__count__BITNR 0
1719
1720 #define R_ATA_TRANSFER_CNT__count__count__VAL REG_VAL_VAL
1721
1722
1723 #endif
1724
1725 /*
1726 * R_BUS_CONFIG
1727 * - type: WO
1728 * - addr: 0xb0000004
1729 * - group: Bus interface configuration registers
1730 */
1731
1732 #if USE_GROUP__Bus_interface_configuration_registers
1733
1734 #define R_BUS_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000004)
1735
1736 #ifndef REG_NO_SHADOW
1737 #define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_BUS_CONFIG + 0))
1738 #define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_BUS_CONFIG + 0))
1739 #else /* REG_NO_SHADOW */
1740 #define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
1741 #define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
1742 #endif /* REG_NO_SHADOW */
1743
1744 #define R_BUS_CONFIG__STYPECAST REG_STYPECAST_UDWORD
1745 #define R_BUS_CONFIG__SVAL REG_SVAL_SHADOW
1746 #define R_BUS_CONFIG__SVAL_I REG_SVAL_I_SHADOW
1747 #define R_BUS_CONFIG__TYPECAST REG_TYPECAST_UDWORD
1748 #define R_BUS_CONFIG__TYPE (REG_UDWORD)
1749 #define R_BUS_CONFIG__GET REG_GET_WO
1750 #define R_BUS_CONFIG__IGET REG_IGET_WO
1751 #define R_BUS_CONFIG__SET REG_SET_WO
1752 #define R_BUS_CONFIG__ISET REG_ISET_WO
1753 #define R_BUS_CONFIG__SET_VAL REG_SET_VAL_WO
1754 #define R_BUS_CONFIG__EQL REG_EQL_WO
1755 #define R_BUS_CONFIG__IEQL REG_IEQL_WO
1756 #define R_BUS_CONFIG__RD REG_RD_WO
1757 #define R_BUS_CONFIG__IRD REG_IRD_WO
1758 #define R_BUS_CONFIG__WR REG_WR_WO
1759 #define R_BUS_CONFIG__IWR REG_IWR_WO
1760
1761 #define R_BUS_CONFIG__WRITE(addr,value) \
1762 (*(addr) = (value))
1763
1764 #define R_BUS_CONFIG__sram_type__sram_type__MASK 0x00000200U
1765 #define R_BUS_CONFIG__dma_burst__dma_burst__MASK 0x00000100U
1766 #define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__MASK 0x00000080U
1767 #define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__MASK 0x00000040U
1768 #define R_BUS_CONFIG__sram_wr__sram_wr__MASK 0x00000020U
1769 #define R_BUS_CONFIG__flash_wr__flash_wr__MASK 0x00000010U
1770 #define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__MASK 0x00000008U
1771 #define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__MASK 0x00000004U
1772 #define R_BUS_CONFIG__sram_bw__sram_bw__MASK 0x00000002U
1773 #define R_BUS_CONFIG__flash_bw__flash_bw__MASK 0x00000001U
1774
1775 #define R_BUS_CONFIG__sram_type__MAX 0x1
1776 #define R_BUS_CONFIG__dma_burst__MAX 0x1
1777 #define R_BUS_CONFIG__pcs4_7_wr__MAX 0x1
1778 #define R_BUS_CONFIG__pcs0_3_wr__MAX 0x1
1779 #define R_BUS_CONFIG__sram_wr__MAX 0x1
1780 #define R_BUS_CONFIG__flash_wr__MAX 0x1
1781 #define R_BUS_CONFIG__pcs4_7_bw__MAX 0x1
1782 #define R_BUS_CONFIG__pcs0_3_bw__MAX 0x1
1783 #define R_BUS_CONFIG__sram_bw__MAX 0x1
1784 #define R_BUS_CONFIG__flash_bw__MAX 0x1
1785
1786 #define R_BUS_CONFIG__sram_type__MIN 0
1787 #define R_BUS_CONFIG__dma_burst__MIN 0
1788 #define R_BUS_CONFIG__pcs4_7_wr__MIN 0
1789 #define R_BUS_CONFIG__pcs0_3_wr__MIN 0
1790 #define R_BUS_CONFIG__sram_wr__MIN 0
1791 #define R_BUS_CONFIG__flash_wr__MIN 0
1792 #define R_BUS_CONFIG__pcs4_7_bw__MIN 0
1793 #define R_BUS_CONFIG__pcs0_3_bw__MIN 0
1794 #define R_BUS_CONFIG__sram_bw__MIN 0
1795 #define R_BUS_CONFIG__flash_bw__MIN 0
1796
1797 #define R_BUS_CONFIG__sram_type__BITNR 9
1798 #define R_BUS_CONFIG__dma_burst__BITNR 8
1799 #define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
1800 #define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
1801 #define R_BUS_CONFIG__sram_wr__BITNR 5
1802 #define R_BUS_CONFIG__flash_wr__BITNR 4
1803 #define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
1804 #define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
1805 #define R_BUS_CONFIG__sram_bw__BITNR 1
1806 #define R_BUS_CONFIG__flash_bw__BITNR 0
1807
1808 #define R_BUS_CONFIG__sram_type__sram_type__VAL REG_VAL_ENUM
1809 #define R_BUS_CONFIG__dma_burst__dma_burst__VAL REG_VAL_ENUM
1810 #define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__VAL REG_VAL_ENUM
1811 #define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__VAL REG_VAL_ENUM
1812 #define R_BUS_CONFIG__sram_wr__sram_wr__VAL REG_VAL_ENUM
1813 #define R_BUS_CONFIG__flash_wr__flash_wr__VAL REG_VAL_ENUM
1814 #define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__VAL REG_VAL_ENUM
1815 #define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__VAL REG_VAL_ENUM
1816 #define R_BUS_CONFIG__sram_bw__sram_bw__VAL REG_VAL_ENUM
1817 #define R_BUS_CONFIG__flash_bw__flash_bw__VAL REG_VAL_ENUM
1818
1819 #define R_BUS_CONFIG__sram_type__sram_type__bwe 0
1820 #define R_BUS_CONFIG__sram_type__sram_type__cwe 1
1821 #define R_BUS_CONFIG__dma_burst__dma_burst__burst16 1
1822 #define R_BUS_CONFIG__dma_burst__dma_burst__burst32 0
1823 #define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__ext 1
1824 #define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__norm 0
1825 #define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__ext 1
1826 #define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__norm 0
1827 #define R_BUS_CONFIG__sram_wr__sram_wr__ext 1
1828 #define R_BUS_CONFIG__sram_wr__sram_wr__norm 0
1829 #define R_BUS_CONFIG__flash_wr__flash_wr__ext 1
1830 #define R_BUS_CONFIG__flash_wr__flash_wr__norm 0
1831 #define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw16 0
1832 #define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw32 1
1833 #define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw16 0
1834 #define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw32 1
1835 #define R_BUS_CONFIG__sram_bw__sram_bw__bw16 0
1836 #define R_BUS_CONFIG__sram_bw__sram_bw__bw32 1
1837 #define R_BUS_CONFIG__flash_bw__flash_bw__bw16 0
1838 #define R_BUS_CONFIG__flash_bw__flash_bw__bw32 1
1839
1840 #endif
1841
1842 /*
1843 * R_BUS_STATUS
1844 * - type: RO
1845 * - addr: 0xb0000004
1846 * - group: Bus interface configuration registers
1847 */
1848
1849 #if USE_GROUP__Bus_interface_configuration_registers
1850
1851 #define R_BUS_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000004)
1852 #define R_BUS_STATUS__SVAL REG_SVAL_SHADOW
1853 #define R_BUS_STATUS__SVAL_I REG_SVAL_I_SHADOW
1854 #define R_BUS_STATUS__TYPECAST REG_TYPECAST_UDWORD
1855 #define R_BUS_STATUS__TYPE (REG_UDWORD)
1856 #define R_BUS_STATUS__GET REG_GET_RO
1857 #define R_BUS_STATUS__IGET REG_IGET_RO
1858 #define R_BUS_STATUS__SET REG_SET_RO
1859 #define R_BUS_STATUS__ISET REG_ISET_RO
1860 #define R_BUS_STATUS__SET_VAL REG_SET_VAL_RO
1861 #define R_BUS_STATUS__EQL REG_EQL_RO
1862 #define R_BUS_STATUS__IEQL REG_IEQL_RO
1863 #define R_BUS_STATUS__RD REG_RD_RO
1864 #define R_BUS_STATUS__IRD REG_IRD_RO
1865 #define R_BUS_STATUS__WR REG_WR_RO
1866 #define R_BUS_STATUS__IWR REG_IWR_RO
1867
1868 #define R_BUS_STATUS__READ(addr) \
1869 (*(addr))
1870
1871 #define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__MASK 0x00000020U
1872 #define R_BUS_STATUS__both_faults__both_faults__MASK 0x00000010U
1873 #define R_BUS_STATUS__bsen___bsen___MASK 0x00000008U
1874 #define R_BUS_STATUS__boot__boot__MASK 0x00000006U
1875 #define R_BUS_STATUS__flashw__flashw__MASK 0x00000001U
1876
1877 #define R_BUS_STATUS__pll_lock_tm__MAX 0x1
1878 #define R_BUS_STATUS__both_faults__MAX 0x1
1879 #define R_BUS_STATUS__bsen___MAX 0x1
1880 #define R_BUS_STATUS__boot__MAX 0x3
1881 #define R_BUS_STATUS__flashw__MAX 0x1
1882
1883 #define R_BUS_STATUS__pll_lock_tm__MIN 0
1884 #define R_BUS_STATUS__both_faults__MIN 0
1885 #define R_BUS_STATUS__bsen___MIN 0
1886 #define R_BUS_STATUS__boot__MIN 0
1887 #define R_BUS_STATUS__flashw__MIN 0
1888
1889 #define R_BUS_STATUS__pll_lock_tm__BITNR 5
1890 #define R_BUS_STATUS__both_faults__BITNR 4
1891 #define R_BUS_STATUS__bsen___BITNR 3
1892 #define R_BUS_STATUS__boot__BITNR 1
1893 #define R_BUS_STATUS__flashw__BITNR 0
1894
1895 #define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__VAL REG_VAL_ENUM
1896 #define R_BUS_STATUS__both_faults__both_faults__VAL REG_VAL_ENUM
1897 #define R_BUS_STATUS__bsen___bsen___VAL REG_VAL_ENUM
1898 #define R_BUS_STATUS__boot__boot__VAL REG_VAL_ENUM
1899 #define R_BUS_STATUS__flashw__flashw__VAL REG_VAL_ENUM
1900
1901 #define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__counting 1
1902 #define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__expired 0
1903 #define R_BUS_STATUS__both_faults__both_faults__no 0
1904 #define R_BUS_STATUS__both_faults__both_faults__yes 1
1905 #define R_BUS_STATUS__bsen___bsen___disable 1
1906 #define R_BUS_STATUS__bsen___bsen___enable 0
1907 #define R_BUS_STATUS__boot__boot__network 2
1908 #define R_BUS_STATUS__boot__boot__parallel 3
1909 #define R_BUS_STATUS__boot__boot__serial 1
1910 #define R_BUS_STATUS__boot__boot__uncached 0
1911 #define R_BUS_STATUS__flashw__flashw__bw16 0
1912 #define R_BUS_STATUS__flashw__flashw__bw32 1
1913
1914 #endif
1915
1916 /*
1917 * R_CLOCK_PRESCALE
1918 * - type: WO
1919 * - addr: 0xb00000f0
1920 * - group: Timer registers
1921 */
1922
1923 #if USE_GROUP__Timer_registers
1924
1925 #define R_CLOCK_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f0)
1926
1927 #ifndef REG_NO_SHADOW
1928 #define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0))
1929 #define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0))
1930 #else /* REG_NO_SHADOW */
1931 #define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
1932 #define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
1933 #endif /* REG_NO_SHADOW */
1934
1935 #define R_CLOCK_PRESCALE__STYPECAST REG_STYPECAST_UDWORD
1936 #define R_CLOCK_PRESCALE__SVAL REG_SVAL_SHADOW
1937 #define R_CLOCK_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
1938 #define R_CLOCK_PRESCALE__TYPECAST REG_TYPECAST_UDWORD
1939 #define R_CLOCK_PRESCALE__TYPE (REG_UDWORD)
1940 #define R_CLOCK_PRESCALE__GET REG_GET_WO
1941 #define R_CLOCK_PRESCALE__IGET REG_IGET_WO
1942 #define R_CLOCK_PRESCALE__SET REG_SET_WO
1943 #define R_CLOCK_PRESCALE__ISET REG_ISET_WO
1944 #define R_CLOCK_PRESCALE__SET_VAL REG_SET_VAL_WO
1945 #define R_CLOCK_PRESCALE__EQL REG_EQL_WO
1946 #define R_CLOCK_PRESCALE__IEQL REG_IEQL_WO
1947 #define R_CLOCK_PRESCALE__RD REG_RD_WO
1948 #define R_CLOCK_PRESCALE__IRD REG_IRD_WO
1949 #define R_CLOCK_PRESCALE__WR REG_WR_WO
1950 #define R_CLOCK_PRESCALE__IWR REG_IWR_WO
1951
1952 #define R_CLOCK_PRESCALE__WRITE(addr,value) \
1953 (*(addr) = (value))
1954
1955 #define R_CLOCK_PRESCALE__ser_presc__ser_presc__MASK 0xffff0000U
1956 #define R_CLOCK_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU
1957
1958 #define R_CLOCK_PRESCALE__ser_presc__MAX 0xffff
1959 #define R_CLOCK_PRESCALE__tim_presc__MAX 0xffff
1960
1961 #define R_CLOCK_PRESCALE__ser_presc__MIN 0
1962 #define R_CLOCK_PRESCALE__tim_presc__MIN 0
1963
1964 #define R_CLOCK_PRESCALE__ser_presc__BITNR 16
1965 #define R_CLOCK_PRESCALE__tim_presc__BITNR 0
1966
1967 #define R_CLOCK_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL
1968 #define R_CLOCK_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL
1969
1970
1971 #endif
1972
1973 /*
1974 * R_DMA_CH0_BUF
1975 * - type: RW
1976 * - addr: 0xb0000108
1977 * - group: DMA registers
1978 */
1979
1980 #if USE_GROUP__DMA_registers
1981
1982 #define R_DMA_CH0_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000108)
1983 #define R_DMA_CH0_BUF__SVAL REG_SVAL_SHADOW
1984 #define R_DMA_CH0_BUF__SVAL_I REG_SVAL_I_SHADOW
1985 #define R_DMA_CH0_BUF__TYPECAST REG_TYPECAST_UDWORD
1986 #define R_DMA_CH0_BUF__TYPE (REG_UDWORD)
1987 #define R_DMA_CH0_BUF__GET REG_GET_RW
1988 #define R_DMA_CH0_BUF__IGET REG_IGET_RW
1989 #define R_DMA_CH0_BUF__SET REG_SET_RW
1990 #define R_DMA_CH0_BUF__ISET REG_ISET_RW
1991 #define R_DMA_CH0_BUF__SET_VAL REG_SET_VAL_RW
1992 #define R_DMA_CH0_BUF__EQL REG_EQL_RW
1993 #define R_DMA_CH0_BUF__IEQL REG_IEQL_RW
1994 #define R_DMA_CH0_BUF__RD REG_RD_RW
1995 #define R_DMA_CH0_BUF__IRD REG_IRD_RW
1996 #define R_DMA_CH0_BUF__WR REG_WR_RW
1997 #define R_DMA_CH0_BUF__IWR REG_IWR_RW
1998
1999 #define R_DMA_CH0_BUF__WRITE(addr,value) \
2000 (*(addr) = (value))
2001 #define R_DMA_CH0_BUF__READ(addr) \
2002 (*(addr))
2003
2004 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2005 #define R_DMA_CH0_BUF__FIRST 0
2006 #define R_DMA_CH0_BUF__LAST 9
2007 #define R_DMA_CH0_BUF__OFFSET 16
2008 /* end */
2009
2010 #define R_DMA_CH0_BUF__buf__buf__MASK 0xffffffffU
2011
2012 #define R_DMA_CH0_BUF__buf__MAX 0xffffffff
2013
2014 #define R_DMA_CH0_BUF__buf__MIN 0
2015
2016 #define R_DMA_CH0_BUF__buf__BITNR 0
2017
2018 #define R_DMA_CH0_BUF__buf__buf__VAL REG_VAL_VAL
2019
2020
2021 #endif
2022
2023 /*
2024 * R_DMA_CH0_CLR_INTR
2025 * - type: WO
2026 * - addr: 0xb00001d1
2027 * - group: DMA registers
2028 */
2029
2030 #if USE_GROUP__DMA_registers
2031
2032 #define R_DMA_CH0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d1)
2033
2034 #ifndef REG_NO_SHADOW
2035 #define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH0_CLR_INTR + 0))
2036 #define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH0_CLR_INTR + 0))
2037 #else /* REG_NO_SHADOW */
2038 #define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
2039 #define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
2040 #endif /* REG_NO_SHADOW */
2041
2042 #define R_DMA_CH0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
2043 #define R_DMA_CH0_CLR_INTR__SVAL REG_SVAL_ZERO
2044 #define R_DMA_CH0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
2045 #define R_DMA_CH0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
2046 #define R_DMA_CH0_CLR_INTR__TYPE (REG_BYTE)
2047 #define R_DMA_CH0_CLR_INTR__GET REG_GET_WO
2048 #define R_DMA_CH0_CLR_INTR__IGET REG_IGET_WO
2049 #define R_DMA_CH0_CLR_INTR__SET REG_SET_WO
2050 #define R_DMA_CH0_CLR_INTR__ISET REG_ISET_WO
2051 #define R_DMA_CH0_CLR_INTR__SET_VAL REG_SET_VAL_WO
2052 #define R_DMA_CH0_CLR_INTR__EQL REG_EQL_WO
2053 #define R_DMA_CH0_CLR_INTR__IEQL REG_IEQL_WO
2054 #define R_DMA_CH0_CLR_INTR__RD REG_RD_WO
2055 #define R_DMA_CH0_CLR_INTR__IRD REG_IRD_WO
2056 #define R_DMA_CH0_CLR_INTR__WR REG_WR_WO
2057 #define R_DMA_CH0_CLR_INTR__IWR REG_IWR_WO
2058
2059 #define R_DMA_CH0_CLR_INTR__WRITE(addr,value) \
2060 (*(addr) = (value))
2061
2062 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2063 #define R_DMA_CH0_CLR_INTR__FIRST 0
2064 #define R_DMA_CH0_CLR_INTR__IOFFSET 0
2065 #define R_DMA_CH0_CLR_INTR__LAST 9
2066 #define R_DMA_CH0_CLR_INTR__OFFSET 4
2067 #define R_DMA_CH0_CLR_INTR__SOFFSET 0
2068 /* end */
2069
2070 #define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
2071 #define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
2072
2073 #define R_DMA_CH0_CLR_INTR__clr_eop__MAX 0x1
2074 #define R_DMA_CH0_CLR_INTR__clr_descr__MAX 0x1
2075
2076 #define R_DMA_CH0_CLR_INTR__clr_eop__MIN 0
2077 #define R_DMA_CH0_CLR_INTR__clr_descr__MIN 0
2078
2079 #define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
2080 #define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
2081
2082 #define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
2083 #define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
2084
2085 #define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__do 1
2086 #define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__dont 0
2087 #define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__do 1
2088 #define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__dont 0
2089
2090 #endif
2091
2092 /*
2093 * R_DMA_CH0_CMD
2094 * - type: RW
2095 * - addr: 0xb00001d0
2096 * - group: DMA registers
2097 */
2098
2099 #if USE_GROUP__DMA_registers
2100
2101 #define R_DMA_CH0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d0)
2102 #define R_DMA_CH0_CMD__SVAL REG_SVAL_SHADOW
2103 #define R_DMA_CH0_CMD__SVAL_I REG_SVAL_I_SHADOW
2104 #define R_DMA_CH0_CMD__TYPECAST REG_TYPECAST_BYTE
2105 #define R_DMA_CH0_CMD__TYPE (REG_BYTE)
2106 #define R_DMA_CH0_CMD__GET REG_GET_RW
2107 #define R_DMA_CH0_CMD__IGET REG_IGET_RW
2108 #define R_DMA_CH0_CMD__SET REG_SET_RW
2109 #define R_DMA_CH0_CMD__ISET REG_ISET_RW
2110 #define R_DMA_CH0_CMD__SET_VAL REG_SET_VAL_RW
2111 #define R_DMA_CH0_CMD__EQL REG_EQL_RW
2112 #define R_DMA_CH0_CMD__IEQL REG_IEQL_RW
2113 #define R_DMA_CH0_CMD__RD REG_RD_RW
2114 #define R_DMA_CH0_CMD__IRD REG_IRD_RW
2115 #define R_DMA_CH0_CMD__WR REG_WR_RW
2116 #define R_DMA_CH0_CMD__IWR REG_IWR_RW
2117
2118 #define R_DMA_CH0_CMD__WRITE(addr,value) \
2119 (*(addr) = (value))
2120 #define R_DMA_CH0_CMD__READ(addr) \
2121 (*(addr))
2122
2123 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2124 #define R_DMA_CH0_CMD__FIRST 0
2125 #define R_DMA_CH0_CMD__LAST 9
2126 #define R_DMA_CH0_CMD__OFFSET 4
2127 /* end */
2128
2129 #define R_DMA_CH0_CMD__cmd__cmd__MASK 0x00000007U
2130
2131 #define R_DMA_CH0_CMD__cmd__MAX 0x7
2132
2133 #define R_DMA_CH0_CMD__cmd__MIN 0
2134
2135 #define R_DMA_CH0_CMD__cmd__BITNR 0
2136
2137 #define R_DMA_CH0_CMD__cmd__cmd__VAL REG_VAL_ENUM
2138
2139 #define R_DMA_CH0_CMD__cmd__cmd__continue 3
2140 #define R_DMA_CH0_CMD__cmd__cmd__hold 0
2141 #define R_DMA_CH0_CMD__cmd__cmd__reset 4
2142 #define R_DMA_CH0_CMD__cmd__cmd__restart 3
2143 #define R_DMA_CH0_CMD__cmd__cmd__start 1
2144
2145 #endif
2146
2147 /*
2148 * R_DMA_CH0_DESCR
2149 * - type: RW
2150 * - addr: 0xb000010c
2151 * - group: DMA registers
2152 */
2153
2154 #if USE_GROUP__DMA_registers
2155
2156 #define R_DMA_CH0_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000010c)
2157 #define R_DMA_CH0_DESCR__SVAL REG_SVAL_SHADOW
2158 #define R_DMA_CH0_DESCR__SVAL_I REG_SVAL_I_SHADOW
2159 #define R_DMA_CH0_DESCR__TYPECAST REG_TYPECAST_UDWORD
2160 #define R_DMA_CH0_DESCR__TYPE (REG_UDWORD)
2161 #define R_DMA_CH0_DESCR__GET REG_GET_RW
2162 #define R_DMA_CH0_DESCR__IGET REG_IGET_RW
2163 #define R_DMA_CH0_DESCR__SET REG_SET_RW
2164 #define R_DMA_CH0_DESCR__ISET REG_ISET_RW
2165 #define R_DMA_CH0_DESCR__SET_VAL REG_SET_VAL_RW
2166 #define R_DMA_CH0_DESCR__EQL REG_EQL_RW
2167 #define R_DMA_CH0_DESCR__IEQL REG_IEQL_RW
2168 #define R_DMA_CH0_DESCR__RD REG_RD_RW
2169 #define R_DMA_CH0_DESCR__IRD REG_IRD_RW
2170 #define R_DMA_CH0_DESCR__WR REG_WR_RW
2171 #define R_DMA_CH0_DESCR__IWR REG_IWR_RW
2172
2173 #define R_DMA_CH0_DESCR__WRITE(addr,value) \
2174 (*(addr) = (value))
2175 #define R_DMA_CH0_DESCR__READ(addr) \
2176 (*(addr))
2177
2178 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2179 #define R_DMA_CH0_DESCR__FIRST 0
2180 #define R_DMA_CH0_DESCR__LAST 9
2181 #define R_DMA_CH0_DESCR__OFFSET 16
2182 /* end */
2183
2184 #define R_DMA_CH0_DESCR__descr__descr__MASK 0xffffffffU
2185
2186 #define R_DMA_CH0_DESCR__descr__MAX 0xffffffff
2187
2188 #define R_DMA_CH0_DESCR__descr__MIN 0
2189
2190 #define R_DMA_CH0_DESCR__descr__BITNR 0
2191
2192 #define R_DMA_CH0_DESCR__descr__descr__VAL REG_VAL_VAL
2193
2194
2195 #endif
2196
2197 /*
2198 * R_DMA_CH0_FIRST
2199 * - type: RW
2200 * - addr: 0xb00001a0
2201 * - group: DMA registers
2202 */
2203
2204 #if USE_GROUP__DMA_registers
2205
2206 #define R_DMA_CH0_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a0)
2207 #define R_DMA_CH0_FIRST__SVAL REG_SVAL_SHADOW
2208 #define R_DMA_CH0_FIRST__SVAL_I REG_SVAL_I_SHADOW
2209 #define R_DMA_CH0_FIRST__TYPECAST REG_TYPECAST_UDWORD
2210 #define R_DMA_CH0_FIRST__TYPE (REG_UDWORD)
2211 #define R_DMA_CH0_FIRST__GET REG_GET_RW
2212 #define R_DMA_CH0_FIRST__IGET REG_IGET_RW
2213 #define R_DMA_CH0_FIRST__SET REG_SET_RW
2214 #define R_DMA_CH0_FIRST__ISET REG_ISET_RW
2215 #define R_DMA_CH0_FIRST__SET_VAL REG_SET_VAL_RW
2216 #define R_DMA_CH0_FIRST__EQL REG_EQL_RW
2217 #define R_DMA_CH0_FIRST__IEQL REG_IEQL_RW
2218 #define R_DMA_CH0_FIRST__RD REG_RD_RW
2219 #define R_DMA_CH0_FIRST__IRD REG_IRD_RW
2220 #define R_DMA_CH0_FIRST__WR REG_WR_RW
2221 #define R_DMA_CH0_FIRST__IWR REG_IWR_RW
2222
2223 #define R_DMA_CH0_FIRST__WRITE(addr,value) \
2224 (*(addr) = (value))
2225 #define R_DMA_CH0_FIRST__READ(addr) \
2226 (*(addr))
2227
2228 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2229 #define R_DMA_CH0_FIRST__FIRST 0
2230 #define R_DMA_CH0_FIRST__LAST 9
2231 #define R_DMA_CH0_FIRST__OFFSET 4
2232 /* end */
2233
2234 #define R_DMA_CH0_FIRST__first__first__MASK 0xffffffffU
2235
2236 #define R_DMA_CH0_FIRST__first__MAX 0xffffffff
2237
2238 #define R_DMA_CH0_FIRST__first__MIN 0
2239
2240 #define R_DMA_CH0_FIRST__first__BITNR 0
2241
2242 #define R_DMA_CH0_FIRST__first__first__VAL REG_VAL_VAL
2243
2244
2245 #endif
2246
2247 /*
2248 * R_DMA_CH0_HWSW
2249 * - type: RW
2250 * - addr: 0xb0000100
2251 * - group: DMA registers
2252 */
2253
2254 #if USE_GROUP__DMA_registers
2255
2256 #define R_DMA_CH0_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000100)
2257 #define R_DMA_CH0_HWSW__SVAL REG_SVAL_SHADOW
2258 #define R_DMA_CH0_HWSW__SVAL_I REG_SVAL_I_SHADOW
2259 #define R_DMA_CH0_HWSW__TYPECAST REG_TYPECAST_UDWORD
2260 #define R_DMA_CH0_HWSW__TYPE (REG_UDWORD)
2261 #define R_DMA_CH0_HWSW__GET REG_GET_RW
2262 #define R_DMA_CH0_HWSW__IGET REG_IGET_RW
2263 #define R_DMA_CH0_HWSW__SET REG_SET_RW
2264 #define R_DMA_CH0_HWSW__ISET REG_ISET_RW
2265 #define R_DMA_CH0_HWSW__SET_VAL REG_SET_VAL_RW
2266 #define R_DMA_CH0_HWSW__EQL REG_EQL_RW
2267 #define R_DMA_CH0_HWSW__IEQL REG_IEQL_RW
2268 #define R_DMA_CH0_HWSW__RD REG_RD_RW
2269 #define R_DMA_CH0_HWSW__IRD REG_IRD_RW
2270 #define R_DMA_CH0_HWSW__WR REG_WR_RW
2271 #define R_DMA_CH0_HWSW__IWR REG_IWR_RW
2272
2273 #define R_DMA_CH0_HWSW__WRITE(addr,value) \
2274 (*(addr) = (value))
2275 #define R_DMA_CH0_HWSW__READ(addr) \
2276 (*(addr))
2277
2278 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2279 #define R_DMA_CH0_HWSW__FIRST 0
2280 #define R_DMA_CH0_HWSW__LAST 9
2281 #define R_DMA_CH0_HWSW__OFFSET 16
2282 /* end */
2283
2284 #define R_DMA_CH0_HWSW__hw__hw__MASK 0xffff0000U
2285 #define R_DMA_CH0_HWSW__sw__sw__MASK 0x0000ffffU
2286
2287 #define R_DMA_CH0_HWSW__hw__MAX 0xffff
2288 #define R_DMA_CH0_HWSW__sw__MAX 0xffff
2289
2290 #define R_DMA_CH0_HWSW__hw__MIN 0
2291 #define R_DMA_CH0_HWSW__sw__MIN 0
2292
2293 #define R_DMA_CH0_HWSW__hw__BITNR 16
2294 #define R_DMA_CH0_HWSW__sw__BITNR 0
2295
2296 #define R_DMA_CH0_HWSW__hw__hw__VAL REG_VAL_VAL
2297 #define R_DMA_CH0_HWSW__sw__sw__VAL REG_VAL_VAL
2298
2299
2300 #endif
2301
2302 /*
2303 * R_DMA_CH0_NEXT
2304 * - type: RW
2305 * - addr: 0xb0000104
2306 * - group: DMA registers
2307 */
2308
2309 #if USE_GROUP__DMA_registers
2310
2311 #define R_DMA_CH0_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000104)
2312 #define R_DMA_CH0_NEXT__SVAL REG_SVAL_SHADOW
2313 #define R_DMA_CH0_NEXT__SVAL_I REG_SVAL_I_SHADOW
2314 #define R_DMA_CH0_NEXT__TYPECAST REG_TYPECAST_UDWORD
2315 #define R_DMA_CH0_NEXT__TYPE (REG_UDWORD)
2316 #define R_DMA_CH0_NEXT__GET REG_GET_RW
2317 #define R_DMA_CH0_NEXT__IGET REG_IGET_RW
2318 #define R_DMA_CH0_NEXT__SET REG_SET_RW
2319 #define R_DMA_CH0_NEXT__ISET REG_ISET_RW
2320 #define R_DMA_CH0_NEXT__SET_VAL REG_SET_VAL_RW
2321 #define R_DMA_CH0_NEXT__EQL REG_EQL_RW
2322 #define R_DMA_CH0_NEXT__IEQL REG_IEQL_RW
2323 #define R_DMA_CH0_NEXT__RD REG_RD_RW
2324 #define R_DMA_CH0_NEXT__IRD REG_IRD_RW
2325 #define R_DMA_CH0_NEXT__WR REG_WR_RW
2326 #define R_DMA_CH0_NEXT__IWR REG_IWR_RW
2327
2328 #define R_DMA_CH0_NEXT__WRITE(addr,value) \
2329 (*(addr) = (value))
2330 #define R_DMA_CH0_NEXT__READ(addr) \
2331 (*(addr))
2332
2333 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2334 #define R_DMA_CH0_NEXT__FIRST 0
2335 #define R_DMA_CH0_NEXT__LAST 9
2336 #define R_DMA_CH0_NEXT__OFFSET 16
2337 /* end */
2338
2339 #define R_DMA_CH0_NEXT__next__next__MASK 0xffffffffU
2340
2341 #define R_DMA_CH0_NEXT__next__MAX 0xffffffff
2342
2343 #define R_DMA_CH0_NEXT__next__MIN 0
2344
2345 #define R_DMA_CH0_NEXT__next__BITNR 0
2346
2347 #define R_DMA_CH0_NEXT__next__next__VAL REG_VAL_VAL
2348
2349
2350 #endif
2351
2352 /*
2353 * R_DMA_CH0_STATUS
2354 * - type: RO
2355 * - addr: 0xb00001d2
2356 * - group: DMA registers
2357 */
2358
2359 #if USE_GROUP__DMA_registers
2360
2361 #define R_DMA_CH0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d2)
2362 #define R_DMA_CH0_STATUS__SVAL REG_SVAL_SHADOW
2363 #define R_DMA_CH0_STATUS__SVAL_I REG_SVAL_I_SHADOW
2364 #define R_DMA_CH0_STATUS__TYPECAST REG_TYPECAST_BYTE
2365 #define R_DMA_CH0_STATUS__TYPE (REG_BYTE)
2366 #define R_DMA_CH0_STATUS__GET REG_GET_RO
2367 #define R_DMA_CH0_STATUS__IGET REG_IGET_RO
2368 #define R_DMA_CH0_STATUS__SET REG_SET_RO
2369 #define R_DMA_CH0_STATUS__ISET REG_ISET_RO
2370 #define R_DMA_CH0_STATUS__SET_VAL REG_SET_VAL_RO
2371 #define R_DMA_CH0_STATUS__EQL REG_EQL_RO
2372 #define R_DMA_CH0_STATUS__IEQL REG_IEQL_RO
2373 #define R_DMA_CH0_STATUS__RD REG_RD_RO
2374 #define R_DMA_CH0_STATUS__IRD REG_IRD_RO
2375 #define R_DMA_CH0_STATUS__WR REG_WR_RO
2376 #define R_DMA_CH0_STATUS__IWR REG_IWR_RO
2377
2378 #define R_DMA_CH0_STATUS__READ(addr) \
2379 (*(addr))
2380
2381 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
2382 #define R_DMA_CH0_STATUS__FIRST 0
2383 #define R_DMA_CH0_STATUS__LAST 9
2384 #define R_DMA_CH0_STATUS__OFFSET 4
2385 /* end */
2386
2387 #define R_DMA_CH0_STATUS__avail__avail__MASK 0x0000007fU
2388
2389 #define R_DMA_CH0_STATUS__avail__MAX 0x7f
2390
2391 #define R_DMA_CH0_STATUS__avail__MIN 0
2392
2393 #define R_DMA_CH0_STATUS__avail__BITNR 0
2394
2395 #define R_DMA_CH0_STATUS__avail__avail__VAL REG_VAL_VAL
2396
2397
2398 #endif
2399
2400 /*
2401 * R_DMA_CH1_BUF
2402 * - type: RW
2403 * - addr: 0xb0000118
2404 * - group: DMA registers
2405 */
2406
2407 #if USE_GROUP__DMA_registers
2408
2409 #define R_DMA_CH1_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000118)
2410 #define R_DMA_CH1_BUF__SVAL REG_SVAL_SHADOW
2411 #define R_DMA_CH1_BUF__SVAL_I REG_SVAL_I_SHADOW
2412 #define R_DMA_CH1_BUF__TYPECAST REG_TYPECAST_UDWORD
2413 #define R_DMA_CH1_BUF__TYPE (REG_UDWORD)
2414 #define R_DMA_CH1_BUF__GET REG_GET_RW
2415 #define R_DMA_CH1_BUF__IGET REG_IGET_RW
2416 #define R_DMA_CH1_BUF__SET REG_SET_RW
2417 #define R_DMA_CH1_BUF__ISET REG_ISET_RW
2418 #define R_DMA_CH1_BUF__SET_VAL REG_SET_VAL_RW
2419 #define R_DMA_CH1_BUF__EQL REG_EQL_RW
2420 #define R_DMA_CH1_BUF__IEQL REG_IEQL_RW
2421 #define R_DMA_CH1_BUF__RD REG_RD_RW
2422 #define R_DMA_CH1_BUF__IRD REG_IRD_RW
2423 #define R_DMA_CH1_BUF__WR REG_WR_RW
2424 #define R_DMA_CH1_BUF__IWR REG_IWR_RW
2425
2426 #define R_DMA_CH1_BUF__WRITE(addr,value) \
2427 (*(addr) = (value))
2428 #define R_DMA_CH1_BUF__READ(addr) \
2429 (*(addr))
2430
2431 #define R_DMA_CH1_BUF__buf__buf__MASK 0xffffffffU
2432
2433 #define R_DMA_CH1_BUF__buf__MAX 0xffffffff
2434
2435 #define R_DMA_CH1_BUF__buf__MIN 0
2436
2437 #define R_DMA_CH1_BUF__buf__BITNR 0
2438
2439 #define R_DMA_CH1_BUF__buf__buf__VAL REG_VAL_VAL
2440
2441
2442 #endif
2443
2444 /*
2445 * R_DMA_CH1_CLR_INTR
2446 * - type: WO
2447 * - addr: 0xb00001d5
2448 * - group: DMA registers
2449 */
2450
2451 #if USE_GROUP__DMA_registers
2452
2453 #define R_DMA_CH1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d5)
2454
2455 #ifndef REG_NO_SHADOW
2456 #define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH1_CLR_INTR + 0))
2457 #define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH1_CLR_INTR + 0))
2458 #else /* REG_NO_SHADOW */
2459 #define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
2460 #define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
2461 #endif /* REG_NO_SHADOW */
2462
2463 #define R_DMA_CH1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
2464 #define R_DMA_CH1_CLR_INTR__SVAL REG_SVAL_ZERO
2465 #define R_DMA_CH1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
2466 #define R_DMA_CH1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
2467 #define R_DMA_CH1_CLR_INTR__TYPE (REG_BYTE)
2468 #define R_DMA_CH1_CLR_INTR__GET REG_GET_WO
2469 #define R_DMA_CH1_CLR_INTR__IGET REG_IGET_WO
2470 #define R_DMA_CH1_CLR_INTR__SET REG_SET_WO
2471 #define R_DMA_CH1_CLR_INTR__ISET REG_ISET_WO
2472 #define R_DMA_CH1_CLR_INTR__SET_VAL REG_SET_VAL_WO
2473 #define R_DMA_CH1_CLR_INTR__EQL REG_EQL_WO
2474 #define R_DMA_CH1_CLR_INTR__IEQL REG_IEQL_WO
2475 #define R_DMA_CH1_CLR_INTR__RD REG_RD_WO
2476 #define R_DMA_CH1_CLR_INTR__IRD REG_IRD_WO
2477 #define R_DMA_CH1_CLR_INTR__WR REG_WR_WO
2478 #define R_DMA_CH1_CLR_INTR__IWR REG_IWR_WO
2479
2480 #define R_DMA_CH1_CLR_INTR__WRITE(addr,value) \
2481 (*(addr) = (value))
2482
2483 #define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
2484 #define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
2485
2486 #define R_DMA_CH1_CLR_INTR__clr_eop__MAX 0x1
2487 #define R_DMA_CH1_CLR_INTR__clr_descr__MAX 0x1
2488
2489 #define R_DMA_CH1_CLR_INTR__clr_eop__MIN 0
2490 #define R_DMA_CH1_CLR_INTR__clr_descr__MIN 0
2491
2492 #define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
2493 #define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
2494
2495 #define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
2496 #define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
2497
2498 #define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__do 1
2499 #define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__dont 0
2500 #define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__do 1
2501 #define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__dont 0
2502
2503 #endif
2504
2505 /*
2506 * R_DMA_CH1_CMD
2507 * - type: RW
2508 * - addr: 0xb00001d4
2509 * - group: DMA registers
2510 */
2511
2512 #if USE_GROUP__DMA_registers
2513
2514 #define R_DMA_CH1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d4)
2515 #define R_DMA_CH1_CMD__SVAL REG_SVAL_SHADOW
2516 #define R_DMA_CH1_CMD__SVAL_I REG_SVAL_I_SHADOW
2517 #define R_DMA_CH1_CMD__TYPECAST REG_TYPECAST_BYTE
2518 #define R_DMA_CH1_CMD__TYPE (REG_BYTE)
2519 #define R_DMA_CH1_CMD__GET REG_GET_RW
2520 #define R_DMA_CH1_CMD__IGET REG_IGET_RW
2521 #define R_DMA_CH1_CMD__SET REG_SET_RW
2522 #define R_DMA_CH1_CMD__ISET REG_ISET_RW
2523 #define R_DMA_CH1_CMD__SET_VAL REG_SET_VAL_RW
2524 #define R_DMA_CH1_CMD__EQL REG_EQL_RW
2525 #define R_DMA_CH1_CMD__IEQL REG_IEQL_RW
2526 #define R_DMA_CH1_CMD__RD REG_RD_RW
2527 #define R_DMA_CH1_CMD__IRD REG_IRD_RW
2528 #define R_DMA_CH1_CMD__WR REG_WR_RW
2529 #define R_DMA_CH1_CMD__IWR REG_IWR_RW
2530
2531 #define R_DMA_CH1_CMD__WRITE(addr,value) \
2532 (*(addr) = (value))
2533 #define R_DMA_CH1_CMD__READ(addr) \
2534 (*(addr))
2535
2536 #define R_DMA_CH1_CMD__cmd__cmd__MASK 0x00000007U
2537
2538 #define R_DMA_CH1_CMD__cmd__MAX 0x7
2539
2540 #define R_DMA_CH1_CMD__cmd__MIN 0
2541
2542 #define R_DMA_CH1_CMD__cmd__BITNR 0
2543
2544 #define R_DMA_CH1_CMD__cmd__cmd__VAL REG_VAL_ENUM
2545
2546 #define R_DMA_CH1_CMD__cmd__cmd__continue 3
2547 #define R_DMA_CH1_CMD__cmd__cmd__hold 0
2548 #define R_DMA_CH1_CMD__cmd__cmd__reset 4
2549 #define R_DMA_CH1_CMD__cmd__cmd__restart 3
2550 #define R_DMA_CH1_CMD__cmd__cmd__start 1
2551
2552 #endif
2553
2554 /*
2555 * R_DMA_CH1_DESCR
2556 * - type: RW
2557 * - addr: 0xb000011c
2558 * - group: DMA registers
2559 */
2560
2561 #if USE_GROUP__DMA_registers
2562
2563 #define R_DMA_CH1_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000011c)
2564 #define R_DMA_CH1_DESCR__SVAL REG_SVAL_SHADOW
2565 #define R_DMA_CH1_DESCR__SVAL_I REG_SVAL_I_SHADOW
2566 #define R_DMA_CH1_DESCR__TYPECAST REG_TYPECAST_UDWORD
2567 #define R_DMA_CH1_DESCR__TYPE (REG_UDWORD)
2568 #define R_DMA_CH1_DESCR__GET REG_GET_RW
2569 #define R_DMA_CH1_DESCR__IGET REG_IGET_RW
2570 #define R_DMA_CH1_DESCR__SET REG_SET_RW
2571 #define R_DMA_CH1_DESCR__ISET REG_ISET_RW
2572 #define R_DMA_CH1_DESCR__SET_VAL REG_SET_VAL_RW
2573 #define R_DMA_CH1_DESCR__EQL REG_EQL_RW
2574 #define R_DMA_CH1_DESCR__IEQL REG_IEQL_RW
2575 #define R_DMA_CH1_DESCR__RD REG_RD_RW
2576 #define R_DMA_CH1_DESCR__IRD REG_IRD_RW
2577 #define R_DMA_CH1_DESCR__WR REG_WR_RW
2578 #define R_DMA_CH1_DESCR__IWR REG_IWR_RW
2579
2580 #define R_DMA_CH1_DESCR__WRITE(addr,value) \
2581 (*(addr) = (value))
2582 #define R_DMA_CH1_DESCR__READ(addr) \
2583 (*(addr))
2584
2585 #define R_DMA_CH1_DESCR__descr__descr__MASK 0xffffffffU
2586
2587 #define R_DMA_CH1_DESCR__descr__MAX 0xffffffff
2588
2589 #define R_DMA_CH1_DESCR__descr__MIN 0
2590
2591 #define R_DMA_CH1_DESCR__descr__BITNR 0
2592
2593 #define R_DMA_CH1_DESCR__descr__descr__VAL REG_VAL_VAL
2594
2595
2596 #endif
2597
2598 /*
2599 * R_DMA_CH1_FIRST
2600 * - type: RW
2601 * - addr: 0xb00001a4
2602 * - group: DMA registers
2603 */
2604
2605 #if USE_GROUP__DMA_registers
2606
2607 #define R_DMA_CH1_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a4)
2608 #define R_DMA_CH1_FIRST__SVAL REG_SVAL_SHADOW
2609 #define R_DMA_CH1_FIRST__SVAL_I REG_SVAL_I_SHADOW
2610 #define R_DMA_CH1_FIRST__TYPECAST REG_TYPECAST_UDWORD
2611 #define R_DMA_CH1_FIRST__TYPE (REG_UDWORD)
2612 #define R_DMA_CH1_FIRST__GET REG_GET_RW
2613 #define R_DMA_CH1_FIRST__IGET REG_IGET_RW
2614 #define R_DMA_CH1_FIRST__SET REG_SET_RW
2615 #define R_DMA_CH1_FIRST__ISET REG_ISET_RW
2616 #define R_DMA_CH1_FIRST__SET_VAL REG_SET_VAL_RW
2617 #define R_DMA_CH1_FIRST__EQL REG_EQL_RW
2618 #define R_DMA_CH1_FIRST__IEQL REG_IEQL_RW
2619 #define R_DMA_CH1_FIRST__RD REG_RD_RW
2620 #define R_DMA_CH1_FIRST__IRD REG_IRD_RW
2621 #define R_DMA_CH1_FIRST__WR REG_WR_RW
2622 #define R_DMA_CH1_FIRST__IWR REG_IWR_RW
2623
2624 #define R_DMA_CH1_FIRST__WRITE(addr,value) \
2625 (*(addr) = (value))
2626 #define R_DMA_CH1_FIRST__READ(addr) \
2627 (*(addr))
2628
2629 #define R_DMA_CH1_FIRST__first__first__MASK 0xffffffffU
2630
2631 #define R_DMA_CH1_FIRST__first__MAX 0xffffffff
2632
2633 #define R_DMA_CH1_FIRST__first__MIN 0
2634
2635 #define R_DMA_CH1_FIRST__first__BITNR 0
2636
2637 #define R_DMA_CH1_FIRST__first__first__VAL REG_VAL_VAL
2638
2639
2640 #endif
2641
2642 /*
2643 * R_DMA_CH1_HWSW
2644 * - type: RW
2645 * - addr: 0xb0000110
2646 * - group: DMA registers
2647 */
2648
2649 #if USE_GROUP__DMA_registers
2650
2651 #define R_DMA_CH1_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000110)
2652 #define R_DMA_CH1_HWSW__SVAL REG_SVAL_SHADOW
2653 #define R_DMA_CH1_HWSW__SVAL_I REG_SVAL_I_SHADOW
2654 #define R_DMA_CH1_HWSW__TYPECAST REG_TYPECAST_UDWORD
2655 #define R_DMA_CH1_HWSW__TYPE (REG_UDWORD)
2656 #define R_DMA_CH1_HWSW__GET REG_GET_RW
2657 #define R_DMA_CH1_HWSW__IGET REG_IGET_RW
2658 #define R_DMA_CH1_HWSW__SET REG_SET_RW
2659 #define R_DMA_CH1_HWSW__ISET REG_ISET_RW
2660 #define R_DMA_CH1_HWSW__SET_VAL REG_SET_VAL_RW
2661 #define R_DMA_CH1_HWSW__EQL REG_EQL_RW
2662 #define R_DMA_CH1_HWSW__IEQL REG_IEQL_RW
2663 #define R_DMA_CH1_HWSW__RD REG_RD_RW
2664 #define R_DMA_CH1_HWSW__IRD REG_IRD_RW
2665 #define R_DMA_CH1_HWSW__WR REG_WR_RW
2666 #define R_DMA_CH1_HWSW__IWR REG_IWR_RW
2667
2668 #define R_DMA_CH1_HWSW__WRITE(addr,value) \
2669 (*(addr) = (value))
2670 #define R_DMA_CH1_HWSW__READ(addr) \
2671 (*(addr))
2672
2673 #define R_DMA_CH1_HWSW__hw__hw__MASK 0xffff0000U
2674 #define R_DMA_CH1_HWSW__sw__sw__MASK 0x0000ffffU
2675
2676 #define R_DMA_CH1_HWSW__hw__MAX 0xffff
2677 #define R_DMA_CH1_HWSW__sw__MAX 0xffff
2678
2679 #define R_DMA_CH1_HWSW__hw__MIN 0
2680 #define R_DMA_CH1_HWSW__sw__MIN 0
2681
2682 #define R_DMA_CH1_HWSW__hw__BITNR 16
2683 #define R_DMA_CH1_HWSW__sw__BITNR 0
2684
2685 #define R_DMA_CH1_HWSW__hw__hw__VAL REG_VAL_VAL
2686 #define R_DMA_CH1_HWSW__sw__sw__VAL REG_VAL_VAL
2687
2688
2689 #endif
2690
2691 /*
2692 * R_DMA_CH1_NEXT
2693 * - type: RW
2694 * - addr: 0xb0000114
2695 * - group: DMA registers
2696 */
2697
2698 #if USE_GROUP__DMA_registers
2699
2700 #define R_DMA_CH1_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000114)
2701 #define R_DMA_CH1_NEXT__SVAL REG_SVAL_SHADOW
2702 #define R_DMA_CH1_NEXT__SVAL_I REG_SVAL_I_SHADOW
2703 #define R_DMA_CH1_NEXT__TYPECAST REG_TYPECAST_UDWORD
2704 #define R_DMA_CH1_NEXT__TYPE (REG_UDWORD)
2705 #define R_DMA_CH1_NEXT__GET REG_GET_RW
2706 #define R_DMA_CH1_NEXT__IGET REG_IGET_RW
2707 #define R_DMA_CH1_NEXT__SET REG_SET_RW
2708 #define R_DMA_CH1_NEXT__ISET REG_ISET_RW
2709 #define R_DMA_CH1_NEXT__SET_VAL REG_SET_VAL_RW
2710 #define R_DMA_CH1_NEXT__EQL REG_EQL_RW
2711 #define R_DMA_CH1_NEXT__IEQL REG_IEQL_RW
2712 #define R_DMA_CH1_NEXT__RD REG_RD_RW
2713 #define R_DMA_CH1_NEXT__IRD REG_IRD_RW
2714 #define R_DMA_CH1_NEXT__WR REG_WR_RW
2715 #define R_DMA_CH1_NEXT__IWR REG_IWR_RW
2716
2717 #define R_DMA_CH1_NEXT__WRITE(addr,value) \
2718 (*(addr) = (value))
2719 #define R_DMA_CH1_NEXT__READ(addr) \
2720 (*(addr))
2721
2722 #define R_DMA_CH1_NEXT__next__next__MASK 0xffffffffU
2723
2724 #define R_DMA_CH1_NEXT__next__MAX 0xffffffff
2725
2726 #define R_DMA_CH1_NEXT__next__MIN 0
2727
2728 #define R_DMA_CH1_NEXT__next__BITNR 0
2729
2730 #define R_DMA_CH1_NEXT__next__next__VAL REG_VAL_VAL
2731
2732
2733 #endif
2734
2735 /*
2736 * R_DMA_CH1_STATUS
2737 * - type: RO
2738 * - addr: 0xb00001d6
2739 * - group: DMA registers
2740 */
2741
2742 #if USE_GROUP__DMA_registers
2743
2744 #define R_DMA_CH1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d6)
2745 #define R_DMA_CH1_STATUS__SVAL REG_SVAL_SHADOW
2746 #define R_DMA_CH1_STATUS__SVAL_I REG_SVAL_I_SHADOW
2747 #define R_DMA_CH1_STATUS__TYPECAST REG_TYPECAST_BYTE
2748 #define R_DMA_CH1_STATUS__TYPE (REG_BYTE)
2749 #define R_DMA_CH1_STATUS__GET REG_GET_RO
2750 #define R_DMA_CH1_STATUS__IGET REG_IGET_RO
2751 #define R_DMA_CH1_STATUS__SET REG_SET_RO
2752 #define R_DMA_CH1_STATUS__ISET REG_ISET_RO
2753 #define R_DMA_CH1_STATUS__SET_VAL REG_SET_VAL_RO
2754 #define R_DMA_CH1_STATUS__EQL REG_EQL_RO
2755 #define R_DMA_CH1_STATUS__IEQL REG_IEQL_RO
2756 #define R_DMA_CH1_STATUS__RD REG_RD_RO
2757 #define R_DMA_CH1_STATUS__IRD REG_IRD_RO
2758 #define R_DMA_CH1_STATUS__WR REG_WR_RO
2759 #define R_DMA_CH1_STATUS__IWR REG_IWR_RO
2760
2761 #define R_DMA_CH1_STATUS__READ(addr) \
2762 (*(addr))
2763
2764 #define R_DMA_CH1_STATUS__avail__avail__MASK 0x0000007fU
2765
2766 #define R_DMA_CH1_STATUS__avail__MAX 0x7f
2767
2768 #define R_DMA_CH1_STATUS__avail__MIN 0
2769
2770 #define R_DMA_CH1_STATUS__avail__BITNR 0
2771
2772 #define R_DMA_CH1_STATUS__avail__avail__VAL REG_VAL_VAL
2773
2774
2775 #endif
2776
2777 /*
2778 * R_DMA_CH2_BUF
2779 * - type: RW
2780 * - addr: 0xb0000128
2781 * - group: DMA registers
2782 */
2783
2784 #if USE_GROUP__DMA_registers
2785
2786 #define R_DMA_CH2_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000128)
2787 #define R_DMA_CH2_BUF__SVAL REG_SVAL_SHADOW
2788 #define R_DMA_CH2_BUF__SVAL_I REG_SVAL_I_SHADOW
2789 #define R_DMA_CH2_BUF__TYPECAST REG_TYPECAST_UDWORD
2790 #define R_DMA_CH2_BUF__TYPE (REG_UDWORD)
2791 #define R_DMA_CH2_BUF__GET REG_GET_RW
2792 #define R_DMA_CH2_BUF__IGET REG_IGET_RW
2793 #define R_DMA_CH2_BUF__SET REG_SET_RW
2794 #define R_DMA_CH2_BUF__ISET REG_ISET_RW
2795 #define R_DMA_CH2_BUF__SET_VAL REG_SET_VAL_RW
2796 #define R_DMA_CH2_BUF__EQL REG_EQL_RW
2797 #define R_DMA_CH2_BUF__IEQL REG_IEQL_RW
2798 #define R_DMA_CH2_BUF__RD REG_RD_RW
2799 #define R_DMA_CH2_BUF__IRD REG_IRD_RW
2800 #define R_DMA_CH2_BUF__WR REG_WR_RW
2801 #define R_DMA_CH2_BUF__IWR REG_IWR_RW
2802
2803 #define R_DMA_CH2_BUF__WRITE(addr,value) \
2804 (*(addr) = (value))
2805 #define R_DMA_CH2_BUF__READ(addr) \
2806 (*(addr))
2807
2808 #define R_DMA_CH2_BUF__buf__buf__MASK 0xffffffffU
2809
2810 #define R_DMA_CH2_BUF__buf__MAX 0xffffffff
2811
2812 #define R_DMA_CH2_BUF__buf__MIN 0
2813
2814 #define R_DMA_CH2_BUF__buf__BITNR 0
2815
2816 #define R_DMA_CH2_BUF__buf__buf__VAL REG_VAL_VAL
2817
2818
2819 #endif
2820
2821 /*
2822 * R_DMA_CH2_CLR_INTR
2823 * - type: WO
2824 * - addr: 0xb00001d9
2825 * - group: DMA registers
2826 */
2827
2828 #if USE_GROUP__DMA_registers
2829
2830 #define R_DMA_CH2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d9)
2831
2832 #ifndef REG_NO_SHADOW
2833 #define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH2_CLR_INTR + 0))
2834 #define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH2_CLR_INTR + 0))
2835 #else /* REG_NO_SHADOW */
2836 #define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
2837 #define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
2838 #endif /* REG_NO_SHADOW */
2839
2840 #define R_DMA_CH2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
2841 #define R_DMA_CH2_CLR_INTR__SVAL REG_SVAL_ZERO
2842 #define R_DMA_CH2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
2843 #define R_DMA_CH2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
2844 #define R_DMA_CH2_CLR_INTR__TYPE (REG_BYTE)
2845 #define R_DMA_CH2_CLR_INTR__GET REG_GET_WO
2846 #define R_DMA_CH2_CLR_INTR__IGET REG_IGET_WO
2847 #define R_DMA_CH2_CLR_INTR__SET REG_SET_WO
2848 #define R_DMA_CH2_CLR_INTR__ISET REG_ISET_WO
2849 #define R_DMA_CH2_CLR_INTR__SET_VAL REG_SET_VAL_WO
2850 #define R_DMA_CH2_CLR_INTR__EQL REG_EQL_WO
2851 #define R_DMA_CH2_CLR_INTR__IEQL REG_IEQL_WO
2852 #define R_DMA_CH2_CLR_INTR__RD REG_RD_WO
2853 #define R_DMA_CH2_CLR_INTR__IRD REG_IRD_WO
2854 #define R_DMA_CH2_CLR_INTR__WR REG_WR_WO
2855 #define R_DMA_CH2_CLR_INTR__IWR REG_IWR_WO
2856
2857 #define R_DMA_CH2_CLR_INTR__WRITE(addr,value) \
2858 (*(addr) = (value))
2859
2860 #define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
2861 #define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
2862
2863 #define R_DMA_CH2_CLR_INTR__clr_eop__MAX 0x1
2864 #define R_DMA_CH2_CLR_INTR__clr_descr__MAX 0x1
2865
2866 #define R_DMA_CH2_CLR_INTR__clr_eop__MIN 0
2867 #define R_DMA_CH2_CLR_INTR__clr_descr__MIN 0
2868
2869 #define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
2870 #define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
2871
2872 #define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
2873 #define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
2874
2875 #define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__do 1
2876 #define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__dont 0
2877 #define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__do 1
2878 #define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__dont 0
2879
2880 #endif
2881
2882 /*
2883 * R_DMA_CH2_CMD
2884 * - type: RW
2885 * - addr: 0xb00001d8
2886 * - group: DMA registers
2887 */
2888
2889 #if USE_GROUP__DMA_registers
2890
2891 #define R_DMA_CH2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d8)
2892 #define R_DMA_CH2_CMD__SVAL REG_SVAL_SHADOW
2893 #define R_DMA_CH2_CMD__SVAL_I REG_SVAL_I_SHADOW
2894 #define R_DMA_CH2_CMD__TYPECAST REG_TYPECAST_BYTE
2895 #define R_DMA_CH2_CMD__TYPE (REG_BYTE)
2896 #define R_DMA_CH2_CMD__GET REG_GET_RW
2897 #define R_DMA_CH2_CMD__IGET REG_IGET_RW
2898 #define R_DMA_CH2_CMD__SET REG_SET_RW
2899 #define R_DMA_CH2_CMD__ISET REG_ISET_RW
2900 #define R_DMA_CH2_CMD__SET_VAL REG_SET_VAL_RW
2901 #define R_DMA_CH2_CMD__EQL REG_EQL_RW
2902 #define R_DMA_CH2_CMD__IEQL REG_IEQL_RW
2903 #define R_DMA_CH2_CMD__RD REG_RD_RW
2904 #define R_DMA_CH2_CMD__IRD REG_IRD_RW
2905 #define R_DMA_CH2_CMD__WR REG_WR_RW
2906 #define R_DMA_CH2_CMD__IWR REG_IWR_RW
2907
2908 #define R_DMA_CH2_CMD__WRITE(addr,value) \
2909 (*(addr) = (value))
2910 #define R_DMA_CH2_CMD__READ(addr) \
2911 (*(addr))
2912
2913 #define R_DMA_CH2_CMD__cmd__cmd__MASK 0x00000007U
2914
2915 #define R_DMA_CH2_CMD__cmd__MAX 0x7
2916
2917 #define R_DMA_CH2_CMD__cmd__MIN 0
2918
2919 #define R_DMA_CH2_CMD__cmd__BITNR 0
2920
2921 #define R_DMA_CH2_CMD__cmd__cmd__VAL REG_VAL_ENUM
2922
2923 #define R_DMA_CH2_CMD__cmd__cmd__continue 3
2924 #define R_DMA_CH2_CMD__cmd__cmd__hold 0
2925 #define R_DMA_CH2_CMD__cmd__cmd__reset 4
2926 #define R_DMA_CH2_CMD__cmd__cmd__restart 3
2927 #define R_DMA_CH2_CMD__cmd__cmd__start 1
2928
2929 #endif
2930
2931 /*
2932 * R_DMA_CH2_DESCR
2933 * - type: RW
2934 * - addr: 0xb000012c
2935 * - group: DMA registers
2936 */
2937
2938 #if USE_GROUP__DMA_registers
2939
2940 #define R_DMA_CH2_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000012c)
2941 #define R_DMA_CH2_DESCR__SVAL REG_SVAL_SHADOW
2942 #define R_DMA_CH2_DESCR__SVAL_I REG_SVAL_I_SHADOW
2943 #define R_DMA_CH2_DESCR__TYPECAST REG_TYPECAST_UDWORD
2944 #define R_DMA_CH2_DESCR__TYPE (REG_UDWORD)
2945 #define R_DMA_CH2_DESCR__GET REG_GET_RW
2946 #define R_DMA_CH2_DESCR__IGET REG_IGET_RW
2947 #define R_DMA_CH2_DESCR__SET REG_SET_RW
2948 #define R_DMA_CH2_DESCR__ISET REG_ISET_RW
2949 #define R_DMA_CH2_DESCR__SET_VAL REG_SET_VAL_RW
2950 #define R_DMA_CH2_DESCR__EQL REG_EQL_RW
2951 #define R_DMA_CH2_DESCR__IEQL REG_IEQL_RW
2952 #define R_DMA_CH2_DESCR__RD REG_RD_RW
2953 #define R_DMA_CH2_DESCR__IRD REG_IRD_RW
2954 #define R_DMA_CH2_DESCR__WR REG_WR_RW
2955 #define R_DMA_CH2_DESCR__IWR REG_IWR_RW
2956
2957 #define R_DMA_CH2_DESCR__WRITE(addr,value) \
2958 (*(addr) = (value))
2959 #define R_DMA_CH2_DESCR__READ(addr) \
2960 (*(addr))
2961
2962 #define R_DMA_CH2_DESCR__descr__descr__MASK 0xffffffffU
2963
2964 #define R_DMA_CH2_DESCR__descr__MAX 0xffffffff
2965
2966 #define R_DMA_CH2_DESCR__descr__MIN 0
2967
2968 #define R_DMA_CH2_DESCR__descr__BITNR 0
2969
2970 #define R_DMA_CH2_DESCR__descr__descr__VAL REG_VAL_VAL
2971
2972
2973 #endif
2974
2975 /*
2976 * R_DMA_CH2_FIRST
2977 * - type: RW
2978 * - addr: 0xb00001a8
2979 * - group: DMA registers
2980 */
2981
2982 #if USE_GROUP__DMA_registers
2983
2984 #define R_DMA_CH2_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a8)
2985 #define R_DMA_CH2_FIRST__SVAL REG_SVAL_SHADOW
2986 #define R_DMA_CH2_FIRST__SVAL_I REG_SVAL_I_SHADOW
2987 #define R_DMA_CH2_FIRST__TYPECAST REG_TYPECAST_UDWORD
2988 #define R_DMA_CH2_FIRST__TYPE (REG_UDWORD)
2989 #define R_DMA_CH2_FIRST__GET REG_GET_RW
2990 #define R_DMA_CH2_FIRST__IGET REG_IGET_RW
2991 #define R_DMA_CH2_FIRST__SET REG_SET_RW
2992 #define R_DMA_CH2_FIRST__ISET REG_ISET_RW
2993 #define R_DMA_CH2_FIRST__SET_VAL REG_SET_VAL_RW
2994 #define R_DMA_CH2_FIRST__EQL REG_EQL_RW
2995 #define R_DMA_CH2_FIRST__IEQL REG_IEQL_RW
2996 #define R_DMA_CH2_FIRST__RD REG_RD_RW
2997 #define R_DMA_CH2_FIRST__IRD REG_IRD_RW
2998 #define R_DMA_CH2_FIRST__WR REG_WR_RW
2999 #define R_DMA_CH2_FIRST__IWR REG_IWR_RW
3000
3001 #define R_DMA_CH2_FIRST__WRITE(addr,value) \
3002 (*(addr) = (value))
3003 #define R_DMA_CH2_FIRST__READ(addr) \
3004 (*(addr))
3005
3006 #define R_DMA_CH2_FIRST__first__first__MASK 0xffffffffU
3007
3008 #define R_DMA_CH2_FIRST__first__MAX 0xffffffff
3009
3010 #define R_DMA_CH2_FIRST__first__MIN 0
3011
3012 #define R_DMA_CH2_FIRST__first__BITNR 0
3013
3014 #define R_DMA_CH2_FIRST__first__first__VAL REG_VAL_VAL
3015
3016
3017 #endif
3018
3019 /*
3020 * R_DMA_CH2_HWSW
3021 * - type: RW
3022 * - addr: 0xb0000120
3023 * - group: DMA registers
3024 */
3025
3026 #if USE_GROUP__DMA_registers
3027
3028 #define R_DMA_CH2_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000120)
3029 #define R_DMA_CH2_HWSW__SVAL REG_SVAL_SHADOW
3030 #define R_DMA_CH2_HWSW__SVAL_I REG_SVAL_I_SHADOW
3031 #define R_DMA_CH2_HWSW__TYPECAST REG_TYPECAST_UDWORD
3032 #define R_DMA_CH2_HWSW__TYPE (REG_UDWORD)
3033 #define R_DMA_CH2_HWSW__GET REG_GET_RW
3034 #define R_DMA_CH2_HWSW__IGET REG_IGET_RW
3035 #define R_DMA_CH2_HWSW__SET REG_SET_RW
3036 #define R_DMA_CH2_HWSW__ISET REG_ISET_RW
3037 #define R_DMA_CH2_HWSW__SET_VAL REG_SET_VAL_RW
3038 #define R_DMA_CH2_HWSW__EQL REG_EQL_RW
3039 #define R_DMA_CH2_HWSW__IEQL REG_IEQL_RW
3040 #define R_DMA_CH2_HWSW__RD REG_RD_RW
3041 #define R_DMA_CH2_HWSW__IRD REG_IRD_RW
3042 #define R_DMA_CH2_HWSW__WR REG_WR_RW
3043 #define R_DMA_CH2_HWSW__IWR REG_IWR_RW
3044
3045 #define R_DMA_CH2_HWSW__WRITE(addr,value) \
3046 (*(addr) = (value))
3047 #define R_DMA_CH2_HWSW__READ(addr) \
3048 (*(addr))
3049
3050 #define R_DMA_CH2_HWSW__hw__hw__MASK 0xffff0000U
3051 #define R_DMA_CH2_HWSW__sw__sw__MASK 0x0000ffffU
3052
3053 #define R_DMA_CH2_HWSW__hw__MAX 0xffff
3054 #define R_DMA_CH2_HWSW__sw__MAX 0xffff
3055
3056 #define R_DMA_CH2_HWSW__hw__MIN 0
3057 #define R_DMA_CH2_HWSW__sw__MIN 0
3058
3059 #define R_DMA_CH2_HWSW__hw__BITNR 16
3060 #define R_DMA_CH2_HWSW__sw__BITNR 0
3061
3062 #define R_DMA_CH2_HWSW__hw__hw__VAL REG_VAL_VAL
3063 #define R_DMA_CH2_HWSW__sw__sw__VAL REG_VAL_VAL
3064
3065
3066 #endif
3067
3068 /*
3069 * R_DMA_CH2_NEXT
3070 * - type: RW
3071 * - addr: 0xb0000124
3072 * - group: DMA registers
3073 */
3074
3075 #if USE_GROUP__DMA_registers
3076
3077 #define R_DMA_CH2_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000124)
3078 #define R_DMA_CH2_NEXT__SVAL REG_SVAL_SHADOW
3079 #define R_DMA_CH2_NEXT__SVAL_I REG_SVAL_I_SHADOW
3080 #define R_DMA_CH2_NEXT__TYPECAST REG_TYPECAST_UDWORD
3081 #define R_DMA_CH2_NEXT__TYPE (REG_UDWORD)
3082 #define R_DMA_CH2_NEXT__GET REG_GET_RW
3083 #define R_DMA_CH2_NEXT__IGET REG_IGET_RW
3084 #define R_DMA_CH2_NEXT__SET REG_SET_RW
3085 #define R_DMA_CH2_NEXT__ISET REG_ISET_RW
3086 #define R_DMA_CH2_NEXT__SET_VAL REG_SET_VAL_RW
3087 #define R_DMA_CH2_NEXT__EQL REG_EQL_RW
3088 #define R_DMA_CH2_NEXT__IEQL REG_IEQL_RW
3089 #define R_DMA_CH2_NEXT__RD REG_RD_RW
3090 #define R_DMA_CH2_NEXT__IRD REG_IRD_RW
3091 #define R_DMA_CH2_NEXT__WR REG_WR_RW
3092 #define R_DMA_CH2_NEXT__IWR REG_IWR_RW
3093
3094 #define R_DMA_CH2_NEXT__WRITE(addr,value) \
3095 (*(addr) = (value))
3096 #define R_DMA_CH2_NEXT__READ(addr) \
3097 (*(addr))
3098
3099 #define R_DMA_CH2_NEXT__next__next__MASK 0xffffffffU
3100
3101 #define R_DMA_CH2_NEXT__next__MAX 0xffffffff
3102
3103 #define R_DMA_CH2_NEXT__next__MIN 0
3104
3105 #define R_DMA_CH2_NEXT__next__BITNR 0
3106
3107 #define R_DMA_CH2_NEXT__next__next__VAL REG_VAL_VAL
3108
3109
3110 #endif
3111
3112 /*
3113 * R_DMA_CH2_STATUS
3114 * - type: RO
3115 * - addr: 0xb00001da
3116 * - group: DMA registers
3117 */
3118
3119 #if USE_GROUP__DMA_registers
3120
3121 #define R_DMA_CH2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001da)
3122 #define R_DMA_CH2_STATUS__SVAL REG_SVAL_SHADOW
3123 #define R_DMA_CH2_STATUS__SVAL_I REG_SVAL_I_SHADOW
3124 #define R_DMA_CH2_STATUS__TYPECAST REG_TYPECAST_BYTE
3125 #define R_DMA_CH2_STATUS__TYPE (REG_BYTE)
3126 #define R_DMA_CH2_STATUS__GET REG_GET_RO
3127 #define R_DMA_CH2_STATUS__IGET REG_IGET_RO
3128 #define R_DMA_CH2_STATUS__SET REG_SET_RO
3129 #define R_DMA_CH2_STATUS__ISET REG_ISET_RO
3130 #define R_DMA_CH2_STATUS__SET_VAL REG_SET_VAL_RO
3131 #define R_DMA_CH2_STATUS__EQL REG_EQL_RO
3132 #define R_DMA_CH2_STATUS__IEQL REG_IEQL_RO
3133 #define R_DMA_CH2_STATUS__RD REG_RD_RO
3134 #define R_DMA_CH2_STATUS__IRD REG_IRD_RO
3135 #define R_DMA_CH2_STATUS__WR REG_WR_RO
3136 #define R_DMA_CH2_STATUS__IWR REG_IWR_RO
3137
3138 #define R_DMA_CH2_STATUS__READ(addr) \
3139 (*(addr))
3140
3141 #define R_DMA_CH2_STATUS__avail__avail__MASK 0x0000007fU
3142
3143 #define R_DMA_CH2_STATUS__avail__MAX 0x7f
3144
3145 #define R_DMA_CH2_STATUS__avail__MIN 0
3146
3147 #define R_DMA_CH2_STATUS__avail__BITNR 0
3148
3149 #define R_DMA_CH2_STATUS__avail__avail__VAL REG_VAL_VAL
3150
3151
3152 #endif
3153
3154 /*
3155 * R_DMA_CH3_BUF
3156 * - type: RW
3157 * - addr: 0xb0000138
3158 * - group: DMA registers
3159 */
3160
3161 #if USE_GROUP__DMA_registers
3162
3163 #define R_DMA_CH3_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000138)
3164 #define R_DMA_CH3_BUF__SVAL REG_SVAL_SHADOW
3165 #define R_DMA_CH3_BUF__SVAL_I REG_SVAL_I_SHADOW
3166 #define R_DMA_CH3_BUF__TYPECAST REG_TYPECAST_UDWORD
3167 #define R_DMA_CH3_BUF__TYPE (REG_UDWORD)
3168 #define R_DMA_CH3_BUF__GET REG_GET_RW
3169 #define R_DMA_CH3_BUF__IGET REG_IGET_RW
3170 #define R_DMA_CH3_BUF__SET REG_SET_RW
3171 #define R_DMA_CH3_BUF__ISET REG_ISET_RW
3172 #define R_DMA_CH3_BUF__SET_VAL REG_SET_VAL_RW
3173 #define R_DMA_CH3_BUF__EQL REG_EQL_RW
3174 #define R_DMA_CH3_BUF__IEQL REG_IEQL_RW
3175 #define R_DMA_CH3_BUF__RD REG_RD_RW
3176 #define R_DMA_CH3_BUF__IRD REG_IRD_RW
3177 #define R_DMA_CH3_BUF__WR REG_WR_RW
3178 #define R_DMA_CH3_BUF__IWR REG_IWR_RW
3179
3180 #define R_DMA_CH3_BUF__WRITE(addr,value) \
3181 (*(addr) = (value))
3182 #define R_DMA_CH3_BUF__READ(addr) \
3183 (*(addr))
3184
3185 #define R_DMA_CH3_BUF__buf__buf__MASK 0xffffffffU
3186
3187 #define R_DMA_CH3_BUF__buf__MAX 0xffffffff
3188
3189 #define R_DMA_CH3_BUF__buf__MIN 0
3190
3191 #define R_DMA_CH3_BUF__buf__BITNR 0
3192
3193 #define R_DMA_CH3_BUF__buf__buf__VAL REG_VAL_VAL
3194
3195
3196 #endif
3197
3198 /*
3199 * R_DMA_CH3_CLR_INTR
3200 * - type: WO
3201 * - addr: 0xb00001dd
3202 * - group: DMA registers
3203 */
3204
3205 #if USE_GROUP__DMA_registers
3206
3207 #define R_DMA_CH3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001dd)
3208
3209 #ifndef REG_NO_SHADOW
3210 #define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH3_CLR_INTR + 0))
3211 #define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH3_CLR_INTR + 0))
3212 #else /* REG_NO_SHADOW */
3213 #define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
3214 #define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
3215 #endif /* REG_NO_SHADOW */
3216
3217 #define R_DMA_CH3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
3218 #define R_DMA_CH3_CLR_INTR__SVAL REG_SVAL_ZERO
3219 #define R_DMA_CH3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
3220 #define R_DMA_CH3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
3221 #define R_DMA_CH3_CLR_INTR__TYPE (REG_BYTE)
3222 #define R_DMA_CH3_CLR_INTR__GET REG_GET_WO
3223 #define R_DMA_CH3_CLR_INTR__IGET REG_IGET_WO
3224 #define R_DMA_CH3_CLR_INTR__SET REG_SET_WO
3225 #define R_DMA_CH3_CLR_INTR__ISET REG_ISET_WO
3226 #define R_DMA_CH3_CLR_INTR__SET_VAL REG_SET_VAL_WO
3227 #define R_DMA_CH3_CLR_INTR__EQL REG_EQL_WO
3228 #define R_DMA_CH3_CLR_INTR__IEQL REG_IEQL_WO
3229 #define R_DMA_CH3_CLR_INTR__RD REG_RD_WO
3230 #define R_DMA_CH3_CLR_INTR__IRD REG_IRD_WO
3231 #define R_DMA_CH3_CLR_INTR__WR REG_WR_WO
3232 #define R_DMA_CH3_CLR_INTR__IWR REG_IWR_WO
3233
3234 #define R_DMA_CH3_CLR_INTR__WRITE(addr,value) \
3235 (*(addr) = (value))
3236
3237 #define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
3238 #define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
3239
3240 #define R_DMA_CH3_CLR_INTR__clr_eop__MAX 0x1
3241 #define R_DMA_CH3_CLR_INTR__clr_descr__MAX 0x1
3242
3243 #define R_DMA_CH3_CLR_INTR__clr_eop__MIN 0
3244 #define R_DMA_CH3_CLR_INTR__clr_descr__MIN 0
3245
3246 #define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
3247 #define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
3248
3249 #define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
3250 #define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
3251
3252 #define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__do 1
3253 #define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__dont 0
3254 #define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__do 1
3255 #define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__dont 0
3256
3257 #endif
3258
3259 /*
3260 * R_DMA_CH3_CMD
3261 * - type: RW
3262 * - addr: 0xb00001dc
3263 * - group: DMA registers
3264 */
3265
3266 #if USE_GROUP__DMA_registers
3267
3268 #define R_DMA_CH3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001dc)
3269 #define R_DMA_CH3_CMD__SVAL REG_SVAL_SHADOW
3270 #define R_DMA_CH3_CMD__SVAL_I REG_SVAL_I_SHADOW
3271 #define R_DMA_CH3_CMD__TYPECAST REG_TYPECAST_BYTE
3272 #define R_DMA_CH3_CMD__TYPE (REG_BYTE)
3273 #define R_DMA_CH3_CMD__GET REG_GET_RW
3274 #define R_DMA_CH3_CMD__IGET REG_IGET_RW
3275 #define R_DMA_CH3_CMD__SET REG_SET_RW
3276 #define R_DMA_CH3_CMD__ISET REG_ISET_RW
3277 #define R_DMA_CH3_CMD__SET_VAL REG_SET_VAL_RW
3278 #define R_DMA_CH3_CMD__EQL REG_EQL_RW
3279 #define R_DMA_CH3_CMD__IEQL REG_IEQL_RW
3280 #define R_DMA_CH3_CMD__RD REG_RD_RW
3281 #define R_DMA_CH3_CMD__IRD REG_IRD_RW
3282 #define R_DMA_CH3_CMD__WR REG_WR_RW
3283 #define R_DMA_CH3_CMD__IWR REG_IWR_RW
3284
3285 #define R_DMA_CH3_CMD__WRITE(addr,value) \
3286 (*(addr) = (value))
3287 #define R_DMA_CH3_CMD__READ(addr) \
3288 (*(addr))
3289
3290 #define R_DMA_CH3_CMD__cmd__cmd__MASK 0x00000007U
3291
3292 #define R_DMA_CH3_CMD__cmd__MAX 0x7
3293
3294 #define R_DMA_CH3_CMD__cmd__MIN 0
3295
3296 #define R_DMA_CH3_CMD__cmd__BITNR 0
3297
3298 #define R_DMA_CH3_CMD__cmd__cmd__VAL REG_VAL_ENUM
3299
3300 #define R_DMA_CH3_CMD__cmd__cmd__continue 3
3301 #define R_DMA_CH3_CMD__cmd__cmd__hold 0
3302 #define R_DMA_CH3_CMD__cmd__cmd__reset 4
3303 #define R_DMA_CH3_CMD__cmd__cmd__restart 3
3304 #define R_DMA_CH3_CMD__cmd__cmd__start 1
3305
3306 #endif
3307
3308 /*
3309 * R_DMA_CH3_DESCR
3310 * - type: RW
3311 * - addr: 0xb000013c
3312 * - group: DMA registers
3313 */
3314
3315 #if USE_GROUP__DMA_registers
3316
3317 #define R_DMA_CH3_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000013c)
3318 #define R_DMA_CH3_DESCR__SVAL REG_SVAL_SHADOW
3319 #define R_DMA_CH3_DESCR__SVAL_I REG_SVAL_I_SHADOW
3320 #define R_DMA_CH3_DESCR__TYPECAST REG_TYPECAST_UDWORD
3321 #define R_DMA_CH3_DESCR__TYPE (REG_UDWORD)
3322 #define R_DMA_CH3_DESCR__GET REG_GET_RW
3323 #define R_DMA_CH3_DESCR__IGET REG_IGET_RW
3324 #define R_DMA_CH3_DESCR__SET REG_SET_RW
3325 #define R_DMA_CH3_DESCR__ISET REG_ISET_RW
3326 #define R_DMA_CH3_DESCR__SET_VAL REG_SET_VAL_RW
3327 #define R_DMA_CH3_DESCR__EQL REG_EQL_RW
3328 #define R_DMA_CH3_DESCR__IEQL REG_IEQL_RW
3329 #define R_DMA_CH3_DESCR__RD REG_RD_RW
3330 #define R_DMA_CH3_DESCR__IRD REG_IRD_RW
3331 #define R_DMA_CH3_DESCR__WR REG_WR_RW
3332 #define R_DMA_CH3_DESCR__IWR REG_IWR_RW
3333
3334 #define R_DMA_CH3_DESCR__WRITE(addr,value) \
3335 (*(addr) = (value))
3336 #define R_DMA_CH3_DESCR__READ(addr) \
3337 (*(addr))
3338
3339 #define R_DMA_CH3_DESCR__descr__descr__MASK 0xffffffffU
3340
3341 #define R_DMA_CH3_DESCR__descr__MAX 0xffffffff
3342
3343 #define R_DMA_CH3_DESCR__descr__MIN 0
3344
3345 #define R_DMA_CH3_DESCR__descr__BITNR 0
3346
3347 #define R_DMA_CH3_DESCR__descr__descr__VAL REG_VAL_VAL
3348
3349
3350 #endif
3351
3352 /*
3353 * R_DMA_CH3_FIRST
3354 * - type: RW
3355 * - addr: 0xb00001ac
3356 * - group: DMA registers
3357 */
3358
3359 #if USE_GROUP__DMA_registers
3360
3361 #define R_DMA_CH3_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001ac)
3362 #define R_DMA_CH3_FIRST__SVAL REG_SVAL_SHADOW
3363 #define R_DMA_CH3_FIRST__SVAL_I REG_SVAL_I_SHADOW
3364 #define R_DMA_CH3_FIRST__TYPECAST REG_TYPECAST_UDWORD
3365 #define R_DMA_CH3_FIRST__TYPE (REG_UDWORD)
3366 #define R_DMA_CH3_FIRST__GET REG_GET_RW
3367 #define R_DMA_CH3_FIRST__IGET REG_IGET_RW
3368 #define R_DMA_CH3_FIRST__SET REG_SET_RW
3369 #define R_DMA_CH3_FIRST__ISET REG_ISET_RW
3370 #define R_DMA_CH3_FIRST__SET_VAL REG_SET_VAL_RW
3371 #define R_DMA_CH3_FIRST__EQL REG_EQL_RW
3372 #define R_DMA_CH3_FIRST__IEQL REG_IEQL_RW
3373 #define R_DMA_CH3_FIRST__RD REG_RD_RW
3374 #define R_DMA_CH3_FIRST__IRD REG_IRD_RW
3375 #define R_DMA_CH3_FIRST__WR REG_WR_RW
3376 #define R_DMA_CH3_FIRST__IWR REG_IWR_RW
3377
3378 #define R_DMA_CH3_FIRST__WRITE(addr,value) \
3379 (*(addr) = (value))
3380 #define R_DMA_CH3_FIRST__READ(addr) \
3381 (*(addr))
3382
3383 #define R_DMA_CH3_FIRST__first__first__MASK 0xffffffffU
3384
3385 #define R_DMA_CH3_FIRST__first__MAX 0xffffffff
3386
3387 #define R_DMA_CH3_FIRST__first__MIN 0
3388
3389 #define R_DMA_CH3_FIRST__first__BITNR 0
3390
3391 #define R_DMA_CH3_FIRST__first__first__VAL REG_VAL_VAL
3392
3393
3394 #endif
3395
3396 /*
3397 * R_DMA_CH3_HWSW
3398 * - type: RW
3399 * - addr: 0xb0000130
3400 * - group: DMA registers
3401 */
3402
3403 #if USE_GROUP__DMA_registers
3404
3405 #define R_DMA_CH3_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000130)
3406 #define R_DMA_CH3_HWSW__SVAL REG_SVAL_SHADOW
3407 #define R_DMA_CH3_HWSW__SVAL_I REG_SVAL_I_SHADOW
3408 #define R_DMA_CH3_HWSW__TYPECAST REG_TYPECAST_UDWORD
3409 #define R_DMA_CH3_HWSW__TYPE (REG_UDWORD)
3410 #define R_DMA_CH3_HWSW__GET REG_GET_RW
3411 #define R_DMA_CH3_HWSW__IGET REG_IGET_RW
3412 #define R_DMA_CH3_HWSW__SET REG_SET_RW
3413 #define R_DMA_CH3_HWSW__ISET REG_ISET_RW
3414 #define R_DMA_CH3_HWSW__SET_VAL REG_SET_VAL_RW
3415 #define R_DMA_CH3_HWSW__EQL REG_EQL_RW
3416 #define R_DMA_CH3_HWSW__IEQL REG_IEQL_RW
3417 #define R_DMA_CH3_HWSW__RD REG_RD_RW
3418 #define R_DMA_CH3_HWSW__IRD REG_IRD_RW
3419 #define R_DMA_CH3_HWSW__WR REG_WR_RW
3420 #define R_DMA_CH3_HWSW__IWR REG_IWR_RW
3421
3422 #define R_DMA_CH3_HWSW__WRITE(addr,value) \
3423 (*(addr) = (value))
3424 #define R_DMA_CH3_HWSW__READ(addr) \
3425 (*(addr))
3426
3427 #define R_DMA_CH3_HWSW__hw__hw__MASK 0xffff0000U
3428 #define R_DMA_CH3_HWSW__sw__sw__MASK 0x0000ffffU
3429
3430 #define R_DMA_CH3_HWSW__hw__MAX 0xffff
3431 #define R_DMA_CH3_HWSW__sw__MAX 0xffff
3432
3433 #define R_DMA_CH3_HWSW__hw__MIN 0
3434 #define R_DMA_CH3_HWSW__sw__MIN 0
3435
3436 #define R_DMA_CH3_HWSW__hw__BITNR 16
3437 #define R_DMA_CH3_HWSW__sw__BITNR 0
3438
3439 #define R_DMA_CH3_HWSW__hw__hw__VAL REG_VAL_VAL
3440 #define R_DMA_CH3_HWSW__sw__sw__VAL REG_VAL_VAL
3441
3442
3443 #endif
3444
3445 /*
3446 * R_DMA_CH3_NEXT
3447 * - type: RW
3448 * - addr: 0xb0000134
3449 * - group: DMA registers
3450 */
3451
3452 #if USE_GROUP__DMA_registers
3453
3454 #define R_DMA_CH3_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000134)
3455 #define R_DMA_CH3_NEXT__SVAL REG_SVAL_SHADOW
3456 #define R_DMA_CH3_NEXT__SVAL_I REG_SVAL_I_SHADOW
3457 #define R_DMA_CH3_NEXT__TYPECAST REG_TYPECAST_UDWORD
3458 #define R_DMA_CH3_NEXT__TYPE (REG_UDWORD)
3459 #define R_DMA_CH3_NEXT__GET REG_GET_RW
3460 #define R_DMA_CH3_NEXT__IGET REG_IGET_RW
3461 #define R_DMA_CH3_NEXT__SET REG_SET_RW
3462 #define R_DMA_CH3_NEXT__ISET REG_ISET_RW
3463 #define R_DMA_CH3_NEXT__SET_VAL REG_SET_VAL_RW
3464 #define R_DMA_CH3_NEXT__EQL REG_EQL_RW
3465 #define R_DMA_CH3_NEXT__IEQL REG_IEQL_RW
3466 #define R_DMA_CH3_NEXT__RD REG_RD_RW
3467 #define R_DMA_CH3_NEXT__IRD REG_IRD_RW
3468 #define R_DMA_CH3_NEXT__WR REG_WR_RW
3469 #define R_DMA_CH3_NEXT__IWR REG_IWR_RW
3470
3471 #define R_DMA_CH3_NEXT__WRITE(addr,value) \
3472 (*(addr) = (value))
3473 #define R_DMA_CH3_NEXT__READ(addr) \
3474 (*(addr))
3475
3476 #define R_DMA_CH3_NEXT__next__next__MASK 0xffffffffU
3477
3478 #define R_DMA_CH3_NEXT__next__MAX 0xffffffff
3479
3480 #define R_DMA_CH3_NEXT__next__MIN 0
3481
3482 #define R_DMA_CH3_NEXT__next__BITNR 0
3483
3484 #define R_DMA_CH3_NEXT__next__next__VAL REG_VAL_VAL
3485
3486
3487 #endif
3488
3489 /*
3490 * R_DMA_CH3_STATUS
3491 * - type: RO
3492 * - addr: 0xb00001de
3493 * - group: DMA registers
3494 */
3495
3496 #if USE_GROUP__DMA_registers
3497
3498 #define R_DMA_CH3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001de)
3499 #define R_DMA_CH3_STATUS__SVAL REG_SVAL_SHADOW
3500 #define R_DMA_CH3_STATUS__SVAL_I REG_SVAL_I_SHADOW
3501 #define R_DMA_CH3_STATUS__TYPECAST REG_TYPECAST_BYTE
3502 #define R_DMA_CH3_STATUS__TYPE (REG_BYTE)
3503 #define R_DMA_CH3_STATUS__GET REG_GET_RO
3504 #define R_DMA_CH3_STATUS__IGET REG_IGET_RO
3505 #define R_DMA_CH3_STATUS__SET REG_SET_RO
3506 #define R_DMA_CH3_STATUS__ISET REG_ISET_RO
3507 #define R_DMA_CH3_STATUS__SET_VAL REG_SET_VAL_RO
3508 #define R_DMA_CH3_STATUS__EQL REG_EQL_RO
3509 #define R_DMA_CH3_STATUS__IEQL REG_IEQL_RO
3510 #define R_DMA_CH3_STATUS__RD REG_RD_RO
3511 #define R_DMA_CH3_STATUS__IRD REG_IRD_RO
3512 #define R_DMA_CH3_STATUS__WR REG_WR_RO
3513 #define R_DMA_CH3_STATUS__IWR REG_IWR_RO
3514
3515 #define R_DMA_CH3_STATUS__READ(addr) \
3516 (*(addr))
3517
3518 #define R_DMA_CH3_STATUS__avail__avail__MASK 0x0000007fU
3519
3520 #define R_DMA_CH3_STATUS__avail__MAX 0x7f
3521
3522 #define R_DMA_CH3_STATUS__avail__MIN 0
3523
3524 #define R_DMA_CH3_STATUS__avail__BITNR 0
3525
3526 #define R_DMA_CH3_STATUS__avail__avail__VAL REG_VAL_VAL
3527
3528
3529 #endif
3530
3531 /*
3532 * R_DMA_CH4_BUF
3533 * - type: RW
3534 * - addr: 0xb0000148
3535 * - group: DMA registers
3536 */
3537
3538 #if USE_GROUP__DMA_registers
3539
3540 #define R_DMA_CH4_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000148)
3541 #define R_DMA_CH4_BUF__SVAL REG_SVAL_SHADOW
3542 #define R_DMA_CH4_BUF__SVAL_I REG_SVAL_I_SHADOW
3543 #define R_DMA_CH4_BUF__TYPECAST REG_TYPECAST_UDWORD
3544 #define R_DMA_CH4_BUF__TYPE (REG_UDWORD)
3545 #define R_DMA_CH4_BUF__GET REG_GET_RW
3546 #define R_DMA_CH4_BUF__IGET REG_IGET_RW
3547 #define R_DMA_CH4_BUF__SET REG_SET_RW
3548 #define R_DMA_CH4_BUF__ISET REG_ISET_RW
3549 #define R_DMA_CH4_BUF__SET_VAL REG_SET_VAL_RW
3550 #define R_DMA_CH4_BUF__EQL REG_EQL_RW
3551 #define R_DMA_CH4_BUF__IEQL REG_IEQL_RW
3552 #define R_DMA_CH4_BUF__RD REG_RD_RW
3553 #define R_DMA_CH4_BUF__IRD REG_IRD_RW
3554 #define R_DMA_CH4_BUF__WR REG_WR_RW
3555 #define R_DMA_CH4_BUF__IWR REG_IWR_RW
3556
3557 #define R_DMA_CH4_BUF__WRITE(addr,value) \
3558 (*(addr) = (value))
3559 #define R_DMA_CH4_BUF__READ(addr) \
3560 (*(addr))
3561
3562 #define R_DMA_CH4_BUF__buf__buf__MASK 0xffffffffU
3563
3564 #define R_DMA_CH4_BUF__buf__MAX 0xffffffff
3565
3566 #define R_DMA_CH4_BUF__buf__MIN 0
3567
3568 #define R_DMA_CH4_BUF__buf__BITNR 0
3569
3570 #define R_DMA_CH4_BUF__buf__buf__VAL REG_VAL_VAL
3571
3572
3573 #endif
3574
3575 /*
3576 * R_DMA_CH4_CLR_INTR
3577 * - type: WO
3578 * - addr: 0xb00001e1
3579 * - group: DMA registers
3580 */
3581
3582 #if USE_GROUP__DMA_registers
3583
3584 #define R_DMA_CH4_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e1)
3585
3586 #ifndef REG_NO_SHADOW
3587 #define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH4_CLR_INTR + 0))
3588 #define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH4_CLR_INTR + 0))
3589 #else /* REG_NO_SHADOW */
3590 #define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
3591 #define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
3592 #endif /* REG_NO_SHADOW */
3593
3594 #define R_DMA_CH4_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
3595 #define R_DMA_CH4_CLR_INTR__SVAL REG_SVAL_ZERO
3596 #define R_DMA_CH4_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
3597 #define R_DMA_CH4_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
3598 #define R_DMA_CH4_CLR_INTR__TYPE (REG_BYTE)
3599 #define R_DMA_CH4_CLR_INTR__GET REG_GET_WO
3600 #define R_DMA_CH4_CLR_INTR__IGET REG_IGET_WO
3601 #define R_DMA_CH4_CLR_INTR__SET REG_SET_WO
3602 #define R_DMA_CH4_CLR_INTR__ISET REG_ISET_WO
3603 #define R_DMA_CH4_CLR_INTR__SET_VAL REG_SET_VAL_WO
3604 #define R_DMA_CH4_CLR_INTR__EQL REG_EQL_WO
3605 #define R_DMA_CH4_CLR_INTR__IEQL REG_IEQL_WO
3606 #define R_DMA_CH4_CLR_INTR__RD REG_RD_WO
3607 #define R_DMA_CH4_CLR_INTR__IRD REG_IRD_WO
3608 #define R_DMA_CH4_CLR_INTR__WR REG_WR_WO
3609 #define R_DMA_CH4_CLR_INTR__IWR REG_IWR_WO
3610
3611 #define R_DMA_CH4_CLR_INTR__WRITE(addr,value) \
3612 (*(addr) = (value))
3613
3614 #define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
3615 #define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
3616
3617 #define R_DMA_CH4_CLR_INTR__clr_eop__MAX 0x1
3618 #define R_DMA_CH4_CLR_INTR__clr_descr__MAX 0x1
3619
3620 #define R_DMA_CH4_CLR_INTR__clr_eop__MIN 0
3621 #define R_DMA_CH4_CLR_INTR__clr_descr__MIN 0
3622
3623 #define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
3624 #define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
3625
3626 #define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
3627 #define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
3628
3629 #define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__do 1
3630 #define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__dont 0
3631 #define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__do 1
3632 #define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__dont 0
3633
3634 #endif
3635
3636 /*
3637 * R_DMA_CH4_CMD
3638 * - type: RW
3639 * - addr: 0xb00001e0
3640 * - group: DMA registers
3641 */
3642
3643 #if USE_GROUP__DMA_registers
3644
3645 #define R_DMA_CH4_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e0)
3646 #define R_DMA_CH4_CMD__SVAL REG_SVAL_SHADOW
3647 #define R_DMA_CH4_CMD__SVAL_I REG_SVAL_I_SHADOW
3648 #define R_DMA_CH4_CMD__TYPECAST REG_TYPECAST_BYTE
3649 #define R_DMA_CH4_CMD__TYPE (REG_BYTE)
3650 #define R_DMA_CH4_CMD__GET REG_GET_RW
3651 #define R_DMA_CH4_CMD__IGET REG_IGET_RW
3652 #define R_DMA_CH4_CMD__SET REG_SET_RW
3653 #define R_DMA_CH4_CMD__ISET REG_ISET_RW
3654 #define R_DMA_CH4_CMD__SET_VAL REG_SET_VAL_RW
3655 #define R_DMA_CH4_CMD__EQL REG_EQL_RW
3656 #define R_DMA_CH4_CMD__IEQL REG_IEQL_RW
3657 #define R_DMA_CH4_CMD__RD REG_RD_RW
3658 #define R_DMA_CH4_CMD__IRD REG_IRD_RW
3659 #define R_DMA_CH4_CMD__WR REG_WR_RW
3660 #define R_DMA_CH4_CMD__IWR REG_IWR_RW
3661
3662 #define R_DMA_CH4_CMD__WRITE(addr,value) \
3663 (*(addr) = (value))
3664 #define R_DMA_CH4_CMD__READ(addr) \
3665 (*(addr))
3666
3667 #define R_DMA_CH4_CMD__cmd__cmd__MASK 0x00000007U
3668
3669 #define R_DMA_CH4_CMD__cmd__MAX 0x7
3670
3671 #define R_DMA_CH4_CMD__cmd__MIN 0
3672
3673 #define R_DMA_CH4_CMD__cmd__BITNR 0
3674
3675 #define R_DMA_CH4_CMD__cmd__cmd__VAL REG_VAL_ENUM
3676
3677 #define R_DMA_CH4_CMD__cmd__cmd__continue 3
3678 #define R_DMA_CH4_CMD__cmd__cmd__hold 0
3679 #define R_DMA_CH4_CMD__cmd__cmd__reset 4
3680 #define R_DMA_CH4_CMD__cmd__cmd__restart 3
3681 #define R_DMA_CH4_CMD__cmd__cmd__start 1
3682
3683 #endif
3684
3685 /*
3686 * R_DMA_CH4_DESCR
3687 * - type: RW
3688 * - addr: 0xb000014c
3689 * - group: DMA registers
3690 */
3691
3692 #if USE_GROUP__DMA_registers
3693
3694 #define R_DMA_CH4_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000014c)
3695 #define R_DMA_CH4_DESCR__SVAL REG_SVAL_SHADOW
3696 #define R_DMA_CH4_DESCR__SVAL_I REG_SVAL_I_SHADOW
3697 #define R_DMA_CH4_DESCR__TYPECAST REG_TYPECAST_UDWORD
3698 #define R_DMA_CH4_DESCR__TYPE (REG_UDWORD)
3699 #define R_DMA_CH4_DESCR__GET REG_GET_RW
3700 #define R_DMA_CH4_DESCR__IGET REG_IGET_RW
3701 #define R_DMA_CH4_DESCR__SET REG_SET_RW
3702 #define R_DMA_CH4_DESCR__ISET REG_ISET_RW
3703 #define R_DMA_CH4_DESCR__SET_VAL REG_SET_VAL_RW
3704 #define R_DMA_CH4_DESCR__EQL REG_EQL_RW
3705 #define R_DMA_CH4_DESCR__IEQL REG_IEQL_RW
3706 #define R_DMA_CH4_DESCR__RD REG_RD_RW
3707 #define R_DMA_CH4_DESCR__IRD REG_IRD_RW
3708 #define R_DMA_CH4_DESCR__WR REG_WR_RW
3709 #define R_DMA_CH4_DESCR__IWR REG_IWR_RW
3710
3711 #define R_DMA_CH4_DESCR__WRITE(addr,value) \
3712 (*(addr) = (value))
3713 #define R_DMA_CH4_DESCR__READ(addr) \
3714 (*(addr))
3715
3716 #define R_DMA_CH4_DESCR__descr__descr__MASK 0xffffffffU
3717
3718 #define R_DMA_CH4_DESCR__descr__MAX 0xffffffff
3719
3720 #define R_DMA_CH4_DESCR__descr__MIN 0
3721
3722 #define R_DMA_CH4_DESCR__descr__BITNR 0
3723
3724 #define R_DMA_CH4_DESCR__descr__descr__VAL REG_VAL_VAL
3725
3726
3727 #endif
3728
3729 /*
3730 * R_DMA_CH4_FIRST
3731 * - type: RW
3732 * - addr: 0xb00001b0
3733 * - group: DMA registers
3734 */
3735
3736 #if USE_GROUP__DMA_registers
3737
3738 #define R_DMA_CH4_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b0)
3739 #define R_DMA_CH4_FIRST__SVAL REG_SVAL_SHADOW
3740 #define R_DMA_CH4_FIRST__SVAL_I REG_SVAL_I_SHADOW
3741 #define R_DMA_CH4_FIRST__TYPECAST REG_TYPECAST_UDWORD
3742 #define R_DMA_CH4_FIRST__TYPE (REG_UDWORD)
3743 #define R_DMA_CH4_FIRST__GET REG_GET_RW
3744 #define R_DMA_CH4_FIRST__IGET REG_IGET_RW
3745 #define R_DMA_CH4_FIRST__SET REG_SET_RW
3746 #define R_DMA_CH4_FIRST__ISET REG_ISET_RW
3747 #define R_DMA_CH4_FIRST__SET_VAL REG_SET_VAL_RW
3748 #define R_DMA_CH4_FIRST__EQL REG_EQL_RW
3749 #define R_DMA_CH4_FIRST__IEQL REG_IEQL_RW
3750 #define R_DMA_CH4_FIRST__RD REG_RD_RW
3751 #define R_DMA_CH4_FIRST__IRD REG_IRD_RW
3752 #define R_DMA_CH4_FIRST__WR REG_WR_RW
3753 #define R_DMA_CH4_FIRST__IWR REG_IWR_RW
3754
3755 #define R_DMA_CH4_FIRST__WRITE(addr,value) \
3756 (*(addr) = (value))
3757 #define R_DMA_CH4_FIRST__READ(addr) \
3758 (*(addr))
3759
3760 #define R_DMA_CH4_FIRST__first__first__MASK 0xffffffffU
3761
3762 #define R_DMA_CH4_FIRST__first__MAX 0xffffffff
3763
3764 #define R_DMA_CH4_FIRST__first__MIN 0
3765
3766 #define R_DMA_CH4_FIRST__first__BITNR 0
3767
3768 #define R_DMA_CH4_FIRST__first__first__VAL REG_VAL_VAL
3769
3770
3771 #endif
3772
3773 /*
3774 * R_DMA_CH4_HWSW
3775 * - type: RW
3776 * - addr: 0xb0000140
3777 * - group: DMA registers
3778 */
3779
3780 #if USE_GROUP__DMA_registers
3781
3782 #define R_DMA_CH4_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000140)
3783 #define R_DMA_CH4_HWSW__SVAL REG_SVAL_SHADOW
3784 #define R_DMA_CH4_HWSW__SVAL_I REG_SVAL_I_SHADOW
3785 #define R_DMA_CH4_HWSW__TYPECAST REG_TYPECAST_UDWORD
3786 #define R_DMA_CH4_HWSW__TYPE (REG_UDWORD)
3787 #define R_DMA_CH4_HWSW__GET REG_GET_RW
3788 #define R_DMA_CH4_HWSW__IGET REG_IGET_RW
3789 #define R_DMA_CH4_HWSW__SET REG_SET_RW
3790 #define R_DMA_CH4_HWSW__ISET REG_ISET_RW
3791 #define R_DMA_CH4_HWSW__SET_VAL REG_SET_VAL_RW
3792 #define R_DMA_CH4_HWSW__EQL REG_EQL_RW
3793 #define R_DMA_CH4_HWSW__IEQL REG_IEQL_RW
3794 #define R_DMA_CH4_HWSW__RD REG_RD_RW
3795 #define R_DMA_CH4_HWSW__IRD REG_IRD_RW
3796 #define R_DMA_CH4_HWSW__WR REG_WR_RW
3797 #define R_DMA_CH4_HWSW__IWR REG_IWR_RW
3798
3799 #define R_DMA_CH4_HWSW__WRITE(addr,value) \
3800 (*(addr) = (value))
3801 #define R_DMA_CH4_HWSW__READ(addr) \
3802 (*(addr))
3803
3804 #define R_DMA_CH4_HWSW__hw__hw__MASK 0xffff0000U
3805 #define R_DMA_CH4_HWSW__sw__sw__MASK 0x0000ffffU
3806
3807 #define R_DMA_CH4_HWSW__hw__MAX 0xffff
3808 #define R_DMA_CH4_HWSW__sw__MAX 0xffff
3809
3810 #define R_DMA_CH4_HWSW__hw__MIN 0
3811 #define R_DMA_CH4_HWSW__sw__MIN 0
3812
3813 #define R_DMA_CH4_HWSW__hw__BITNR 16
3814 #define R_DMA_CH4_HWSW__sw__BITNR 0
3815
3816 #define R_DMA_CH4_HWSW__hw__hw__VAL REG_VAL_VAL
3817 #define R_DMA_CH4_HWSW__sw__sw__VAL REG_VAL_VAL
3818
3819
3820 #endif
3821
3822 /*
3823 * R_DMA_CH4_NEXT
3824 * - type: RW
3825 * - addr: 0xb0000144
3826 * - group: DMA registers
3827 */
3828
3829 #if USE_GROUP__DMA_registers
3830
3831 #define R_DMA_CH4_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000144)
3832 #define R_DMA_CH4_NEXT__SVAL REG_SVAL_SHADOW
3833 #define R_DMA_CH4_NEXT__SVAL_I REG_SVAL_I_SHADOW
3834 #define R_DMA_CH4_NEXT__TYPECAST REG_TYPECAST_UDWORD
3835 #define R_DMA_CH4_NEXT__TYPE (REG_UDWORD)
3836 #define R_DMA_CH4_NEXT__GET REG_GET_RW
3837 #define R_DMA_CH4_NEXT__IGET REG_IGET_RW
3838 #define R_DMA_CH4_NEXT__SET REG_SET_RW
3839 #define R_DMA_CH4_NEXT__ISET REG_ISET_RW
3840 #define R_DMA_CH4_NEXT__SET_VAL REG_SET_VAL_RW
3841 #define R_DMA_CH4_NEXT__EQL REG_EQL_RW
3842 #define R_DMA_CH4_NEXT__IEQL REG_IEQL_RW
3843 #define R_DMA_CH4_NEXT__RD REG_RD_RW
3844 #define R_DMA_CH4_NEXT__IRD REG_IRD_RW
3845 #define R_DMA_CH4_NEXT__WR REG_WR_RW
3846 #define R_DMA_CH4_NEXT__IWR REG_IWR_RW
3847
3848 #define R_DMA_CH4_NEXT__WRITE(addr,value) \
3849 (*(addr) = (value))
3850 #define R_DMA_CH4_NEXT__READ(addr) \
3851 (*(addr))
3852
3853 #define R_DMA_CH4_NEXT__next__next__MASK 0xffffffffU
3854
3855 #define R_DMA_CH4_NEXT__next__MAX 0xffffffff
3856
3857 #define R_DMA_CH4_NEXT__next__MIN 0
3858
3859 #define R_DMA_CH4_NEXT__next__BITNR 0
3860
3861 #define R_DMA_CH4_NEXT__next__next__VAL REG_VAL_VAL
3862
3863
3864 #endif
3865
3866 /*
3867 * R_DMA_CH4_STATUS
3868 * - type: RO
3869 * - addr: 0xb00001e2
3870 * - group: DMA registers
3871 */
3872
3873 #if USE_GROUP__DMA_registers
3874
3875 #define R_DMA_CH4_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e2)
3876 #define R_DMA_CH4_STATUS__SVAL REG_SVAL_SHADOW
3877 #define R_DMA_CH4_STATUS__SVAL_I REG_SVAL_I_SHADOW
3878 #define R_DMA_CH4_STATUS__TYPECAST REG_TYPECAST_BYTE
3879 #define R_DMA_CH4_STATUS__TYPE (REG_BYTE)
3880 #define R_DMA_CH4_STATUS__GET REG_GET_RO
3881 #define R_DMA_CH4_STATUS__IGET REG_IGET_RO
3882 #define R_DMA_CH4_STATUS__SET REG_SET_RO
3883 #define R_DMA_CH4_STATUS__ISET REG_ISET_RO
3884 #define R_DMA_CH4_STATUS__SET_VAL REG_SET_VAL_RO
3885 #define R_DMA_CH4_STATUS__EQL REG_EQL_RO
3886 #define R_DMA_CH4_STATUS__IEQL REG_IEQL_RO
3887 #define R_DMA_CH4_STATUS__RD REG_RD_RO
3888 #define R_DMA_CH4_STATUS__IRD REG_IRD_RO
3889 #define R_DMA_CH4_STATUS__WR REG_WR_RO
3890 #define R_DMA_CH4_STATUS__IWR REG_IWR_RO
3891
3892 #define R_DMA_CH4_STATUS__READ(addr) \
3893 (*(addr))
3894
3895 #define R_DMA_CH4_STATUS__avail__avail__MASK 0x0000007fU
3896
3897 #define R_DMA_CH4_STATUS__avail__MAX 0x7f
3898
3899 #define R_DMA_CH4_STATUS__avail__MIN 0
3900
3901 #define R_DMA_CH4_STATUS__avail__BITNR 0
3902
3903 #define R_DMA_CH4_STATUS__avail__avail__VAL REG_VAL_VAL
3904
3905
3906 #endif
3907
3908 /*
3909 * R_DMA_CH5_BUF
3910 * - type: RW
3911 * - addr: 0xb0000158
3912 * - group: DMA registers
3913 */
3914
3915 #if USE_GROUP__DMA_registers
3916
3917 #define R_DMA_CH5_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000158)
3918 #define R_DMA_CH5_BUF__SVAL REG_SVAL_SHADOW
3919 #define R_DMA_CH5_BUF__SVAL_I REG_SVAL_I_SHADOW
3920 #define R_DMA_CH5_BUF__TYPECAST REG_TYPECAST_UDWORD
3921 #define R_DMA_CH5_BUF__TYPE (REG_UDWORD)
3922 #define R_DMA_CH5_BUF__GET REG_GET_RW
3923 #define R_DMA_CH5_BUF__IGET REG_IGET_RW
3924 #define R_DMA_CH5_BUF__SET REG_SET_RW
3925 #define R_DMA_CH5_BUF__ISET REG_ISET_RW
3926 #define R_DMA_CH5_BUF__SET_VAL REG_SET_VAL_RW
3927 #define R_DMA_CH5_BUF__EQL REG_EQL_RW
3928 #define R_DMA_CH5_BUF__IEQL REG_IEQL_RW
3929 #define R_DMA_CH5_BUF__RD REG_RD_RW
3930 #define R_DMA_CH5_BUF__IRD REG_IRD_RW
3931 #define R_DMA_CH5_BUF__WR REG_WR_RW
3932 #define R_DMA_CH5_BUF__IWR REG_IWR_RW
3933
3934 #define R_DMA_CH5_BUF__WRITE(addr,value) \
3935 (*(addr) = (value))
3936 #define R_DMA_CH5_BUF__READ(addr) \
3937 (*(addr))
3938
3939 #define R_DMA_CH5_BUF__buf__buf__MASK 0xffffffffU
3940
3941 #define R_DMA_CH5_BUF__buf__MAX 0xffffffff
3942
3943 #define R_DMA_CH5_BUF__buf__MIN 0
3944
3945 #define R_DMA_CH5_BUF__buf__BITNR 0
3946
3947 #define R_DMA_CH5_BUF__buf__buf__VAL REG_VAL_VAL
3948
3949
3950 #endif
3951
3952 /*
3953 * R_DMA_CH5_CLR_INTR
3954 * - type: WO
3955 * - addr: 0xb00001e5
3956 * - group: DMA registers
3957 */
3958
3959 #if USE_GROUP__DMA_registers
3960
3961 #define R_DMA_CH5_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e5)
3962
3963 #ifndef REG_NO_SHADOW
3964 #define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH5_CLR_INTR + 0))
3965 #define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH5_CLR_INTR + 0))
3966 #else /* REG_NO_SHADOW */
3967 #define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
3968 #define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
3969 #endif /* REG_NO_SHADOW */
3970
3971 #define R_DMA_CH5_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
3972 #define R_DMA_CH5_CLR_INTR__SVAL REG_SVAL_ZERO
3973 #define R_DMA_CH5_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
3974 #define R_DMA_CH5_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
3975 #define R_DMA_CH5_CLR_INTR__TYPE (REG_BYTE)
3976 #define R_DMA_CH5_CLR_INTR__GET REG_GET_WO
3977 #define R_DMA_CH5_CLR_INTR__IGET REG_IGET_WO
3978 #define R_DMA_CH5_CLR_INTR__SET REG_SET_WO
3979 #define R_DMA_CH5_CLR_INTR__ISET REG_ISET_WO
3980 #define R_DMA_CH5_CLR_INTR__SET_VAL REG_SET_VAL_WO
3981 #define R_DMA_CH5_CLR_INTR__EQL REG_EQL_WO
3982 #define R_DMA_CH5_CLR_INTR__IEQL REG_IEQL_WO
3983 #define R_DMA_CH5_CLR_INTR__RD REG_RD_WO
3984 #define R_DMA_CH5_CLR_INTR__IRD REG_IRD_WO
3985 #define R_DMA_CH5_CLR_INTR__WR REG_WR_WO
3986 #define R_DMA_CH5_CLR_INTR__IWR REG_IWR_WO
3987
3988 #define R_DMA_CH5_CLR_INTR__WRITE(addr,value) \
3989 (*(addr) = (value))
3990
3991 #define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
3992 #define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
3993
3994 #define R_DMA_CH5_CLR_INTR__clr_eop__MAX 0x1
3995 #define R_DMA_CH5_CLR_INTR__clr_descr__MAX 0x1
3996
3997 #define R_DMA_CH5_CLR_INTR__clr_eop__MIN 0
3998 #define R_DMA_CH5_CLR_INTR__clr_descr__MIN 0
3999
4000 #define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
4001 #define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
4002
4003 #define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
4004 #define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
4005
4006 #define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__do 1
4007 #define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__dont 0
4008 #define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__do 1
4009 #define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__dont 0
4010
4011 #endif
4012
4013 /*
4014 * R_DMA_CH5_CMD
4015 * - type: RW
4016 * - addr: 0xb00001e4
4017 * - group: DMA registers
4018 */
4019
4020 #if USE_GROUP__DMA_registers
4021
4022 #define R_DMA_CH5_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e4)
4023 #define R_DMA_CH5_CMD__SVAL REG_SVAL_SHADOW
4024 #define R_DMA_CH5_CMD__SVAL_I REG_SVAL_I_SHADOW
4025 #define R_DMA_CH5_CMD__TYPECAST REG_TYPECAST_BYTE
4026 #define R_DMA_CH5_CMD__TYPE (REG_BYTE)
4027 #define R_DMA_CH5_CMD__GET REG_GET_RW
4028 #define R_DMA_CH5_CMD__IGET REG_IGET_RW
4029 #define R_DMA_CH5_CMD__SET REG_SET_RW
4030 #define R_DMA_CH5_CMD__ISET REG_ISET_RW
4031 #define R_DMA_CH5_CMD__SET_VAL REG_SET_VAL_RW
4032 #define R_DMA_CH5_CMD__EQL REG_EQL_RW
4033 #define R_DMA_CH5_CMD__IEQL REG_IEQL_RW
4034 #define R_DMA_CH5_CMD__RD REG_RD_RW
4035 #define R_DMA_CH5_CMD__IRD REG_IRD_RW
4036 #define R_DMA_CH5_CMD__WR REG_WR_RW
4037 #define R_DMA_CH5_CMD__IWR REG_IWR_RW
4038
4039 #define R_DMA_CH5_CMD__WRITE(addr,value) \
4040 (*(addr) = (value))
4041 #define R_DMA_CH5_CMD__READ(addr) \
4042 (*(addr))
4043
4044 #define R_DMA_CH5_CMD__cmd__cmd__MASK 0x00000007U
4045
4046 #define R_DMA_CH5_CMD__cmd__MAX 0x7
4047
4048 #define R_DMA_CH5_CMD__cmd__MIN 0
4049
4050 #define R_DMA_CH5_CMD__cmd__BITNR 0
4051
4052 #define R_DMA_CH5_CMD__cmd__cmd__VAL REG_VAL_ENUM
4053
4054 #define R_DMA_CH5_CMD__cmd__cmd__continue 3
4055 #define R_DMA_CH5_CMD__cmd__cmd__hold 0
4056 #define R_DMA_CH5_CMD__cmd__cmd__reset 4
4057 #define R_DMA_CH5_CMD__cmd__cmd__restart 3
4058 #define R_DMA_CH5_CMD__cmd__cmd__start 1
4059
4060 #endif
4061
4062 /*
4063 * R_DMA_CH5_DESCR
4064 * - type: RW
4065 * - addr: 0xb000015c
4066 * - group: DMA registers
4067 */
4068
4069 #if USE_GROUP__DMA_registers
4070
4071 #define R_DMA_CH5_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000015c)
4072 #define R_DMA_CH5_DESCR__SVAL REG_SVAL_SHADOW
4073 #define R_DMA_CH5_DESCR__SVAL_I REG_SVAL_I_SHADOW
4074 #define R_DMA_CH5_DESCR__TYPECAST REG_TYPECAST_UDWORD
4075 #define R_DMA_CH5_DESCR__TYPE (REG_UDWORD)
4076 #define R_DMA_CH5_DESCR__GET REG_GET_RW
4077 #define R_DMA_CH5_DESCR__IGET REG_IGET_RW
4078 #define R_DMA_CH5_DESCR__SET REG_SET_RW
4079 #define R_DMA_CH5_DESCR__ISET REG_ISET_RW
4080 #define R_DMA_CH5_DESCR__SET_VAL REG_SET_VAL_RW
4081 #define R_DMA_CH5_DESCR__EQL REG_EQL_RW
4082 #define R_DMA_CH5_DESCR__IEQL REG_IEQL_RW
4083 #define R_DMA_CH5_DESCR__RD REG_RD_RW
4084 #define R_DMA_CH5_DESCR__IRD REG_IRD_RW
4085 #define R_DMA_CH5_DESCR__WR REG_WR_RW
4086 #define R_DMA_CH5_DESCR__IWR REG_IWR_RW
4087
4088 #define R_DMA_CH5_DESCR__WRITE(addr,value) \
4089 (*(addr) = (value))
4090 #define R_DMA_CH5_DESCR__READ(addr) \
4091 (*(addr))
4092
4093 #define R_DMA_CH5_DESCR__descr__descr__MASK 0xffffffffU
4094
4095 #define R_DMA_CH5_DESCR__descr__MAX 0xffffffff
4096
4097 #define R_DMA_CH5_DESCR__descr__MIN 0
4098
4099 #define R_DMA_CH5_DESCR__descr__BITNR 0
4100
4101 #define R_DMA_CH5_DESCR__descr__descr__VAL REG_VAL_VAL
4102
4103
4104 #endif
4105
4106 /*
4107 * R_DMA_CH5_FIRST
4108 * - type: RW
4109 * - addr: 0xb00001b4
4110 * - group: DMA registers
4111 */
4112
4113 #if USE_GROUP__DMA_registers
4114
4115 #define R_DMA_CH5_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b4)
4116 #define R_DMA_CH5_FIRST__SVAL REG_SVAL_SHADOW
4117 #define R_DMA_CH5_FIRST__SVAL_I REG_SVAL_I_SHADOW
4118 #define R_DMA_CH5_FIRST__TYPECAST REG_TYPECAST_UDWORD
4119 #define R_DMA_CH5_FIRST__TYPE (REG_UDWORD)
4120 #define R_DMA_CH5_FIRST__GET REG_GET_RW
4121 #define R_DMA_CH5_FIRST__IGET REG_IGET_RW
4122 #define R_DMA_CH5_FIRST__SET REG_SET_RW
4123 #define R_DMA_CH5_FIRST__ISET REG_ISET_RW
4124 #define R_DMA_CH5_FIRST__SET_VAL REG_SET_VAL_RW
4125 #define R_DMA_CH5_FIRST__EQL REG_EQL_RW
4126 #define R_DMA_CH5_FIRST__IEQL REG_IEQL_RW
4127 #define R_DMA_CH5_FIRST__RD REG_RD_RW
4128 #define R_DMA_CH5_FIRST__IRD REG_IRD_RW
4129 #define R_DMA_CH5_FIRST__WR REG_WR_RW
4130 #define R_DMA_CH5_FIRST__IWR REG_IWR_RW
4131
4132 #define R_DMA_CH5_FIRST__WRITE(addr,value) \
4133 (*(addr) = (value))
4134 #define R_DMA_CH5_FIRST__READ(addr) \
4135 (*(addr))
4136
4137 #define R_DMA_CH5_FIRST__first__first__MASK 0xffffffffU
4138
4139 #define R_DMA_CH5_FIRST__first__MAX 0xffffffff
4140
4141 #define R_DMA_CH5_FIRST__first__MIN 0
4142
4143 #define R_DMA_CH5_FIRST__first__BITNR 0
4144
4145 #define R_DMA_CH5_FIRST__first__first__VAL REG_VAL_VAL
4146
4147
4148 #endif
4149
4150 /*
4151 * R_DMA_CH5_HWSW
4152 * - type: RW
4153 * - addr: 0xb0000150
4154 * - group: DMA registers
4155 */
4156
4157 #if USE_GROUP__DMA_registers
4158
4159 #define R_DMA_CH5_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000150)
4160 #define R_DMA_CH5_HWSW__SVAL REG_SVAL_SHADOW
4161 #define R_DMA_CH5_HWSW__SVAL_I REG_SVAL_I_SHADOW
4162 #define R_DMA_CH5_HWSW__TYPECAST REG_TYPECAST_UDWORD
4163 #define R_DMA_CH5_HWSW__TYPE (REG_UDWORD)
4164 #define R_DMA_CH5_HWSW__GET REG_GET_RW
4165 #define R_DMA_CH5_HWSW__IGET REG_IGET_RW
4166 #define R_DMA_CH5_HWSW__SET REG_SET_RW
4167 #define R_DMA_CH5_HWSW__ISET REG_ISET_RW
4168 #define R_DMA_CH5_HWSW__SET_VAL REG_SET_VAL_RW
4169 #define R_DMA_CH5_HWSW__EQL REG_EQL_RW
4170 #define R_DMA_CH5_HWSW__IEQL REG_IEQL_RW
4171 #define R_DMA_CH5_HWSW__RD REG_RD_RW
4172 #define R_DMA_CH5_HWSW__IRD REG_IRD_RW
4173 #define R_DMA_CH5_HWSW__WR REG_WR_RW
4174 #define R_DMA_CH5_HWSW__IWR REG_IWR_RW
4175
4176 #define R_DMA_CH5_HWSW__WRITE(addr,value) \
4177 (*(addr) = (value))
4178 #define R_DMA_CH5_HWSW__READ(addr) \
4179 (*(addr))
4180
4181 #define R_DMA_CH5_HWSW__hw__hw__MASK 0xffff0000U
4182 #define R_DMA_CH5_HWSW__sw__sw__MASK 0x0000ffffU
4183
4184 #define R_DMA_CH5_HWSW__hw__MAX 0xffff
4185 #define R_DMA_CH5_HWSW__sw__MAX 0xffff
4186
4187 #define R_DMA_CH5_HWSW__hw__MIN 0
4188 #define R_DMA_CH5_HWSW__sw__MIN 0
4189
4190 #define R_DMA_CH5_HWSW__hw__BITNR 16
4191 #define R_DMA_CH5_HWSW__sw__BITNR 0
4192
4193 #define R_DMA_CH5_HWSW__hw__hw__VAL REG_VAL_VAL
4194 #define R_DMA_CH5_HWSW__sw__sw__VAL REG_VAL_VAL
4195
4196
4197 #endif
4198
4199 /*
4200 * R_DMA_CH5_NEXT
4201 * - type: RW
4202 * - addr: 0xb0000154
4203 * - group: DMA registers
4204 */
4205
4206 #if USE_GROUP__DMA_registers
4207
4208 #define R_DMA_CH5_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000154)
4209 #define R_DMA_CH5_NEXT__SVAL REG_SVAL_SHADOW
4210 #define R_DMA_CH5_NEXT__SVAL_I REG_SVAL_I_SHADOW
4211 #define R_DMA_CH5_NEXT__TYPECAST REG_TYPECAST_UDWORD
4212 #define R_DMA_CH5_NEXT__TYPE (REG_UDWORD)
4213 #define R_DMA_CH5_NEXT__GET REG_GET_RW
4214 #define R_DMA_CH5_NEXT__IGET REG_IGET_RW
4215 #define R_DMA_CH5_NEXT__SET REG_SET_RW
4216 #define R_DMA_CH5_NEXT__ISET REG_ISET_RW
4217 #define R_DMA_CH5_NEXT__SET_VAL REG_SET_VAL_RW
4218 #define R_DMA_CH5_NEXT__EQL REG_EQL_RW
4219 #define R_DMA_CH5_NEXT__IEQL REG_IEQL_RW
4220 #define R_DMA_CH5_NEXT__RD REG_RD_RW
4221 #define R_DMA_CH5_NEXT__IRD REG_IRD_RW
4222 #define R_DMA_CH5_NEXT__WR REG_WR_RW
4223 #define R_DMA_CH5_NEXT__IWR REG_IWR_RW
4224
4225 #define R_DMA_CH5_NEXT__WRITE(addr,value) \
4226 (*(addr) = (value))
4227 #define R_DMA_CH5_NEXT__READ(addr) \
4228 (*(addr))
4229
4230 #define R_DMA_CH5_NEXT__next__next__MASK 0xffffffffU
4231
4232 #define R_DMA_CH5_NEXT__next__MAX 0xffffffff
4233
4234 #define R_DMA_CH5_NEXT__next__MIN 0
4235
4236 #define R_DMA_CH5_NEXT__next__BITNR 0
4237
4238 #define R_DMA_CH5_NEXT__next__next__VAL REG_VAL_VAL
4239
4240
4241 #endif
4242
4243 /*
4244 * R_DMA_CH5_STATUS
4245 * - type: RO
4246 * - addr: 0xb00001e6
4247 * - group: DMA registers
4248 */
4249
4250 #if USE_GROUP__DMA_registers
4251
4252 #define R_DMA_CH5_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e6)
4253 #define R_DMA_CH5_STATUS__SVAL REG_SVAL_SHADOW
4254 #define R_DMA_CH5_STATUS__SVAL_I REG_SVAL_I_SHADOW
4255 #define R_DMA_CH5_STATUS__TYPECAST REG_TYPECAST_BYTE
4256 #define R_DMA_CH5_STATUS__TYPE (REG_BYTE)
4257 #define R_DMA_CH5_STATUS__GET REG_GET_RO
4258 #define R_DMA_CH5_STATUS__IGET REG_IGET_RO
4259 #define R_DMA_CH5_STATUS__SET REG_SET_RO
4260 #define R_DMA_CH5_STATUS__ISET REG_ISET_RO
4261 #define R_DMA_CH5_STATUS__SET_VAL REG_SET_VAL_RO
4262 #define R_DMA_CH5_STATUS__EQL REG_EQL_RO
4263 #define R_DMA_CH5_STATUS__IEQL REG_IEQL_RO
4264 #define R_DMA_CH5_STATUS__RD REG_RD_RO
4265 #define R_DMA_CH5_STATUS__IRD REG_IRD_RO
4266 #define R_DMA_CH5_STATUS__WR REG_WR_RO
4267 #define R_DMA_CH5_STATUS__IWR REG_IWR_RO
4268
4269 #define R_DMA_CH5_STATUS__READ(addr) \
4270 (*(addr))
4271
4272 #define R_DMA_CH5_STATUS__avail__avail__MASK 0x0000007fU
4273
4274 #define R_DMA_CH5_STATUS__avail__MAX 0x7f
4275
4276 #define R_DMA_CH5_STATUS__avail__MIN 0
4277
4278 #define R_DMA_CH5_STATUS__avail__BITNR 0
4279
4280 #define R_DMA_CH5_STATUS__avail__avail__VAL REG_VAL_VAL
4281
4282
4283 #endif
4284
4285 /*
4286 * R_DMA_CH6_BUF
4287 * - type: RW
4288 * - addr: 0xb0000168
4289 * - group: DMA registers
4290 */
4291
4292 #if USE_GROUP__DMA_registers
4293
4294 #define R_DMA_CH6_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000168)
4295 #define R_DMA_CH6_BUF__SVAL REG_SVAL_SHADOW
4296 #define R_DMA_CH6_BUF__SVAL_I REG_SVAL_I_SHADOW
4297 #define R_DMA_CH6_BUF__TYPECAST REG_TYPECAST_UDWORD
4298 #define R_DMA_CH6_BUF__TYPE (REG_UDWORD)
4299 #define R_DMA_CH6_BUF__GET REG_GET_RW
4300 #define R_DMA_CH6_BUF__IGET REG_IGET_RW
4301 #define R_DMA_CH6_BUF__SET REG_SET_RW
4302 #define R_DMA_CH6_BUF__ISET REG_ISET_RW
4303 #define R_DMA_CH6_BUF__SET_VAL REG_SET_VAL_RW
4304 #define R_DMA_CH6_BUF__EQL REG_EQL_RW
4305 #define R_DMA_CH6_BUF__IEQL REG_IEQL_RW
4306 #define R_DMA_CH6_BUF__RD REG_RD_RW
4307 #define R_DMA_CH6_BUF__IRD REG_IRD_RW
4308 #define R_DMA_CH6_BUF__WR REG_WR_RW
4309 #define R_DMA_CH6_BUF__IWR REG_IWR_RW
4310
4311 #define R_DMA_CH6_BUF__WRITE(addr,value) \
4312 (*(addr) = (value))
4313 #define R_DMA_CH6_BUF__READ(addr) \
4314 (*(addr))
4315
4316 #define R_DMA_CH6_BUF__buf__buf__MASK 0xffffffffU
4317
4318 #define R_DMA_CH6_BUF__buf__MAX 0xffffffff
4319
4320 #define R_DMA_CH6_BUF__buf__MIN 0
4321
4322 #define R_DMA_CH6_BUF__buf__BITNR 0
4323
4324 #define R_DMA_CH6_BUF__buf__buf__VAL REG_VAL_VAL
4325
4326
4327 #endif
4328
4329 /*
4330 * R_DMA_CH6_CLR_INTR
4331 * - type: WO
4332 * - addr: 0xb00001e9
4333 * - group: DMA registers
4334 */
4335
4336 #if USE_GROUP__DMA_registers
4337
4338 #define R_DMA_CH6_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e9)
4339
4340 #ifndef REG_NO_SHADOW
4341 #define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH6_CLR_INTR + 0))
4342 #define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH6_CLR_INTR + 0))
4343 #else /* REG_NO_SHADOW */
4344 #define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
4345 #define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
4346 #endif /* REG_NO_SHADOW */
4347
4348 #define R_DMA_CH6_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
4349 #define R_DMA_CH6_CLR_INTR__SVAL REG_SVAL_ZERO
4350 #define R_DMA_CH6_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
4351 #define R_DMA_CH6_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
4352 #define R_DMA_CH6_CLR_INTR__TYPE (REG_BYTE)
4353 #define R_DMA_CH6_CLR_INTR__GET REG_GET_WO
4354 #define R_DMA_CH6_CLR_INTR__IGET REG_IGET_WO
4355 #define R_DMA_CH6_CLR_INTR__SET REG_SET_WO
4356 #define R_DMA_CH6_CLR_INTR__ISET REG_ISET_WO
4357 #define R_DMA_CH6_CLR_INTR__SET_VAL REG_SET_VAL_WO
4358 #define R_DMA_CH6_CLR_INTR__EQL REG_EQL_WO
4359 #define R_DMA_CH6_CLR_INTR__IEQL REG_IEQL_WO
4360 #define R_DMA_CH6_CLR_INTR__RD REG_RD_WO
4361 #define R_DMA_CH6_CLR_INTR__IRD REG_IRD_WO
4362 #define R_DMA_CH6_CLR_INTR__WR REG_WR_WO
4363 #define R_DMA_CH6_CLR_INTR__IWR REG_IWR_WO
4364
4365 #define R_DMA_CH6_CLR_INTR__WRITE(addr,value) \
4366 (*(addr) = (value))
4367
4368 #define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
4369 #define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
4370
4371 #define R_DMA_CH6_CLR_INTR__clr_eop__MAX 0x1
4372 #define R_DMA_CH6_CLR_INTR__clr_descr__MAX 0x1
4373
4374 #define R_DMA_CH6_CLR_INTR__clr_eop__MIN 0
4375 #define R_DMA_CH6_CLR_INTR__clr_descr__MIN 0
4376
4377 #define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
4378 #define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
4379
4380 #define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
4381 #define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
4382
4383 #define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__do 1
4384 #define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__dont 0
4385 #define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__do 1
4386 #define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__dont 0
4387
4388 #endif
4389
4390 /*
4391 * R_DMA_CH6_CMD
4392 * - type: RW
4393 * - addr: 0xb00001e8
4394 * - group: DMA registers
4395 */
4396
4397 #if USE_GROUP__DMA_registers
4398
4399 #define R_DMA_CH6_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e8)
4400 #define R_DMA_CH6_CMD__SVAL REG_SVAL_SHADOW
4401 #define R_DMA_CH6_CMD__SVAL_I REG_SVAL_I_SHADOW
4402 #define R_DMA_CH6_CMD__TYPECAST REG_TYPECAST_BYTE
4403 #define R_DMA_CH6_CMD__TYPE (REG_BYTE)
4404 #define R_DMA_CH6_CMD__GET REG_GET_RW
4405 #define R_DMA_CH6_CMD__IGET REG_IGET_RW
4406 #define R_DMA_CH6_CMD__SET REG_SET_RW
4407 #define R_DMA_CH6_CMD__ISET REG_ISET_RW
4408 #define R_DMA_CH6_CMD__SET_VAL REG_SET_VAL_RW
4409 #define R_DMA_CH6_CMD__EQL REG_EQL_RW
4410 #define R_DMA_CH6_CMD__IEQL REG_IEQL_RW
4411 #define R_DMA_CH6_CMD__RD REG_RD_RW
4412 #define R_DMA_CH6_CMD__IRD REG_IRD_RW
4413 #define R_DMA_CH6_CMD__WR REG_WR_RW
4414 #define R_DMA_CH6_CMD__IWR REG_IWR_RW
4415
4416 #define R_DMA_CH6_CMD__WRITE(addr,value) \
4417 (*(addr) = (value))
4418 #define R_DMA_CH6_CMD__READ(addr) \
4419 (*(addr))
4420
4421 #define R_DMA_CH6_CMD__cmd__cmd__MASK 0x00000007U
4422
4423 #define R_DMA_CH6_CMD__cmd__MAX 0x7
4424
4425 #define R_DMA_CH6_CMD__cmd__MIN 0
4426
4427 #define R_DMA_CH6_CMD__cmd__BITNR 0
4428
4429 #define R_DMA_CH6_CMD__cmd__cmd__VAL REG_VAL_ENUM
4430
4431 #define R_DMA_CH6_CMD__cmd__cmd__continue 3
4432 #define R_DMA_CH6_CMD__cmd__cmd__hold 0
4433 #define R_DMA_CH6_CMD__cmd__cmd__reset 4
4434 #define R_DMA_CH6_CMD__cmd__cmd__restart 3
4435 #define R_DMA_CH6_CMD__cmd__cmd__start 1
4436
4437 #endif
4438
4439 /*
4440 * R_DMA_CH6_DESCR
4441 * - type: RW
4442 * - addr: 0xb000016c
4443 * - group: DMA registers
4444 */
4445
4446 #if USE_GROUP__DMA_registers
4447
4448 #define R_DMA_CH6_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000016c)
4449 #define R_DMA_CH6_DESCR__SVAL REG_SVAL_SHADOW
4450 #define R_DMA_CH6_DESCR__SVAL_I REG_SVAL_I_SHADOW
4451 #define R_DMA_CH6_DESCR__TYPECAST REG_TYPECAST_UDWORD
4452 #define R_DMA_CH6_DESCR__TYPE (REG_UDWORD)
4453 #define R_DMA_CH6_DESCR__GET REG_GET_RW
4454 #define R_DMA_CH6_DESCR__IGET REG_IGET_RW
4455 #define R_DMA_CH6_DESCR__SET REG_SET_RW
4456 #define R_DMA_CH6_DESCR__ISET REG_ISET_RW
4457 #define R_DMA_CH6_DESCR__SET_VAL REG_SET_VAL_RW
4458 #define R_DMA_CH6_DESCR__EQL REG_EQL_RW
4459 #define R_DMA_CH6_DESCR__IEQL REG_IEQL_RW
4460 #define R_DMA_CH6_DESCR__RD REG_RD_RW
4461 #define R_DMA_CH6_DESCR__IRD REG_IRD_RW
4462 #define R_DMA_CH6_DESCR__WR REG_WR_RW
4463 #define R_DMA_CH6_DESCR__IWR REG_IWR_RW
4464
4465 #define R_DMA_CH6_DESCR__WRITE(addr,value) \
4466 (*(addr) = (value))
4467 #define R_DMA_CH6_DESCR__READ(addr) \
4468 (*(addr))
4469
4470 #define R_DMA_CH6_DESCR__descr__descr__MASK 0xffffffffU
4471
4472 #define R_DMA_CH6_DESCR__descr__MAX 0xffffffff
4473
4474 #define R_DMA_CH6_DESCR__descr__MIN 0
4475
4476 #define R_DMA_CH6_DESCR__descr__BITNR 0
4477
4478 #define R_DMA_CH6_DESCR__descr__descr__VAL REG_VAL_VAL
4479
4480
4481 #endif
4482
4483 /*
4484 * R_DMA_CH6_FIRST
4485 * - type: RW
4486 * - addr: 0xb00001b8
4487 * - group: DMA registers
4488 */
4489
4490 #if USE_GROUP__DMA_registers
4491
4492 #define R_DMA_CH6_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b8)
4493 #define R_DMA_CH6_FIRST__SVAL REG_SVAL_SHADOW
4494 #define R_DMA_CH6_FIRST__SVAL_I REG_SVAL_I_SHADOW
4495 #define R_DMA_CH6_FIRST__TYPECAST REG_TYPECAST_UDWORD
4496 #define R_DMA_CH6_FIRST__TYPE (REG_UDWORD)
4497 #define R_DMA_CH6_FIRST__GET REG_GET_RW
4498 #define R_DMA_CH6_FIRST__IGET REG_IGET_RW
4499 #define R_DMA_CH6_FIRST__SET REG_SET_RW
4500 #define R_DMA_CH6_FIRST__ISET REG_ISET_RW
4501 #define R_DMA_CH6_FIRST__SET_VAL REG_SET_VAL_RW
4502 #define R_DMA_CH6_FIRST__EQL REG_EQL_RW
4503 #define R_DMA_CH6_FIRST__IEQL REG_IEQL_RW
4504 #define R_DMA_CH6_FIRST__RD REG_RD_RW
4505 #define R_DMA_CH6_FIRST__IRD REG_IRD_RW
4506 #define R_DMA_CH6_FIRST__WR REG_WR_RW
4507 #define R_DMA_CH6_FIRST__IWR REG_IWR_RW
4508
4509 #define R_DMA_CH6_FIRST__WRITE(addr,value) \
4510 (*(addr) = (value))
4511 #define R_DMA_CH6_FIRST__READ(addr) \
4512 (*(addr))
4513
4514 #define R_DMA_CH6_FIRST__first__first__MASK 0xffffffffU
4515
4516 #define R_DMA_CH6_FIRST__first__MAX 0xffffffff
4517
4518 #define R_DMA_CH6_FIRST__first__MIN 0
4519
4520 #define R_DMA_CH6_FIRST__first__BITNR 0
4521
4522 #define R_DMA_CH6_FIRST__first__first__VAL REG_VAL_VAL
4523
4524
4525 #endif
4526
4527 /*
4528 * R_DMA_CH6_HWSW
4529 * - type: RW
4530 * - addr: 0xb0000160
4531 * - group: DMA registers
4532 */
4533
4534 #if USE_GROUP__DMA_registers
4535
4536 #define R_DMA_CH6_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000160)
4537 #define R_DMA_CH6_HWSW__SVAL REG_SVAL_SHADOW
4538 #define R_DMA_CH6_HWSW__SVAL_I REG_SVAL_I_SHADOW
4539 #define R_DMA_CH6_HWSW__TYPECAST REG_TYPECAST_UDWORD
4540 #define R_DMA_CH6_HWSW__TYPE (REG_UDWORD)
4541 #define R_DMA_CH6_HWSW__GET REG_GET_RW
4542 #define R_DMA_CH6_HWSW__IGET REG_IGET_RW
4543 #define R_DMA_CH6_HWSW__SET REG_SET_RW
4544 #define R_DMA_CH6_HWSW__ISET REG_ISET_RW
4545 #define R_DMA_CH6_HWSW__SET_VAL REG_SET_VAL_RW
4546 #define R_DMA_CH6_HWSW__EQL REG_EQL_RW
4547 #define R_DMA_CH6_HWSW__IEQL REG_IEQL_RW
4548 #define R_DMA_CH6_HWSW__RD REG_RD_RW
4549 #define R_DMA_CH6_HWSW__IRD REG_IRD_RW
4550 #define R_DMA_CH6_HWSW__WR REG_WR_RW
4551 #define R_DMA_CH6_HWSW__IWR REG_IWR_RW
4552
4553 #define R_DMA_CH6_HWSW__WRITE(addr,value) \
4554 (*(addr) = (value))
4555 #define R_DMA_CH6_HWSW__READ(addr) \
4556 (*(addr))
4557
4558 #define R_DMA_CH6_HWSW__hw__hw__MASK 0xffff0000U
4559 #define R_DMA_CH6_HWSW__sw__sw__MASK 0x0000ffffU
4560
4561 #define R_DMA_CH6_HWSW__hw__MAX 0xffff
4562 #define R_DMA_CH6_HWSW__sw__MAX 0xffff
4563
4564 #define R_DMA_CH6_HWSW__hw__MIN 0
4565 #define R_DMA_CH6_HWSW__sw__MIN 0
4566
4567 #define R_DMA_CH6_HWSW__hw__BITNR 16
4568 #define R_DMA_CH6_HWSW__sw__BITNR 0
4569
4570 #define R_DMA_CH6_HWSW__hw__hw__VAL REG_VAL_VAL
4571 #define R_DMA_CH6_HWSW__sw__sw__VAL REG_VAL_VAL
4572
4573
4574 #endif
4575
4576 /*
4577 * R_DMA_CH6_NEXT
4578 * - type: RW
4579 * - addr: 0xb0000164
4580 * - group: DMA registers
4581 */
4582
4583 #if USE_GROUP__DMA_registers
4584
4585 #define R_DMA_CH6_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000164)
4586 #define R_DMA_CH6_NEXT__SVAL REG_SVAL_SHADOW
4587 #define R_DMA_CH6_NEXT__SVAL_I REG_SVAL_I_SHADOW
4588 #define R_DMA_CH6_NEXT__TYPECAST REG_TYPECAST_UDWORD
4589 #define R_DMA_CH6_NEXT__TYPE (REG_UDWORD)
4590 #define R_DMA_CH6_NEXT__GET REG_GET_RW
4591 #define R_DMA_CH6_NEXT__IGET REG_IGET_RW
4592 #define R_DMA_CH6_NEXT__SET REG_SET_RW
4593 #define R_DMA_CH6_NEXT__ISET REG_ISET_RW
4594 #define R_DMA_CH6_NEXT__SET_VAL REG_SET_VAL_RW
4595 #define R_DMA_CH6_NEXT__EQL REG_EQL_RW
4596 #define R_DMA_CH6_NEXT__IEQL REG_IEQL_RW
4597 #define R_DMA_CH6_NEXT__RD REG_RD_RW
4598 #define R_DMA_CH6_NEXT__IRD REG_IRD_RW
4599 #define R_DMA_CH6_NEXT__WR REG_WR_RW
4600 #define R_DMA_CH6_NEXT__IWR REG_IWR_RW
4601
4602 #define R_DMA_CH6_NEXT__WRITE(addr,value) \
4603 (*(addr) = (value))
4604 #define R_DMA_CH6_NEXT__READ(addr) \
4605 (*(addr))
4606
4607 #define R_DMA_CH6_NEXT__next__next__MASK 0xffffffffU
4608
4609 #define R_DMA_CH6_NEXT__next__MAX 0xffffffff
4610
4611 #define R_DMA_CH6_NEXT__next__MIN 0
4612
4613 #define R_DMA_CH6_NEXT__next__BITNR 0
4614
4615 #define R_DMA_CH6_NEXT__next__next__VAL REG_VAL_VAL
4616
4617
4618 #endif
4619
4620 /*
4621 * R_DMA_CH6_STATUS
4622 * - type: RO
4623 * - addr: 0xb00001ea
4624 * - group: DMA registers
4625 */
4626
4627 #if USE_GROUP__DMA_registers
4628
4629 #define R_DMA_CH6_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ea)
4630 #define R_DMA_CH6_STATUS__SVAL REG_SVAL_SHADOW
4631 #define R_DMA_CH6_STATUS__SVAL_I REG_SVAL_I_SHADOW
4632 #define R_DMA_CH6_STATUS__TYPECAST REG_TYPECAST_BYTE
4633 #define R_DMA_CH6_STATUS__TYPE (REG_BYTE)
4634 #define R_DMA_CH6_STATUS__GET REG_GET_RO
4635 #define R_DMA_CH6_STATUS__IGET REG_IGET_RO
4636 #define R_DMA_CH6_STATUS__SET REG_SET_RO
4637 #define R_DMA_CH6_STATUS__ISET REG_ISET_RO
4638 #define R_DMA_CH6_STATUS__SET_VAL REG_SET_VAL_RO
4639 #define R_DMA_CH6_STATUS__EQL REG_EQL_RO
4640 #define R_DMA_CH6_STATUS__IEQL REG_IEQL_RO
4641 #define R_DMA_CH6_STATUS__RD REG_RD_RO
4642 #define R_DMA_CH6_STATUS__IRD REG_IRD_RO
4643 #define R_DMA_CH6_STATUS__WR REG_WR_RO
4644 #define R_DMA_CH6_STATUS__IWR REG_IWR_RO
4645
4646 #define R_DMA_CH6_STATUS__READ(addr) \
4647 (*(addr))
4648
4649 #define R_DMA_CH6_STATUS__avail__avail__MASK 0x0000007fU
4650
4651 #define R_DMA_CH6_STATUS__avail__MAX 0x7f
4652
4653 #define R_DMA_CH6_STATUS__avail__MIN 0
4654
4655 #define R_DMA_CH6_STATUS__avail__BITNR 0
4656
4657 #define R_DMA_CH6_STATUS__avail__avail__VAL REG_VAL_VAL
4658
4659
4660 #endif
4661
4662 /*
4663 * R_DMA_CH7_BUF
4664 * - type: RW
4665 * - addr: 0xb0000178
4666 * - group: DMA registers
4667 */
4668
4669 #if USE_GROUP__DMA_registers
4670
4671 #define R_DMA_CH7_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000178)
4672 #define R_DMA_CH7_BUF__SVAL REG_SVAL_SHADOW
4673 #define R_DMA_CH7_BUF__SVAL_I REG_SVAL_I_SHADOW
4674 #define R_DMA_CH7_BUF__TYPECAST REG_TYPECAST_UDWORD
4675 #define R_DMA_CH7_BUF__TYPE (REG_UDWORD)
4676 #define R_DMA_CH7_BUF__GET REG_GET_RW
4677 #define R_DMA_CH7_BUF__IGET REG_IGET_RW
4678 #define R_DMA_CH7_BUF__SET REG_SET_RW
4679 #define R_DMA_CH7_BUF__ISET REG_ISET_RW
4680 #define R_DMA_CH7_BUF__SET_VAL REG_SET_VAL_RW
4681 #define R_DMA_CH7_BUF__EQL REG_EQL_RW
4682 #define R_DMA_CH7_BUF__IEQL REG_IEQL_RW
4683 #define R_DMA_CH7_BUF__RD REG_RD_RW
4684 #define R_DMA_CH7_BUF__IRD REG_IRD_RW
4685 #define R_DMA_CH7_BUF__WR REG_WR_RW
4686 #define R_DMA_CH7_BUF__IWR REG_IWR_RW
4687
4688 #define R_DMA_CH7_BUF__WRITE(addr,value) \
4689 (*(addr) = (value))
4690 #define R_DMA_CH7_BUF__READ(addr) \
4691 (*(addr))
4692
4693 #define R_DMA_CH7_BUF__buf__buf__MASK 0xffffffffU
4694
4695 #define R_DMA_CH7_BUF__buf__MAX 0xffffffff
4696
4697 #define R_DMA_CH7_BUF__buf__MIN 0
4698
4699 #define R_DMA_CH7_BUF__buf__BITNR 0
4700
4701 #define R_DMA_CH7_BUF__buf__buf__VAL REG_VAL_VAL
4702
4703
4704 #endif
4705
4706 /*
4707 * R_DMA_CH7_CLR_INTR
4708 * - type: WO
4709 * - addr: 0xb00001ed
4710 * - group: DMA registers
4711 */
4712
4713 #if USE_GROUP__DMA_registers
4714
4715 #define R_DMA_CH7_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ed)
4716
4717 #ifndef REG_NO_SHADOW
4718 #define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH7_CLR_INTR + 0))
4719 #define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH7_CLR_INTR + 0))
4720 #else /* REG_NO_SHADOW */
4721 #define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
4722 #define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
4723 #endif /* REG_NO_SHADOW */
4724
4725 #define R_DMA_CH7_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
4726 #define R_DMA_CH7_CLR_INTR__SVAL REG_SVAL_ZERO
4727 #define R_DMA_CH7_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
4728 #define R_DMA_CH7_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
4729 #define R_DMA_CH7_CLR_INTR__TYPE (REG_BYTE)
4730 #define R_DMA_CH7_CLR_INTR__GET REG_GET_WO
4731 #define R_DMA_CH7_CLR_INTR__IGET REG_IGET_WO
4732 #define R_DMA_CH7_CLR_INTR__SET REG_SET_WO
4733 #define R_DMA_CH7_CLR_INTR__ISET REG_ISET_WO
4734 #define R_DMA_CH7_CLR_INTR__SET_VAL REG_SET_VAL_WO
4735 #define R_DMA_CH7_CLR_INTR__EQL REG_EQL_WO
4736 #define R_DMA_CH7_CLR_INTR__IEQL REG_IEQL_WO
4737 #define R_DMA_CH7_CLR_INTR__RD REG_RD_WO
4738 #define R_DMA_CH7_CLR_INTR__IRD REG_IRD_WO
4739 #define R_DMA_CH7_CLR_INTR__WR REG_WR_WO
4740 #define R_DMA_CH7_CLR_INTR__IWR REG_IWR_WO
4741
4742 #define R_DMA_CH7_CLR_INTR__WRITE(addr,value) \
4743 (*(addr) = (value))
4744
4745 #define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
4746 #define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
4747
4748 #define R_DMA_CH7_CLR_INTR__clr_eop__MAX 0x1
4749 #define R_DMA_CH7_CLR_INTR__clr_descr__MAX 0x1
4750
4751 #define R_DMA_CH7_CLR_INTR__clr_eop__MIN 0
4752 #define R_DMA_CH7_CLR_INTR__clr_descr__MIN 0
4753
4754 #define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
4755 #define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
4756
4757 #define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
4758 #define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
4759
4760 #define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__do 1
4761 #define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__dont 0
4762 #define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__do 1
4763 #define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__dont 0
4764
4765 #endif
4766
4767 /*
4768 * R_DMA_CH7_CMD
4769 * - type: RW
4770 * - addr: 0xb00001ec
4771 * - group: DMA registers
4772 */
4773
4774 #if USE_GROUP__DMA_registers
4775
4776 #define R_DMA_CH7_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001ec)
4777 #define R_DMA_CH7_CMD__SVAL REG_SVAL_SHADOW
4778 #define R_DMA_CH7_CMD__SVAL_I REG_SVAL_I_SHADOW
4779 #define R_DMA_CH7_CMD__TYPECAST REG_TYPECAST_BYTE
4780 #define R_DMA_CH7_CMD__TYPE (REG_BYTE)
4781 #define R_DMA_CH7_CMD__GET REG_GET_RW
4782 #define R_DMA_CH7_CMD__IGET REG_IGET_RW
4783 #define R_DMA_CH7_CMD__SET REG_SET_RW
4784 #define R_DMA_CH7_CMD__ISET REG_ISET_RW
4785 #define R_DMA_CH7_CMD__SET_VAL REG_SET_VAL_RW
4786 #define R_DMA_CH7_CMD__EQL REG_EQL_RW
4787 #define R_DMA_CH7_CMD__IEQL REG_IEQL_RW
4788 #define R_DMA_CH7_CMD__RD REG_RD_RW
4789 #define R_DMA_CH7_CMD__IRD REG_IRD_RW
4790 #define R_DMA_CH7_CMD__WR REG_WR_RW
4791 #define R_DMA_CH7_CMD__IWR REG_IWR_RW
4792
4793 #define R_DMA_CH7_CMD__WRITE(addr,value) \
4794 (*(addr) = (value))
4795 #define R_DMA_CH7_CMD__READ(addr) \
4796 (*(addr))
4797
4798 #define R_DMA_CH7_CMD__cmd__cmd__MASK 0x00000007U
4799
4800 #define R_DMA_CH7_CMD__cmd__MAX 0x7
4801
4802 #define R_DMA_CH7_CMD__cmd__MIN 0
4803
4804 #define R_DMA_CH7_CMD__cmd__BITNR 0
4805
4806 #define R_DMA_CH7_CMD__cmd__cmd__VAL REG_VAL_ENUM
4807
4808 #define R_DMA_CH7_CMD__cmd__cmd__continue 3
4809 #define R_DMA_CH7_CMD__cmd__cmd__hold 0
4810 #define R_DMA_CH7_CMD__cmd__cmd__reset 4
4811 #define R_DMA_CH7_CMD__cmd__cmd__restart 3
4812 #define R_DMA_CH7_CMD__cmd__cmd__start 1
4813
4814 #endif
4815
4816 /*
4817 * R_DMA_CH7_DESCR
4818 * - type: RW
4819 * - addr: 0xb000017c
4820 * - group: DMA registers
4821 */
4822
4823 #if USE_GROUP__DMA_registers
4824
4825 #define R_DMA_CH7_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000017c)
4826 #define R_DMA_CH7_DESCR__SVAL REG_SVAL_SHADOW
4827 #define R_DMA_CH7_DESCR__SVAL_I REG_SVAL_I_SHADOW
4828 #define R_DMA_CH7_DESCR__TYPECAST REG_TYPECAST_UDWORD
4829 #define R_DMA_CH7_DESCR__TYPE (REG_UDWORD)
4830 #define R_DMA_CH7_DESCR__GET REG_GET_RW
4831 #define R_DMA_CH7_DESCR__IGET REG_IGET_RW
4832 #define R_DMA_CH7_DESCR__SET REG_SET_RW
4833 #define R_DMA_CH7_DESCR__ISET REG_ISET_RW
4834 #define R_DMA_CH7_DESCR__SET_VAL REG_SET_VAL_RW
4835 #define R_DMA_CH7_DESCR__EQL REG_EQL_RW
4836 #define R_DMA_CH7_DESCR__IEQL REG_IEQL_RW
4837 #define R_DMA_CH7_DESCR__RD REG_RD_RW
4838 #define R_DMA_CH7_DESCR__IRD REG_IRD_RW
4839 #define R_DMA_CH7_DESCR__WR REG_WR_RW
4840 #define R_DMA_CH7_DESCR__IWR REG_IWR_RW
4841
4842 #define R_DMA_CH7_DESCR__WRITE(addr,value) \
4843 (*(addr) = (value))
4844 #define R_DMA_CH7_DESCR__READ(addr) \
4845 (*(addr))
4846
4847 #define R_DMA_CH7_DESCR__descr__descr__MASK 0xffffffffU
4848
4849 #define R_DMA_CH7_DESCR__descr__MAX 0xffffffff
4850
4851 #define R_DMA_CH7_DESCR__descr__MIN 0
4852
4853 #define R_DMA_CH7_DESCR__descr__BITNR 0
4854
4855 #define R_DMA_CH7_DESCR__descr__descr__VAL REG_VAL_VAL
4856
4857
4858 #endif
4859
4860 /*
4861 * R_DMA_CH7_FIRST
4862 * - type: RW
4863 * - addr: 0xb00001bc
4864 * - group: DMA registers
4865 */
4866
4867 #if USE_GROUP__DMA_registers
4868
4869 #define R_DMA_CH7_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001bc)
4870 #define R_DMA_CH7_FIRST__SVAL REG_SVAL_SHADOW
4871 #define R_DMA_CH7_FIRST__SVAL_I REG_SVAL_I_SHADOW
4872 #define R_DMA_CH7_FIRST__TYPECAST REG_TYPECAST_UDWORD
4873 #define R_DMA_CH7_FIRST__TYPE (REG_UDWORD)
4874 #define R_DMA_CH7_FIRST__GET REG_GET_RW
4875 #define R_DMA_CH7_FIRST__IGET REG_IGET_RW
4876 #define R_DMA_CH7_FIRST__SET REG_SET_RW
4877 #define R_DMA_CH7_FIRST__ISET REG_ISET_RW
4878 #define R_DMA_CH7_FIRST__SET_VAL REG_SET_VAL_RW
4879 #define R_DMA_CH7_FIRST__EQL REG_EQL_RW
4880 #define R_DMA_CH7_FIRST__IEQL REG_IEQL_RW
4881 #define R_DMA_CH7_FIRST__RD REG_RD_RW
4882 #define R_DMA_CH7_FIRST__IRD REG_IRD_RW
4883 #define R_DMA_CH7_FIRST__WR REG_WR_RW
4884 #define R_DMA_CH7_FIRST__IWR REG_IWR_RW
4885
4886 #define R_DMA_CH7_FIRST__WRITE(addr,value) \
4887 (*(addr) = (value))
4888 #define R_DMA_CH7_FIRST__READ(addr) \
4889 (*(addr))
4890
4891 #define R_DMA_CH7_FIRST__first__first__MASK 0xffffffffU
4892
4893 #define R_DMA_CH7_FIRST__first__MAX 0xffffffff
4894
4895 #define R_DMA_CH7_FIRST__first__MIN 0
4896
4897 #define R_DMA_CH7_FIRST__first__BITNR 0
4898
4899 #define R_DMA_CH7_FIRST__first__first__VAL REG_VAL_VAL
4900
4901
4902 #endif
4903
4904 /*
4905 * R_DMA_CH7_HWSW
4906 * - type: RW
4907 * - addr: 0xb0000170
4908 * - group: DMA registers
4909 */
4910
4911 #if USE_GROUP__DMA_registers
4912
4913 #define R_DMA_CH7_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000170)
4914 #define R_DMA_CH7_HWSW__SVAL REG_SVAL_SHADOW
4915 #define R_DMA_CH7_HWSW__SVAL_I REG_SVAL_I_SHADOW
4916 #define R_DMA_CH7_HWSW__TYPECAST REG_TYPECAST_UDWORD
4917 #define R_DMA_CH7_HWSW__TYPE (REG_UDWORD)
4918 #define R_DMA_CH7_HWSW__GET REG_GET_RW
4919 #define R_DMA_CH7_HWSW__IGET REG_IGET_RW
4920 #define R_DMA_CH7_HWSW__SET REG_SET_RW
4921 #define R_DMA_CH7_HWSW__ISET REG_ISET_RW
4922 #define R_DMA_CH7_HWSW__SET_VAL REG_SET_VAL_RW
4923 #define R_DMA_CH7_HWSW__EQL REG_EQL_RW
4924 #define R_DMA_CH7_HWSW__IEQL REG_IEQL_RW
4925 #define R_DMA_CH7_HWSW__RD REG_RD_RW
4926 #define R_DMA_CH7_HWSW__IRD REG_IRD_RW
4927 #define R_DMA_CH7_HWSW__WR REG_WR_RW
4928 #define R_DMA_CH7_HWSW__IWR REG_IWR_RW
4929
4930 #define R_DMA_CH7_HWSW__WRITE(addr,value) \
4931 (*(addr) = (value))
4932 #define R_DMA_CH7_HWSW__READ(addr) \
4933 (*(addr))
4934
4935 #define R_DMA_CH7_HWSW__hw__hw__MASK 0xffff0000U
4936 #define R_DMA_CH7_HWSW__sw__sw__MASK 0x0000ffffU
4937
4938 #define R_DMA_CH7_HWSW__hw__MAX 0xffff
4939 #define R_DMA_CH7_HWSW__sw__MAX 0xffff
4940
4941 #define R_DMA_CH7_HWSW__hw__MIN 0
4942 #define R_DMA_CH7_HWSW__sw__MIN 0
4943
4944 #define R_DMA_CH7_HWSW__hw__BITNR 16
4945 #define R_DMA_CH7_HWSW__sw__BITNR 0
4946
4947 #define R_DMA_CH7_HWSW__hw__hw__VAL REG_VAL_VAL
4948 #define R_DMA_CH7_HWSW__sw__sw__VAL REG_VAL_VAL
4949
4950
4951 #endif
4952
4953 /*
4954 * R_DMA_CH7_NEXT
4955 * - type: RW
4956 * - addr: 0xb0000174
4957 * - group: DMA registers
4958 */
4959
4960 #if USE_GROUP__DMA_registers
4961
4962 #define R_DMA_CH7_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000174)
4963 #define R_DMA_CH7_NEXT__SVAL REG_SVAL_SHADOW
4964 #define R_DMA_CH7_NEXT__SVAL_I REG_SVAL_I_SHADOW
4965 #define R_DMA_CH7_NEXT__TYPECAST REG_TYPECAST_UDWORD
4966 #define R_DMA_CH7_NEXT__TYPE (REG_UDWORD)
4967 #define R_DMA_CH7_NEXT__GET REG_GET_RW
4968 #define R_DMA_CH7_NEXT__IGET REG_IGET_RW
4969 #define R_DMA_CH7_NEXT__SET REG_SET_RW
4970 #define R_DMA_CH7_NEXT__ISET REG_ISET_RW
4971 #define R_DMA_CH7_NEXT__SET_VAL REG_SET_VAL_RW
4972 #define R_DMA_CH7_NEXT__EQL REG_EQL_RW
4973 #define R_DMA_CH7_NEXT__IEQL REG_IEQL_RW
4974 #define R_DMA_CH7_NEXT__RD REG_RD_RW
4975 #define R_DMA_CH7_NEXT__IRD REG_IRD_RW
4976 #define R_DMA_CH7_NEXT__WR REG_WR_RW
4977 #define R_DMA_CH7_NEXT__IWR REG_IWR_RW
4978
4979 #define R_DMA_CH7_NEXT__WRITE(addr,value) \
4980 (*(addr) = (value))
4981 #define R_DMA_CH7_NEXT__READ(addr) \
4982 (*(addr))
4983
4984 #define R_DMA_CH7_NEXT__next__next__MASK 0xffffffffU
4985
4986 #define R_DMA_CH7_NEXT__next__MAX 0xffffffff
4987
4988 #define R_DMA_CH7_NEXT__next__MIN 0
4989
4990 #define R_DMA_CH7_NEXT__next__BITNR 0
4991
4992 #define R_DMA_CH7_NEXT__next__next__VAL REG_VAL_VAL
4993
4994
4995 #endif
4996
4997 /*
4998 * R_DMA_CH7_STATUS
4999 * - type: RO
5000 * - addr: 0xb00001ee
5001 * - group: DMA registers
5002 */
5003
5004 #if USE_GROUP__DMA_registers
5005
5006 #define R_DMA_CH7_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ee)
5007 #define R_DMA_CH7_STATUS__SVAL REG_SVAL_SHADOW
5008 #define R_DMA_CH7_STATUS__SVAL_I REG_SVAL_I_SHADOW
5009 #define R_DMA_CH7_STATUS__TYPECAST REG_TYPECAST_BYTE
5010 #define R_DMA_CH7_STATUS__TYPE (REG_BYTE)
5011 #define R_DMA_CH7_STATUS__GET REG_GET_RO
5012 #define R_DMA_CH7_STATUS__IGET REG_IGET_RO
5013 #define R_DMA_CH7_STATUS__SET REG_SET_RO
5014 #define R_DMA_CH7_STATUS__ISET REG_ISET_RO
5015 #define R_DMA_CH7_STATUS__SET_VAL REG_SET_VAL_RO
5016 #define R_DMA_CH7_STATUS__EQL REG_EQL_RO
5017 #define R_DMA_CH7_STATUS__IEQL REG_IEQL_RO
5018 #define R_DMA_CH7_STATUS__RD REG_RD_RO
5019 #define R_DMA_CH7_STATUS__IRD REG_IRD_RO
5020 #define R_DMA_CH7_STATUS__WR REG_WR_RO
5021 #define R_DMA_CH7_STATUS__IWR REG_IWR_RO
5022
5023 #define R_DMA_CH7_STATUS__READ(addr) \
5024 (*(addr))
5025
5026 #define R_DMA_CH7_STATUS__avail__avail__MASK 0x0000007fU
5027
5028 #define R_DMA_CH7_STATUS__avail__MAX 0x7f
5029
5030 #define R_DMA_CH7_STATUS__avail__MIN 0
5031
5032 #define R_DMA_CH7_STATUS__avail__BITNR 0
5033
5034 #define R_DMA_CH7_STATUS__avail__avail__VAL REG_VAL_VAL
5035
5036
5037 #endif
5038
5039 /*
5040 * R_DMA_CH8_BUF
5041 * - type: RW
5042 * - addr: 0xb0000188
5043 * - group: DMA registers
5044 */
5045
5046 #if USE_GROUP__DMA_registers
5047
5048 #define R_DMA_CH8_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000188)
5049 #define R_DMA_CH8_BUF__SVAL REG_SVAL_SHADOW
5050 #define R_DMA_CH8_BUF__SVAL_I REG_SVAL_I_SHADOW
5051 #define R_DMA_CH8_BUF__TYPECAST REG_TYPECAST_UDWORD
5052 #define R_DMA_CH8_BUF__TYPE (REG_UDWORD)
5053 #define R_DMA_CH8_BUF__GET REG_GET_RW
5054 #define R_DMA_CH8_BUF__IGET REG_IGET_RW
5055 #define R_DMA_CH8_BUF__SET REG_SET_RW
5056 #define R_DMA_CH8_BUF__ISET REG_ISET_RW
5057 #define R_DMA_CH8_BUF__SET_VAL REG_SET_VAL_RW
5058 #define R_DMA_CH8_BUF__EQL REG_EQL_RW
5059 #define R_DMA_CH8_BUF__IEQL REG_IEQL_RW
5060 #define R_DMA_CH8_BUF__RD REG_RD_RW
5061 #define R_DMA_CH8_BUF__IRD REG_IRD_RW
5062 #define R_DMA_CH8_BUF__WR REG_WR_RW
5063 #define R_DMA_CH8_BUF__IWR REG_IWR_RW
5064
5065 #define R_DMA_CH8_BUF__WRITE(addr,value) \
5066 (*(addr) = (value))
5067 #define R_DMA_CH8_BUF__READ(addr) \
5068 (*(addr))
5069
5070 #define R_DMA_CH8_BUF__buf__buf__MASK 0xffffffffU
5071
5072 #define R_DMA_CH8_BUF__buf__MAX 0xffffffff
5073
5074 #define R_DMA_CH8_BUF__buf__MIN 0
5075
5076 #define R_DMA_CH8_BUF__buf__BITNR 0
5077
5078 #define R_DMA_CH8_BUF__buf__buf__VAL REG_VAL_VAL
5079
5080
5081 #endif
5082
5083 /*
5084 * R_DMA_CH8_CLR_INTR
5085 * - type: WO
5086 * - addr: 0xb00001f1
5087 * - group: DMA registers
5088 */
5089
5090 #if USE_GROUP__DMA_registers
5091
5092 #define R_DMA_CH8_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f1)
5093
5094 #ifndef REG_NO_SHADOW
5095 #define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_CLR_INTR + 0))
5096 #define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_CLR_INTR + 0))
5097 #else /* REG_NO_SHADOW */
5098 #define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
5099 #define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
5100 #endif /* REG_NO_SHADOW */
5101
5102 #define R_DMA_CH8_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
5103 #define R_DMA_CH8_CLR_INTR__SVAL REG_SVAL_ZERO
5104 #define R_DMA_CH8_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
5105 #define R_DMA_CH8_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
5106 #define R_DMA_CH8_CLR_INTR__TYPE (REG_BYTE)
5107 #define R_DMA_CH8_CLR_INTR__GET REG_GET_WO
5108 #define R_DMA_CH8_CLR_INTR__IGET REG_IGET_WO
5109 #define R_DMA_CH8_CLR_INTR__SET REG_SET_WO
5110 #define R_DMA_CH8_CLR_INTR__ISET REG_ISET_WO
5111 #define R_DMA_CH8_CLR_INTR__SET_VAL REG_SET_VAL_WO
5112 #define R_DMA_CH8_CLR_INTR__EQL REG_EQL_WO
5113 #define R_DMA_CH8_CLR_INTR__IEQL REG_IEQL_WO
5114 #define R_DMA_CH8_CLR_INTR__RD REG_RD_WO
5115 #define R_DMA_CH8_CLR_INTR__IRD REG_IRD_WO
5116 #define R_DMA_CH8_CLR_INTR__WR REG_WR_WO
5117 #define R_DMA_CH8_CLR_INTR__IWR REG_IWR_WO
5118
5119 #define R_DMA_CH8_CLR_INTR__WRITE(addr,value) \
5120 (*(addr) = (value))
5121
5122 #define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
5123 #define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
5124
5125 #define R_DMA_CH8_CLR_INTR__clr_eop__MAX 0x1
5126 #define R_DMA_CH8_CLR_INTR__clr_descr__MAX 0x1
5127
5128 #define R_DMA_CH8_CLR_INTR__clr_eop__MIN 0
5129 #define R_DMA_CH8_CLR_INTR__clr_descr__MIN 0
5130
5131 #define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
5132 #define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
5133
5134 #define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
5135 #define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
5136
5137 #define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__do 1
5138 #define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__dont 0
5139 #define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__do 1
5140 #define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__dont 0
5141
5142 #endif
5143
5144 /*
5145 * R_DMA_CH8_CMD
5146 * - type: RW
5147 * - addr: 0xb00001f0
5148 * - group: DMA registers
5149 */
5150
5151 #if USE_GROUP__DMA_registers
5152
5153 #define R_DMA_CH8_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f0)
5154 #define R_DMA_CH8_CMD__SVAL REG_SVAL_SHADOW
5155 #define R_DMA_CH8_CMD__SVAL_I REG_SVAL_I_SHADOW
5156 #define R_DMA_CH8_CMD__TYPECAST REG_TYPECAST_BYTE
5157 #define R_DMA_CH8_CMD__TYPE (REG_BYTE)
5158 #define R_DMA_CH8_CMD__GET REG_GET_RW
5159 #define R_DMA_CH8_CMD__IGET REG_IGET_RW
5160 #define R_DMA_CH8_CMD__SET REG_SET_RW
5161 #define R_DMA_CH8_CMD__ISET REG_ISET_RW
5162 #define R_DMA_CH8_CMD__SET_VAL REG_SET_VAL_RW
5163 #define R_DMA_CH8_CMD__EQL REG_EQL_RW
5164 #define R_DMA_CH8_CMD__IEQL REG_IEQL_RW
5165 #define R_DMA_CH8_CMD__RD REG_RD_RW
5166 #define R_DMA_CH8_CMD__IRD REG_IRD_RW
5167 #define R_DMA_CH8_CMD__WR REG_WR_RW
5168 #define R_DMA_CH8_CMD__IWR REG_IWR_RW
5169
5170 #define R_DMA_CH8_CMD__WRITE(addr,value) \
5171 (*(addr) = (value))
5172 #define R_DMA_CH8_CMD__READ(addr) \
5173 (*(addr))
5174
5175 #define R_DMA_CH8_CMD__cmd__cmd__MASK 0x00000007U
5176
5177 #define R_DMA_CH8_CMD__cmd__MAX 0x7
5178
5179 #define R_DMA_CH8_CMD__cmd__MIN 0
5180
5181 #define R_DMA_CH8_CMD__cmd__BITNR 0
5182
5183 #define R_DMA_CH8_CMD__cmd__cmd__VAL REG_VAL_ENUM
5184
5185 #define R_DMA_CH8_CMD__cmd__cmd__continue 3
5186 #define R_DMA_CH8_CMD__cmd__cmd__hold 0
5187 #define R_DMA_CH8_CMD__cmd__cmd__reset 4
5188 #define R_DMA_CH8_CMD__cmd__cmd__restart 3
5189 #define R_DMA_CH8_CMD__cmd__cmd__start 1
5190
5191 #endif
5192
5193 /*
5194 * R_DMA_CH8_DESCR
5195 * - type: RW
5196 * - addr: 0xb000018c
5197 * - group: DMA registers
5198 */
5199
5200 #if USE_GROUP__DMA_registers
5201
5202 #define R_DMA_CH8_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000018c)
5203 #define R_DMA_CH8_DESCR__SVAL REG_SVAL_SHADOW
5204 #define R_DMA_CH8_DESCR__SVAL_I REG_SVAL_I_SHADOW
5205 #define R_DMA_CH8_DESCR__TYPECAST REG_TYPECAST_UDWORD
5206 #define R_DMA_CH8_DESCR__TYPE (REG_UDWORD)
5207 #define R_DMA_CH8_DESCR__GET REG_GET_RW
5208 #define R_DMA_CH8_DESCR__IGET REG_IGET_RW
5209 #define R_DMA_CH8_DESCR__SET REG_SET_RW
5210 #define R_DMA_CH8_DESCR__ISET REG_ISET_RW
5211 #define R_DMA_CH8_DESCR__SET_VAL REG_SET_VAL_RW
5212 #define R_DMA_CH8_DESCR__EQL REG_EQL_RW
5213 #define R_DMA_CH8_DESCR__IEQL REG_IEQL_RW
5214 #define R_DMA_CH8_DESCR__RD REG_RD_RW
5215 #define R_DMA_CH8_DESCR__IRD REG_IRD_RW
5216 #define R_DMA_CH8_DESCR__WR REG_WR_RW
5217 #define R_DMA_CH8_DESCR__IWR REG_IWR_RW
5218
5219 #define R_DMA_CH8_DESCR__WRITE(addr,value) \
5220 (*(addr) = (value))
5221 #define R_DMA_CH8_DESCR__READ(addr) \
5222 (*(addr))
5223
5224 #define R_DMA_CH8_DESCR__descr__descr__MASK 0xffffffffU
5225
5226 #define R_DMA_CH8_DESCR__descr__MAX 0xffffffff
5227
5228 #define R_DMA_CH8_DESCR__descr__MIN 0
5229
5230 #define R_DMA_CH8_DESCR__descr__BITNR 0
5231
5232 #define R_DMA_CH8_DESCR__descr__descr__VAL REG_VAL_VAL
5233
5234
5235 #endif
5236
5237 /*
5238 * R_DMA_CH8_FIRST
5239 * - type: RW
5240 * - addr: 0xb00001c0
5241 * - group: DMA registers
5242 */
5243
5244 #if USE_GROUP__DMA_registers
5245
5246 #define R_DMA_CH8_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c0)
5247 #define R_DMA_CH8_FIRST__SVAL REG_SVAL_SHADOW
5248 #define R_DMA_CH8_FIRST__SVAL_I REG_SVAL_I_SHADOW
5249 #define R_DMA_CH8_FIRST__TYPECAST REG_TYPECAST_UDWORD
5250 #define R_DMA_CH8_FIRST__TYPE (REG_UDWORD)
5251 #define R_DMA_CH8_FIRST__GET REG_GET_RW
5252 #define R_DMA_CH8_FIRST__IGET REG_IGET_RW
5253 #define R_DMA_CH8_FIRST__SET REG_SET_RW
5254 #define R_DMA_CH8_FIRST__ISET REG_ISET_RW
5255 #define R_DMA_CH8_FIRST__SET_VAL REG_SET_VAL_RW
5256 #define R_DMA_CH8_FIRST__EQL REG_EQL_RW
5257 #define R_DMA_CH8_FIRST__IEQL REG_IEQL_RW
5258 #define R_DMA_CH8_FIRST__RD REG_RD_RW
5259 #define R_DMA_CH8_FIRST__IRD REG_IRD_RW
5260 #define R_DMA_CH8_FIRST__WR REG_WR_RW
5261 #define R_DMA_CH8_FIRST__IWR REG_IWR_RW
5262
5263 #define R_DMA_CH8_FIRST__WRITE(addr,value) \
5264 (*(addr) = (value))
5265 #define R_DMA_CH8_FIRST__READ(addr) \
5266 (*(addr))
5267
5268 #define R_DMA_CH8_FIRST__first__first__MASK 0xffffffffU
5269
5270 #define R_DMA_CH8_FIRST__first__MAX 0xffffffff
5271
5272 #define R_DMA_CH8_FIRST__first__MIN 0
5273
5274 #define R_DMA_CH8_FIRST__first__BITNR 0
5275
5276 #define R_DMA_CH8_FIRST__first__first__VAL REG_VAL_VAL
5277
5278
5279 #endif
5280
5281 /*
5282 * R_DMA_CH8_HWSW
5283 * - type: RW
5284 * - addr: 0xb0000180
5285 * - group: DMA registers
5286 */
5287
5288 #if USE_GROUP__DMA_registers
5289
5290 #define R_DMA_CH8_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000180)
5291 #define R_DMA_CH8_HWSW__SVAL REG_SVAL_SHADOW
5292 #define R_DMA_CH8_HWSW__SVAL_I REG_SVAL_I_SHADOW
5293 #define R_DMA_CH8_HWSW__TYPECAST REG_TYPECAST_UDWORD
5294 #define R_DMA_CH8_HWSW__TYPE (REG_UDWORD)
5295 #define R_DMA_CH8_HWSW__GET REG_GET_RW
5296 #define R_DMA_CH8_HWSW__IGET REG_IGET_RW
5297 #define R_DMA_CH8_HWSW__SET REG_SET_RW
5298 #define R_DMA_CH8_HWSW__ISET REG_ISET_RW
5299 #define R_DMA_CH8_HWSW__SET_VAL REG_SET_VAL_RW
5300 #define R_DMA_CH8_HWSW__EQL REG_EQL_RW
5301 #define R_DMA_CH8_HWSW__IEQL REG_IEQL_RW
5302 #define R_DMA_CH8_HWSW__RD REG_RD_RW
5303 #define R_DMA_CH8_HWSW__IRD REG_IRD_RW
5304 #define R_DMA_CH8_HWSW__WR REG_WR_RW
5305 #define R_DMA_CH8_HWSW__IWR REG_IWR_RW
5306
5307 #define R_DMA_CH8_HWSW__WRITE(addr,value) \
5308 (*(addr) = (value))
5309 #define R_DMA_CH8_HWSW__READ(addr) \
5310 (*(addr))
5311
5312 #define R_DMA_CH8_HWSW__hw__hw__MASK 0xffff0000U
5313 #define R_DMA_CH8_HWSW__sw__sw__MASK 0x0000ffffU
5314
5315 #define R_DMA_CH8_HWSW__hw__MAX 0xffff
5316 #define R_DMA_CH8_HWSW__sw__MAX 0xffff
5317
5318 #define R_DMA_CH8_HWSW__hw__MIN 0
5319 #define R_DMA_CH8_HWSW__sw__MIN 0
5320
5321 #define R_DMA_CH8_HWSW__hw__BITNR 16
5322 #define R_DMA_CH8_HWSW__sw__BITNR 0
5323
5324 #define R_DMA_CH8_HWSW__hw__hw__VAL REG_VAL_VAL
5325 #define R_DMA_CH8_HWSW__sw__sw__VAL REG_VAL_VAL
5326
5327
5328 #endif
5329
5330 /*
5331 * R_DMA_CH8_NEP
5332 * - type: RW
5333 * - addr: 0xb00001c0
5334 * - group: DMA registers
5335 */
5336
5337 #if USE_GROUP__DMA_registers
5338
5339 #define R_DMA_CH8_NEP__ADDR (REG_TYPECAST_UDWORD 0xb00001c0)
5340 #define R_DMA_CH8_NEP__SVAL REG_SVAL_SHADOW
5341 #define R_DMA_CH8_NEP__SVAL_I REG_SVAL_I_SHADOW
5342 #define R_DMA_CH8_NEP__TYPECAST REG_TYPECAST_UDWORD
5343 #define R_DMA_CH8_NEP__TYPE (REG_UDWORD)
5344 #define R_DMA_CH8_NEP__GET REG_GET_RW
5345 #define R_DMA_CH8_NEP__IGET REG_IGET_RW
5346 #define R_DMA_CH8_NEP__SET REG_SET_RW
5347 #define R_DMA_CH8_NEP__ISET REG_ISET_RW
5348 #define R_DMA_CH8_NEP__SET_VAL REG_SET_VAL_RW
5349 #define R_DMA_CH8_NEP__EQL REG_EQL_RW
5350 #define R_DMA_CH8_NEP__IEQL REG_IEQL_RW
5351 #define R_DMA_CH8_NEP__RD REG_RD_RW
5352 #define R_DMA_CH8_NEP__IRD REG_IRD_RW
5353 #define R_DMA_CH8_NEP__WR REG_WR_RW
5354 #define R_DMA_CH8_NEP__IWR REG_IWR_RW
5355
5356 #define R_DMA_CH8_NEP__WRITE(addr,value) \
5357 (*(addr) = (value))
5358 #define R_DMA_CH8_NEP__READ(addr) \
5359 (*(addr))
5360
5361 #define R_DMA_CH8_NEP__nep__nep__MASK 0xffffffffU
5362
5363 #define R_DMA_CH8_NEP__nep__MAX 0xffffffff
5364
5365 #define R_DMA_CH8_NEP__nep__MIN 0
5366
5367 #define R_DMA_CH8_NEP__nep__BITNR 0
5368
5369 #define R_DMA_CH8_NEP__nep__nep__VAL REG_VAL_VAL
5370
5371
5372 #endif
5373
5374 /*
5375 * R_DMA_CH8_NEXT
5376 * - type: RW
5377 * - addr: 0xb0000184
5378 * - group: DMA registers
5379 */
5380
5381 #if USE_GROUP__DMA_registers
5382
5383 #define R_DMA_CH8_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000184)
5384 #define R_DMA_CH8_NEXT__SVAL REG_SVAL_SHADOW
5385 #define R_DMA_CH8_NEXT__SVAL_I REG_SVAL_I_SHADOW
5386 #define R_DMA_CH8_NEXT__TYPECAST REG_TYPECAST_UDWORD
5387 #define R_DMA_CH8_NEXT__TYPE (REG_UDWORD)
5388 #define R_DMA_CH8_NEXT__GET REG_GET_RW
5389 #define R_DMA_CH8_NEXT__IGET REG_IGET_RW
5390 #define R_DMA_CH8_NEXT__SET REG_SET_RW
5391 #define R_DMA_CH8_NEXT__ISET REG_ISET_RW
5392 #define R_DMA_CH8_NEXT__SET_VAL REG_SET_VAL_RW
5393 #define R_DMA_CH8_NEXT__EQL REG_EQL_RW
5394 #define R_DMA_CH8_NEXT__IEQL REG_IEQL_RW
5395 #define R_DMA_CH8_NEXT__RD REG_RD_RW
5396 #define R_DMA_CH8_NEXT__IRD REG_IRD_RW
5397 #define R_DMA_CH8_NEXT__WR REG_WR_RW
5398 #define R_DMA_CH8_NEXT__IWR REG_IWR_RW
5399
5400 #define R_DMA_CH8_NEXT__WRITE(addr,value) \
5401 (*(addr) = (value))
5402 #define R_DMA_CH8_NEXT__READ(addr) \
5403 (*(addr))
5404
5405 #define R_DMA_CH8_NEXT__next__next__MASK 0xffffffffU
5406
5407 #define R_DMA_CH8_NEXT__next__MAX 0xffffffff
5408
5409 #define R_DMA_CH8_NEXT__next__MIN 0
5410
5411 #define R_DMA_CH8_NEXT__next__BITNR 0
5412
5413 #define R_DMA_CH8_NEXT__next__next__VAL REG_VAL_VAL
5414
5415
5416 #endif
5417
5418 /*
5419 * R_DMA_CH8_STATUS
5420 * - type: RO
5421 * - addr: 0xb00001f2
5422 * - group: DMA registers
5423 */
5424
5425 #if USE_GROUP__DMA_registers
5426
5427 #define R_DMA_CH8_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f2)
5428 #define R_DMA_CH8_STATUS__SVAL REG_SVAL_SHADOW
5429 #define R_DMA_CH8_STATUS__SVAL_I REG_SVAL_I_SHADOW
5430 #define R_DMA_CH8_STATUS__TYPECAST REG_TYPECAST_BYTE
5431 #define R_DMA_CH8_STATUS__TYPE (REG_BYTE)
5432 #define R_DMA_CH8_STATUS__GET REG_GET_RO
5433 #define R_DMA_CH8_STATUS__IGET REG_IGET_RO
5434 #define R_DMA_CH8_STATUS__SET REG_SET_RO
5435 #define R_DMA_CH8_STATUS__ISET REG_ISET_RO
5436 #define R_DMA_CH8_STATUS__SET_VAL REG_SET_VAL_RO
5437 #define R_DMA_CH8_STATUS__EQL REG_EQL_RO
5438 #define R_DMA_CH8_STATUS__IEQL REG_IEQL_RO
5439 #define R_DMA_CH8_STATUS__RD REG_RD_RO
5440 #define R_DMA_CH8_STATUS__IRD REG_IRD_RO
5441 #define R_DMA_CH8_STATUS__WR REG_WR_RO
5442 #define R_DMA_CH8_STATUS__IWR REG_IWR_RO
5443
5444 #define R_DMA_CH8_STATUS__READ(addr) \
5445 (*(addr))
5446
5447 #define R_DMA_CH8_STATUS__avail__avail__MASK 0x0000007fU
5448
5449 #define R_DMA_CH8_STATUS__avail__MAX 0x7f
5450
5451 #define R_DMA_CH8_STATUS__avail__MIN 0
5452
5453 #define R_DMA_CH8_STATUS__avail__BITNR 0
5454
5455 #define R_DMA_CH8_STATUS__avail__avail__VAL REG_VAL_VAL
5456
5457
5458 #endif
5459
5460 /*
5461 * R_DMA_CH8_SUB
5462 * - type: RW
5463 * - addr: 0xb000018c
5464 * - group: DMA registers
5465 */
5466
5467 #if USE_GROUP__DMA_registers
5468
5469 #define R_DMA_CH8_SUB__ADDR (REG_TYPECAST_UDWORD 0xb000018c)
5470 #define R_DMA_CH8_SUB__SVAL REG_SVAL_SHADOW
5471 #define R_DMA_CH8_SUB__SVAL_I REG_SVAL_I_SHADOW
5472 #define R_DMA_CH8_SUB__TYPECAST REG_TYPECAST_UDWORD
5473 #define R_DMA_CH8_SUB__TYPE (REG_UDWORD)
5474 #define R_DMA_CH8_SUB__GET REG_GET_RW
5475 #define R_DMA_CH8_SUB__IGET REG_IGET_RW
5476 #define R_DMA_CH8_SUB__SET REG_SET_RW
5477 #define R_DMA_CH8_SUB__ISET REG_ISET_RW
5478 #define R_DMA_CH8_SUB__SET_VAL REG_SET_VAL_RW
5479 #define R_DMA_CH8_SUB__EQL REG_EQL_RW
5480 #define R_DMA_CH8_SUB__IEQL REG_IEQL_RW
5481 #define R_DMA_CH8_SUB__RD REG_RD_RW
5482 #define R_DMA_CH8_SUB__IRD REG_IRD_RW
5483 #define R_DMA_CH8_SUB__WR REG_WR_RW
5484 #define R_DMA_CH8_SUB__IWR REG_IWR_RW
5485
5486 #define R_DMA_CH8_SUB__WRITE(addr,value) \
5487 (*(addr) = (value))
5488 #define R_DMA_CH8_SUB__READ(addr) \
5489 (*(addr))
5490
5491 #define R_DMA_CH8_SUB__sub__sub__MASK 0xffffffffU
5492
5493 #define R_DMA_CH8_SUB__sub__MAX 0xffffffff
5494
5495 #define R_DMA_CH8_SUB__sub__MIN 0
5496
5497 #define R_DMA_CH8_SUB__sub__BITNR 0
5498
5499 #define R_DMA_CH8_SUB__sub__sub__VAL REG_VAL_VAL
5500
5501
5502 #endif
5503
5504 /*
5505 * R_DMA_CH8_SUB0_CLR_INTR
5506 * - type: WO
5507 * - addr: 0xb00001e3
5508 * - group: DMA registers
5509 */
5510
5511 #if USE_GROUP__DMA_registers
5512
5513 #define R_DMA_CH8_SUB0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e3)
5514
5515 #ifndef REG_NO_SHADOW
5516 #define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0))
5517 #define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0))
5518 #else /* REG_NO_SHADOW */
5519 #define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
5520 #define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
5521 #endif /* REG_NO_SHADOW */
5522
5523 #define R_DMA_CH8_SUB0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
5524 #define R_DMA_CH8_SUB0_CLR_INTR__SVAL REG_SVAL_ZERO
5525 #define R_DMA_CH8_SUB0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
5526 #define R_DMA_CH8_SUB0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
5527 #define R_DMA_CH8_SUB0_CLR_INTR__TYPE (REG_BYTE)
5528 #define R_DMA_CH8_SUB0_CLR_INTR__GET REG_GET_WO
5529 #define R_DMA_CH8_SUB0_CLR_INTR__IGET REG_IGET_WO
5530 #define R_DMA_CH8_SUB0_CLR_INTR__SET REG_SET_WO
5531 #define R_DMA_CH8_SUB0_CLR_INTR__ISET REG_ISET_WO
5532 #define R_DMA_CH8_SUB0_CLR_INTR__SET_VAL REG_SET_VAL_WO
5533 #define R_DMA_CH8_SUB0_CLR_INTR__EQL REG_EQL_WO
5534 #define R_DMA_CH8_SUB0_CLR_INTR__IEQL REG_IEQL_WO
5535 #define R_DMA_CH8_SUB0_CLR_INTR__RD REG_RD_WO
5536 #define R_DMA_CH8_SUB0_CLR_INTR__IRD REG_IRD_WO
5537 #define R_DMA_CH8_SUB0_CLR_INTR__WR REG_WR_WO
5538 #define R_DMA_CH8_SUB0_CLR_INTR__IWR REG_IWR_WO
5539
5540 #define R_DMA_CH8_SUB0_CLR_INTR__WRITE(addr,value) \
5541 (*(addr) = (value))
5542
5543 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
5544
5545 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MAX 0x1
5546
5547 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MIN 0
5548
5549 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
5550
5551 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
5552
5553 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__do 1
5554 #define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__dont 0
5555
5556 #endif
5557
5558 /*
5559 * R_DMA_CH8_SUB0_CMD
5560 * - type: RW
5561 * - addr: 0xb00001d3
5562 * - group: DMA registers
5563 */
5564
5565 #if USE_GROUP__DMA_registers
5566
5567 #define R_DMA_CH8_SUB0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d3)
5568 #define R_DMA_CH8_SUB0_CMD__SVAL REG_SVAL_SHADOW
5569 #define R_DMA_CH8_SUB0_CMD__SVAL_I REG_SVAL_I_SHADOW
5570 #define R_DMA_CH8_SUB0_CMD__TYPECAST REG_TYPECAST_BYTE
5571 #define R_DMA_CH8_SUB0_CMD__TYPE (REG_BYTE)
5572 #define R_DMA_CH8_SUB0_CMD__GET REG_GET_RW
5573 #define R_DMA_CH8_SUB0_CMD__IGET REG_IGET_RW
5574 #define R_DMA_CH8_SUB0_CMD__SET REG_SET_RW
5575 #define R_DMA_CH8_SUB0_CMD__ISET REG_ISET_RW
5576 #define R_DMA_CH8_SUB0_CMD__SET_VAL REG_SET_VAL_RW
5577 #define R_DMA_CH8_SUB0_CMD__EQL REG_EQL_RW
5578 #define R_DMA_CH8_SUB0_CMD__IEQL REG_IEQL_RW
5579 #define R_DMA_CH8_SUB0_CMD__RD REG_RD_RW
5580 #define R_DMA_CH8_SUB0_CMD__IRD REG_IRD_RW
5581 #define R_DMA_CH8_SUB0_CMD__WR REG_WR_RW
5582 #define R_DMA_CH8_SUB0_CMD__IWR REG_IWR_RW
5583
5584 #define R_DMA_CH8_SUB0_CMD__WRITE(addr,value) \
5585 (*(addr) = (value))
5586 #define R_DMA_CH8_SUB0_CMD__READ(addr) \
5587 (*(addr))
5588
5589 #define R_DMA_CH8_SUB0_CMD__cmd__cmd__MASK 0x00000001U
5590
5591 #define R_DMA_CH8_SUB0_CMD__cmd__MAX 0x1
5592
5593 #define R_DMA_CH8_SUB0_CMD__cmd__MIN 0
5594
5595 #define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
5596
5597 #define R_DMA_CH8_SUB0_CMD__cmd__cmd__VAL REG_VAL_ENUM
5598
5599 #define R_DMA_CH8_SUB0_CMD__cmd__cmd__start 1
5600 #define R_DMA_CH8_SUB0_CMD__cmd__cmd__stop 0
5601
5602 #endif
5603
5604 /*
5605 * R_DMA_CH8_SUB0_EP
5606 * - type: RW
5607 * - addr: 0xb00001c8
5608 * - group: DMA registers
5609 */
5610
5611 #if USE_GROUP__DMA_registers
5612
5613 #define R_DMA_CH8_SUB0_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001c8)
5614 #define R_DMA_CH8_SUB0_EP__SVAL REG_SVAL_SHADOW
5615 #define R_DMA_CH8_SUB0_EP__SVAL_I REG_SVAL_I_SHADOW
5616 #define R_DMA_CH8_SUB0_EP__TYPECAST REG_TYPECAST_UDWORD
5617 #define R_DMA_CH8_SUB0_EP__TYPE (REG_UDWORD)
5618 #define R_DMA_CH8_SUB0_EP__GET REG_GET_RW
5619 #define R_DMA_CH8_SUB0_EP__IGET REG_IGET_RW
5620 #define R_DMA_CH8_SUB0_EP__SET REG_SET_RW
5621 #define R_DMA_CH8_SUB0_EP__ISET REG_ISET_RW
5622 #define R_DMA_CH8_SUB0_EP__SET_VAL REG_SET_VAL_RW
5623 #define R_DMA_CH8_SUB0_EP__EQL REG_EQL_RW
5624 #define R_DMA_CH8_SUB0_EP__IEQL REG_IEQL_RW
5625 #define R_DMA_CH8_SUB0_EP__RD REG_RD_RW
5626 #define R_DMA_CH8_SUB0_EP__IRD REG_IRD_RW
5627 #define R_DMA_CH8_SUB0_EP__WR REG_WR_RW
5628 #define R_DMA_CH8_SUB0_EP__IWR REG_IWR_RW
5629
5630 #define R_DMA_CH8_SUB0_EP__WRITE(addr,value) \
5631 (*(addr) = (value))
5632 #define R_DMA_CH8_SUB0_EP__READ(addr) \
5633 (*(addr))
5634
5635 #define R_DMA_CH8_SUB0_EP__ep__ep__MASK 0xffffffffU
5636
5637 #define R_DMA_CH8_SUB0_EP__ep__MAX 0xffffffff
5638
5639 #define R_DMA_CH8_SUB0_EP__ep__MIN 0
5640
5641 #define R_DMA_CH8_SUB0_EP__ep__BITNR 0
5642
5643 #define R_DMA_CH8_SUB0_EP__ep__ep__VAL REG_VAL_VAL
5644
5645
5646 #endif
5647
5648 /*
5649 * R_DMA_CH8_SUB1_CLR_INTR
5650 * - type: WO
5651 * - addr: 0xb00001e7
5652 * - group: DMA registers
5653 */
5654
5655 #if USE_GROUP__DMA_registers
5656
5657 #define R_DMA_CH8_SUB1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e7)
5658
5659 #ifndef REG_NO_SHADOW
5660 #define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0))
5661 #define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0))
5662 #else /* REG_NO_SHADOW */
5663 #define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
5664 #define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
5665 #endif /* REG_NO_SHADOW */
5666
5667 #define R_DMA_CH8_SUB1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
5668 #define R_DMA_CH8_SUB1_CLR_INTR__SVAL REG_SVAL_ZERO
5669 #define R_DMA_CH8_SUB1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
5670 #define R_DMA_CH8_SUB1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
5671 #define R_DMA_CH8_SUB1_CLR_INTR__TYPE (REG_BYTE)
5672 #define R_DMA_CH8_SUB1_CLR_INTR__GET REG_GET_WO
5673 #define R_DMA_CH8_SUB1_CLR_INTR__IGET REG_IGET_WO
5674 #define R_DMA_CH8_SUB1_CLR_INTR__SET REG_SET_WO
5675 #define R_DMA_CH8_SUB1_CLR_INTR__ISET REG_ISET_WO
5676 #define R_DMA_CH8_SUB1_CLR_INTR__SET_VAL REG_SET_VAL_WO
5677 #define R_DMA_CH8_SUB1_CLR_INTR__EQL REG_EQL_WO
5678 #define R_DMA_CH8_SUB1_CLR_INTR__IEQL REG_IEQL_WO
5679 #define R_DMA_CH8_SUB1_CLR_INTR__RD REG_RD_WO
5680 #define R_DMA_CH8_SUB1_CLR_INTR__IRD REG_IRD_WO
5681 #define R_DMA_CH8_SUB1_CLR_INTR__WR REG_WR_WO
5682 #define R_DMA_CH8_SUB1_CLR_INTR__IWR REG_IWR_WO
5683
5684 #define R_DMA_CH8_SUB1_CLR_INTR__WRITE(addr,value) \
5685 (*(addr) = (value))
5686
5687 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
5688
5689 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MAX 0x1
5690
5691 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MIN 0
5692
5693 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
5694
5695 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
5696
5697 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__do 1
5698 #define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__dont 0
5699
5700 #endif
5701
5702 /*
5703 * R_DMA_CH8_SUB1_CMD
5704 * - type: RW
5705 * - addr: 0xb00001d7
5706 * - group: DMA registers
5707 */
5708
5709 #if USE_GROUP__DMA_registers
5710
5711 #define R_DMA_CH8_SUB1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d7)
5712 #define R_DMA_CH8_SUB1_CMD__SVAL REG_SVAL_SHADOW
5713 #define R_DMA_CH8_SUB1_CMD__SVAL_I REG_SVAL_I_SHADOW
5714 #define R_DMA_CH8_SUB1_CMD__TYPECAST REG_TYPECAST_BYTE
5715 #define R_DMA_CH8_SUB1_CMD__TYPE (REG_BYTE)
5716 #define R_DMA_CH8_SUB1_CMD__GET REG_GET_RW
5717 #define R_DMA_CH8_SUB1_CMD__IGET REG_IGET_RW
5718 #define R_DMA_CH8_SUB1_CMD__SET REG_SET_RW
5719 #define R_DMA_CH8_SUB1_CMD__ISET REG_ISET_RW
5720 #define R_DMA_CH8_SUB1_CMD__SET_VAL REG_SET_VAL_RW
5721 #define R_DMA_CH8_SUB1_CMD__EQL REG_EQL_RW
5722 #define R_DMA_CH8_SUB1_CMD__IEQL REG_IEQL_RW
5723 #define R_DMA_CH8_SUB1_CMD__RD REG_RD_RW
5724 #define R_DMA_CH8_SUB1_CMD__IRD REG_IRD_RW
5725 #define R_DMA_CH8_SUB1_CMD__WR REG_WR_RW
5726 #define R_DMA_CH8_SUB1_CMD__IWR REG_IWR_RW
5727
5728 #define R_DMA_CH8_SUB1_CMD__WRITE(addr,value) \
5729 (*(addr) = (value))
5730 #define R_DMA_CH8_SUB1_CMD__READ(addr) \
5731 (*(addr))
5732
5733 #define R_DMA_CH8_SUB1_CMD__cmd__cmd__MASK 0x00000001U
5734
5735 #define R_DMA_CH8_SUB1_CMD__cmd__MAX 0x1
5736
5737 #define R_DMA_CH8_SUB1_CMD__cmd__MIN 0
5738
5739 #define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
5740
5741 #define R_DMA_CH8_SUB1_CMD__cmd__cmd__VAL REG_VAL_ENUM
5742
5743 #define R_DMA_CH8_SUB1_CMD__cmd__cmd__start 1
5744 #define R_DMA_CH8_SUB1_CMD__cmd__cmd__stop 0
5745
5746 #endif
5747
5748 /*
5749 * R_DMA_CH8_SUB1_EP
5750 * - type: RW
5751 * - addr: 0xb00001cc
5752 * - group: DMA registers
5753 */
5754
5755 #if USE_GROUP__DMA_registers
5756
5757 #define R_DMA_CH8_SUB1_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001cc)
5758 #define R_DMA_CH8_SUB1_EP__SVAL REG_SVAL_SHADOW
5759 #define R_DMA_CH8_SUB1_EP__SVAL_I REG_SVAL_I_SHADOW
5760 #define R_DMA_CH8_SUB1_EP__TYPECAST REG_TYPECAST_UDWORD
5761 #define R_DMA_CH8_SUB1_EP__TYPE (REG_UDWORD)
5762 #define R_DMA_CH8_SUB1_EP__GET REG_GET_RW
5763 #define R_DMA_CH8_SUB1_EP__IGET REG_IGET_RW
5764 #define R_DMA_CH8_SUB1_EP__SET REG_SET_RW
5765 #define R_DMA_CH8_SUB1_EP__ISET REG_ISET_RW
5766 #define R_DMA_CH8_SUB1_EP__SET_VAL REG_SET_VAL_RW
5767 #define R_DMA_CH8_SUB1_EP__EQL REG_EQL_RW
5768 #define R_DMA_CH8_SUB1_EP__IEQL REG_IEQL_RW
5769 #define R_DMA_CH8_SUB1_EP__RD REG_RD_RW
5770 #define R_DMA_CH8_SUB1_EP__IRD REG_IRD_RW
5771 #define R_DMA_CH8_SUB1_EP__WR REG_WR_RW
5772 #define R_DMA_CH8_SUB1_EP__IWR REG_IWR_RW
5773
5774 #define R_DMA_CH8_SUB1_EP__WRITE(addr,value) \
5775 (*(addr) = (value))
5776 #define R_DMA_CH8_SUB1_EP__READ(addr) \
5777 (*(addr))
5778
5779 #define R_DMA_CH8_SUB1_EP__ep__ep__MASK 0xffffffffU
5780
5781 #define R_DMA_CH8_SUB1_EP__ep__MAX 0xffffffff
5782
5783 #define R_DMA_CH8_SUB1_EP__ep__MIN 0
5784
5785 #define R_DMA_CH8_SUB1_EP__ep__BITNR 0
5786
5787 #define R_DMA_CH8_SUB1_EP__ep__ep__VAL REG_VAL_VAL
5788
5789
5790 #endif
5791
5792 /*
5793 * R_DMA_CH8_SUB2_CLR_INTR
5794 * - type: WO
5795 * - addr: 0xb00001eb
5796 * - group: DMA registers
5797 */
5798
5799 #if USE_GROUP__DMA_registers
5800
5801 #define R_DMA_CH8_SUB2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001eb)
5802
5803 #ifndef REG_NO_SHADOW
5804 #define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0))
5805 #define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0))
5806 #else /* REG_NO_SHADOW */
5807 #define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
5808 #define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
5809 #endif /* REG_NO_SHADOW */
5810
5811 #define R_DMA_CH8_SUB2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
5812 #define R_DMA_CH8_SUB2_CLR_INTR__SVAL REG_SVAL_ZERO
5813 #define R_DMA_CH8_SUB2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
5814 #define R_DMA_CH8_SUB2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
5815 #define R_DMA_CH8_SUB2_CLR_INTR__TYPE (REG_BYTE)
5816 #define R_DMA_CH8_SUB2_CLR_INTR__GET REG_GET_WO
5817 #define R_DMA_CH8_SUB2_CLR_INTR__IGET REG_IGET_WO
5818 #define R_DMA_CH8_SUB2_CLR_INTR__SET REG_SET_WO
5819 #define R_DMA_CH8_SUB2_CLR_INTR__ISET REG_ISET_WO
5820 #define R_DMA_CH8_SUB2_CLR_INTR__SET_VAL REG_SET_VAL_WO
5821 #define R_DMA_CH8_SUB2_CLR_INTR__EQL REG_EQL_WO
5822 #define R_DMA_CH8_SUB2_CLR_INTR__IEQL REG_IEQL_WO
5823 #define R_DMA_CH8_SUB2_CLR_INTR__RD REG_RD_WO
5824 #define R_DMA_CH8_SUB2_CLR_INTR__IRD REG_IRD_WO
5825 #define R_DMA_CH8_SUB2_CLR_INTR__WR REG_WR_WO
5826 #define R_DMA_CH8_SUB2_CLR_INTR__IWR REG_IWR_WO
5827
5828 #define R_DMA_CH8_SUB2_CLR_INTR__WRITE(addr,value) \
5829 (*(addr) = (value))
5830
5831 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
5832
5833 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MAX 0x1
5834
5835 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MIN 0
5836
5837 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
5838
5839 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
5840
5841 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__do 1
5842 #define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__dont 0
5843
5844 #endif
5845
5846 /*
5847 * R_DMA_CH8_SUB2_CMD
5848 * - type: RW
5849 * - addr: 0xb00001db
5850 * - group: DMA registers
5851 */
5852
5853 #if USE_GROUP__DMA_registers
5854
5855 #define R_DMA_CH8_SUB2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001db)
5856 #define R_DMA_CH8_SUB2_CMD__SVAL REG_SVAL_SHADOW
5857 #define R_DMA_CH8_SUB2_CMD__SVAL_I REG_SVAL_I_SHADOW
5858 #define R_DMA_CH8_SUB2_CMD__TYPECAST REG_TYPECAST_BYTE
5859 #define R_DMA_CH8_SUB2_CMD__TYPE (REG_BYTE)
5860 #define R_DMA_CH8_SUB2_CMD__GET REG_GET_RW
5861 #define R_DMA_CH8_SUB2_CMD__IGET REG_IGET_RW
5862 #define R_DMA_CH8_SUB2_CMD__SET REG_SET_RW
5863 #define R_DMA_CH8_SUB2_CMD__ISET REG_ISET_RW
5864 #define R_DMA_CH8_SUB2_CMD__SET_VAL REG_SET_VAL_RW
5865 #define R_DMA_CH8_SUB2_CMD__EQL REG_EQL_RW
5866 #define R_DMA_CH8_SUB2_CMD__IEQL REG_IEQL_RW
5867 #define R_DMA_CH8_SUB2_CMD__RD REG_RD_RW
5868 #define R_DMA_CH8_SUB2_CMD__IRD REG_IRD_RW
5869 #define R_DMA_CH8_SUB2_CMD__WR REG_WR_RW
5870 #define R_DMA_CH8_SUB2_CMD__IWR REG_IWR_RW
5871
5872 #define R_DMA_CH8_SUB2_CMD__WRITE(addr,value) \
5873 (*(addr) = (value))
5874 #define R_DMA_CH8_SUB2_CMD__READ(addr) \
5875 (*(addr))
5876
5877 #define R_DMA_CH8_SUB2_CMD__cmd__cmd__MASK 0x00000001U
5878
5879 #define R_DMA_CH8_SUB2_CMD__cmd__MAX 0x1
5880
5881 #define R_DMA_CH8_SUB2_CMD__cmd__MIN 0
5882
5883 #define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
5884
5885 #define R_DMA_CH8_SUB2_CMD__cmd__cmd__VAL REG_VAL_ENUM
5886
5887 #define R_DMA_CH8_SUB2_CMD__cmd__cmd__start 1
5888 #define R_DMA_CH8_SUB2_CMD__cmd__cmd__stop 0
5889
5890 #endif
5891
5892 /*
5893 * R_DMA_CH8_SUB2_EP
5894 * - type: RW
5895 * - addr: 0xb00001f8
5896 * - group: DMA registers
5897 */
5898
5899 #if USE_GROUP__DMA_registers
5900
5901 #define R_DMA_CH8_SUB2_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001f8)
5902 #define R_DMA_CH8_SUB2_EP__SVAL REG_SVAL_SHADOW
5903 #define R_DMA_CH8_SUB2_EP__SVAL_I REG_SVAL_I_SHADOW
5904 #define R_DMA_CH8_SUB2_EP__TYPECAST REG_TYPECAST_UDWORD
5905 #define R_DMA_CH8_SUB2_EP__TYPE (REG_UDWORD)
5906 #define R_DMA_CH8_SUB2_EP__GET REG_GET_RW
5907 #define R_DMA_CH8_SUB2_EP__IGET REG_IGET_RW
5908 #define R_DMA_CH8_SUB2_EP__SET REG_SET_RW
5909 #define R_DMA_CH8_SUB2_EP__ISET REG_ISET_RW
5910 #define R_DMA_CH8_SUB2_EP__SET_VAL REG_SET_VAL_RW
5911 #define R_DMA_CH8_SUB2_EP__EQL REG_EQL_RW
5912 #define R_DMA_CH8_SUB2_EP__IEQL REG_IEQL_RW
5913 #define R_DMA_CH8_SUB2_EP__RD REG_RD_RW
5914 #define R_DMA_CH8_SUB2_EP__IRD REG_IRD_RW
5915 #define R_DMA_CH8_SUB2_EP__WR REG_WR_RW
5916 #define R_DMA_CH8_SUB2_EP__IWR REG_IWR_RW
5917
5918 #define R_DMA_CH8_SUB2_EP__WRITE(addr,value) \
5919 (*(addr) = (value))
5920 #define R_DMA_CH8_SUB2_EP__READ(addr) \
5921 (*(addr))
5922
5923 #define R_DMA_CH8_SUB2_EP__ep__ep__MASK 0xffffffffU
5924
5925 #define R_DMA_CH8_SUB2_EP__ep__MAX 0xffffffff
5926
5927 #define R_DMA_CH8_SUB2_EP__ep__MIN 0
5928
5929 #define R_DMA_CH8_SUB2_EP__ep__BITNR 0
5930
5931 #define R_DMA_CH8_SUB2_EP__ep__ep__VAL REG_VAL_VAL
5932
5933
5934 #endif
5935
5936 /*
5937 * R_DMA_CH8_SUB3_CLR_INTR
5938 * - type: WO
5939 * - addr: 0xb00001ef
5940 * - group: DMA registers
5941 */
5942
5943 #if USE_GROUP__DMA_registers
5944
5945 #define R_DMA_CH8_SUB3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ef)
5946
5947 #ifndef REG_NO_SHADOW
5948 #define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0))
5949 #define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0))
5950 #else /* REG_NO_SHADOW */
5951 #define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
5952 #define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
5953 #endif /* REG_NO_SHADOW */
5954
5955 #define R_DMA_CH8_SUB3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
5956 #define R_DMA_CH8_SUB3_CLR_INTR__SVAL REG_SVAL_ZERO
5957 #define R_DMA_CH8_SUB3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
5958 #define R_DMA_CH8_SUB3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
5959 #define R_DMA_CH8_SUB3_CLR_INTR__TYPE (REG_BYTE)
5960 #define R_DMA_CH8_SUB3_CLR_INTR__GET REG_GET_WO
5961 #define R_DMA_CH8_SUB3_CLR_INTR__IGET REG_IGET_WO
5962 #define R_DMA_CH8_SUB3_CLR_INTR__SET REG_SET_WO
5963 #define R_DMA_CH8_SUB3_CLR_INTR__ISET REG_ISET_WO
5964 #define R_DMA_CH8_SUB3_CLR_INTR__SET_VAL REG_SET_VAL_WO
5965 #define R_DMA_CH8_SUB3_CLR_INTR__EQL REG_EQL_WO
5966 #define R_DMA_CH8_SUB3_CLR_INTR__IEQL REG_IEQL_WO
5967 #define R_DMA_CH8_SUB3_CLR_INTR__RD REG_RD_WO
5968 #define R_DMA_CH8_SUB3_CLR_INTR__IRD REG_IRD_WO
5969 #define R_DMA_CH8_SUB3_CLR_INTR__WR REG_WR_WO
5970 #define R_DMA_CH8_SUB3_CLR_INTR__IWR REG_IWR_WO
5971
5972 #define R_DMA_CH8_SUB3_CLR_INTR__WRITE(addr,value) \
5973 (*(addr) = (value))
5974
5975 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
5976
5977 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MAX 0x1
5978
5979 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MIN 0
5980
5981 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
5982
5983 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
5984
5985 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__do 1
5986 #define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__dont 0
5987
5988 #endif
5989
5990 /*
5991 * R_DMA_CH8_SUB3_CMD
5992 * - type: RW
5993 * - addr: 0xb00001df
5994 * - group: DMA registers
5995 */
5996
5997 #if USE_GROUP__DMA_registers
5998
5999 #define R_DMA_CH8_SUB3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001df)
6000 #define R_DMA_CH8_SUB3_CMD__SVAL REG_SVAL_SHADOW
6001 #define R_DMA_CH8_SUB3_CMD__SVAL_I REG_SVAL_I_SHADOW
6002 #define R_DMA_CH8_SUB3_CMD__TYPECAST REG_TYPECAST_BYTE
6003 #define R_DMA_CH8_SUB3_CMD__TYPE (REG_BYTE)
6004 #define R_DMA_CH8_SUB3_CMD__GET REG_GET_RW
6005 #define R_DMA_CH8_SUB3_CMD__IGET REG_IGET_RW
6006 #define R_DMA_CH8_SUB3_CMD__SET REG_SET_RW
6007 #define R_DMA_CH8_SUB3_CMD__ISET REG_ISET_RW
6008 #define R_DMA_CH8_SUB3_CMD__SET_VAL REG_SET_VAL_RW
6009 #define R_DMA_CH8_SUB3_CMD__EQL REG_EQL_RW
6010 #define R_DMA_CH8_SUB3_CMD__IEQL REG_IEQL_RW
6011 #define R_DMA_CH8_SUB3_CMD__RD REG_RD_RW
6012 #define R_DMA_CH8_SUB3_CMD__IRD REG_IRD_RW
6013 #define R_DMA_CH8_SUB3_CMD__WR REG_WR_RW
6014 #define R_DMA_CH8_SUB3_CMD__IWR REG_IWR_RW
6015
6016 #define R_DMA_CH8_SUB3_CMD__WRITE(addr,value) \
6017 (*(addr) = (value))
6018 #define R_DMA_CH8_SUB3_CMD__READ(addr) \
6019 (*(addr))
6020
6021 #define R_DMA_CH8_SUB3_CMD__cmd__cmd__MASK 0x00000001U
6022
6023 #define R_DMA_CH8_SUB3_CMD__cmd__MAX 0x1
6024
6025 #define R_DMA_CH8_SUB3_CMD__cmd__MIN 0
6026
6027 #define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
6028
6029 #define R_DMA_CH8_SUB3_CMD__cmd__cmd__VAL REG_VAL_ENUM
6030
6031 #define R_DMA_CH8_SUB3_CMD__cmd__cmd__start 1
6032 #define R_DMA_CH8_SUB3_CMD__cmd__cmd__stop 0
6033
6034 #endif
6035
6036 /*
6037 * R_DMA_CH8_SUB3_EP
6038 * - type: RW
6039 * - addr: 0xb00001fc
6040 * - group: DMA registers
6041 */
6042
6043 #if USE_GROUP__DMA_registers
6044
6045 #define R_DMA_CH8_SUB3_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001fc)
6046 #define R_DMA_CH8_SUB3_EP__SVAL REG_SVAL_SHADOW
6047 #define R_DMA_CH8_SUB3_EP__SVAL_I REG_SVAL_I_SHADOW
6048 #define R_DMA_CH8_SUB3_EP__TYPECAST REG_TYPECAST_UDWORD
6049 #define R_DMA_CH8_SUB3_EP__TYPE (REG_UDWORD)
6050 #define R_DMA_CH8_SUB3_EP__GET REG_GET_RW
6051 #define R_DMA_CH8_SUB3_EP__IGET REG_IGET_RW
6052 #define R_DMA_CH8_SUB3_EP__SET REG_SET_RW
6053 #define R_DMA_CH8_SUB3_EP__ISET REG_ISET_RW
6054 #define R_DMA_CH8_SUB3_EP__SET_VAL REG_SET_VAL_RW
6055 #define R_DMA_CH8_SUB3_EP__EQL REG_EQL_RW
6056 #define R_DMA_CH8_SUB3_EP__IEQL REG_IEQL_RW
6057 #define R_DMA_CH8_SUB3_EP__RD REG_RD_RW
6058 #define R_DMA_CH8_SUB3_EP__IRD REG_IRD_RW
6059 #define R_DMA_CH8_SUB3_EP__WR REG_WR_RW
6060 #define R_DMA_CH8_SUB3_EP__IWR REG_IWR_RW
6061
6062 #define R_DMA_CH8_SUB3_EP__WRITE(addr,value) \
6063 (*(addr) = (value))
6064 #define R_DMA_CH8_SUB3_EP__READ(addr) \
6065 (*(addr))
6066
6067 #define R_DMA_CH8_SUB3_EP__ep__ep__MASK 0xffffffffU
6068
6069 #define R_DMA_CH8_SUB3_EP__ep__MAX 0xffffffff
6070
6071 #define R_DMA_CH8_SUB3_EP__ep__MIN 0
6072
6073 #define R_DMA_CH8_SUB3_EP__ep__BITNR 0
6074
6075 #define R_DMA_CH8_SUB3_EP__ep__ep__VAL REG_VAL_VAL
6076
6077
6078 #endif
6079
6080 /*
6081 * R_DMA_CH9_BUF
6082 * - type: RW
6083 * - addr: 0xb0000198
6084 * - group: DMA registers
6085 */
6086
6087 #if USE_GROUP__DMA_registers
6088
6089 #define R_DMA_CH9_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000198)
6090 #define R_DMA_CH9_BUF__SVAL REG_SVAL_SHADOW
6091 #define R_DMA_CH9_BUF__SVAL_I REG_SVAL_I_SHADOW
6092 #define R_DMA_CH9_BUF__TYPECAST REG_TYPECAST_UDWORD
6093 #define R_DMA_CH9_BUF__TYPE (REG_UDWORD)
6094 #define R_DMA_CH9_BUF__GET REG_GET_RW
6095 #define R_DMA_CH9_BUF__IGET REG_IGET_RW
6096 #define R_DMA_CH9_BUF__SET REG_SET_RW
6097 #define R_DMA_CH9_BUF__ISET REG_ISET_RW
6098 #define R_DMA_CH9_BUF__SET_VAL REG_SET_VAL_RW
6099 #define R_DMA_CH9_BUF__EQL REG_EQL_RW
6100 #define R_DMA_CH9_BUF__IEQL REG_IEQL_RW
6101 #define R_DMA_CH9_BUF__RD REG_RD_RW
6102 #define R_DMA_CH9_BUF__IRD REG_IRD_RW
6103 #define R_DMA_CH9_BUF__WR REG_WR_RW
6104 #define R_DMA_CH9_BUF__IWR REG_IWR_RW
6105
6106 #define R_DMA_CH9_BUF__WRITE(addr,value) \
6107 (*(addr) = (value))
6108 #define R_DMA_CH9_BUF__READ(addr) \
6109 (*(addr))
6110
6111 #define R_DMA_CH9_BUF__buf__buf__MASK 0xffffffffU
6112
6113 #define R_DMA_CH9_BUF__buf__MAX 0xffffffff
6114
6115 #define R_DMA_CH9_BUF__buf__MIN 0
6116
6117 #define R_DMA_CH9_BUF__buf__BITNR 0
6118
6119 #define R_DMA_CH9_BUF__buf__buf__VAL REG_VAL_VAL
6120
6121
6122 #endif
6123
6124 /*
6125 * R_DMA_CH9_CLR_INTR
6126 * - type: WO
6127 * - addr: 0xb00001f5
6128 * - group: DMA registers
6129 */
6130
6131 #if USE_GROUP__DMA_registers
6132
6133 #define R_DMA_CH9_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f5)
6134
6135 #ifndef REG_NO_SHADOW
6136 #define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH9_CLR_INTR + 0))
6137 #define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH9_CLR_INTR + 0))
6138 #else /* REG_NO_SHADOW */
6139 #define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
6140 #define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
6141 #endif /* REG_NO_SHADOW */
6142
6143 #define R_DMA_CH9_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
6144 #define R_DMA_CH9_CLR_INTR__SVAL REG_SVAL_ZERO
6145 #define R_DMA_CH9_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
6146 #define R_DMA_CH9_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
6147 #define R_DMA_CH9_CLR_INTR__TYPE (REG_BYTE)
6148 #define R_DMA_CH9_CLR_INTR__GET REG_GET_WO
6149 #define R_DMA_CH9_CLR_INTR__IGET REG_IGET_WO
6150 #define R_DMA_CH9_CLR_INTR__SET REG_SET_WO
6151 #define R_DMA_CH9_CLR_INTR__ISET REG_ISET_WO
6152 #define R_DMA_CH9_CLR_INTR__SET_VAL REG_SET_VAL_WO
6153 #define R_DMA_CH9_CLR_INTR__EQL REG_EQL_WO
6154 #define R_DMA_CH9_CLR_INTR__IEQL REG_IEQL_WO
6155 #define R_DMA_CH9_CLR_INTR__RD REG_RD_WO
6156 #define R_DMA_CH9_CLR_INTR__IRD REG_IRD_WO
6157 #define R_DMA_CH9_CLR_INTR__WR REG_WR_WO
6158 #define R_DMA_CH9_CLR_INTR__IWR REG_IWR_WO
6159
6160 #define R_DMA_CH9_CLR_INTR__WRITE(addr,value) \
6161 (*(addr) = (value))
6162
6163 #define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
6164 #define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
6165
6166 #define R_DMA_CH9_CLR_INTR__clr_eop__MAX 0x1
6167 #define R_DMA_CH9_CLR_INTR__clr_descr__MAX 0x1
6168
6169 #define R_DMA_CH9_CLR_INTR__clr_eop__MIN 0
6170 #define R_DMA_CH9_CLR_INTR__clr_descr__MIN 0
6171
6172 #define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
6173 #define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
6174
6175 #define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
6176 #define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
6177
6178 #define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__do 1
6179 #define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__dont 0
6180 #define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__do 1
6181 #define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__dont 0
6182
6183 #endif
6184
6185 /*
6186 * R_DMA_CH9_CMD
6187 * - type: RW
6188 * - addr: 0xb00001f4
6189 * - group: DMA registers
6190 */
6191
6192 #if USE_GROUP__DMA_registers
6193
6194 #define R_DMA_CH9_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f4)
6195 #define R_DMA_CH9_CMD__SVAL REG_SVAL_SHADOW
6196 #define R_DMA_CH9_CMD__SVAL_I REG_SVAL_I_SHADOW
6197 #define R_DMA_CH9_CMD__TYPECAST REG_TYPECAST_BYTE
6198 #define R_DMA_CH9_CMD__TYPE (REG_BYTE)
6199 #define R_DMA_CH9_CMD__GET REG_GET_RW
6200 #define R_DMA_CH9_CMD__IGET REG_IGET_RW
6201 #define R_DMA_CH9_CMD__SET REG_SET_RW
6202 #define R_DMA_CH9_CMD__ISET REG_ISET_RW
6203 #define R_DMA_CH9_CMD__SET_VAL REG_SET_VAL_RW
6204 #define R_DMA_CH9_CMD__EQL REG_EQL_RW
6205 #define R_DMA_CH9_CMD__IEQL REG_IEQL_RW
6206 #define R_DMA_CH9_CMD__RD REG_RD_RW
6207 #define R_DMA_CH9_CMD__IRD REG_IRD_RW
6208 #define R_DMA_CH9_CMD__WR REG_WR_RW
6209 #define R_DMA_CH9_CMD__IWR REG_IWR_RW
6210
6211 #define R_DMA_CH9_CMD__WRITE(addr,value) \
6212 (*(addr) = (value))
6213 #define R_DMA_CH9_CMD__READ(addr) \
6214 (*(addr))
6215
6216 #define R_DMA_CH9_CMD__cmd__cmd__MASK 0x00000007U
6217
6218 #define R_DMA_CH9_CMD__cmd__MAX 0x7
6219
6220 #define R_DMA_CH9_CMD__cmd__MIN 0
6221
6222 #define R_DMA_CH9_CMD__cmd__BITNR 0
6223
6224 #define R_DMA_CH9_CMD__cmd__cmd__VAL REG_VAL_ENUM
6225
6226 #define R_DMA_CH9_CMD__cmd__cmd__continue 3
6227 #define R_DMA_CH9_CMD__cmd__cmd__hold 0
6228 #define R_DMA_CH9_CMD__cmd__cmd__reset 4
6229 #define R_DMA_CH9_CMD__cmd__cmd__restart 3
6230 #define R_DMA_CH9_CMD__cmd__cmd__start 1
6231
6232 #endif
6233
6234 /*
6235 * R_DMA_CH9_DESCR
6236 * - type: RW
6237 * - addr: 0xb000019c
6238 * - group: DMA registers
6239 */
6240
6241 #if USE_GROUP__DMA_registers
6242
6243 #define R_DMA_CH9_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000019c)
6244 #define R_DMA_CH9_DESCR__SVAL REG_SVAL_SHADOW
6245 #define R_DMA_CH9_DESCR__SVAL_I REG_SVAL_I_SHADOW
6246 #define R_DMA_CH9_DESCR__TYPECAST REG_TYPECAST_UDWORD
6247 #define R_DMA_CH9_DESCR__TYPE (REG_UDWORD)
6248 #define R_DMA_CH9_DESCR__GET REG_GET_RW
6249 #define R_DMA_CH9_DESCR__IGET REG_IGET_RW
6250 #define R_DMA_CH9_DESCR__SET REG_SET_RW
6251 #define R_DMA_CH9_DESCR__ISET REG_ISET_RW
6252 #define R_DMA_CH9_DESCR__SET_VAL REG_SET_VAL_RW
6253 #define R_DMA_CH9_DESCR__EQL REG_EQL_RW
6254 #define R_DMA_CH9_DESCR__IEQL REG_IEQL_RW
6255 #define R_DMA_CH9_DESCR__RD REG_RD_RW
6256 #define R_DMA_CH9_DESCR__IRD REG_IRD_RW
6257 #define R_DMA_CH9_DESCR__WR REG_WR_RW
6258 #define R_DMA_CH9_DESCR__IWR REG_IWR_RW
6259
6260 #define R_DMA_CH9_DESCR__WRITE(addr,value) \
6261 (*(addr) = (value))
6262 #define R_DMA_CH9_DESCR__READ(addr) \
6263 (*(addr))
6264
6265 #define R_DMA_CH9_DESCR__descr__descr__MASK 0xffffffffU
6266
6267 #define R_DMA_CH9_DESCR__descr__MAX 0xffffffff
6268
6269 #define R_DMA_CH9_DESCR__descr__MIN 0
6270
6271 #define R_DMA_CH9_DESCR__descr__BITNR 0
6272
6273 #define R_DMA_CH9_DESCR__descr__descr__VAL REG_VAL_VAL
6274
6275
6276 #endif
6277
6278 /*
6279 * R_DMA_CH9_FIRST
6280 * - type: RW
6281 * - addr: 0xb00001c4
6282 * - group: DMA registers
6283 */
6284
6285 #if USE_GROUP__DMA_registers
6286
6287 #define R_DMA_CH9_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c4)
6288 #define R_DMA_CH9_FIRST__SVAL REG_SVAL_SHADOW
6289 #define R_DMA_CH9_FIRST__SVAL_I REG_SVAL_I_SHADOW
6290 #define R_DMA_CH9_FIRST__TYPECAST REG_TYPECAST_UDWORD
6291 #define R_DMA_CH9_FIRST__TYPE (REG_UDWORD)
6292 #define R_DMA_CH9_FIRST__GET REG_GET_RW
6293 #define R_DMA_CH9_FIRST__IGET REG_IGET_RW
6294 #define R_DMA_CH9_FIRST__SET REG_SET_RW
6295 #define R_DMA_CH9_FIRST__ISET REG_ISET_RW
6296 #define R_DMA_CH9_FIRST__SET_VAL REG_SET_VAL_RW
6297 #define R_DMA_CH9_FIRST__EQL REG_EQL_RW
6298 #define R_DMA_CH9_FIRST__IEQL REG_IEQL_RW
6299 #define R_DMA_CH9_FIRST__RD REG_RD_RW
6300 #define R_DMA_CH9_FIRST__IRD REG_IRD_RW
6301 #define R_DMA_CH9_FIRST__WR REG_WR_RW
6302 #define R_DMA_CH9_FIRST__IWR REG_IWR_RW
6303
6304 #define R_DMA_CH9_FIRST__WRITE(addr,value) \
6305 (*(addr) = (value))
6306 #define R_DMA_CH9_FIRST__READ(addr) \
6307 (*(addr))
6308
6309 #define R_DMA_CH9_FIRST__first__first__MASK 0xffffffffU
6310
6311 #define R_DMA_CH9_FIRST__first__MAX 0xffffffff
6312
6313 #define R_DMA_CH9_FIRST__first__MIN 0
6314
6315 #define R_DMA_CH9_FIRST__first__BITNR 0
6316
6317 #define R_DMA_CH9_FIRST__first__first__VAL REG_VAL_VAL
6318
6319
6320 #endif
6321
6322 /*
6323 * R_DMA_CH9_HWSW
6324 * - type: RW
6325 * - addr: 0xb0000190
6326 * - group: DMA registers
6327 */
6328
6329 #if USE_GROUP__DMA_registers
6330
6331 #define R_DMA_CH9_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000190)
6332 #define R_DMA_CH9_HWSW__SVAL REG_SVAL_SHADOW
6333 #define R_DMA_CH9_HWSW__SVAL_I REG_SVAL_I_SHADOW
6334 #define R_DMA_CH9_HWSW__TYPECAST REG_TYPECAST_UDWORD
6335 #define R_DMA_CH9_HWSW__TYPE (REG_UDWORD)
6336 #define R_DMA_CH9_HWSW__GET REG_GET_RW
6337 #define R_DMA_CH9_HWSW__IGET REG_IGET_RW
6338 #define R_DMA_CH9_HWSW__SET REG_SET_RW
6339 #define R_DMA_CH9_HWSW__ISET REG_ISET_RW
6340 #define R_DMA_CH9_HWSW__SET_VAL REG_SET_VAL_RW
6341 #define R_DMA_CH9_HWSW__EQL REG_EQL_RW
6342 #define R_DMA_CH9_HWSW__IEQL REG_IEQL_RW
6343 #define R_DMA_CH9_HWSW__RD REG_RD_RW
6344 #define R_DMA_CH9_HWSW__IRD REG_IRD_RW
6345 #define R_DMA_CH9_HWSW__WR REG_WR_RW
6346 #define R_DMA_CH9_HWSW__IWR REG_IWR_RW
6347
6348 #define R_DMA_CH9_HWSW__WRITE(addr,value) \
6349 (*(addr) = (value))
6350 #define R_DMA_CH9_HWSW__READ(addr) \
6351 (*(addr))
6352
6353 #define R_DMA_CH9_HWSW__hw__hw__MASK 0xffff0000U
6354 #define R_DMA_CH9_HWSW__sw__sw__MASK 0x0000ffffU
6355
6356 #define R_DMA_CH9_HWSW__hw__MAX 0xffff
6357 #define R_DMA_CH9_HWSW__sw__MAX 0xffff
6358
6359 #define R_DMA_CH9_HWSW__hw__MIN 0
6360 #define R_DMA_CH9_HWSW__sw__MIN 0
6361
6362 #define R_DMA_CH9_HWSW__hw__BITNR 16
6363 #define R_DMA_CH9_HWSW__sw__BITNR 0
6364
6365 #define R_DMA_CH9_HWSW__hw__hw__VAL REG_VAL_VAL
6366 #define R_DMA_CH9_HWSW__sw__sw__VAL REG_VAL_VAL
6367
6368
6369 #endif
6370
6371 /*
6372 * R_DMA_CH9_NEXT
6373 * - type: RW
6374 * - addr: 0xb0000194
6375 * - group: DMA registers
6376 */
6377
6378 #if USE_GROUP__DMA_registers
6379
6380 #define R_DMA_CH9_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000194)
6381 #define R_DMA_CH9_NEXT__SVAL REG_SVAL_SHADOW
6382 #define R_DMA_CH9_NEXT__SVAL_I REG_SVAL_I_SHADOW
6383 #define R_DMA_CH9_NEXT__TYPECAST REG_TYPECAST_UDWORD
6384 #define R_DMA_CH9_NEXT__TYPE (REG_UDWORD)
6385 #define R_DMA_CH9_NEXT__GET REG_GET_RW
6386 #define R_DMA_CH9_NEXT__IGET REG_IGET_RW
6387 #define R_DMA_CH9_NEXT__SET REG_SET_RW
6388 #define R_DMA_CH9_NEXT__ISET REG_ISET_RW
6389 #define R_DMA_CH9_NEXT__SET_VAL REG_SET_VAL_RW
6390 #define R_DMA_CH9_NEXT__EQL REG_EQL_RW
6391 #define R_DMA_CH9_NEXT__IEQL REG_IEQL_RW
6392 #define R_DMA_CH9_NEXT__RD REG_RD_RW
6393 #define R_DMA_CH9_NEXT__IRD REG_IRD_RW
6394 #define R_DMA_CH9_NEXT__WR REG_WR_RW
6395 #define R_DMA_CH9_NEXT__IWR REG_IWR_RW
6396
6397 #define R_DMA_CH9_NEXT__WRITE(addr,value) \
6398 (*(addr) = (value))
6399 #define R_DMA_CH9_NEXT__READ(addr) \
6400 (*(addr))
6401
6402 #define R_DMA_CH9_NEXT__next__next__MASK 0xffffffffU
6403
6404 #define R_DMA_CH9_NEXT__next__MAX 0xffffffff
6405
6406 #define R_DMA_CH9_NEXT__next__MIN 0
6407
6408 #define R_DMA_CH9_NEXT__next__BITNR 0
6409
6410 #define R_DMA_CH9_NEXT__next__next__VAL REG_VAL_VAL
6411
6412
6413 #endif
6414
6415 /*
6416 * R_DMA_CH9_STATUS
6417 * - type: RO
6418 * - addr: 0xb00001f6
6419 * - group: DMA registers
6420 */
6421
6422 #if USE_GROUP__DMA_registers
6423
6424 #define R_DMA_CH9_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f6)
6425 #define R_DMA_CH9_STATUS__SVAL REG_SVAL_SHADOW
6426 #define R_DMA_CH9_STATUS__SVAL_I REG_SVAL_I_SHADOW
6427 #define R_DMA_CH9_STATUS__TYPECAST REG_TYPECAST_BYTE
6428 #define R_DMA_CH9_STATUS__TYPE (REG_BYTE)
6429 #define R_DMA_CH9_STATUS__GET REG_GET_RO
6430 #define R_DMA_CH9_STATUS__IGET REG_IGET_RO
6431 #define R_DMA_CH9_STATUS__SET REG_SET_RO
6432 #define R_DMA_CH9_STATUS__ISET REG_ISET_RO
6433 #define R_DMA_CH9_STATUS__SET_VAL REG_SET_VAL_RO
6434 #define R_DMA_CH9_STATUS__EQL REG_EQL_RO
6435 #define R_DMA_CH9_STATUS__IEQL REG_IEQL_RO
6436 #define R_DMA_CH9_STATUS__RD REG_RD_RO
6437 #define R_DMA_CH9_STATUS__IRD REG_IRD_RO
6438 #define R_DMA_CH9_STATUS__WR REG_WR_RO
6439 #define R_DMA_CH9_STATUS__IWR REG_IWR_RO
6440
6441 #define R_DMA_CH9_STATUS__READ(addr) \
6442 (*(addr))
6443
6444 #define R_DMA_CH9_STATUS__avail__avail__MASK 0x0000007fU
6445
6446 #define R_DMA_CH9_STATUS__avail__MAX 0x7f
6447
6448 #define R_DMA_CH9_STATUS__avail__MIN 0
6449
6450 #define R_DMA_CH9_STATUS__avail__BITNR 0
6451
6452 #define R_DMA_CH9_STATUS__avail__avail__VAL REG_VAL_VAL
6453
6454
6455 #endif
6456
6457 /*
6458 * R_DRAM_CONFIG
6459 * - type: WO
6460 * - addr: 0xb000000c
6461 * - group: Bus interface configuration registers
6462 */
6463
6464 #if USE_GROUP__Bus_interface_configuration_registers
6465
6466 #define R_DRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c)
6467
6468 #ifndef REG_NO_SHADOW
6469 #define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0))
6470 #define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0))
6471 #else /* REG_NO_SHADOW */
6472 #define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
6473 #define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
6474 #endif /* REG_NO_SHADOW */
6475
6476 #define R_DRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
6477 #define R_DRAM_CONFIG__SVAL REG_SVAL_SHADOW
6478 #define R_DRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
6479 #define R_DRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
6480 #define R_DRAM_CONFIG__TYPE (REG_UDWORD)
6481 #define R_DRAM_CONFIG__GET REG_GET_WO
6482 #define R_DRAM_CONFIG__IGET REG_IGET_WO
6483 #define R_DRAM_CONFIG__SET REG_SET_WO
6484 #define R_DRAM_CONFIG__ISET REG_ISET_WO
6485 #define R_DRAM_CONFIG__SET_VAL REG_SET_VAL_WO
6486 #define R_DRAM_CONFIG__EQL REG_EQL_WO
6487 #define R_DRAM_CONFIG__IEQL REG_IEQL_WO
6488 #define R_DRAM_CONFIG__RD REG_RD_WO
6489 #define R_DRAM_CONFIG__IRD REG_IRD_WO
6490 #define R_DRAM_CONFIG__WR REG_WR_WO
6491 #define R_DRAM_CONFIG__IWR REG_IWR_WO
6492
6493 #define R_DRAM_CONFIG__WRITE(addr,value) \
6494 (*(addr) = (value))
6495
6496 #define R_DRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U
6497 #define R_DRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U
6498 #define R_DRAM_CONFIG__sh1__sh1__MASK 0x38000000U
6499 #define R_DRAM_CONFIG__sh0__sh0__MASK 0x07000000U
6500 #define R_DRAM_CONFIG__w__w__MASK 0x00800000U
6501 #define R_DRAM_CONFIG__c__c__MASK 0x00400000U
6502 #define R_DRAM_CONFIG__e__e__MASK 0x00200000U
6503 #define R_DRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U
6504 #define R_DRAM_CONFIG__ca1__ca1__MASK 0x0000e000U
6505 #define R_DRAM_CONFIG__bank23sel__bank23sel__MASK 0x00001f00U
6506 #define R_DRAM_CONFIG__ca0__ca0__MASK 0x000000e0U
6507 #define R_DRAM_CONFIG__bank01sel__bank01sel__MASK 0x0000001fU
6508
6509 #define R_DRAM_CONFIG__wmm1__MAX 0x1
6510 #define R_DRAM_CONFIG__wmm0__MAX 0x1
6511 #define R_DRAM_CONFIG__sh1__MAX 7
6512 #define R_DRAM_CONFIG__sh0__MAX 7
6513 #define R_DRAM_CONFIG__w__MAX 0x1
6514 #define R_DRAM_CONFIG__c__MAX 0x1
6515 #define R_DRAM_CONFIG__e__MAX 0x1
6516 #define R_DRAM_CONFIG__group_sel__MAX 0x1f
6517 #define R_DRAM_CONFIG__ca1__MAX 7
6518 #define R_DRAM_CONFIG__bank23sel__MAX 0x1f
6519 #define R_DRAM_CONFIG__ca0__MAX 7
6520 #define R_DRAM_CONFIG__bank01sel__MAX 0x1f
6521
6522 #define R_DRAM_CONFIG__wmm1__MIN 0
6523 #define R_DRAM_CONFIG__wmm0__MIN 0
6524 #define R_DRAM_CONFIG__sh1__MIN 0
6525 #define R_DRAM_CONFIG__sh0__MIN 0
6526 #define R_DRAM_CONFIG__w__MIN 0
6527 #define R_DRAM_CONFIG__c__MIN 0
6528 #define R_DRAM_CONFIG__e__MIN 0
6529 #define R_DRAM_CONFIG__group_sel__MIN 0
6530 #define R_DRAM_CONFIG__ca1__MIN 0
6531 #define R_DRAM_CONFIG__bank23sel__MIN 0
6532 #define R_DRAM_CONFIG__ca0__MIN 0
6533 #define R_DRAM_CONFIG__bank01sel__MIN 0
6534
6535 #define R_DRAM_CONFIG__wmm1__BITNR 31
6536 #define R_DRAM_CONFIG__wmm0__BITNR 30
6537 #define R_DRAM_CONFIG__sh1__BITNR 27
6538 #define R_DRAM_CONFIG__sh0__BITNR 24
6539 #define R_DRAM_CONFIG__w__BITNR 23
6540 #define R_DRAM_CONFIG__c__BITNR 22
6541 #define R_DRAM_CONFIG__e__BITNR 21
6542 #define R_DRAM_CONFIG__group_sel__BITNR 16
6543 #define R_DRAM_CONFIG__ca1__BITNR 13
6544 #define R_DRAM_CONFIG__bank23sel__BITNR 8
6545 #define R_DRAM_CONFIG__ca0__BITNR 5
6546 #define R_DRAM_CONFIG__bank01sel__BITNR 0
6547
6548 #define R_DRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM
6549 #define R_DRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM
6550 #define R_DRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL
6551 #define R_DRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL
6552 #define R_DRAM_CONFIG__w__w__VAL REG_VAL_ENUM
6553 #define R_DRAM_CONFIG__c__c__VAL REG_VAL_ENUM
6554 #define R_DRAM_CONFIG__e__e__VAL REG_VAL_ENUM
6555 #define R_DRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM
6556 #define R_DRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL
6557 #define R_DRAM_CONFIG__bank23sel__bank23sel__VAL REG_VAL_ENUM
6558 #define R_DRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL
6559 #define R_DRAM_CONFIG__bank01sel__bank01sel__VAL REG_VAL_ENUM
6560
6561 #define R_DRAM_CONFIG__wmm1__wmm1__norm 0
6562 #define R_DRAM_CONFIG__wmm1__wmm1__wmm 1
6563 #define R_DRAM_CONFIG__wmm0__wmm0__norm 0
6564 #define R_DRAM_CONFIG__wmm0__wmm0__wmm 1
6565 #define R_DRAM_CONFIG__w__w__bw16 0
6566 #define R_DRAM_CONFIG__w__w__bw32 1
6567 #define R_DRAM_CONFIG__c__c__bank 1
6568 #define R_DRAM_CONFIG__c__c__byte 0
6569 #define R_DRAM_CONFIG__e__e__edo 1
6570 #define R_DRAM_CONFIG__e__e__fast 0
6571 #define R_DRAM_CONFIG__group_sel__group_sel__bit10 10
6572 #define R_DRAM_CONFIG__group_sel__group_sel__bit11 11
6573 #define R_DRAM_CONFIG__group_sel__group_sel__bit12 12
6574 #define R_DRAM_CONFIG__group_sel__group_sel__bit13 13
6575 #define R_DRAM_CONFIG__group_sel__group_sel__bit14 14
6576 #define R_DRAM_CONFIG__group_sel__group_sel__bit15 15
6577 #define R_DRAM_CONFIG__group_sel__group_sel__bit16 16
6578 #define R_DRAM_CONFIG__group_sel__group_sel__bit17 17
6579 #define R_DRAM_CONFIG__group_sel__group_sel__bit18 18
6580 #define R_DRAM_CONFIG__group_sel__group_sel__bit19 19
6581 #define R_DRAM_CONFIG__group_sel__group_sel__bit20 20
6582 #define R_DRAM_CONFIG__group_sel__group_sel__bit21 21
6583 #define R_DRAM_CONFIG__group_sel__group_sel__bit22 22
6584 #define R_DRAM_CONFIG__group_sel__group_sel__bit23 23
6585 #define R_DRAM_CONFIG__group_sel__group_sel__bit24 24
6586 #define R_DRAM_CONFIG__group_sel__group_sel__bit25 25
6587 #define R_DRAM_CONFIG__group_sel__group_sel__bit26 26
6588 #define R_DRAM_CONFIG__group_sel__group_sel__bit27 27
6589 #define R_DRAM_CONFIG__group_sel__group_sel__bit28 28
6590 #define R_DRAM_CONFIG__group_sel__group_sel__bit29 29
6591 #define R_DRAM_CONFIG__group_sel__group_sel__bit9 9
6592 #define R_DRAM_CONFIG__group_sel__group_sel__grp0 0
6593 #define R_DRAM_CONFIG__group_sel__group_sel__grp1 1
6594 #define R_DRAM_CONFIG__bank23sel__bank23sel__bank0 0
6595 #define R_DRAM_CONFIG__bank23sel__bank23sel__bank1 1
6596 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit10 10
6597 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit11 11
6598 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit12 12
6599 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit13 13
6600 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit14 14
6601 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit15 15
6602 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit16 16
6603 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit17 17
6604 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit18 18
6605 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit19 19
6606 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit20 20
6607 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit21 21
6608 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit22 22
6609 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit23 23
6610 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit24 24
6611 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit25 25
6612 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit26 26
6613 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit27 27
6614 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit28 28
6615 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit29 29
6616 #define R_DRAM_CONFIG__bank23sel__bank23sel__bit9 9
6617 #define R_DRAM_CONFIG__bank01sel__bank01sel__bank0 0
6618 #define R_DRAM_CONFIG__bank01sel__bank01sel__bank1 1
6619 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit10 10
6620 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit11 11
6621 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit12 12
6622 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit13 13
6623 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit14 14
6624 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit15 15
6625 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit16 16
6626 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit17 17
6627 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit18 18
6628 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit19 19
6629 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit20 20
6630 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit21 21
6631 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit22 22
6632 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit23 23
6633 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit24 24
6634 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit25 25
6635 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit26 26
6636 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit27 27
6637 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit28 28
6638 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit29 29
6639 #define R_DRAM_CONFIG__bank01sel__bank01sel__bit9 9
6640
6641 #endif
6642
6643 /*
6644 * R_DRAM_TIMING
6645 * - type: WO
6646 * - addr: 0xb0000008
6647 * - group: Bus interface configuration registers
6648 */
6649
6650 #if USE_GROUP__Bus_interface_configuration_registers
6651
6652 #define R_DRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008)
6653
6654 #ifndef REG_NO_SHADOW
6655 #define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0))
6656 #define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0))
6657 #else /* REG_NO_SHADOW */
6658 #define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
6659 #define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
6660 #endif /* REG_NO_SHADOW */
6661
6662 #define R_DRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD
6663 #define R_DRAM_TIMING__SVAL REG_SVAL_SHADOW
6664 #define R_DRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW
6665 #define R_DRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD
6666 #define R_DRAM_TIMING__TYPE (REG_UDWORD)
6667 #define R_DRAM_TIMING__GET REG_GET_WO
6668 #define R_DRAM_TIMING__IGET REG_IGET_WO
6669 #define R_DRAM_TIMING__SET REG_SET_WO
6670 #define R_DRAM_TIMING__ISET REG_ISET_WO
6671 #define R_DRAM_TIMING__SET_VAL REG_SET_VAL_WO
6672 #define R_DRAM_TIMING__EQL REG_EQL_WO
6673 #define R_DRAM_TIMING__IEQL REG_IEQL_WO
6674 #define R_DRAM_TIMING__RD REG_RD_WO
6675 #define R_DRAM_TIMING__IRD REG_IRD_WO
6676 #define R_DRAM_TIMING__WR REG_WR_WO
6677 #define R_DRAM_TIMING__IWR REG_IWR_WO
6678
6679 #define R_DRAM_TIMING__WRITE(addr,value) \
6680 (*(addr) = (value))
6681
6682 #define R_DRAM_TIMING__sdram__sdram__MASK 0x80000000U
6683 #define R_DRAM_TIMING__ref__ref__MASK 0x0000c000U
6684 #define R_DRAM_TIMING__rp__rp__MASK 0x00003000U
6685 #define R_DRAM_TIMING__rs__rs__MASK 0x00000c00U
6686 #define R_DRAM_TIMING__rh__rh__MASK 0x00000300U
6687 #define R_DRAM_TIMING__w__w__MASK 0x00000080U
6688 #define R_DRAM_TIMING__c__c__MASK 0x00000040U
6689 #define R_DRAM_TIMING__cz__cz__MASK 0x00000030U
6690 #define R_DRAM_TIMING__cp__cp__MASK 0x0000000cU
6691 #define R_DRAM_TIMING__cw__cw__MASK 0x00000003U
6692
6693 #define R_DRAM_TIMING__sdram__MAX 0x1
6694 #define R_DRAM_TIMING__ref__MAX 0x3
6695 #define R_DRAM_TIMING__rp__MAX 3
6696 #define R_DRAM_TIMING__rs__MAX 3
6697 #define R_DRAM_TIMING__rh__MAX 3
6698 #define R_DRAM_TIMING__w__MAX 0x1
6699 #define R_DRAM_TIMING__c__MAX 0x1
6700 #define R_DRAM_TIMING__cz__MAX 3
6701 #define R_DRAM_TIMING__cp__MAX 3
6702 #define R_DRAM_TIMING__cw__MAX 3
6703
6704 #define R_DRAM_TIMING__sdram__MIN 0
6705 #define R_DRAM_TIMING__ref__MIN 0
6706 #define R_DRAM_TIMING__rp__MIN 0
6707 #define R_DRAM_TIMING__rs__MIN 0
6708 #define R_DRAM_TIMING__rh__MIN 0
6709 #define R_DRAM_TIMING__w__MIN 0
6710 #define R_DRAM_TIMING__c__MIN 0
6711 #define R_DRAM_TIMING__cz__MIN 0
6712 #define R_DRAM_TIMING__cp__MIN 0
6713 #define R_DRAM_TIMING__cw__MIN 0
6714
6715 #define R_DRAM_TIMING__sdram__BITNR 31
6716 #define R_DRAM_TIMING__ref__BITNR 14
6717 #define R_DRAM_TIMING__rp__BITNR 12
6718 #define R_DRAM_TIMING__rs__BITNR 10
6719 #define R_DRAM_TIMING__rh__BITNR 8
6720 #define R_DRAM_TIMING__w__BITNR 7
6721 #define R_DRAM_TIMING__c__BITNR 6
6722 #define R_DRAM_TIMING__cz__BITNR 4
6723 #define R_DRAM_TIMING__cp__BITNR 2
6724 #define R_DRAM_TIMING__cw__BITNR 0
6725
6726 #define R_DRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM
6727 #define R_DRAM_TIMING__ref__ref__VAL REG_VAL_ENUM
6728 #define R_DRAM_TIMING__rp__rp__VAL REG_VAL_VAL
6729 #define R_DRAM_TIMING__rs__rs__VAL REG_VAL_VAL
6730 #define R_DRAM_TIMING__rh__rh__VAL REG_VAL_VAL
6731 #define R_DRAM_TIMING__w__w__VAL REG_VAL_ENUM
6732 #define R_DRAM_TIMING__c__c__VAL REG_VAL_ENUM
6733 #define R_DRAM_TIMING__cz__cz__VAL REG_VAL_VAL
6734 #define R_DRAM_TIMING__cp__cp__VAL REG_VAL_VAL
6735 #define R_DRAM_TIMING__cw__cw__VAL REG_VAL_VAL
6736
6737 #define R_DRAM_TIMING__sdram__sdram__disable 0
6738 #define R_DRAM_TIMING__sdram__sdram__enable 1
6739 #define R_DRAM_TIMING__ref__ref__disable 3
6740 #define R_DRAM_TIMING__ref__ref__e13us 1
6741 #define R_DRAM_TIMING__ref__ref__e52us 0
6742 #define R_DRAM_TIMING__ref__ref__e8700ns 2
6743 #define R_DRAM_TIMING__w__w__ext 1
6744 #define R_DRAM_TIMING__w__w__norm 0
6745 #define R_DRAM_TIMING__c__c__ext 1
6746 #define R_DRAM_TIMING__c__c__norm 0
6747
6748 #endif
6749
6750 /*
6751 * R_EXT_DMA_0_ADDR
6752 * - type: WO
6753 * - addr: 0xb0000014
6754 * - group: External DMA registers
6755 */
6756
6757 #if USE_GROUP__External_DMA_registers
6758
6759 #define R_EXT_DMA_0_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000014)
6760
6761 #ifndef REG_NO_SHADOW
6762 #define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_ADDR + 0))
6763 #define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_ADDR + 0))
6764 #else /* REG_NO_SHADOW */
6765 #define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
6766 #define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
6767 #endif /* REG_NO_SHADOW */
6768
6769 #define R_EXT_DMA_0_ADDR__STYPECAST REG_STYPECAST_UDWORD
6770 #define R_EXT_DMA_0_ADDR__SVAL REG_SVAL_SHADOW
6771 #define R_EXT_DMA_0_ADDR__SVAL_I REG_SVAL_I_SHADOW
6772 #define R_EXT_DMA_0_ADDR__TYPECAST REG_TYPECAST_UDWORD
6773 #define R_EXT_DMA_0_ADDR__TYPE (REG_UDWORD)
6774 #define R_EXT_DMA_0_ADDR__GET REG_GET_WO
6775 #define R_EXT_DMA_0_ADDR__IGET REG_IGET_WO
6776 #define R_EXT_DMA_0_ADDR__SET REG_SET_WO
6777 #define R_EXT_DMA_0_ADDR__ISET REG_ISET_WO
6778 #define R_EXT_DMA_0_ADDR__SET_VAL REG_SET_VAL_WO
6779 #define R_EXT_DMA_0_ADDR__EQL REG_EQL_WO
6780 #define R_EXT_DMA_0_ADDR__IEQL REG_IEQL_WO
6781 #define R_EXT_DMA_0_ADDR__RD REG_RD_WO
6782 #define R_EXT_DMA_0_ADDR__IRD REG_IRD_WO
6783 #define R_EXT_DMA_0_ADDR__WR REG_WR_WO
6784 #define R_EXT_DMA_0_ADDR__IWR REG_IWR_WO
6785
6786 #define R_EXT_DMA_0_ADDR__WRITE(addr,value) \
6787 (*(addr) = (value))
6788
6789 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
6790 #define R_EXT_DMA_0_ADDR__FIRST 0
6791 #define R_EXT_DMA_0_ADDR__IOFFSET 8
6792 #define R_EXT_DMA_0_ADDR__LAST 1
6793 #define R_EXT_DMA_0_ADDR__OFFSET 8
6794 #define R_EXT_DMA_0_ADDR__SOFFSET 8
6795 /* end */
6796
6797 #define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU
6798
6799 #define R_EXT_DMA_0_ADDR__ext0_addr__MAX 0xfffffff
6800
6801 #define R_EXT_DMA_0_ADDR__ext0_addr__MIN 0
6802
6803 #define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
6804
6805 #define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL
6806
6807
6808 #endif
6809
6810 /*
6811 * R_EXT_DMA_0_CMD
6812 * - type: WO
6813 * - addr: 0xb0000010
6814 * - group: External DMA registers
6815 */
6816
6817 #if USE_GROUP__External_DMA_registers
6818
6819 #define R_EXT_DMA_0_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000010)
6820
6821 #ifndef REG_NO_SHADOW
6822 #define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_CMD + 0))
6823 #define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_CMD + 0))
6824 #else /* REG_NO_SHADOW */
6825 #define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
6826 #define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
6827 #endif /* REG_NO_SHADOW */
6828
6829 #define R_EXT_DMA_0_CMD__STYPECAST REG_STYPECAST_UDWORD
6830 #define R_EXT_DMA_0_CMD__SVAL REG_SVAL_SHADOW
6831 #define R_EXT_DMA_0_CMD__SVAL_I REG_SVAL_I_SHADOW
6832 #define R_EXT_DMA_0_CMD__TYPECAST REG_TYPECAST_UDWORD
6833 #define R_EXT_DMA_0_CMD__TYPE (REG_UDWORD)
6834 #define R_EXT_DMA_0_CMD__GET REG_GET_WO
6835 #define R_EXT_DMA_0_CMD__IGET REG_IGET_WO
6836 #define R_EXT_DMA_0_CMD__SET REG_SET_WO
6837 #define R_EXT_DMA_0_CMD__ISET REG_ISET_WO
6838 #define R_EXT_DMA_0_CMD__SET_VAL REG_SET_VAL_WO
6839 #define R_EXT_DMA_0_CMD__EQL REG_EQL_WO
6840 #define R_EXT_DMA_0_CMD__IEQL REG_IEQL_WO
6841 #define R_EXT_DMA_0_CMD__RD REG_RD_WO
6842 #define R_EXT_DMA_0_CMD__IRD REG_IRD_WO
6843 #define R_EXT_DMA_0_CMD__WR REG_WR_WO
6844 #define R_EXT_DMA_0_CMD__IWR REG_IWR_WO
6845
6846 #define R_EXT_DMA_0_CMD__WRITE(addr,value) \
6847 (*(addr) = (value))
6848
6849 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
6850 #define R_EXT_DMA_0_CMD__FIRST 0
6851 #define R_EXT_DMA_0_CMD__IOFFSET 8
6852 #define R_EXT_DMA_0_CMD__LAST 1
6853 #define R_EXT_DMA_0_CMD__OFFSET 8
6854 #define R_EXT_DMA_0_CMD__SOFFSET 8
6855 /* end */
6856
6857 #define R_EXT_DMA_0_CMD__cnt__cnt__MASK 0x00800000U
6858 #define R_EXT_DMA_0_CMD__rqpol__rqpol__MASK 0x00400000U
6859 #define R_EXT_DMA_0_CMD__apol__apol__MASK 0x00200000U
6860 #define R_EXT_DMA_0_CMD__rq_ack__rq_ack__MASK 0x00100000U
6861 #define R_EXT_DMA_0_CMD__wid__wid__MASK 0x000c0000U
6862 #define R_EXT_DMA_0_CMD__dir__dir__MASK 0x00020000U
6863 #define R_EXT_DMA_0_CMD__run__run__MASK 0x00010000U
6864 #define R_EXT_DMA_0_CMD__trf_count__trf_count__MASK 0x0000ffffU
6865
6866 #define R_EXT_DMA_0_CMD__cnt__MAX 0x1
6867 #define R_EXT_DMA_0_CMD__rqpol__MAX 0x1
6868 #define R_EXT_DMA_0_CMD__apol__MAX 0x1
6869 #define R_EXT_DMA_0_CMD__rq_ack__MAX 0x1
6870 #define R_EXT_DMA_0_CMD__wid__MAX 0x3
6871 #define R_EXT_DMA_0_CMD__dir__MAX 0x1
6872 #define R_EXT_DMA_0_CMD__run__MAX 0x1
6873 #define R_EXT_DMA_0_CMD__trf_count__MAX 0xffff
6874
6875 #define R_EXT_DMA_0_CMD__cnt__MIN 0
6876 #define R_EXT_DMA_0_CMD__rqpol__MIN 0
6877 #define R_EXT_DMA_0_CMD__apol__MIN 0
6878 #define R_EXT_DMA_0_CMD__rq_ack__MIN 0
6879 #define R_EXT_DMA_0_CMD__wid__MIN 0
6880 #define R_EXT_DMA_0_CMD__dir__MIN 0
6881 #define R_EXT_DMA_0_CMD__run__MIN 0
6882 #define R_EXT_DMA_0_CMD__trf_count__MIN 0
6883
6884 #define R_EXT_DMA_0_CMD__cnt__BITNR 23
6885 #define R_EXT_DMA_0_CMD__rqpol__BITNR 22
6886 #define R_EXT_DMA_0_CMD__apol__BITNR 21
6887 #define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
6888 #define R_EXT_DMA_0_CMD__wid__BITNR 18
6889 #define R_EXT_DMA_0_CMD__dir__BITNR 17
6890 #define R_EXT_DMA_0_CMD__run__BITNR 16
6891 #define R_EXT_DMA_0_CMD__trf_count__BITNR 0
6892
6893 #define R_EXT_DMA_0_CMD__cnt__cnt__VAL REG_VAL_ENUM
6894 #define R_EXT_DMA_0_CMD__rqpol__rqpol__VAL REG_VAL_ENUM
6895 #define R_EXT_DMA_0_CMD__apol__apol__VAL REG_VAL_ENUM
6896 #define R_EXT_DMA_0_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM
6897 #define R_EXT_DMA_0_CMD__wid__wid__VAL REG_VAL_ENUM
6898 #define R_EXT_DMA_0_CMD__dir__dir__VAL REG_VAL_ENUM
6899 #define R_EXT_DMA_0_CMD__run__run__VAL REG_VAL_ENUM
6900 #define R_EXT_DMA_0_CMD__trf_count__trf_count__VAL REG_VAL_VAL
6901
6902 #define R_EXT_DMA_0_CMD__cnt__cnt__disable 0
6903 #define R_EXT_DMA_0_CMD__cnt__cnt__enable 1
6904 #define R_EXT_DMA_0_CMD__rqpol__rqpol__ahigh 0
6905 #define R_EXT_DMA_0_CMD__rqpol__rqpol__alow 1
6906 #define R_EXT_DMA_0_CMD__apol__apol__ahigh 0
6907 #define R_EXT_DMA_0_CMD__apol__apol__alow 1
6908 #define R_EXT_DMA_0_CMD__rq_ack__rq_ack__burst 0
6909 #define R_EXT_DMA_0_CMD__rq_ack__rq_ack__handsh 1
6910 #define R_EXT_DMA_0_CMD__wid__wid__byte 0
6911 #define R_EXT_DMA_0_CMD__wid__wid__dword 2
6912 #define R_EXT_DMA_0_CMD__wid__wid__word 1
6913 #define R_EXT_DMA_0_CMD__dir__dir__input 0
6914 #define R_EXT_DMA_0_CMD__dir__dir__output 1
6915 #define R_EXT_DMA_0_CMD__run__run__start 1
6916 #define R_EXT_DMA_0_CMD__run__run__stop 0
6917
6918 #endif
6919
6920 /*
6921 * R_EXT_DMA_0_STAT
6922 * - type: RO
6923 * - addr: 0xb0000010
6924 * - group: External DMA registers
6925 */
6926
6927 #if USE_GROUP__External_DMA_registers
6928
6929 #define R_EXT_DMA_0_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000010)
6930 #define R_EXT_DMA_0_STAT__SVAL REG_SVAL_SHADOW
6931 #define R_EXT_DMA_0_STAT__SVAL_I REG_SVAL_I_SHADOW
6932 #define R_EXT_DMA_0_STAT__TYPECAST REG_TYPECAST_UDWORD
6933 #define R_EXT_DMA_0_STAT__TYPE (REG_UDWORD)
6934 #define R_EXT_DMA_0_STAT__GET REG_GET_RO
6935 #define R_EXT_DMA_0_STAT__IGET REG_IGET_RO
6936 #define R_EXT_DMA_0_STAT__SET REG_SET_RO
6937 #define R_EXT_DMA_0_STAT__ISET REG_ISET_RO
6938 #define R_EXT_DMA_0_STAT__SET_VAL REG_SET_VAL_RO
6939 #define R_EXT_DMA_0_STAT__EQL REG_EQL_RO
6940 #define R_EXT_DMA_0_STAT__IEQL REG_IEQL_RO
6941 #define R_EXT_DMA_0_STAT__RD REG_RD_RO
6942 #define R_EXT_DMA_0_STAT__IRD REG_IRD_RO
6943 #define R_EXT_DMA_0_STAT__WR REG_WR_RO
6944 #define R_EXT_DMA_0_STAT__IWR REG_IWR_RO
6945
6946 #define R_EXT_DMA_0_STAT__READ(addr) \
6947 (*(addr))
6948
6949 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
6950 #define R_EXT_DMA_0_STAT__FIRST 0
6951 #define R_EXT_DMA_0_STAT__LAST 1
6952 #define R_EXT_DMA_0_STAT__OFFSET 8
6953 /* end */
6954
6955 #define R_EXT_DMA_0_STAT__run__run__MASK 0x00010000U
6956 #define R_EXT_DMA_0_STAT__trf_count__trf_count__MASK 0x0000ffffU
6957
6958 #define R_EXT_DMA_0_STAT__run__MAX 0x1
6959 #define R_EXT_DMA_0_STAT__trf_count__MAX 0xffff
6960
6961 #define R_EXT_DMA_0_STAT__run__MIN 0
6962 #define R_EXT_DMA_0_STAT__trf_count__MIN 0
6963
6964 #define R_EXT_DMA_0_STAT__run__BITNR 16
6965 #define R_EXT_DMA_0_STAT__trf_count__BITNR 0
6966
6967 #define R_EXT_DMA_0_STAT__run__run__VAL REG_VAL_ENUM
6968 #define R_EXT_DMA_0_STAT__trf_count__trf_count__VAL REG_VAL_VAL
6969
6970 #define R_EXT_DMA_0_STAT__run__run__start 1
6971 #define R_EXT_DMA_0_STAT__run__run__stop 0
6972
6973 #endif
6974
6975 /*
6976 * R_EXT_DMA_1_ADDR
6977 * - type: WO
6978 * - addr: 0xb000001c
6979 * - group: External DMA registers
6980 */
6981
6982 #if USE_GROUP__External_DMA_registers
6983
6984 #define R_EXT_DMA_1_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb000001c)
6985
6986 #ifndef REG_NO_SHADOW
6987 #define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_ADDR + 0))
6988 #define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_ADDR + 0))
6989 #else /* REG_NO_SHADOW */
6990 #define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
6991 #define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
6992 #endif /* REG_NO_SHADOW */
6993
6994 #define R_EXT_DMA_1_ADDR__STYPECAST REG_STYPECAST_UDWORD
6995 #define R_EXT_DMA_1_ADDR__SVAL REG_SVAL_SHADOW
6996 #define R_EXT_DMA_1_ADDR__SVAL_I REG_SVAL_I_SHADOW
6997 #define R_EXT_DMA_1_ADDR__TYPECAST REG_TYPECAST_UDWORD
6998 #define R_EXT_DMA_1_ADDR__TYPE (REG_UDWORD)
6999 #define R_EXT_DMA_1_ADDR__GET REG_GET_WO
7000 #define R_EXT_DMA_1_ADDR__IGET REG_IGET_WO
7001 #define R_EXT_DMA_1_ADDR__SET REG_SET_WO
7002 #define R_EXT_DMA_1_ADDR__ISET REG_ISET_WO
7003 #define R_EXT_DMA_1_ADDR__SET_VAL REG_SET_VAL_WO
7004 #define R_EXT_DMA_1_ADDR__EQL REG_EQL_WO
7005 #define R_EXT_DMA_1_ADDR__IEQL REG_IEQL_WO
7006 #define R_EXT_DMA_1_ADDR__RD REG_RD_WO
7007 #define R_EXT_DMA_1_ADDR__IRD REG_IRD_WO
7008 #define R_EXT_DMA_1_ADDR__WR REG_WR_WO
7009 #define R_EXT_DMA_1_ADDR__IWR REG_IWR_WO
7010
7011 #define R_EXT_DMA_1_ADDR__WRITE(addr,value) \
7012 (*(addr) = (value))
7013
7014 #define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU
7015
7016 #define R_EXT_DMA_1_ADDR__ext0_addr__MAX 0xfffffff
7017
7018 #define R_EXT_DMA_1_ADDR__ext0_addr__MIN 0
7019
7020 #define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
7021
7022 #define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL
7023
7024
7025 #endif
7026
7027 /*
7028 * R_EXT_DMA_1_CMD
7029 * - type: WO
7030 * - addr: 0xb0000018
7031 * - group: External DMA registers
7032 */
7033
7034 #if USE_GROUP__External_DMA_registers
7035
7036 #define R_EXT_DMA_1_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000018)
7037
7038 #ifndef REG_NO_SHADOW
7039 #define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_CMD + 0))
7040 #define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_CMD + 0))
7041 #else /* REG_NO_SHADOW */
7042 #define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
7043 #define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
7044 #endif /* REG_NO_SHADOW */
7045
7046 #define R_EXT_DMA_1_CMD__STYPECAST REG_STYPECAST_UDWORD
7047 #define R_EXT_DMA_1_CMD__SVAL REG_SVAL_SHADOW
7048 #define R_EXT_DMA_1_CMD__SVAL_I REG_SVAL_I_SHADOW
7049 #define R_EXT_DMA_1_CMD__TYPECAST REG_TYPECAST_UDWORD
7050 #define R_EXT_DMA_1_CMD__TYPE (REG_UDWORD)
7051 #define R_EXT_DMA_1_CMD__GET REG_GET_WO
7052 #define R_EXT_DMA_1_CMD__IGET REG_IGET_WO
7053 #define R_EXT_DMA_1_CMD__SET REG_SET_WO
7054 #define R_EXT_DMA_1_CMD__ISET REG_ISET_WO
7055 #define R_EXT_DMA_1_CMD__SET_VAL REG_SET_VAL_WO
7056 #define R_EXT_DMA_1_CMD__EQL REG_EQL_WO
7057 #define R_EXT_DMA_1_CMD__IEQL REG_IEQL_WO
7058 #define R_EXT_DMA_1_CMD__RD REG_RD_WO
7059 #define R_EXT_DMA_1_CMD__IRD REG_IRD_WO
7060 #define R_EXT_DMA_1_CMD__WR REG_WR_WO
7061 #define R_EXT_DMA_1_CMD__IWR REG_IWR_WO
7062
7063 #define R_EXT_DMA_1_CMD__WRITE(addr,value) \
7064 (*(addr) = (value))
7065
7066 #define R_EXT_DMA_1_CMD__cnt__cnt__MASK 0x00800000U
7067 #define R_EXT_DMA_1_CMD__rqpol__rqpol__MASK 0x00400000U
7068 #define R_EXT_DMA_1_CMD__apol__apol__MASK 0x00200000U
7069 #define R_EXT_DMA_1_CMD__rq_ack__rq_ack__MASK 0x00100000U
7070 #define R_EXT_DMA_1_CMD__wid__wid__MASK 0x000c0000U
7071 #define R_EXT_DMA_1_CMD__dir__dir__MASK 0x00020000U
7072 #define R_EXT_DMA_1_CMD__run__run__MASK 0x00010000U
7073 #define R_EXT_DMA_1_CMD__trf_count__trf_count__MASK 0x0000ffffU
7074
7075 #define R_EXT_DMA_1_CMD__cnt__MAX 0x1
7076 #define R_EXT_DMA_1_CMD__rqpol__MAX 0x1
7077 #define R_EXT_DMA_1_CMD__apol__MAX 0x1
7078 #define R_EXT_DMA_1_CMD__rq_ack__MAX 0x1
7079 #define R_EXT_DMA_1_CMD__wid__MAX 0x3
7080 #define R_EXT_DMA_1_CMD__dir__MAX 0x1
7081 #define R_EXT_DMA_1_CMD__run__MAX 0x1
7082 #define R_EXT_DMA_1_CMD__trf_count__MAX 0xffff
7083
7084 #define R_EXT_DMA_1_CMD__cnt__MIN 0
7085 #define R_EXT_DMA_1_CMD__rqpol__MIN 0
7086 #define R_EXT_DMA_1_CMD__apol__MIN 0
7087 #define R_EXT_DMA_1_CMD__rq_ack__MIN 0
7088 #define R_EXT_DMA_1_CMD__wid__MIN 0
7089 #define R_EXT_DMA_1_CMD__dir__MIN 0
7090 #define R_EXT_DMA_1_CMD__run__MIN 0
7091 #define R_EXT_DMA_1_CMD__trf_count__MIN 0
7092
7093 #define R_EXT_DMA_1_CMD__cnt__BITNR 23
7094 #define R_EXT_DMA_1_CMD__rqpol__BITNR 22
7095 #define R_EXT_DMA_1_CMD__apol__BITNR 21
7096 #define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
7097 #define R_EXT_DMA_1_CMD__wid__BITNR 18
7098 #define R_EXT_DMA_1_CMD__dir__BITNR 17
7099 #define R_EXT_DMA_1_CMD__run__BITNR 16
7100 #define R_EXT_DMA_1_CMD__trf_count__BITNR 0
7101
7102 #define R_EXT_DMA_1_CMD__cnt__cnt__VAL REG_VAL_ENUM
7103 #define R_EXT_DMA_1_CMD__rqpol__rqpol__VAL REG_VAL_ENUM
7104 #define R_EXT_DMA_1_CMD__apol__apol__VAL REG_VAL_ENUM
7105 #define R_EXT_DMA_1_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM
7106 #define R_EXT_DMA_1_CMD__wid__wid__VAL REG_VAL_ENUM
7107 #define R_EXT_DMA_1_CMD__dir__dir__VAL REG_VAL_ENUM
7108 #define R_EXT_DMA_1_CMD__run__run__VAL REG_VAL_ENUM
7109 #define R_EXT_DMA_1_CMD__trf_count__trf_count__VAL REG_VAL_VAL
7110
7111 #define R_EXT_DMA_1_CMD__cnt__cnt__disable 0
7112 #define R_EXT_DMA_1_CMD__cnt__cnt__enable 1
7113 #define R_EXT_DMA_1_CMD__rqpol__rqpol__ahigh 0
7114 #define R_EXT_DMA_1_CMD__rqpol__rqpol__alow 1
7115 #define R_EXT_DMA_1_CMD__apol__apol__ahigh 0
7116 #define R_EXT_DMA_1_CMD__apol__apol__alow 1
7117 #define R_EXT_DMA_1_CMD__rq_ack__rq_ack__burst 0
7118 #define R_EXT_DMA_1_CMD__rq_ack__rq_ack__handsh 1
7119 #define R_EXT_DMA_1_CMD__wid__wid__byte 0
7120 #define R_EXT_DMA_1_CMD__wid__wid__dword 2
7121 #define R_EXT_DMA_1_CMD__wid__wid__word 1
7122 #define R_EXT_DMA_1_CMD__dir__dir__input 0
7123 #define R_EXT_DMA_1_CMD__dir__dir__output 1
7124 #define R_EXT_DMA_1_CMD__run__run__start 1
7125 #define R_EXT_DMA_1_CMD__run__run__stop 0
7126
7127 #endif
7128
7129 /*
7130 * R_EXT_DMA_1_STAT
7131 * - type: RO
7132 * - addr: 0xb0000018
7133 * - group: External DMA registers
7134 */
7135
7136 #if USE_GROUP__External_DMA_registers
7137
7138 #define R_EXT_DMA_1_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000018)
7139 #define R_EXT_DMA_1_STAT__SVAL REG_SVAL_SHADOW
7140 #define R_EXT_DMA_1_STAT__SVAL_I REG_SVAL_I_SHADOW
7141 #define R_EXT_DMA_1_STAT__TYPECAST REG_TYPECAST_UDWORD
7142 #define R_EXT_DMA_1_STAT__TYPE (REG_UDWORD)
7143 #define R_EXT_DMA_1_STAT__GET REG_GET_RO
7144 #define R_EXT_DMA_1_STAT__IGET REG_IGET_RO
7145 #define R_EXT_DMA_1_STAT__SET REG_SET_RO
7146 #define R_EXT_DMA_1_STAT__ISET REG_ISET_RO
7147 #define R_EXT_DMA_1_STAT__SET_VAL REG_SET_VAL_RO
7148 #define R_EXT_DMA_1_STAT__EQL REG_EQL_RO
7149 #define R_EXT_DMA_1_STAT__IEQL REG_IEQL_RO
7150 #define R_EXT_DMA_1_STAT__RD REG_RD_RO
7151 #define R_EXT_DMA_1_STAT__IRD REG_IRD_RO
7152 #define R_EXT_DMA_1_STAT__WR REG_WR_RO
7153 #define R_EXT_DMA_1_STAT__IWR REG_IWR_RO
7154
7155 #define R_EXT_DMA_1_STAT__READ(addr) \
7156 (*(addr))
7157
7158 #define R_EXT_DMA_1_STAT__run__run__MASK 0x00010000U
7159 #define R_EXT_DMA_1_STAT__trf_count__trf_count__MASK 0x0000ffffU
7160
7161 #define R_EXT_DMA_1_STAT__run__MAX 0x1
7162 #define R_EXT_DMA_1_STAT__trf_count__MAX 0xffff
7163
7164 #define R_EXT_DMA_1_STAT__run__MIN 0
7165 #define R_EXT_DMA_1_STAT__trf_count__MIN 0
7166
7167 #define R_EXT_DMA_1_STAT__run__BITNR 16
7168 #define R_EXT_DMA_1_STAT__trf_count__BITNR 0
7169
7170 #define R_EXT_DMA_1_STAT__run__run__VAL REG_VAL_ENUM
7171 #define R_EXT_DMA_1_STAT__trf_count__trf_count__VAL REG_VAL_VAL
7172
7173 #define R_EXT_DMA_1_STAT__run__run__start 1
7174 #define R_EXT_DMA_1_STAT__run__run__stop 0
7175
7176 #endif
7177
7178 /*
7179 * R_GEN_CONFIG
7180 * - type: WO
7181 * - addr: 0xb000002c
7182 * - group: General config registers
7183 */
7184
7185 #if USE_GROUP__General_config_registers
7186
7187 #define R_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000002c)
7188
7189 #ifndef REG_NO_SHADOW
7190 #define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG + 0))
7191 #define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG + 0))
7192 #else /* REG_NO_SHADOW */
7193 #define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
7194 #define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
7195 #endif /* REG_NO_SHADOW */
7196
7197 #define R_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD
7198 #define R_GEN_CONFIG__SVAL REG_SVAL_SHADOW
7199 #define R_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW
7200 #define R_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD
7201 #define R_GEN_CONFIG__TYPE (REG_UDWORD)
7202 #define R_GEN_CONFIG__GET REG_GET_WO
7203 #define R_GEN_CONFIG__IGET REG_IGET_WO
7204 #define R_GEN_CONFIG__SET REG_SET_WO
7205 #define R_GEN_CONFIG__ISET REG_ISET_WO
7206 #define R_GEN_CONFIG__SET_VAL REG_SET_VAL_WO
7207 #define R_GEN_CONFIG__EQL REG_EQL_WO
7208 #define R_GEN_CONFIG__IEQL REG_IEQL_WO
7209 #define R_GEN_CONFIG__RD REG_RD_WO
7210 #define R_GEN_CONFIG__IRD REG_IRD_WO
7211 #define R_GEN_CONFIG__WR REG_WR_WO
7212 #define R_GEN_CONFIG__IWR REG_IWR_WO
7213
7214 #define R_GEN_CONFIG__WRITE(addr,value) \
7215 (*(addr) = (value))
7216
7217 #define R_GEN_CONFIG__par_w__par_w__MASK 0x80000000U
7218 #define R_GEN_CONFIG__usb2__usb2__MASK 0x40000000U
7219 #define R_GEN_CONFIG__usb1__usb1__MASK 0x20000000U
7220 #define R_GEN_CONFIG__g24dir__g24dir__MASK 0x08000000U
7221 #define R_GEN_CONFIG__g16_23dir__g16_23dir__MASK 0x04000000U
7222 #define R_GEN_CONFIG__g16_20dir__g16_20dir__MASK 0x04000000U
7223 #define R_GEN_CONFIG__g16_23dir__g16_20dir__MASK 0x04000000U
7224 #define R_GEN_CONFIG__g8_15dir__g8_15dir__MASK 0x02000000U
7225 #define R_GEN_CONFIG__g0dir__g0dir__MASK 0x01000000U
7226 #define R_GEN_CONFIG__dma9__dma9__MASK 0x00800000U
7227 #define R_GEN_CONFIG__dma8__dma8__MASK 0x00400000U
7228 #define R_GEN_CONFIG__dma7__dma7__MASK 0x00300000U
7229 #define R_GEN_CONFIG__dma6__dma6__MASK 0x000c0000U
7230 #define R_GEN_CONFIG__dma5__dma5__MASK 0x00030000U
7231 #define R_GEN_CONFIG__dma4__dma4__MASK 0x0000c000U
7232 #define R_GEN_CONFIG__dma3__dma3__MASK 0x00003000U
7233 #define R_GEN_CONFIG__dma2__dma2__MASK 0x00000c00U
7234 #define R_GEN_CONFIG__mio_w__mio_w__MASK 0x00000200U
7235 #define R_GEN_CONFIG__ser3__ser3__MASK 0x00000100U
7236 #define R_GEN_CONFIG__par1__par1__MASK 0x00000080U
7237 #define R_GEN_CONFIG__scsi0w__scsi0w__MASK 0x00000040U
7238 #define R_GEN_CONFIG__scsi1__scsi1__MASK 0x00000020U
7239 #define R_GEN_CONFIG__mio__mio__MASK 0x00000010U
7240 #define R_GEN_CONFIG__ser2__ser2__MASK 0x00000008U
7241 #define R_GEN_CONFIG__par0__par0__MASK 0x00000004U
7242 #define R_GEN_CONFIG__ata__ata__MASK 0x00000002U
7243 #define R_GEN_CONFIG__scsi0__scsi0__MASK 0x00000001U
7244
7245 #define R_GEN_CONFIG__par_w__MAX 0x1
7246 #define R_GEN_CONFIG__usb2__MAX 0x1
7247 #define R_GEN_CONFIG__usb1__MAX 0x1
7248 #define R_GEN_CONFIG__g24dir__MAX 0x1
7249 #define R_GEN_CONFIG__g16_23dir__MAX 0x1
7250 #define R_GEN_CONFIG__g16_20dir__MAX 0x1
7251 #define R_GEN_CONFIG__g8_15dir__MAX 0x1
7252 #define R_GEN_CONFIG__g0dir__MAX 0x1
7253 #define R_GEN_CONFIG__dma9__MAX 0x1
7254 #define R_GEN_CONFIG__dma8__MAX 0x1
7255 #define R_GEN_CONFIG__dma7__MAX 0x3
7256 #define R_GEN_CONFIG__dma6__MAX 0x3
7257 #define R_GEN_CONFIG__dma5__MAX 0x3
7258 #define R_GEN_CONFIG__dma4__MAX 0x3
7259 #define R_GEN_CONFIG__dma3__MAX 0x3
7260 #define R_GEN_CONFIG__dma2__MAX 0x3
7261 #define R_GEN_CONFIG__mio_w__MAX 0x1
7262 #define R_GEN_CONFIG__ser3__MAX 0x1
7263 #define R_GEN_CONFIG__par1__MAX 0x1
7264 #define R_GEN_CONFIG__scsi0w__MAX 0x1
7265 #define R_GEN_CONFIG__scsi1__MAX 0x1
7266 #define R_GEN_CONFIG__mio__MAX 0x1
7267 #define R_GEN_CONFIG__ser2__MAX 0x1
7268 #define R_GEN_CONFIG__par0__MAX 0x1
7269 #define R_GEN_CONFIG__ata__MAX 0x1
7270 #define R_GEN_CONFIG__scsi0__MAX 0x1
7271
7272 #define R_GEN_CONFIG__par_w__MIN 0
7273 #define R_GEN_CONFIG__usb2__MIN 0
7274 #define R_GEN_CONFIG__usb1__MIN 0
7275 #define R_GEN_CONFIG__g24dir__MIN 0
7276 #define R_GEN_CONFIG__g16_23dir__MIN 0
7277 #define R_GEN_CONFIG__g16_20dir__MIN 0
7278 #define R_GEN_CONFIG__g8_15dir__MIN 0
7279 #define R_GEN_CONFIG__g0dir__MIN 0
7280 #define R_GEN_CONFIG__dma9__MIN 0
7281 #define R_GEN_CONFIG__dma8__MIN 0
7282 #define R_GEN_CONFIG__dma7__MIN 0
7283 #define R_GEN_CONFIG__dma6__MIN 0
7284 #define R_GEN_CONFIG__dma5__MIN 0
7285 #define R_GEN_CONFIG__dma4__MIN 0
7286 #define R_GEN_CONFIG__dma3__MIN 0
7287 #define R_GEN_CONFIG__dma2__MIN 0
7288 #define R_GEN_CONFIG__mio_w__MIN 0
7289 #define R_GEN_CONFIG__ser3__MIN 0
7290 #define R_GEN_CONFIG__par1__MIN 0
7291 #define R_GEN_CONFIG__scsi0w__MIN 0
7292 #define R_GEN_CONFIG__scsi1__MIN 0
7293 #define R_GEN_CONFIG__mio__MIN 0
7294 #define R_GEN_CONFIG__ser2__MIN 0
7295 #define R_GEN_CONFIG__par0__MIN 0
7296 #define R_GEN_CONFIG__ata__MIN 0
7297 #define R_GEN_CONFIG__scsi0__MIN 0
7298
7299 #define R_GEN_CONFIG__par_w__BITNR 31
7300 #define R_GEN_CONFIG__usb2__BITNR 30
7301 #define R_GEN_CONFIG__usb1__BITNR 29
7302 #define R_GEN_CONFIG__g24dir__BITNR 27
7303 #define R_GEN_CONFIG__g16_23dir__BITNR 26
7304 #define R_GEN_CONFIG__g16_20dir__BITNR 26
7305 #define R_GEN_CONFIG__g8_15dir__BITNR 25
7306 #define R_GEN_CONFIG__g0dir__BITNR 24
7307 #define R_GEN_CONFIG__dma9__BITNR 23
7308 #define R_GEN_CONFIG__dma8__BITNR 22
7309 #define R_GEN_CONFIG__dma7__BITNR 20
7310 #define R_GEN_CONFIG__dma6__BITNR 18
7311 #define R_GEN_CONFIG__dma5__BITNR 16
7312 #define R_GEN_CONFIG__dma4__BITNR 14
7313 #define R_GEN_CONFIG__dma3__BITNR 12
7314 #define R_GEN_CONFIG__dma2__BITNR 10
7315 #define R_GEN_CONFIG__mio_w__BITNR 9
7316 #define R_GEN_CONFIG__ser3__BITNR 8
7317 #define R_GEN_CONFIG__par1__BITNR 7
7318 #define R_GEN_CONFIG__scsi0w__BITNR 6
7319 #define R_GEN_CONFIG__scsi1__BITNR 5
7320 #define R_GEN_CONFIG__mio__BITNR 4
7321 #define R_GEN_CONFIG__ser2__BITNR 3
7322 #define R_GEN_CONFIG__par0__BITNR 2
7323 #define R_GEN_CONFIG__ata__BITNR 1
7324 #define R_GEN_CONFIG__scsi0__BITNR 0
7325
7326 #define R_GEN_CONFIG__par_w__par_w__VAL REG_VAL_ENUM
7327 #define R_GEN_CONFIG__usb2__usb2__VAL REG_VAL_ENUM
7328 #define R_GEN_CONFIG__usb1__usb1__VAL REG_VAL_ENUM
7329 #define R_GEN_CONFIG__g24dir__g24dir__VAL REG_VAL_ENUM
7330 #define R_GEN_CONFIG__g16_23dir__g16_23dir__VAL REG_VAL_ENUM
7331 #define R_GEN_CONFIG__g16_20dir__g16_20dir__VAL REG_VAL_ENUM
7332 #define R_GEN_CONFIG__g16_23dir__g16_20dir__VAL REG_VAL_ENUM
7333 #define R_GEN_CONFIG__g8_15dir__g8_15dir__VAL REG_VAL_ENUM
7334 #define R_GEN_CONFIG__g0dir__g0dir__VAL REG_VAL_ENUM
7335 #define R_GEN_CONFIG__dma9__dma9__VAL REG_VAL_ENUM
7336 #define R_GEN_CONFIG__dma8__dma8__VAL REG_VAL_ENUM
7337 #define R_GEN_CONFIG__dma7__dma7__VAL REG_VAL_ENUM
7338 #define R_GEN_CONFIG__dma6__dma6__VAL REG_VAL_ENUM
7339 #define R_GEN_CONFIG__dma5__dma5__VAL REG_VAL_ENUM
7340 #define R_GEN_CONFIG__dma4__dma4__VAL REG_VAL_ENUM
7341 #define R_GEN_CONFIG__dma3__dma3__VAL REG_VAL_ENUM
7342 #define R_GEN_CONFIG__dma2__dma2__VAL REG_VAL_ENUM
7343 #define R_GEN_CONFIG__mio_w__mio_w__VAL REG_VAL_ENUM
7344 #define R_GEN_CONFIG__ser3__ser3__VAL REG_VAL_ENUM
7345 #define R_GEN_CONFIG__par1__par1__VAL REG_VAL_ENUM
7346 #define R_GEN_CONFIG__scsi0w__scsi0w__VAL REG_VAL_ENUM
7347 #define R_GEN_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM
7348 #define R_GEN_CONFIG__mio__mio__VAL REG_VAL_ENUM
7349 #define R_GEN_CONFIG__ser2__ser2__VAL REG_VAL_ENUM
7350 #define R_GEN_CONFIG__par0__par0__VAL REG_VAL_ENUM
7351 #define R_GEN_CONFIG__ata__ata__VAL REG_VAL_ENUM
7352 #define R_GEN_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM
7353
7354 #define R_GEN_CONFIG__par_w__par_w__disable 0
7355 #define R_GEN_CONFIG__par_w__par_w__select 1
7356 #define R_GEN_CONFIG__usb2__usb2__disable 0
7357 #define R_GEN_CONFIG__usb2__usb2__select 1
7358 #define R_GEN_CONFIG__usb1__usb1__disable 0
7359 #define R_GEN_CONFIG__usb1__usb1__select 1
7360 #define R_GEN_CONFIG__g24dir__g24dir__in 0
7361 #define R_GEN_CONFIG__g24dir__g24dir__out 1
7362 #define R_GEN_CONFIG__g16_23dir__g16_23dir__in 0
7363 #define R_GEN_CONFIG__g16_23dir__g16_23dir__out 1
7364 #define R_GEN_CONFIG__g16_20dir__g16_20dir__in 0
7365 #define R_GEN_CONFIG__g16_20dir__g16_20dir__out 1
7366 #define R_GEN_CONFIG__g8_15dir__g8_15dir__in 0
7367 #define R_GEN_CONFIG__g8_15dir__g8_15dir__out 1
7368 #define R_GEN_CONFIG__g0dir__g0dir__in 0
7369 #define R_GEN_CONFIG__g0dir__g0dir__out 1
7370 #define R_GEN_CONFIG__dma9__dma9__serial1 1
7371 #define R_GEN_CONFIG__dma9__dma9__usb 0
7372 #define R_GEN_CONFIG__dma8__dma8__serial1 1
7373 #define R_GEN_CONFIG__dma8__dma8__usb 0
7374 #define R_GEN_CONFIG__dma7__dma7__extdma1 2
7375 #define R_GEN_CONFIG__dma7__dma7__intdma6 3
7376 #define R_GEN_CONFIG__dma7__dma7__serial0 1
7377 #define R_GEN_CONFIG__dma7__dma7__unused 0
7378 #define R_GEN_CONFIG__dma6__dma6__extdma1 2
7379 #define R_GEN_CONFIG__dma6__dma6__intdma7 3
7380 #define R_GEN_CONFIG__dma6__dma6__serial0 1
7381 #define R_GEN_CONFIG__dma6__dma6__unused 0
7382 #define R_GEN_CONFIG__dma5__dma5__extdma0 3
7383 #define R_GEN_CONFIG__dma5__dma5__par1 0
7384 #define R_GEN_CONFIG__dma5__dma5__scsi1 1
7385 #define R_GEN_CONFIG__dma5__dma5__serial3 2
7386 #define R_GEN_CONFIG__dma4__dma4__extdma0 3
7387 #define R_GEN_CONFIG__dma4__dma4__par1 0
7388 #define R_GEN_CONFIG__dma4__dma4__scsi1 1
7389 #define R_GEN_CONFIG__dma4__dma4__serial3 2
7390 #define R_GEN_CONFIG__dma3__dma3__ata 3
7391 #define R_GEN_CONFIG__dma3__dma3__par0 0
7392 #define R_GEN_CONFIG__dma3__dma3__scsi0 1
7393 #define R_GEN_CONFIG__dma3__dma3__serial2 2
7394 #define R_GEN_CONFIG__dma2__dma2__ata 3
7395 #define R_GEN_CONFIG__dma2__dma2__par0 0
7396 #define R_GEN_CONFIG__dma2__dma2__scsi0 1
7397 #define R_GEN_CONFIG__dma2__dma2__serial2 2
7398 #define R_GEN_CONFIG__mio_w__mio_w__disable 0
7399 #define R_GEN_CONFIG__mio_w__mio_w__select 1
7400 #define R_GEN_CONFIG__ser3__ser3__disable 0
7401 #define R_GEN_CONFIG__ser3__ser3__select 1
7402 #define R_GEN_CONFIG__par1__par1__disable 0
7403 #define R_GEN_CONFIG__par1__par1__select 1
7404 #define R_GEN_CONFIG__scsi0w__scsi0w__disable 0
7405 #define R_GEN_CONFIG__scsi0w__scsi0w__select 1
7406 #define R_GEN_CONFIG__scsi1__scsi1__disable 0
7407 #define R_GEN_CONFIG__scsi1__scsi1__select 1
7408 #define R_GEN_CONFIG__mio__mio__disable 0
7409 #define R_GEN_CONFIG__mio__mio__select 1
7410 #define R_GEN_CONFIG__ser2__ser2__disable 0
7411 #define R_GEN_CONFIG__ser2__ser2__select 1
7412 #define R_GEN_CONFIG__par0__par0__disable 0
7413 #define R_GEN_CONFIG__par0__par0__select 1
7414 #define R_GEN_CONFIG__ata__ata__disable 0
7415 #define R_GEN_CONFIG__ata__ata__select 1
7416 #define R_GEN_CONFIG__scsi0__scsi0__disable 0
7417 #define R_GEN_CONFIG__scsi0__scsi0__select 1
7418
7419 #endif
7420
7421 /*
7422 * R_GEN_CONFIG_II
7423 * - type: WO
7424 * - addr: 0xb0000034
7425 * - group: General config registers
7426 */
7427
7428 #if USE_GROUP__General_config_registers
7429
7430 #define R_GEN_CONFIG_II__ADDR (REG_TYPECAST_UDWORD 0xb0000034)
7431
7432 #ifndef REG_NO_SHADOW
7433 #define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG_II + 0))
7434 #define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG_II + 0))
7435 #else /* REG_NO_SHADOW */
7436 #define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
7437 #define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
7438 #endif /* REG_NO_SHADOW */
7439
7440 #define R_GEN_CONFIG_II__STYPECAST REG_STYPECAST_UDWORD
7441 #define R_GEN_CONFIG_II__SVAL REG_SVAL_SHADOW
7442 #define R_GEN_CONFIG_II__SVAL_I REG_SVAL_I_SHADOW
7443 #define R_GEN_CONFIG_II__TYPECAST REG_TYPECAST_UDWORD
7444 #define R_GEN_CONFIG_II__TYPE (REG_UDWORD)
7445 #define R_GEN_CONFIG_II__GET REG_GET_WO
7446 #define R_GEN_CONFIG_II__IGET REG_IGET_WO
7447 #define R_GEN_CONFIG_II__SET REG_SET_WO
7448 #define R_GEN_CONFIG_II__ISET REG_ISET_WO
7449 #define R_GEN_CONFIG_II__SET_VAL REG_SET_VAL_WO
7450 #define R_GEN_CONFIG_II__EQL REG_EQL_WO
7451 #define R_GEN_CONFIG_II__IEQL REG_IEQL_WO
7452 #define R_GEN_CONFIG_II__RD REG_RD_WO
7453 #define R_GEN_CONFIG_II__IRD REG_IRD_WO
7454 #define R_GEN_CONFIG_II__WR REG_WR_WO
7455 #define R_GEN_CONFIG_II__IWR REG_IWR_WO
7456
7457 #define R_GEN_CONFIG_II__WRITE(addr,value) \
7458 (*(addr) = (value))
7459
7460 #define R_GEN_CONFIG_II__sermode3__sermode3__MASK 0x00000040U
7461 #define R_GEN_CONFIG_II__sermode1__sermode1__MASK 0x00000010U
7462 #define R_GEN_CONFIG_II__ext_clk__ext_clk__MASK 0x00000004U
7463 #define R_GEN_CONFIG_II__ser3__ser3__MASK 0x00000002U
7464 #define R_GEN_CONFIG_II__ser2__ser2__MASK 0x00000001U
7465
7466 #define R_GEN_CONFIG_II__sermode3__MAX 0x1
7467 #define R_GEN_CONFIG_II__sermode1__MAX 0x1
7468 #define R_GEN_CONFIG_II__ext_clk__MAX 0x1
7469 #define R_GEN_CONFIG_II__ser3__MAX 0x1
7470 #define R_GEN_CONFIG_II__ser2__MAX 0x1
7471
7472 #define R_GEN_CONFIG_II__sermode3__MIN 0
7473 #define R_GEN_CONFIG_II__sermode1__MIN 0
7474 #define R_GEN_CONFIG_II__ext_clk__MIN 0
7475 #define R_GEN_CONFIG_II__ser3__MIN 0
7476 #define R_GEN_CONFIG_II__ser2__MIN 0
7477
7478 #define R_GEN_CONFIG_II__sermode3__BITNR 6
7479 #define R_GEN_CONFIG_II__sermode1__BITNR 4
7480 #define R_GEN_CONFIG_II__ext_clk__BITNR 2
7481 #define R_GEN_CONFIG_II__ser3__BITNR 1
7482 #define R_GEN_CONFIG_II__ser2__BITNR 0
7483
7484 #define R_GEN_CONFIG_II__sermode3__sermode3__VAL REG_VAL_ENUM
7485 #define R_GEN_CONFIG_II__sermode1__sermode1__VAL REG_VAL_ENUM
7486 #define R_GEN_CONFIG_II__ext_clk__ext_clk__VAL REG_VAL_ENUM
7487 #define R_GEN_CONFIG_II__ser3__ser3__VAL REG_VAL_ENUM
7488 #define R_GEN_CONFIG_II__ser2__ser2__VAL REG_VAL_ENUM
7489
7490 #define R_GEN_CONFIG_II__sermode3__sermode3__async 0
7491 #define R_GEN_CONFIG_II__sermode3__sermode3__sync 1
7492 #define R_GEN_CONFIG_II__sermode1__sermode1__async 0
7493 #define R_GEN_CONFIG_II__sermode1__sermode1__sync 1
7494 #define R_GEN_CONFIG_II__ext_clk__ext_clk__disable 0
7495 #define R_GEN_CONFIG_II__ext_clk__ext_clk__select 1
7496 #define R_GEN_CONFIG_II__ser3__ser3__disable 0
7497 #define R_GEN_CONFIG_II__ser3__ser3__select 1
7498 #define R_GEN_CONFIG_II__ser2__ser2__disable 0
7499 #define R_GEN_CONFIG_II__ser2__ser2__select 1
7500
7501 #endif
7502
7503 /*
7504 * R_IRQ_MASK0_CLR
7505 * - type: WO
7506 * - addr: 0xb00000c0
7507 * - group: Interrupt mask and status registers
7508 */
7509
7510 #if USE_GROUP__Interrupt_mask_and_status_registers
7511
7512 #define R_IRQ_MASK0_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c0)
7513
7514 #ifndef REG_NO_SHADOW
7515 #define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_CLR + 0))
7516 #define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_CLR + 0))
7517 #else /* REG_NO_SHADOW */
7518 #define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
7519 #define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
7520 #endif /* REG_NO_SHADOW */
7521
7522 #define R_IRQ_MASK0_CLR__STYPECAST REG_STYPECAST_UDWORD
7523 #define R_IRQ_MASK0_CLR__SVAL REG_SVAL_ZERO
7524 #define R_IRQ_MASK0_CLR__SVAL_I REG_SVAL_I_ZERO
7525 #define R_IRQ_MASK0_CLR__TYPECAST REG_TYPECAST_UDWORD
7526 #define R_IRQ_MASK0_CLR__TYPE (REG_UDWORD)
7527 #define R_IRQ_MASK0_CLR__GET REG_GET_WO
7528 #define R_IRQ_MASK0_CLR__IGET REG_IGET_WO
7529 #define R_IRQ_MASK0_CLR__SET REG_SET_WO
7530 #define R_IRQ_MASK0_CLR__ISET REG_ISET_WO
7531 #define R_IRQ_MASK0_CLR__SET_VAL REG_SET_VAL_WO
7532 #define R_IRQ_MASK0_CLR__EQL REG_EQL_WO
7533 #define R_IRQ_MASK0_CLR__IEQL REG_IEQL_WO
7534 #define R_IRQ_MASK0_CLR__RD REG_RD_WO
7535 #define R_IRQ_MASK0_CLR__IRD REG_IRD_WO
7536 #define R_IRQ_MASK0_CLR__WR REG_WR_WO
7537 #define R_IRQ_MASK0_CLR__IWR REG_IWR_WO
7538
7539 #define R_IRQ_MASK0_CLR__WRITE(addr,value) \
7540 (*(addr) = (value))
7541
7542 #define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__MASK 0x80000000U
7543 #define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
7544 #define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__MASK 0x20000000U
7545 #define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__MASK 0x10000000U
7546 #define R_IRQ_MASK0_CLR__deferred__deferred__MASK 0x08000000U
7547 #define R_IRQ_MASK0_CLR__late_col__late_col__MASK 0x04000000U
7548 #define R_IRQ_MASK0_CLR__multiple_col__multiple_col__MASK 0x02000000U
7549 #define R_IRQ_MASK0_CLR__single_col__single_col__MASK 0x01000000U
7550 #define R_IRQ_MASK0_CLR__congestion__congestion__MASK 0x00800000U
7551 #define R_IRQ_MASK0_CLR__oversize__oversize__MASK 0x00400000U
7552 #define R_IRQ_MASK0_CLR__alignment_error__alignment_error__MASK 0x00200000U
7553 #define R_IRQ_MASK0_CLR__crc_error__crc_error__MASK 0x00100000U
7554 #define R_IRQ_MASK0_CLR__overrun__overrun__MASK 0x00080000U
7555 #define R_IRQ_MASK0_CLR__underrun__underrun__MASK 0x00040000U
7556 #define R_IRQ_MASK0_CLR__excessive_col__excessive_col__MASK 0x00020000U
7557 #define R_IRQ_MASK0_CLR__mdio__mdio__MASK 0x00010000U
7558 #define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__MASK 0x00008000U
7559 #define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__MASK 0x00004000U
7560 #define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__MASK 0x00002000U
7561 #define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__MASK 0x00001000U
7562 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
7563 #define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__MASK 0x00000800U
7564 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
7565 #define R_IRQ_MASK0_CLR__par0_peri__par0_peri__MASK 0x00000400U
7566 #define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__MASK 0x00000400U
7567 #define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__MASK 0x00000400U
7568 #define R_IRQ_MASK0_CLR__par0_data__par0_data__MASK 0x00000200U
7569 #define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__MASK 0x00000200U
7570 #define R_IRQ_MASK0_CLR__par0_data__ata_irq1__MASK 0x00000200U
7571 #define R_IRQ_MASK0_CLR__par0_ready__par0_ready__MASK 0x00000100U
7572 #define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__MASK 0x00000100U
7573 #define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__MASK 0x00000100U
7574 #define R_IRQ_MASK0_CLR__mio__mio__MASK 0x00000100U
7575 #define R_IRQ_MASK0_CLR__par0_ready__mio__MASK 0x00000100U
7576 #define R_IRQ_MASK0_CLR__scsi0__scsi0__MASK 0x00000100U
7577 #define R_IRQ_MASK0_CLR__par0_ready__scsi0__MASK 0x00000100U
7578 #define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__MASK 0x00000080U
7579 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
7580 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
7581 #define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__MASK 0x00000008U
7582 #define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__MASK 0x00000004U
7583 #define R_IRQ_MASK0_CLR__timer1__timer1__MASK 0x00000002U
7584 #define R_IRQ_MASK0_CLR__timer0__timer0__MASK 0x00000001U
7585
7586 #define R_IRQ_MASK0_CLR__nmi_pin__MAX 0x1
7587 #define R_IRQ_MASK0_CLR__watchdog_nmi__MAX 0x1
7588 #define R_IRQ_MASK0_CLR__sqe_test_error__MAX 0x1
7589 #define R_IRQ_MASK0_CLR__carrier_loss__MAX 0x1
7590 #define R_IRQ_MASK0_CLR__deferred__MAX 0x1
7591 #define R_IRQ_MASK0_CLR__late_col__MAX 0x1
7592 #define R_IRQ_MASK0_CLR__multiple_col__MAX 0x1
7593 #define R_IRQ_MASK0_CLR__single_col__MAX 0x1
7594 #define R_IRQ_MASK0_CLR__congestion__MAX 0x1
7595 #define R_IRQ_MASK0_CLR__oversize__MAX 0x1
7596 #define R_IRQ_MASK0_CLR__alignment_error__MAX 0x1
7597 #define R_IRQ_MASK0_CLR__crc_error__MAX 0x1
7598 #define R_IRQ_MASK0_CLR__overrun__MAX 0x1
7599 #define R_IRQ_MASK0_CLR__underrun__MAX 0x1
7600 #define R_IRQ_MASK0_CLR__excessive_col__MAX 0x1
7601 #define R_IRQ_MASK0_CLR__mdio__MAX 0x1
7602 #define R_IRQ_MASK0_CLR__ata_drq3__MAX 0x1
7603 #define R_IRQ_MASK0_CLR__ata_drq2__MAX 0x1
7604 #define R_IRQ_MASK0_CLR__ata_drq1__MAX 0x1
7605 #define R_IRQ_MASK0_CLR__ata_drq0__MAX 0x1
7606 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__MAX 0x1
7607 #define R_IRQ_MASK0_CLR__ata_irq3__MAX 0x1
7608 #define R_IRQ_MASK0_CLR__par0_peri__MAX 0x1
7609 #define R_IRQ_MASK0_CLR__ata_irq2__MAX 0x1
7610 #define R_IRQ_MASK0_CLR__par0_data__MAX 0x1
7611 #define R_IRQ_MASK0_CLR__ata_irq1__MAX 0x1
7612 #define R_IRQ_MASK0_CLR__par0_ready__MAX 0x1
7613 #define R_IRQ_MASK0_CLR__ata_irq0__MAX 0x1
7614 #define R_IRQ_MASK0_CLR__mio__MAX 0x1
7615 #define R_IRQ_MASK0_CLR__scsi0__MAX 0x1
7616 #define R_IRQ_MASK0_CLR__ata_dmaend__MAX 0x1
7617 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MAX 0x1
7618 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__MAX 0x1
7619 #define R_IRQ_MASK0_CLR__ext_dma1__MAX 0x1
7620 #define R_IRQ_MASK0_CLR__ext_dma0__MAX 0x1
7621 #define R_IRQ_MASK0_CLR__timer1__MAX 0x1
7622 #define R_IRQ_MASK0_CLR__timer0__MAX 0x1
7623
7624 #define R_IRQ_MASK0_CLR__nmi_pin__MIN 0
7625 #define R_IRQ_MASK0_CLR__watchdog_nmi__MIN 0
7626 #define R_IRQ_MASK0_CLR__sqe_test_error__MIN 0
7627 #define R_IRQ_MASK0_CLR__carrier_loss__MIN 0
7628 #define R_IRQ_MASK0_CLR__deferred__MIN 0
7629 #define R_IRQ_MASK0_CLR__late_col__MIN 0
7630 #define R_IRQ_MASK0_CLR__multiple_col__MIN 0
7631 #define R_IRQ_MASK0_CLR__single_col__MIN 0
7632 #define R_IRQ_MASK0_CLR__congestion__MIN 0
7633 #define R_IRQ_MASK0_CLR__oversize__MIN 0
7634 #define R_IRQ_MASK0_CLR__alignment_error__MIN 0
7635 #define R_IRQ_MASK0_CLR__crc_error__MIN 0
7636 #define R_IRQ_MASK0_CLR__overrun__MIN 0
7637 #define R_IRQ_MASK0_CLR__underrun__MIN 0
7638 #define R_IRQ_MASK0_CLR__excessive_col__MIN 0
7639 #define R_IRQ_MASK0_CLR__mdio__MIN 0
7640 #define R_IRQ_MASK0_CLR__ata_drq3__MIN 0
7641 #define R_IRQ_MASK0_CLR__ata_drq2__MIN 0
7642 #define R_IRQ_MASK0_CLR__ata_drq1__MIN 0
7643 #define R_IRQ_MASK0_CLR__ata_drq0__MIN 0
7644 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__MIN 0
7645 #define R_IRQ_MASK0_CLR__ata_irq3__MIN 0
7646 #define R_IRQ_MASK0_CLR__par0_peri__MIN 0
7647 #define R_IRQ_MASK0_CLR__ata_irq2__MIN 0
7648 #define R_IRQ_MASK0_CLR__par0_data__MIN 0
7649 #define R_IRQ_MASK0_CLR__ata_irq1__MIN 0
7650 #define R_IRQ_MASK0_CLR__par0_ready__MIN 0
7651 #define R_IRQ_MASK0_CLR__ata_irq0__MIN 0
7652 #define R_IRQ_MASK0_CLR__mio__MIN 0
7653 #define R_IRQ_MASK0_CLR__scsi0__MIN 0
7654 #define R_IRQ_MASK0_CLR__ata_dmaend__MIN 0
7655 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MIN 0
7656 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__MIN 0
7657 #define R_IRQ_MASK0_CLR__ext_dma1__MIN 0
7658 #define R_IRQ_MASK0_CLR__ext_dma0__MIN 0
7659 #define R_IRQ_MASK0_CLR__timer1__MIN 0
7660 #define R_IRQ_MASK0_CLR__timer0__MIN 0
7661
7662 #define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
7663 #define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
7664 #define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
7665 #define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
7666 #define R_IRQ_MASK0_CLR__deferred__BITNR 27
7667 #define R_IRQ_MASK0_CLR__late_col__BITNR 26
7668 #define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
7669 #define R_IRQ_MASK0_CLR__single_col__BITNR 24
7670 #define R_IRQ_MASK0_CLR__congestion__BITNR 23
7671 #define R_IRQ_MASK0_CLR__oversize__BITNR 22
7672 #define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
7673 #define R_IRQ_MASK0_CLR__crc_error__BITNR 20
7674 #define R_IRQ_MASK0_CLR__overrun__BITNR 19
7675 #define R_IRQ_MASK0_CLR__underrun__BITNR 18
7676 #define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
7677 #define R_IRQ_MASK0_CLR__mdio__BITNR 16
7678 #define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
7679 #define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
7680 #define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
7681 #define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
7682 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
7683 #define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
7684 #define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
7685 #define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
7686 #define R_IRQ_MASK0_CLR__par0_data__BITNR 9
7687 #define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
7688 #define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
7689 #define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
7690 #define R_IRQ_MASK0_CLR__mio__BITNR 8
7691 #define R_IRQ_MASK0_CLR__scsi0__BITNR 8
7692 #define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
7693 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
7694 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
7695 #define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
7696 #define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
7697 #define R_IRQ_MASK0_CLR__timer1__BITNR 1
7698 #define R_IRQ_MASK0_CLR__timer0__BITNR 0
7699
7700 #define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
7701 #define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
7702 #define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
7703 #define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
7704 #define R_IRQ_MASK0_CLR__deferred__deferred__VAL REG_VAL_ENUM
7705 #define R_IRQ_MASK0_CLR__late_col__late_col__VAL REG_VAL_ENUM
7706 #define R_IRQ_MASK0_CLR__multiple_col__multiple_col__VAL REG_VAL_ENUM
7707 #define R_IRQ_MASK0_CLR__single_col__single_col__VAL REG_VAL_ENUM
7708 #define R_IRQ_MASK0_CLR__congestion__congestion__VAL REG_VAL_ENUM
7709 #define R_IRQ_MASK0_CLR__oversize__oversize__VAL REG_VAL_ENUM
7710 #define R_IRQ_MASK0_CLR__alignment_error__alignment_error__VAL REG_VAL_ENUM
7711 #define R_IRQ_MASK0_CLR__crc_error__crc_error__VAL REG_VAL_ENUM
7712 #define R_IRQ_MASK0_CLR__overrun__overrun__VAL REG_VAL_ENUM
7713 #define R_IRQ_MASK0_CLR__underrun__underrun__VAL REG_VAL_ENUM
7714 #define R_IRQ_MASK0_CLR__excessive_col__excessive_col__VAL REG_VAL_ENUM
7715 #define R_IRQ_MASK0_CLR__mdio__mdio__VAL REG_VAL_ENUM
7716 #define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
7717 #define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
7718 #define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
7719 #define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
7720 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
7721 #define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
7722 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
7723 #define R_IRQ_MASK0_CLR__par0_peri__par0_peri__VAL REG_VAL_ENUM
7724 #define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
7725 #define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__VAL REG_VAL_ENUM
7726 #define R_IRQ_MASK0_CLR__par0_data__par0_data__VAL REG_VAL_ENUM
7727 #define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
7728 #define R_IRQ_MASK0_CLR__par0_data__ata_irq1__VAL REG_VAL_ENUM
7729 #define R_IRQ_MASK0_CLR__par0_ready__par0_ready__VAL REG_VAL_ENUM
7730 #define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
7731 #define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__VAL REG_VAL_ENUM
7732 #define R_IRQ_MASK0_CLR__mio__mio__VAL REG_VAL_ENUM
7733 #define R_IRQ_MASK0_CLR__par0_ready__mio__VAL REG_VAL_ENUM
7734 #define R_IRQ_MASK0_CLR__scsi0__scsi0__VAL REG_VAL_ENUM
7735 #define R_IRQ_MASK0_CLR__par0_ready__scsi0__VAL REG_VAL_ENUM
7736 #define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
7737 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
7738 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
7739 #define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
7740 #define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
7741 #define R_IRQ_MASK0_CLR__timer1__timer1__VAL REG_VAL_ENUM
7742 #define R_IRQ_MASK0_CLR__timer0__timer0__VAL REG_VAL_ENUM
7743
7744 #define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__clr 1
7745 #define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__nop 0
7746 #define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__clr 1
7747 #define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__nop 0
7748 #define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__clr 1
7749 #define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__nop 0
7750 #define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__clr 1
7751 #define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__nop 0
7752 #define R_IRQ_MASK0_CLR__deferred__deferred__clr 1
7753 #define R_IRQ_MASK0_CLR__deferred__deferred__nop 0
7754 #define R_IRQ_MASK0_CLR__late_col__late_col__clr 1
7755 #define R_IRQ_MASK0_CLR__late_col__late_col__nop 0
7756 #define R_IRQ_MASK0_CLR__multiple_col__multiple_col__clr 1
7757 #define R_IRQ_MASK0_CLR__multiple_col__multiple_col__nop 0
7758 #define R_IRQ_MASK0_CLR__single_col__single_col__clr 1
7759 #define R_IRQ_MASK0_CLR__single_col__single_col__nop 0
7760 #define R_IRQ_MASK0_CLR__congestion__congestion__clr 1
7761 #define R_IRQ_MASK0_CLR__congestion__congestion__nop 0
7762 #define R_IRQ_MASK0_CLR__oversize__oversize__clr 1
7763 #define R_IRQ_MASK0_CLR__oversize__oversize__nop 0
7764 #define R_IRQ_MASK0_CLR__alignment_error__alignment_error__clr 1
7765 #define R_IRQ_MASK0_CLR__alignment_error__alignment_error__nop 0
7766 #define R_IRQ_MASK0_CLR__crc_error__crc_error__clr 1
7767 #define R_IRQ_MASK0_CLR__crc_error__crc_error__nop 0
7768 #define R_IRQ_MASK0_CLR__overrun__overrun__clr 1
7769 #define R_IRQ_MASK0_CLR__overrun__overrun__nop 0
7770 #define R_IRQ_MASK0_CLR__underrun__underrun__clr 1
7771 #define R_IRQ_MASK0_CLR__underrun__underrun__nop 0
7772 #define R_IRQ_MASK0_CLR__excessive_col__excessive_col__clr 1
7773 #define R_IRQ_MASK0_CLR__excessive_col__excessive_col__nop 0
7774 #define R_IRQ_MASK0_CLR__mdio__mdio__clr 1
7775 #define R_IRQ_MASK0_CLR__mdio__mdio__nop 0
7776 #define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__clr 1
7777 #define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__nop 0
7778 #define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__clr 1
7779 #define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__nop 0
7780 #define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__clr 1
7781 #define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__nop 0
7782 #define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__clr 1
7783 #define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__nop 0
7784 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__clr 1
7785 #define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__nop 0
7786 #define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__clr 1
7787 #define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__nop 0
7788 #define R_IRQ_MASK0_CLR__par0_peri__par0_peri__clr 1
7789 #define R_IRQ_MASK0_CLR__par0_peri__par0_peri__nop 0
7790 #define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__clr 1
7791 #define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__nop 0
7792 #define R_IRQ_MASK0_CLR__par0_data__par0_data__clr 1
7793 #define R_IRQ_MASK0_CLR__par0_data__par0_data__nop 0
7794 #define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__clr 1
7795 #define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__nop 0
7796 #define R_IRQ_MASK0_CLR__par0_ready__par0_ready__clr 1
7797 #define R_IRQ_MASK0_CLR__par0_ready__par0_ready__nop 0
7798 #define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__clr 1
7799 #define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__nop 0
7800 #define R_IRQ_MASK0_CLR__mio__mio__clr 1
7801 #define R_IRQ_MASK0_CLR__mio__mio__nop 0
7802 #define R_IRQ_MASK0_CLR__scsi0__scsi0__clr 1
7803 #define R_IRQ_MASK0_CLR__scsi0__scsi0__nop 0
7804 #define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__clr 1
7805 #define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__nop 0
7806 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__clr 1
7807 #define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__nop 0
7808 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__clr 1
7809 #define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__nop 0
7810 #define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__clr 1
7811 #define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__nop 0
7812 #define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__clr 1
7813 #define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__nop 0
7814 #define R_IRQ_MASK0_CLR__timer1__timer1__clr 1
7815 #define R_IRQ_MASK0_CLR__timer1__timer1__nop 0
7816 #define R_IRQ_MASK0_CLR__timer0__timer0__clr 1
7817 #define R_IRQ_MASK0_CLR__timer0__timer0__nop 0
7818
7819 #endif
7820
7821 /*
7822 * R_IRQ_MASK0_RD
7823 * - type: RO
7824 * - addr: 0xb00000c0
7825 * - group: Interrupt mask and status registers
7826 */
7827
7828 #if USE_GROUP__Interrupt_mask_and_status_registers
7829
7830 #define R_IRQ_MASK0_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c0)
7831 #define R_IRQ_MASK0_RD__SVAL REG_SVAL_SHADOW
7832 #define R_IRQ_MASK0_RD__SVAL_I REG_SVAL_I_SHADOW
7833 #define R_IRQ_MASK0_RD__TYPECAST REG_TYPECAST_UDWORD
7834 #define R_IRQ_MASK0_RD__TYPE (REG_UDWORD)
7835 #define R_IRQ_MASK0_RD__GET REG_GET_RO
7836 #define R_IRQ_MASK0_RD__IGET REG_IGET_RO
7837 #define R_IRQ_MASK0_RD__SET REG_SET_RO
7838 #define R_IRQ_MASK0_RD__ISET REG_ISET_RO
7839 #define R_IRQ_MASK0_RD__SET_VAL REG_SET_VAL_RO
7840 #define R_IRQ_MASK0_RD__EQL REG_EQL_RO
7841 #define R_IRQ_MASK0_RD__IEQL REG_IEQL_RO
7842 #define R_IRQ_MASK0_RD__RD REG_RD_RO
7843 #define R_IRQ_MASK0_RD__IRD REG_IRD_RO
7844 #define R_IRQ_MASK0_RD__WR REG_WR_RO
7845 #define R_IRQ_MASK0_RD__IWR REG_IWR_RO
7846
7847 #define R_IRQ_MASK0_RD__READ(addr) \
7848 (*(addr))
7849
7850 #define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__MASK 0x80000000U
7851 #define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
7852 #define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__MASK 0x20000000U
7853 #define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__MASK 0x10000000U
7854 #define R_IRQ_MASK0_RD__deferred__deferred__MASK 0x08000000U
7855 #define R_IRQ_MASK0_RD__late_col__late_col__MASK 0x04000000U
7856 #define R_IRQ_MASK0_RD__multiple_col__multiple_col__MASK 0x02000000U
7857 #define R_IRQ_MASK0_RD__single_col__single_col__MASK 0x01000000U
7858 #define R_IRQ_MASK0_RD__congestion__congestion__MASK 0x00800000U
7859 #define R_IRQ_MASK0_RD__oversize__oversize__MASK 0x00400000U
7860 #define R_IRQ_MASK0_RD__alignment_error__alignment_error__MASK 0x00200000U
7861 #define R_IRQ_MASK0_RD__crc_error__crc_error__MASK 0x00100000U
7862 #define R_IRQ_MASK0_RD__overrun__overrun__MASK 0x00080000U
7863 #define R_IRQ_MASK0_RD__underrun__underrun__MASK 0x00040000U
7864 #define R_IRQ_MASK0_RD__excessive_col__excessive_col__MASK 0x00020000U
7865 #define R_IRQ_MASK0_RD__mdio__mdio__MASK 0x00010000U
7866 #define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__MASK 0x00008000U
7867 #define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__MASK 0x00004000U
7868 #define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__MASK 0x00002000U
7869 #define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__MASK 0x00001000U
7870 #define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
7871 #define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__MASK 0x00000800U
7872 #define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
7873 #define R_IRQ_MASK0_RD__par0_peri__par0_peri__MASK 0x00000400U
7874 #define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__MASK 0x00000400U
7875 #define R_IRQ_MASK0_RD__par0_peri__ata_irq2__MASK 0x00000400U
7876 #define R_IRQ_MASK0_RD__par0_data__par0_data__MASK 0x00000200U
7877 #define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__MASK 0x00000200U
7878 #define R_IRQ_MASK0_RD__par0_data__ata_irq1__MASK 0x00000200U
7879 #define R_IRQ_MASK0_RD__par0_ready__par0_ready__MASK 0x00000100U
7880 #define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__MASK 0x00000100U
7881 #define R_IRQ_MASK0_RD__par0_ready__ata_irq0__MASK 0x00000100U
7882 #define R_IRQ_MASK0_RD__mio__mio__MASK 0x00000100U
7883 #define R_IRQ_MASK0_RD__par0_ready__mio__MASK 0x00000100U
7884 #define R_IRQ_MASK0_RD__scsi0__scsi0__MASK 0x00000100U
7885 #define R_IRQ_MASK0_RD__par0_ready__scsi0__MASK 0x00000100U
7886 #define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__MASK 0x00000080U
7887 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
7888 #define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
7889 #define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__MASK 0x00000008U
7890 #define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__MASK 0x00000004U
7891 #define R_IRQ_MASK0_RD__timer1__timer1__MASK 0x00000002U
7892 #define R_IRQ_MASK0_RD__timer0__timer0__MASK 0x00000001U
7893
7894 #define R_IRQ_MASK0_RD__nmi_pin__MAX 0x1
7895 #define R_IRQ_MASK0_RD__watchdog_nmi__MAX 0x1
7896 #define R_IRQ_MASK0_RD__sqe_test_error__MAX 0x1
7897 #define R_IRQ_MASK0_RD__carrier_loss__MAX 0x1
7898 #define R_IRQ_MASK0_RD__deferred__MAX 0x1
7899 #define R_IRQ_MASK0_RD__late_col__MAX 0x1
7900 #define R_IRQ_MASK0_RD__multiple_col__MAX 0x1
7901 #define R_IRQ_MASK0_RD__single_col__MAX 0x1
7902 #define R_IRQ_MASK0_RD__congestion__MAX 0x1
7903 #define R_IRQ_MASK0_RD__oversize__MAX 0x1
7904 #define R_IRQ_MASK0_RD__alignment_error__MAX 0x1
7905 #define R_IRQ_MASK0_RD__crc_error__MAX 0x1
7906 #define R_IRQ_MASK0_RD__overrun__MAX 0x1
7907 #define R_IRQ_MASK0_RD__underrun__MAX 0x1
7908 #define R_IRQ_MASK0_RD__excessive_col__MAX 0x1
7909 #define R_IRQ_MASK0_RD__mdio__MAX 0x1
7910 #define R_IRQ_MASK0_RD__ata_drq3__MAX 0x1
7911 #define R_IRQ_MASK0_RD__ata_drq2__MAX 0x1
7912 #define R_IRQ_MASK0_RD__ata_drq1__MAX 0x1
7913 #define R_IRQ_MASK0_RD__ata_drq0__MAX 0x1
7914 #define R_IRQ_MASK0_RD__par0_ecp_cmd__MAX 0x1
7915 #define R_IRQ_MASK0_RD__ata_irq3__MAX 0x1
7916 #define R_IRQ_MASK0_RD__par0_peri__MAX 0x1
7917 #define R_IRQ_MASK0_RD__ata_irq2__MAX 0x1
7918 #define R_IRQ_MASK0_RD__par0_data__MAX 0x1
7919 #define R_IRQ_MASK0_RD__ata_irq1__MAX 0x1
7920 #define R_IRQ_MASK0_RD__par0_ready__MAX 0x1
7921 #define R_IRQ_MASK0_RD__ata_irq0__MAX 0x1
7922 #define R_IRQ_MASK0_RD__mio__MAX 0x1
7923 #define R_IRQ_MASK0_RD__scsi0__MAX 0x1
7924 #define R_IRQ_MASK0_RD__ata_dmaend__MAX 0x1
7925 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__MAX 0x1
7926 #define R_IRQ_MASK0_RD__irq_int_vector_nr__MAX 0x1
7927 #define R_IRQ_MASK0_RD__ext_dma1__MAX 0x1
7928 #define R_IRQ_MASK0_RD__ext_dma0__MAX 0x1
7929 #define R_IRQ_MASK0_RD__timer1__MAX 0x1
7930 #define R_IRQ_MASK0_RD__timer0__MAX 0x1
7931
7932 #define R_IRQ_MASK0_RD__nmi_pin__MIN 0
7933 #define R_IRQ_MASK0_RD__watchdog_nmi__MIN 0
7934 #define R_IRQ_MASK0_RD__sqe_test_error__MIN 0
7935 #define R_IRQ_MASK0_RD__carrier_loss__MIN 0
7936 #define R_IRQ_MASK0_RD__deferred__MIN 0
7937 #define R_IRQ_MASK0_RD__late_col__MIN 0
7938 #define R_IRQ_MASK0_RD__multiple_col__MIN 0
7939 #define R_IRQ_MASK0_RD__single_col__MIN 0
7940 #define R_IRQ_MASK0_RD__congestion__MIN 0
7941 #define R_IRQ_MASK0_RD__oversize__MIN 0
7942 #define R_IRQ_MASK0_RD__alignment_error__MIN 0
7943 #define R_IRQ_MASK0_RD__crc_error__MIN 0
7944 #define R_IRQ_MASK0_RD__overrun__MIN 0
7945 #define R_IRQ_MASK0_RD__underrun__MIN 0
7946 #define R_IRQ_MASK0_RD__excessive_col__MIN 0
7947 #define R_IRQ_MASK0_RD__mdio__MIN 0
7948 #define R_IRQ_MASK0_RD__ata_drq3__MIN 0
7949 #define R_IRQ_MASK0_RD__ata_drq2__MIN 0
7950 #define R_IRQ_MASK0_RD__ata_drq1__MIN 0
7951 #define R_IRQ_MASK0_RD__ata_drq0__MIN 0
7952 #define R_IRQ_MASK0_RD__par0_ecp_cmd__MIN 0
7953 #define R_IRQ_MASK0_RD__ata_irq3__MIN 0
7954 #define R_IRQ_MASK0_RD__par0_peri__MIN 0
7955 #define R_IRQ_MASK0_RD__ata_irq2__MIN 0
7956 #define R_IRQ_MASK0_RD__par0_data__MIN 0
7957 #define R_IRQ_MASK0_RD__ata_irq1__MIN 0
7958 #define R_IRQ_MASK0_RD__par0_ready__MIN 0
7959 #define R_IRQ_MASK0_RD__ata_irq0__MIN 0
7960 #define R_IRQ_MASK0_RD__mio__MIN 0
7961 #define R_IRQ_MASK0_RD__scsi0__MIN 0
7962 #define R_IRQ_MASK0_RD__ata_dmaend__MIN 0
7963 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__MIN 0
7964 #define R_IRQ_MASK0_RD__irq_int_vector_nr__MIN 0
7965 #define R_IRQ_MASK0_RD__ext_dma1__MIN 0
7966 #define R_IRQ_MASK0_RD__ext_dma0__MIN 0
7967 #define R_IRQ_MASK0_RD__timer1__MIN 0
7968 #define R_IRQ_MASK0_RD__timer0__MIN 0
7969
7970 #define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
7971 #define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
7972 #define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
7973 #define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
7974 #define R_IRQ_MASK0_RD__deferred__BITNR 27
7975 #define R_IRQ_MASK0_RD__late_col__BITNR 26
7976 #define R_IRQ_MASK0_RD__multiple_col__BITNR 25
7977 #define R_IRQ_MASK0_RD__single_col__BITNR 24
7978 #define R_IRQ_MASK0_RD__congestion__BITNR 23
7979 #define R_IRQ_MASK0_RD__oversize__BITNR 22
7980 #define R_IRQ_MASK0_RD__alignment_error__BITNR 21
7981 #define R_IRQ_MASK0_RD__crc_error__BITNR 20
7982 #define R_IRQ_MASK0_RD__overrun__BITNR 19
7983 #define R_IRQ_MASK0_RD__underrun__BITNR 18
7984 #define R_IRQ_MASK0_RD__excessive_col__BITNR 17
7985 #define R_IRQ_MASK0_RD__mdio__BITNR 16
7986 #define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
7987 #define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
7988 #define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
7989 #define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
7990 #define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
7991 #define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
7992 #define R_IRQ_MASK0_RD__par0_peri__BITNR 10
7993 #define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
7994 #define R_IRQ_MASK0_RD__par0_data__BITNR 9
7995 #define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
7996 #define R_IRQ_MASK0_RD__par0_ready__BITNR 8
7997 #define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
7998 #define R_IRQ_MASK0_RD__mio__BITNR 8
7999 #define R_IRQ_MASK0_RD__scsi0__BITNR 8
8000 #define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
8001 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
8002 #define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
8003 #define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
8004 #define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
8005 #define R_IRQ_MASK0_RD__timer1__BITNR 1
8006 #define R_IRQ_MASK0_RD__timer0__BITNR 0
8007
8008 #define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
8009 #define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
8010 #define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
8011 #define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
8012 #define R_IRQ_MASK0_RD__deferred__deferred__VAL REG_VAL_ENUM
8013 #define R_IRQ_MASK0_RD__late_col__late_col__VAL REG_VAL_ENUM
8014 #define R_IRQ_MASK0_RD__multiple_col__multiple_col__VAL REG_VAL_ENUM
8015 #define R_IRQ_MASK0_RD__single_col__single_col__VAL REG_VAL_ENUM
8016 #define R_IRQ_MASK0_RD__congestion__congestion__VAL REG_VAL_ENUM
8017 #define R_IRQ_MASK0_RD__oversize__oversize__VAL REG_VAL_ENUM
8018 #define R_IRQ_MASK0_RD__alignment_error__alignment_error__VAL REG_VAL_ENUM
8019 #define R_IRQ_MASK0_RD__crc_error__crc_error__VAL REG_VAL_ENUM
8020 #define R_IRQ_MASK0_RD__overrun__overrun__VAL REG_VAL_ENUM
8021 #define R_IRQ_MASK0_RD__underrun__underrun__VAL REG_VAL_ENUM
8022 #define R_IRQ_MASK0_RD__excessive_col__excessive_col__VAL REG_VAL_ENUM
8023 #define R_IRQ_MASK0_RD__mdio__mdio__VAL REG_VAL_ENUM
8024 #define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
8025 #define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
8026 #define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
8027 #define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
8028 #define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
8029 #define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
8030 #define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
8031 #define R_IRQ_MASK0_RD__par0_peri__par0_peri__VAL REG_VAL_ENUM
8032 #define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
8033 #define R_IRQ_MASK0_RD__par0_peri__ata_irq2__VAL REG_VAL_ENUM
8034 #define R_IRQ_MASK0_RD__par0_data__par0_data__VAL REG_VAL_ENUM
8035 #define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
8036 #define R_IRQ_MASK0_RD__par0_data__ata_irq1__VAL REG_VAL_ENUM
8037 #define R_IRQ_MASK0_RD__par0_ready__par0_ready__VAL REG_VAL_ENUM
8038 #define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
8039 #define R_IRQ_MASK0_RD__par0_ready__ata_irq0__VAL REG_VAL_ENUM
8040 #define R_IRQ_MASK0_RD__mio__mio__VAL REG_VAL_ENUM
8041 #define R_IRQ_MASK0_RD__par0_ready__mio__VAL REG_VAL_ENUM
8042 #define R_IRQ_MASK0_RD__scsi0__scsi0__VAL REG_VAL_ENUM
8043 #define R_IRQ_MASK0_RD__par0_ready__scsi0__VAL REG_VAL_ENUM
8044 #define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
8045 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
8046 #define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
8047 #define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
8048 #define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
8049 #define R_IRQ_MASK0_RD__timer1__timer1__VAL REG_VAL_ENUM
8050 #define R_IRQ_MASK0_RD__timer0__timer0__VAL REG_VAL_ENUM
8051
8052 #define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__active 1
8053 #define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__inactive 0
8054 #define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__active 1
8055 #define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__inactive 0
8056 #define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__active 1
8057 #define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__inactive 0
8058 #define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__active 1
8059 #define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__inactive 0
8060 #define R_IRQ_MASK0_RD__deferred__deferred__active 1
8061 #define R_IRQ_MASK0_RD__deferred__deferred__inactive 0
8062 #define R_IRQ_MASK0_RD__late_col__late_col__active 1
8063 #define R_IRQ_MASK0_RD__late_col__late_col__inactive 0
8064 #define R_IRQ_MASK0_RD__multiple_col__multiple_col__active 1
8065 #define R_IRQ_MASK0_RD__multiple_col__multiple_col__inactive 0
8066 #define R_IRQ_MASK0_RD__single_col__single_col__active 1
8067 #define R_IRQ_MASK0_RD__single_col__single_col__inactive 0
8068 #define R_IRQ_MASK0_RD__congestion__congestion__active 1
8069 #define R_IRQ_MASK0_RD__congestion__congestion__inactive 0
8070 #define R_IRQ_MASK0_RD__oversize__oversize__active 1
8071 #define R_IRQ_MASK0_RD__oversize__oversize__inactive 0
8072 #define R_IRQ_MASK0_RD__alignment_error__alignment_error__active 1
8073 #define R_IRQ_MASK0_RD__alignment_error__alignment_error__inactive 0
8074 #define R_IRQ_MASK0_RD__crc_error__crc_error__active 1
8075 #define R_IRQ_MASK0_RD__crc_error__crc_error__inactive 0
8076 #define R_IRQ_MASK0_RD__overrun__overrun__active 1
8077 #define R_IRQ_MASK0_RD__overrun__overrun__inactive 0
8078 #define R_IRQ_MASK0_RD__underrun__underrun__active 1
8079 #define R_IRQ_MASK0_RD__underrun__underrun__inactive 0
8080 #define R_IRQ_MASK0_RD__excessive_col__excessive_col__active 1
8081 #define R_IRQ_MASK0_RD__excessive_col__excessive_col__inactive 0
8082 #define R_IRQ_MASK0_RD__mdio__mdio__active 1
8083 #define R_IRQ_MASK0_RD__mdio__mdio__inactive 0
8084 #define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__active 1
8085 #define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__inactive 0
8086 #define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__active 1
8087 #define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__inactive 0
8088 #define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__active 1
8089 #define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__inactive 0
8090 #define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__active 1
8091 #define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__inactive 0
8092 #define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__active 1
8093 #define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__inactive 0
8094 #define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__active 1
8095 #define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__inactive 0
8096 #define R_IRQ_MASK0_RD__par0_peri__par0_peri__active 1
8097 #define R_IRQ_MASK0_RD__par0_peri__par0_peri__inactive 0
8098 #define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__active 1
8099 #define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__inactive 0
8100 #define R_IRQ_MASK0_RD__par0_data__par0_data__active 1
8101 #define R_IRQ_MASK0_RD__par0_data__par0_data__inactive 0
8102 #define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__active 1
8103 #define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__inactive 0
8104 #define R_IRQ_MASK0_RD__par0_ready__par0_ready__active 1
8105 #define R_IRQ_MASK0_RD__par0_ready__par0_ready__inactive 0
8106 #define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__active 1
8107 #define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__inactive 0
8108 #define R_IRQ_MASK0_RD__mio__mio__active 1
8109 #define R_IRQ_MASK0_RD__mio__mio__inactive 0
8110 #define R_IRQ_MASK0_RD__scsi0__scsi0__active 1
8111 #define R_IRQ_MASK0_RD__scsi0__scsi0__inactive 0
8112 #define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__active 1
8113 #define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__inactive 0
8114 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__active 1
8115 #define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0
8116 #define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__active 1
8117 #define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__inactive 0
8118 #define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__active 1
8119 #define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__inactive 0
8120 #define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__active 1
8121 #define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__inactive 0
8122 #define R_IRQ_MASK0_RD__timer1__timer1__active 1
8123 #define R_IRQ_MASK0_RD__timer1__timer1__inactive 0
8124 #define R_IRQ_MASK0_RD__timer0__timer0__active 1
8125 #define R_IRQ_MASK0_RD__timer0__timer0__inactive 0
8126
8127 #endif
8128
8129 /*
8130 * R_IRQ_MASK0_SET
8131 * - type: WO
8132 * - addr: 0xb00000c4
8133 * - group: Interrupt mask and status registers
8134 */
8135
8136 #if USE_GROUP__Interrupt_mask_and_status_registers
8137
8138 #define R_IRQ_MASK0_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000c4)
8139
8140 #ifndef REG_NO_SHADOW
8141 #define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_SET + 0))
8142 #define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_SET + 0))
8143 #else /* REG_NO_SHADOW */
8144 #define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
8145 #define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
8146 #endif /* REG_NO_SHADOW */
8147
8148 #define R_IRQ_MASK0_SET__STYPECAST REG_STYPECAST_UDWORD
8149 #define R_IRQ_MASK0_SET__SVAL REG_SVAL_ZERO
8150 #define R_IRQ_MASK0_SET__SVAL_I REG_SVAL_I_ZERO
8151 #define R_IRQ_MASK0_SET__TYPECAST REG_TYPECAST_UDWORD
8152 #define R_IRQ_MASK0_SET__TYPE (REG_UDWORD)
8153 #define R_IRQ_MASK0_SET__GET REG_GET_WO
8154 #define R_IRQ_MASK0_SET__IGET REG_IGET_WO
8155 #define R_IRQ_MASK0_SET__SET REG_SET_WO
8156 #define R_IRQ_MASK0_SET__ISET REG_ISET_WO
8157 #define R_IRQ_MASK0_SET__SET_VAL REG_SET_VAL_WO
8158 #define R_IRQ_MASK0_SET__EQL REG_EQL_WO
8159 #define R_IRQ_MASK0_SET__IEQL REG_IEQL_WO
8160 #define R_IRQ_MASK0_SET__RD REG_RD_WO
8161 #define R_IRQ_MASK0_SET__IRD REG_IRD_WO
8162 #define R_IRQ_MASK0_SET__WR REG_WR_WO
8163 #define R_IRQ_MASK0_SET__IWR REG_IWR_WO
8164
8165 #define R_IRQ_MASK0_SET__WRITE(addr,value) \
8166 (*(addr) = (value))
8167
8168 #define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__MASK 0x80000000U
8169 #define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
8170 #define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__MASK 0x20000000U
8171 #define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__MASK 0x10000000U
8172 #define R_IRQ_MASK0_SET__deferred__deferred__MASK 0x08000000U
8173 #define R_IRQ_MASK0_SET__late_col__late_col__MASK 0x04000000U
8174 #define R_IRQ_MASK0_SET__multiple_col__multiple_col__MASK 0x02000000U
8175 #define R_IRQ_MASK0_SET__single_col__single_col__MASK 0x01000000U
8176 #define R_IRQ_MASK0_SET__congestion__congestion__MASK 0x00800000U
8177 #define R_IRQ_MASK0_SET__oversize__oversize__MASK 0x00400000U
8178 #define R_IRQ_MASK0_SET__alignment_error__alignment_error__MASK 0x00200000U
8179 #define R_IRQ_MASK0_SET__crc_error__crc_error__MASK 0x00100000U
8180 #define R_IRQ_MASK0_SET__overrun__overrun__MASK 0x00080000U
8181 #define R_IRQ_MASK0_SET__underrun__underrun__MASK 0x00040000U
8182 #define R_IRQ_MASK0_SET__excessive_col__excessive_col__MASK 0x00020000U
8183 #define R_IRQ_MASK0_SET__mdio__mdio__MASK 0x00010000U
8184 #define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__MASK 0x00008000U
8185 #define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__MASK 0x00004000U
8186 #define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__MASK 0x00002000U
8187 #define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__MASK 0x00001000U
8188 #define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
8189 #define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__MASK 0x00000800U
8190 #define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
8191 #define R_IRQ_MASK0_SET__par0_peri__par0_peri__MASK 0x00000400U
8192 #define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__MASK 0x00000400U
8193 #define R_IRQ_MASK0_SET__par0_peri__ata_irq2__MASK 0x00000400U
8194 #define R_IRQ_MASK0_SET__par0_data__par0_data__MASK 0x00000200U
8195 #define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__MASK 0x00000200U
8196 #define R_IRQ_MASK0_SET__par0_data__ata_irq1__MASK 0x00000200U
8197 #define R_IRQ_MASK0_SET__par0_ready__par0_ready__MASK 0x00000100U
8198 #define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__MASK 0x00000100U
8199 #define R_IRQ_MASK0_SET__par0_ready__ata_irq0__MASK 0x00000100U
8200 #define R_IRQ_MASK0_SET__mio__mio__MASK 0x00000100U
8201 #define R_IRQ_MASK0_SET__par0_ready__mio__MASK 0x00000100U
8202 #define R_IRQ_MASK0_SET__scsi0__scsi0__MASK 0x00000100U
8203 #define R_IRQ_MASK0_SET__par0_ready__scsi0__MASK 0x00000100U
8204 #define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__MASK 0x00000080U
8205 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
8206 #define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
8207 #define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__MASK 0x00000008U
8208 #define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__MASK 0x00000004U
8209 #define R_IRQ_MASK0_SET__timer1__timer1__MASK 0x00000002U
8210 #define R_IRQ_MASK0_SET__timer0__timer0__MASK 0x00000001U
8211
8212 #define R_IRQ_MASK0_SET__nmi_pin__MAX 0x1
8213 #define R_IRQ_MASK0_SET__watchdog_nmi__MAX 0x1
8214 #define R_IRQ_MASK0_SET__sqe_test_error__MAX 0x1
8215 #define R_IRQ_MASK0_SET__carrier_loss__MAX 0x1
8216 #define R_IRQ_MASK0_SET__deferred__MAX 0x1
8217 #define R_IRQ_MASK0_SET__late_col__MAX 0x1
8218 #define R_IRQ_MASK0_SET__multiple_col__MAX 0x1
8219 #define R_IRQ_MASK0_SET__single_col__MAX 0x1
8220 #define R_IRQ_MASK0_SET__congestion__MAX 0x1
8221 #define R_IRQ_MASK0_SET__oversize__MAX 0x1
8222 #define R_IRQ_MASK0_SET__alignment_error__MAX 0x1
8223 #define R_IRQ_MASK0_SET__crc_error__MAX 0x1
8224 #define R_IRQ_MASK0_SET__overrun__MAX 0x1
8225 #define R_IRQ_MASK0_SET__underrun__MAX 0x1
8226 #define R_IRQ_MASK0_SET__excessive_col__MAX 0x1
8227 #define R_IRQ_MASK0_SET__mdio__MAX 0x1
8228 #define R_IRQ_MASK0_SET__ata_drq3__MAX 0x1
8229 #define R_IRQ_MASK0_SET__ata_drq2__MAX 0x1
8230 #define R_IRQ_MASK0_SET__ata_drq1__MAX 0x1
8231 #define R_IRQ_MASK0_SET__ata_drq0__MAX 0x1
8232 #define R_IRQ_MASK0_SET__par0_ecp_cmd__MAX 0x1
8233 #define R_IRQ_MASK0_SET__ata_irq3__MAX 0x1
8234 #define R_IRQ_MASK0_SET__par0_peri__MAX 0x1
8235 #define R_IRQ_MASK0_SET__ata_irq2__MAX 0x1
8236 #define R_IRQ_MASK0_SET__par0_data__MAX 0x1
8237 #define R_IRQ_MASK0_SET__ata_irq1__MAX 0x1
8238 #define R_IRQ_MASK0_SET__par0_ready__MAX 0x1
8239 #define R_IRQ_MASK0_SET__ata_irq0__MAX 0x1
8240 #define R_IRQ_MASK0_SET__mio__MAX 0x1
8241 #define R_IRQ_MASK0_SET__scsi0__MAX 0x1
8242 #define R_IRQ_MASK0_SET__ata_dmaend__MAX 0x1
8243 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__MAX 0x1
8244 #define R_IRQ_MASK0_SET__irq_int_vector_nr__MAX 0x1
8245 #define R_IRQ_MASK0_SET__ext_dma1__MAX 0x1
8246 #define R_IRQ_MASK0_SET__ext_dma0__MAX 0x1
8247 #define R_IRQ_MASK0_SET__timer1__MAX 0x1
8248 #define R_IRQ_MASK0_SET__timer0__MAX 0x1
8249
8250 #define R_IRQ_MASK0_SET__nmi_pin__MIN 0
8251 #define R_IRQ_MASK0_SET__watchdog_nmi__MIN 0
8252 #define R_IRQ_MASK0_SET__sqe_test_error__MIN 0
8253 #define R_IRQ_MASK0_SET__carrier_loss__MIN 0
8254 #define R_IRQ_MASK0_SET__deferred__MIN 0
8255 #define R_IRQ_MASK0_SET__late_col__MIN 0
8256 #define R_IRQ_MASK0_SET__multiple_col__MIN 0
8257 #define R_IRQ_MASK0_SET__single_col__MIN 0
8258 #define R_IRQ_MASK0_SET__congestion__MIN 0
8259 #define R_IRQ_MASK0_SET__oversize__MIN 0
8260 #define R_IRQ_MASK0_SET__alignment_error__MIN 0
8261 #define R_IRQ_MASK0_SET__crc_error__MIN 0
8262 #define R_IRQ_MASK0_SET__overrun__MIN 0
8263 #define R_IRQ_MASK0_SET__underrun__MIN 0
8264 #define R_IRQ_MASK0_SET__excessive_col__MIN 0
8265 #define R_IRQ_MASK0_SET__mdio__MIN 0
8266 #define R_IRQ_MASK0_SET__ata_drq3__MIN 0
8267 #define R_IRQ_MASK0_SET__ata_drq2__MIN 0
8268 #define R_IRQ_MASK0_SET__ata_drq1__MIN 0
8269 #define R_IRQ_MASK0_SET__ata_drq0__MIN 0
8270 #define R_IRQ_MASK0_SET__par0_ecp_cmd__MIN 0
8271 #define R_IRQ_MASK0_SET__ata_irq3__MIN 0
8272 #define R_IRQ_MASK0_SET__par0_peri__MIN 0
8273 #define R_IRQ_MASK0_SET__ata_irq2__MIN 0
8274 #define R_IRQ_MASK0_SET__par0_data__MIN 0
8275 #define R_IRQ_MASK0_SET__ata_irq1__MIN 0
8276 #define R_IRQ_MASK0_SET__par0_ready__MIN 0
8277 #define R_IRQ_MASK0_SET__ata_irq0__MIN 0
8278 #define R_IRQ_MASK0_SET__mio__MIN 0
8279 #define R_IRQ_MASK0_SET__scsi0__MIN 0
8280 #define R_IRQ_MASK0_SET__ata_dmaend__MIN 0
8281 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__MIN 0
8282 #define R_IRQ_MASK0_SET__irq_int_vector_nr__MIN 0
8283 #define R_IRQ_MASK0_SET__ext_dma1__MIN 0
8284 #define R_IRQ_MASK0_SET__ext_dma0__MIN 0
8285 #define R_IRQ_MASK0_SET__timer1__MIN 0
8286 #define R_IRQ_MASK0_SET__timer0__MIN 0
8287
8288 #define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
8289 #define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
8290 #define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
8291 #define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
8292 #define R_IRQ_MASK0_SET__deferred__BITNR 27
8293 #define R_IRQ_MASK0_SET__late_col__BITNR 26
8294 #define R_IRQ_MASK0_SET__multiple_col__BITNR 25
8295 #define R_IRQ_MASK0_SET__single_col__BITNR 24
8296 #define R_IRQ_MASK0_SET__congestion__BITNR 23
8297 #define R_IRQ_MASK0_SET__oversize__BITNR 22
8298 #define R_IRQ_MASK0_SET__alignment_error__BITNR 21
8299 #define R_IRQ_MASK0_SET__crc_error__BITNR 20
8300 #define R_IRQ_MASK0_SET__overrun__BITNR 19
8301 #define R_IRQ_MASK0_SET__underrun__BITNR 18
8302 #define R_IRQ_MASK0_SET__excessive_col__BITNR 17
8303 #define R_IRQ_MASK0_SET__mdio__BITNR 16
8304 #define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
8305 #define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
8306 #define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
8307 #define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
8308 #define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
8309 #define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
8310 #define R_IRQ_MASK0_SET__par0_peri__BITNR 10
8311 #define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
8312 #define R_IRQ_MASK0_SET__par0_data__BITNR 9
8313 #define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
8314 #define R_IRQ_MASK0_SET__par0_ready__BITNR 8
8315 #define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
8316 #define R_IRQ_MASK0_SET__mio__BITNR 8
8317 #define R_IRQ_MASK0_SET__scsi0__BITNR 8
8318 #define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
8319 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
8320 #define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
8321 #define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
8322 #define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
8323 #define R_IRQ_MASK0_SET__timer1__BITNR 1
8324 #define R_IRQ_MASK0_SET__timer0__BITNR 0
8325
8326 #define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
8327 #define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
8328 #define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
8329 #define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
8330 #define R_IRQ_MASK0_SET__deferred__deferred__VAL REG_VAL_ENUM
8331 #define R_IRQ_MASK0_SET__late_col__late_col__VAL REG_VAL_ENUM
8332 #define R_IRQ_MASK0_SET__multiple_col__multiple_col__VAL REG_VAL_ENUM
8333 #define R_IRQ_MASK0_SET__single_col__single_col__VAL REG_VAL_ENUM
8334 #define R_IRQ_MASK0_SET__congestion__congestion__VAL REG_VAL_ENUM
8335 #define R_IRQ_MASK0_SET__oversize__oversize__VAL REG_VAL_ENUM
8336 #define R_IRQ_MASK0_SET__alignment_error__alignment_error__VAL REG_VAL_ENUM
8337 #define R_IRQ_MASK0_SET__crc_error__crc_error__VAL REG_VAL_ENUM
8338 #define R_IRQ_MASK0_SET__overrun__overrun__VAL REG_VAL_ENUM
8339 #define R_IRQ_MASK0_SET__underrun__underrun__VAL REG_VAL_ENUM
8340 #define R_IRQ_MASK0_SET__excessive_col__excessive_col__VAL REG_VAL_ENUM
8341 #define R_IRQ_MASK0_SET__mdio__mdio__VAL REG_VAL_ENUM
8342 #define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
8343 #define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
8344 #define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
8345 #define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
8346 #define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
8347 #define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
8348 #define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
8349 #define R_IRQ_MASK0_SET__par0_peri__par0_peri__VAL REG_VAL_ENUM
8350 #define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
8351 #define R_IRQ_MASK0_SET__par0_peri__ata_irq2__VAL REG_VAL_ENUM
8352 #define R_IRQ_MASK0_SET__par0_data__par0_data__VAL REG_VAL_ENUM
8353 #define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
8354 #define R_IRQ_MASK0_SET__par0_data__ata_irq1__VAL REG_VAL_ENUM
8355 #define R_IRQ_MASK0_SET__par0_ready__par0_ready__VAL REG_VAL_ENUM
8356 #define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
8357 #define R_IRQ_MASK0_SET__par0_ready__ata_irq0__VAL REG_VAL_ENUM
8358 #define R_IRQ_MASK0_SET__mio__mio__VAL REG_VAL_ENUM
8359 #define R_IRQ_MASK0_SET__par0_ready__mio__VAL REG_VAL_ENUM
8360 #define R_IRQ_MASK0_SET__scsi0__scsi0__VAL REG_VAL_ENUM
8361 #define R_IRQ_MASK0_SET__par0_ready__scsi0__VAL REG_VAL_ENUM
8362 #define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
8363 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
8364 #define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
8365 #define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
8366 #define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
8367 #define R_IRQ_MASK0_SET__timer1__timer1__VAL REG_VAL_ENUM
8368 #define R_IRQ_MASK0_SET__timer0__timer0__VAL REG_VAL_ENUM
8369
8370 #define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__nop 0
8371 #define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__set 1
8372 #define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__nop 0
8373 #define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__set 1
8374 #define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__nop 0
8375 #define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__set 1
8376 #define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__nop 0
8377 #define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__set 1
8378 #define R_IRQ_MASK0_SET__deferred__deferred__nop 0
8379 #define R_IRQ_MASK0_SET__deferred__deferred__set 1
8380 #define R_IRQ_MASK0_SET__late_col__late_col__nop 0
8381 #define R_IRQ_MASK0_SET__late_col__late_col__set 1
8382 #define R_IRQ_MASK0_SET__multiple_col__multiple_col__nop 0
8383 #define R_IRQ_MASK0_SET__multiple_col__multiple_col__set 1
8384 #define R_IRQ_MASK0_SET__single_col__single_col__nop 0
8385 #define R_IRQ_MASK0_SET__single_col__single_col__set 1
8386 #define R_IRQ_MASK0_SET__congestion__congestion__nop 0
8387 #define R_IRQ_MASK0_SET__congestion__congestion__set 1
8388 #define R_IRQ_MASK0_SET__oversize__oversize__nop 0
8389 #define R_IRQ_MASK0_SET__oversize__oversize__set 1
8390 #define R_IRQ_MASK0_SET__alignment_error__alignment_error__nop 0
8391 #define R_IRQ_MASK0_SET__alignment_error__alignment_error__set 1
8392 #define R_IRQ_MASK0_SET__crc_error__crc_error__nop 0
8393 #define R_IRQ_MASK0_SET__crc_error__crc_error__set 1
8394 #define R_IRQ_MASK0_SET__overrun__overrun__nop 0
8395 #define R_IRQ_MASK0_SET__overrun__overrun__set 1
8396 #define R_IRQ_MASK0_SET__underrun__underrun__nop 0
8397 #define R_IRQ_MASK0_SET__underrun__underrun__set 1
8398 #define R_IRQ_MASK0_SET__excessive_col__excessive_col__nop 0
8399 #define R_IRQ_MASK0_SET__excessive_col__excessive_col__set 1
8400 #define R_IRQ_MASK0_SET__mdio__mdio__nop 0
8401 #define R_IRQ_MASK0_SET__mdio__mdio__set 1
8402 #define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__nop 0
8403 #define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__set 1
8404 #define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__nop 0
8405 #define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__set 1
8406 #define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__nop 0
8407 #define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__set 1
8408 #define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__nop 0
8409 #define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__set 1
8410 #define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__nop 0
8411 #define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__set 1
8412 #define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__nop 0
8413 #define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__set 1
8414 #define R_IRQ_MASK0_SET__par0_peri__par0_peri__nop 0
8415 #define R_IRQ_MASK0_SET__par0_peri__par0_peri__set 1
8416 #define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__nop 0
8417 #define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__set 1
8418 #define R_IRQ_MASK0_SET__par0_data__par0_data__nop 0
8419 #define R_IRQ_MASK0_SET__par0_data__par0_data__set 1
8420 #define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__nop 0
8421 #define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__set 1
8422 #define R_IRQ_MASK0_SET__par0_ready__par0_ready__nop 0
8423 #define R_IRQ_MASK0_SET__par0_ready__par0_ready__set 1
8424 #define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__nop 0
8425 #define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__set 1
8426 #define R_IRQ_MASK0_SET__mio__mio__nop 0
8427 #define R_IRQ_MASK0_SET__mio__mio__set 1
8428 #define R_IRQ_MASK0_SET__scsi0__scsi0__nop 0
8429 #define R_IRQ_MASK0_SET__scsi0__scsi0__set 1
8430 #define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__nop 0
8431 #define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__set 1
8432 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__nop 0
8433 #define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__set 1
8434 #define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__nop 0
8435 #define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__set 1
8436 #define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__nop 0
8437 #define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__set 1
8438 #define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__nop 0
8439 #define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__set 1
8440 #define R_IRQ_MASK0_SET__timer1__timer1__nop 0
8441 #define R_IRQ_MASK0_SET__timer1__timer1__set 1
8442 #define R_IRQ_MASK0_SET__timer0__timer0__nop 0
8443 #define R_IRQ_MASK0_SET__timer0__timer0__set 1
8444
8445 #endif
8446
8447 /*
8448 * R_IRQ_MASK1_CLR
8449 * - type: WO
8450 * - addr: 0xb00000c8
8451 * - group: Interrupt mask and status registers
8452 */
8453
8454 #if USE_GROUP__Interrupt_mask_and_status_registers
8455
8456 #define R_IRQ_MASK1_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c8)
8457
8458 #ifndef REG_NO_SHADOW
8459 #define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_CLR + 0))
8460 #define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_CLR + 0))
8461 #else /* REG_NO_SHADOW */
8462 #define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
8463 #define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
8464 #endif /* REG_NO_SHADOW */
8465
8466 #define R_IRQ_MASK1_CLR__STYPECAST REG_STYPECAST_UDWORD
8467 #define R_IRQ_MASK1_CLR__SVAL REG_SVAL_ZERO
8468 #define R_IRQ_MASK1_CLR__SVAL_I REG_SVAL_I_ZERO
8469 #define R_IRQ_MASK1_CLR__TYPECAST REG_TYPECAST_UDWORD
8470 #define R_IRQ_MASK1_CLR__TYPE (REG_UDWORD)
8471 #define R_IRQ_MASK1_CLR__GET REG_GET_WO
8472 #define R_IRQ_MASK1_CLR__IGET REG_IGET_WO
8473 #define R_IRQ_MASK1_CLR__SET REG_SET_WO
8474 #define R_IRQ_MASK1_CLR__ISET REG_ISET_WO
8475 #define R_IRQ_MASK1_CLR__SET_VAL REG_SET_VAL_WO
8476 #define R_IRQ_MASK1_CLR__EQL REG_EQL_WO
8477 #define R_IRQ_MASK1_CLR__IEQL REG_IEQL_WO
8478 #define R_IRQ_MASK1_CLR__RD REG_RD_WO
8479 #define R_IRQ_MASK1_CLR__IRD REG_IRD_WO
8480 #define R_IRQ_MASK1_CLR__WR REG_WR_WO
8481 #define R_IRQ_MASK1_CLR__IWR REG_IWR_WO
8482
8483 #define R_IRQ_MASK1_CLR__WRITE(addr,value) \
8484 (*(addr) = (value))
8485
8486 #define R_IRQ_MASK1_CLR__sw_int7__sw_int7__MASK 0x80000000U
8487 #define R_IRQ_MASK1_CLR__sw_int6__sw_int6__MASK 0x40000000U
8488 #define R_IRQ_MASK1_CLR__sw_int5__sw_int5__MASK 0x20000000U
8489 #define R_IRQ_MASK1_CLR__sw_int4__sw_int4__MASK 0x10000000U
8490 #define R_IRQ_MASK1_CLR__sw_int3__sw_int3__MASK 0x08000000U
8491 #define R_IRQ_MASK1_CLR__sw_int2__sw_int2__MASK 0x04000000U
8492 #define R_IRQ_MASK1_CLR__sw_int1__sw_int1__MASK 0x02000000U
8493 #define R_IRQ_MASK1_CLR__sw_int0__sw_int0__MASK 0x01000000U
8494 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
8495 #define R_IRQ_MASK1_CLR__par1_peri__par1_peri__MASK 0x00040000U
8496 #define R_IRQ_MASK1_CLR__par1_data__par1_data__MASK 0x00020000U
8497 #define R_IRQ_MASK1_CLR__par1_ready__par1_ready__MASK 0x00010000U
8498 #define R_IRQ_MASK1_CLR__scsi1__scsi1__MASK 0x00010000U
8499 #define R_IRQ_MASK1_CLR__par1_ready__scsi1__MASK 0x00010000U
8500 #define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__MASK 0x00008000U
8501 #define R_IRQ_MASK1_CLR__ser3_data__ser3_data__MASK 0x00004000U
8502 #define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__MASK 0x00002000U
8503 #define R_IRQ_MASK1_CLR__ser2_data__ser2_data__MASK 0x00001000U
8504 #define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__MASK 0x00000800U
8505 #define R_IRQ_MASK1_CLR__ser1_data__ser1_data__MASK 0x00000400U
8506 #define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__MASK 0x00000200U
8507 #define R_IRQ_MASK1_CLR__ser0_data__ser0_data__MASK 0x00000100U
8508 #define R_IRQ_MASK1_CLR__pa7__pa7__MASK 0x00000080U
8509 #define R_IRQ_MASK1_CLR__pa6__pa6__MASK 0x00000040U
8510 #define R_IRQ_MASK1_CLR__pa5__pa5__MASK 0x00000020U
8511 #define R_IRQ_MASK1_CLR__pa4__pa4__MASK 0x00000010U
8512 #define R_IRQ_MASK1_CLR__pa3__pa3__MASK 0x00000008U
8513 #define R_IRQ_MASK1_CLR__pa2__pa2__MASK 0x00000004U
8514 #define R_IRQ_MASK1_CLR__pa1__pa1__MASK 0x00000002U
8515 #define R_IRQ_MASK1_CLR__pa0__pa0__MASK 0x00000001U
8516
8517 #define R_IRQ_MASK1_CLR__sw_int7__MAX 0x1
8518 #define R_IRQ_MASK1_CLR__sw_int6__MAX 0x1
8519 #define R_IRQ_MASK1_CLR__sw_int5__MAX 0x1
8520 #define R_IRQ_MASK1_CLR__sw_int4__MAX 0x1
8521 #define R_IRQ_MASK1_CLR__sw_int3__MAX 0x1
8522 #define R_IRQ_MASK1_CLR__sw_int2__MAX 0x1
8523 #define R_IRQ_MASK1_CLR__sw_int1__MAX 0x1
8524 #define R_IRQ_MASK1_CLR__sw_int0__MAX 0x1
8525 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__MAX 0x1
8526 #define R_IRQ_MASK1_CLR__par1_peri__MAX 0x1
8527 #define R_IRQ_MASK1_CLR__par1_data__MAX 0x1
8528 #define R_IRQ_MASK1_CLR__par1_ready__MAX 0x1
8529 #define R_IRQ_MASK1_CLR__scsi1__MAX 0x1
8530 #define R_IRQ_MASK1_CLR__ser3_ready__MAX 0x1
8531 #define R_IRQ_MASK1_CLR__ser3_data__MAX 0x1
8532 #define R_IRQ_MASK1_CLR__ser2_ready__MAX 0x1
8533 #define R_IRQ_MASK1_CLR__ser2_data__MAX 0x1
8534 #define R_IRQ_MASK1_CLR__ser1_ready__MAX 0x1
8535 #define R_IRQ_MASK1_CLR__ser1_data__MAX 0x1
8536 #define R_IRQ_MASK1_CLR__ser0_ready__MAX 0x1
8537 #define R_IRQ_MASK1_CLR__ser0_data__MAX 0x1
8538 #define R_IRQ_MASK1_CLR__pa7__MAX 0x1
8539 #define R_IRQ_MASK1_CLR__pa6__MAX 0x1
8540 #define R_IRQ_MASK1_CLR__pa5__MAX 0x1
8541 #define R_IRQ_MASK1_CLR__pa4__MAX 0x1
8542 #define R_IRQ_MASK1_CLR__pa3__MAX 0x1
8543 #define R_IRQ_MASK1_CLR__pa2__MAX 0x1
8544 #define R_IRQ_MASK1_CLR__pa1__MAX 0x1
8545 #define R_IRQ_MASK1_CLR__pa0__MAX 0x1
8546
8547 #define R_IRQ_MASK1_CLR__sw_int7__MIN 0
8548 #define R_IRQ_MASK1_CLR__sw_int6__MIN 0
8549 #define R_IRQ_MASK1_CLR__sw_int5__MIN 0
8550 #define R_IRQ_MASK1_CLR__sw_int4__MIN 0
8551 #define R_IRQ_MASK1_CLR__sw_int3__MIN 0
8552 #define R_IRQ_MASK1_CLR__sw_int2__MIN 0
8553 #define R_IRQ_MASK1_CLR__sw_int1__MIN 0
8554 #define R_IRQ_MASK1_CLR__sw_int0__MIN 0
8555 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__MIN 0
8556 #define R_IRQ_MASK1_CLR__par1_peri__MIN 0
8557 #define R_IRQ_MASK1_CLR__par1_data__MIN 0
8558 #define R_IRQ_MASK1_CLR__par1_ready__MIN 0
8559 #define R_IRQ_MASK1_CLR__scsi1__MIN 0
8560 #define R_IRQ_MASK1_CLR__ser3_ready__MIN 0
8561 #define R_IRQ_MASK1_CLR__ser3_data__MIN 0
8562 #define R_IRQ_MASK1_CLR__ser2_ready__MIN 0
8563 #define R_IRQ_MASK1_CLR__ser2_data__MIN 0
8564 #define R_IRQ_MASK1_CLR__ser1_ready__MIN 0
8565 #define R_IRQ_MASK1_CLR__ser1_data__MIN 0
8566 #define R_IRQ_MASK1_CLR__ser0_ready__MIN 0
8567 #define R_IRQ_MASK1_CLR__ser0_data__MIN 0
8568 #define R_IRQ_MASK1_CLR__pa7__MIN 0
8569 #define R_IRQ_MASK1_CLR__pa6__MIN 0
8570 #define R_IRQ_MASK1_CLR__pa5__MIN 0
8571 #define R_IRQ_MASK1_CLR__pa4__MIN 0
8572 #define R_IRQ_MASK1_CLR__pa3__MIN 0
8573 #define R_IRQ_MASK1_CLR__pa2__MIN 0
8574 #define R_IRQ_MASK1_CLR__pa1__MIN 0
8575 #define R_IRQ_MASK1_CLR__pa0__MIN 0
8576
8577 #define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
8578 #define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
8579 #define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
8580 #define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
8581 #define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
8582 #define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
8583 #define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
8584 #define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
8585 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
8586 #define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
8587 #define R_IRQ_MASK1_CLR__par1_data__BITNR 17
8588 #define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
8589 #define R_IRQ_MASK1_CLR__scsi1__BITNR 16
8590 #define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
8591 #define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
8592 #define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
8593 #define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
8594 #define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
8595 #define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
8596 #define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
8597 #define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
8598 #define R_IRQ_MASK1_CLR__pa7__BITNR 7
8599 #define R_IRQ_MASK1_CLR__pa6__BITNR 6
8600 #define R_IRQ_MASK1_CLR__pa5__BITNR 5
8601 #define R_IRQ_MASK1_CLR__pa4__BITNR 4
8602 #define R_IRQ_MASK1_CLR__pa3__BITNR 3
8603 #define R_IRQ_MASK1_CLR__pa2__BITNR 2
8604 #define R_IRQ_MASK1_CLR__pa1__BITNR 1
8605 #define R_IRQ_MASK1_CLR__pa0__BITNR 0
8606
8607 #define R_IRQ_MASK1_CLR__sw_int7__sw_int7__VAL REG_VAL_ENUM
8608 #define R_IRQ_MASK1_CLR__sw_int6__sw_int6__VAL REG_VAL_ENUM
8609 #define R_IRQ_MASK1_CLR__sw_int5__sw_int5__VAL REG_VAL_ENUM
8610 #define R_IRQ_MASK1_CLR__sw_int4__sw_int4__VAL REG_VAL_ENUM
8611 #define R_IRQ_MASK1_CLR__sw_int3__sw_int3__VAL REG_VAL_ENUM
8612 #define R_IRQ_MASK1_CLR__sw_int2__sw_int2__VAL REG_VAL_ENUM
8613 #define R_IRQ_MASK1_CLR__sw_int1__sw_int1__VAL REG_VAL_ENUM
8614 #define R_IRQ_MASK1_CLR__sw_int0__sw_int0__VAL REG_VAL_ENUM
8615 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
8616 #define R_IRQ_MASK1_CLR__par1_peri__par1_peri__VAL REG_VAL_ENUM
8617 #define R_IRQ_MASK1_CLR__par1_data__par1_data__VAL REG_VAL_ENUM
8618 #define R_IRQ_MASK1_CLR__par1_ready__par1_ready__VAL REG_VAL_ENUM
8619 #define R_IRQ_MASK1_CLR__scsi1__scsi1__VAL REG_VAL_ENUM
8620 #define R_IRQ_MASK1_CLR__par1_ready__scsi1__VAL REG_VAL_ENUM
8621 #define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
8622 #define R_IRQ_MASK1_CLR__ser3_data__ser3_data__VAL REG_VAL_ENUM
8623 #define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
8624 #define R_IRQ_MASK1_CLR__ser2_data__ser2_data__VAL REG_VAL_ENUM
8625 #define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
8626 #define R_IRQ_MASK1_CLR__ser1_data__ser1_data__VAL REG_VAL_ENUM
8627 #define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
8628 #define R_IRQ_MASK1_CLR__ser0_data__ser0_data__VAL REG_VAL_ENUM
8629 #define R_IRQ_MASK1_CLR__pa7__pa7__VAL REG_VAL_ENUM
8630 #define R_IRQ_MASK1_CLR__pa6__pa6__VAL REG_VAL_ENUM
8631 #define R_IRQ_MASK1_CLR__pa5__pa5__VAL REG_VAL_ENUM
8632 #define R_IRQ_MASK1_CLR__pa4__pa4__VAL REG_VAL_ENUM
8633 #define R_IRQ_MASK1_CLR__pa3__pa3__VAL REG_VAL_ENUM
8634 #define R_IRQ_MASK1_CLR__pa2__pa2__VAL REG_VAL_ENUM
8635 #define R_IRQ_MASK1_CLR__pa1__pa1__VAL REG_VAL_ENUM
8636 #define R_IRQ_MASK1_CLR__pa0__pa0__VAL REG_VAL_ENUM
8637
8638 #define R_IRQ_MASK1_CLR__sw_int7__sw_int7__clr 1
8639 #define R_IRQ_MASK1_CLR__sw_int7__sw_int7__nop 0
8640 #define R_IRQ_MASK1_CLR__sw_int6__sw_int6__clr 1
8641 #define R_IRQ_MASK1_CLR__sw_int6__sw_int6__nop 0
8642 #define R_IRQ_MASK1_CLR__sw_int5__sw_int5__clr 1
8643 #define R_IRQ_MASK1_CLR__sw_int5__sw_int5__nop 0
8644 #define R_IRQ_MASK1_CLR__sw_int4__sw_int4__clr 1
8645 #define R_IRQ_MASK1_CLR__sw_int4__sw_int4__nop 0
8646 #define R_IRQ_MASK1_CLR__sw_int3__sw_int3__clr 1
8647 #define R_IRQ_MASK1_CLR__sw_int3__sw_int3__nop 0
8648 #define R_IRQ_MASK1_CLR__sw_int2__sw_int2__clr 1
8649 #define R_IRQ_MASK1_CLR__sw_int2__sw_int2__nop 0
8650 #define R_IRQ_MASK1_CLR__sw_int1__sw_int1__clr 1
8651 #define R_IRQ_MASK1_CLR__sw_int1__sw_int1__nop 0
8652 #define R_IRQ_MASK1_CLR__sw_int0__sw_int0__clr 1
8653 #define R_IRQ_MASK1_CLR__sw_int0__sw_int0__nop 0
8654 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__clr 1
8655 #define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__nop 0
8656 #define R_IRQ_MASK1_CLR__par1_peri__par1_peri__clr 1
8657 #define R_IRQ_MASK1_CLR__par1_peri__par1_peri__nop 0
8658 #define R_IRQ_MASK1_CLR__par1_data__par1_data__clr 1
8659 #define R_IRQ_MASK1_CLR__par1_data__par1_data__nop 0
8660 #define R_IRQ_MASK1_CLR__par1_ready__par1_ready__clr 1
8661 #define R_IRQ_MASK1_CLR__par1_ready__par1_ready__nop 0
8662 #define R_IRQ_MASK1_CLR__scsi1__scsi1__clr 1
8663 #define R_IRQ_MASK1_CLR__scsi1__scsi1__nop 0
8664 #define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__clr 1
8665 #define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__nop 0
8666 #define R_IRQ_MASK1_CLR__ser3_data__ser3_data__clr 1
8667 #define R_IRQ_MASK1_CLR__ser3_data__ser3_data__nop 0
8668 #define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__clr 1
8669 #define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__nop 0
8670 #define R_IRQ_MASK1_CLR__ser2_data__ser2_data__clr 1
8671 #define R_IRQ_MASK1_CLR__ser2_data__ser2_data__nop 0
8672 #define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__clr 1
8673 #define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__nop 0
8674 #define R_IRQ_MASK1_CLR__ser1_data__ser1_data__clr 1
8675 #define R_IRQ_MASK1_CLR__ser1_data__ser1_data__nop 0
8676 #define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__clr 1
8677 #define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__nop 0
8678 #define R_IRQ_MASK1_CLR__ser0_data__ser0_data__clr 1
8679 #define R_IRQ_MASK1_CLR__ser0_data__ser0_data__nop 0
8680 #define R_IRQ_MASK1_CLR__pa7__pa7__clr 1
8681 #define R_IRQ_MASK1_CLR__pa7__pa7__nop 0
8682 #define R_IRQ_MASK1_CLR__pa6__pa6__clr 1
8683 #define R_IRQ_MASK1_CLR__pa6__pa6__nop 0
8684 #define R_IRQ_MASK1_CLR__pa5__pa5__clr 1
8685 #define R_IRQ_MASK1_CLR__pa5__pa5__nop 0
8686 #define R_IRQ_MASK1_CLR__pa4__pa4__clr 1
8687 #define R_IRQ_MASK1_CLR__pa4__pa4__nop 0
8688 #define R_IRQ_MASK1_CLR__pa3__pa3__clr 1
8689 #define R_IRQ_MASK1_CLR__pa3__pa3__nop 0
8690 #define R_IRQ_MASK1_CLR__pa2__pa2__clr 1
8691 #define R_IRQ_MASK1_CLR__pa2__pa2__nop 0
8692 #define R_IRQ_MASK1_CLR__pa1__pa1__clr 1
8693 #define R_IRQ_MASK1_CLR__pa1__pa1__nop 0
8694 #define R_IRQ_MASK1_CLR__pa0__pa0__clr 1
8695 #define R_IRQ_MASK1_CLR__pa0__pa0__nop 0
8696
8697 #endif
8698
8699 /*
8700 * R_IRQ_MASK1_RD
8701 * - type: RO
8702 * - addr: 0xb00000c8
8703 * - group: Interrupt mask and status registers
8704 */
8705
8706 #if USE_GROUP__Interrupt_mask_and_status_registers
8707
8708 #define R_IRQ_MASK1_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c8)
8709 #define R_IRQ_MASK1_RD__SVAL REG_SVAL_SHADOW
8710 #define R_IRQ_MASK1_RD__SVAL_I REG_SVAL_I_SHADOW
8711 #define R_IRQ_MASK1_RD__TYPECAST REG_TYPECAST_UDWORD
8712 #define R_IRQ_MASK1_RD__TYPE (REG_UDWORD)
8713 #define R_IRQ_MASK1_RD__GET REG_GET_RO
8714 #define R_IRQ_MASK1_RD__IGET REG_IGET_RO
8715 #define R_IRQ_MASK1_RD__SET REG_SET_RO
8716 #define R_IRQ_MASK1_RD__ISET REG_ISET_RO
8717 #define R_IRQ_MASK1_RD__SET_VAL REG_SET_VAL_RO
8718 #define R_IRQ_MASK1_RD__EQL REG_EQL_RO
8719 #define R_IRQ_MASK1_RD__IEQL REG_IEQL_RO
8720 #define R_IRQ_MASK1_RD__RD REG_RD_RO
8721 #define R_IRQ_MASK1_RD__IRD REG_IRD_RO
8722 #define R_IRQ_MASK1_RD__WR REG_WR_RO
8723 #define R_IRQ_MASK1_RD__IWR REG_IWR_RO
8724
8725 #define R_IRQ_MASK1_RD__READ(addr) \
8726 (*(addr))
8727
8728 #define R_IRQ_MASK1_RD__sw_int7__sw_int7__MASK 0x80000000U
8729 #define R_IRQ_MASK1_RD__sw_int6__sw_int6__MASK 0x40000000U
8730 #define R_IRQ_MASK1_RD__sw_int5__sw_int5__MASK 0x20000000U
8731 #define R_IRQ_MASK1_RD__sw_int4__sw_int4__MASK 0x10000000U
8732 #define R_IRQ_MASK1_RD__sw_int3__sw_int3__MASK 0x08000000U
8733 #define R_IRQ_MASK1_RD__sw_int2__sw_int2__MASK 0x04000000U
8734 #define R_IRQ_MASK1_RD__sw_int1__sw_int1__MASK 0x02000000U
8735 #define R_IRQ_MASK1_RD__sw_int0__sw_int0__MASK 0x01000000U
8736 #define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
8737 #define R_IRQ_MASK1_RD__par1_peri__par1_peri__MASK 0x00040000U
8738 #define R_IRQ_MASK1_RD__par1_data__par1_data__MASK 0x00020000U
8739 #define R_IRQ_MASK1_RD__par1_ready__par1_ready__MASK 0x00010000U
8740 #define R_IRQ_MASK1_RD__scsi1__scsi1__MASK 0x00010000U
8741 #define R_IRQ_MASK1_RD__par1_ready__scsi1__MASK 0x00010000U
8742 #define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__MASK 0x00008000U
8743 #define R_IRQ_MASK1_RD__ser3_data__ser3_data__MASK 0x00004000U
8744 #define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__MASK 0x00002000U
8745 #define R_IRQ_MASK1_RD__ser2_data__ser2_data__MASK 0x00001000U
8746 #define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__MASK 0x00000800U
8747 #define R_IRQ_MASK1_RD__ser1_data__ser1_data__MASK 0x00000400U
8748 #define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__MASK 0x00000200U
8749 #define R_IRQ_MASK1_RD__ser0_data__ser0_data__MASK 0x00000100U
8750 #define R_IRQ_MASK1_RD__pa7__pa7__MASK 0x00000080U
8751 #define R_IRQ_MASK1_RD__pa6__pa6__MASK 0x00000040U
8752 #define R_IRQ_MASK1_RD__pa5__pa5__MASK 0x00000020U
8753 #define R_IRQ_MASK1_RD__pa4__pa4__MASK 0x00000010U
8754 #define R_IRQ_MASK1_RD__pa3__pa3__MASK 0x00000008U
8755 #define R_IRQ_MASK1_RD__pa2__pa2__MASK 0x00000004U
8756 #define R_IRQ_MASK1_RD__pa1__pa1__MASK 0x00000002U
8757 #define R_IRQ_MASK1_RD__pa0__pa0__MASK 0x00000001U
8758
8759 #define R_IRQ_MASK1_RD__sw_int7__MAX 0x1
8760 #define R_IRQ_MASK1_RD__sw_int6__MAX 0x1
8761 #define R_IRQ_MASK1_RD__sw_int5__MAX 0x1
8762 #define R_IRQ_MASK1_RD__sw_int4__MAX 0x1
8763 #define R_IRQ_MASK1_RD__sw_int3__MAX 0x1
8764 #define R_IRQ_MASK1_RD__sw_int2__MAX 0x1
8765 #define R_IRQ_MASK1_RD__sw_int1__MAX 0x1
8766 #define R_IRQ_MASK1_RD__sw_int0__MAX 0x1
8767 #define R_IRQ_MASK1_RD__par1_ecp_cmd__MAX 0x1
8768 #define R_IRQ_MASK1_RD__par1_peri__MAX 0x1
8769 #define R_IRQ_MASK1_RD__par1_data__MAX 0x1
8770 #define R_IRQ_MASK1_RD__par1_ready__MAX 0x1
8771 #define R_IRQ_MASK1_RD__scsi1__MAX 0x1
8772 #define R_IRQ_MASK1_RD__ser3_ready__MAX 0x1
8773 #define R_IRQ_MASK1_RD__ser3_data__MAX 0x1
8774 #define R_IRQ_MASK1_RD__ser2_ready__MAX 0x1
8775 #define R_IRQ_MASK1_RD__ser2_data__MAX 0x1
8776 #define R_IRQ_MASK1_RD__ser1_ready__MAX 0x1
8777 #define R_IRQ_MASK1_RD__ser1_data__MAX 0x1
8778 #define R_IRQ_MASK1_RD__ser0_ready__MAX 0x1
8779 #define R_IRQ_MASK1_RD__ser0_data__MAX 0x1
8780 #define R_IRQ_MASK1_RD__pa7__MAX 0x1
8781 #define R_IRQ_MASK1_RD__pa6__MAX 0x1
8782 #define R_IRQ_MASK1_RD__pa5__MAX 0x1
8783 #define R_IRQ_MASK1_RD__pa4__MAX 0x1
8784 #define R_IRQ_MASK1_RD__pa3__MAX 0x1
8785 #define R_IRQ_MASK1_RD__pa2__MAX 0x1
8786 #define R_IRQ_MASK1_RD__pa1__MAX 0x1
8787 #define R_IRQ_MASK1_RD__pa0__MAX 0x1
8788
8789 #define R_IRQ_MASK1_RD__sw_int7__MIN 0
8790 #define R_IRQ_MASK1_RD__sw_int6__MIN 0
8791 #define R_IRQ_MASK1_RD__sw_int5__MIN 0
8792 #define R_IRQ_MASK1_RD__sw_int4__MIN 0
8793 #define R_IRQ_MASK1_RD__sw_int3__MIN 0
8794 #define R_IRQ_MASK1_RD__sw_int2__MIN 0
8795 #define R_IRQ_MASK1_RD__sw_int1__MIN 0
8796 #define R_IRQ_MASK1_RD__sw_int0__MIN 0
8797 #define R_IRQ_MASK1_RD__par1_ecp_cmd__MIN 0
8798 #define R_IRQ_MASK1_RD__par1_peri__MIN 0
8799 #define R_IRQ_MASK1_RD__par1_data__MIN 0
8800 #define R_IRQ_MASK1_RD__par1_ready__MIN 0
8801 #define R_IRQ_MASK1_RD__scsi1__MIN 0
8802 #define R_IRQ_MASK1_RD__ser3_ready__MIN 0
8803 #define R_IRQ_MASK1_RD__ser3_data__MIN 0
8804 #define R_IRQ_MASK1_RD__ser2_ready__MIN 0
8805 #define R_IRQ_MASK1_RD__ser2_data__MIN 0
8806 #define R_IRQ_MASK1_RD__ser1_ready__MIN 0
8807 #define R_IRQ_MASK1_RD__ser1_data__MIN 0
8808 #define R_IRQ_MASK1_RD__ser0_ready__MIN 0
8809 #define R_IRQ_MASK1_RD__ser0_data__MIN 0
8810 #define R_IRQ_MASK1_RD__pa7__MIN 0
8811 #define R_IRQ_MASK1_RD__pa6__MIN 0
8812 #define R_IRQ_MASK1_RD__pa5__MIN 0
8813 #define R_IRQ_MASK1_RD__pa4__MIN 0
8814 #define R_IRQ_MASK1_RD__pa3__MIN 0
8815 #define R_IRQ_MASK1_RD__pa2__MIN 0
8816 #define R_IRQ_MASK1_RD__pa1__MIN 0
8817 #define R_IRQ_MASK1_RD__pa0__MIN 0
8818
8819 #define R_IRQ_MASK1_RD__sw_int7__BITNR 31
8820 #define R_IRQ_MASK1_RD__sw_int6__BITNR 30
8821 #define R_IRQ_MASK1_RD__sw_int5__BITNR 29
8822 #define R_IRQ_MASK1_RD__sw_int4__BITNR 28
8823 #define R_IRQ_MASK1_RD__sw_int3__BITNR 27
8824 #define R_IRQ_MASK1_RD__sw_int2__BITNR 26
8825 #define R_IRQ_MASK1_RD__sw_int1__BITNR 25
8826 #define R_IRQ_MASK1_RD__sw_int0__BITNR 24
8827 #define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
8828 #define R_IRQ_MASK1_RD__par1_peri__BITNR 18
8829 #define R_IRQ_MASK1_RD__par1_data__BITNR 17
8830 #define R_IRQ_MASK1_RD__par1_ready__BITNR 16
8831 #define R_IRQ_MASK1_RD__scsi1__BITNR 16
8832 #define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
8833 #define R_IRQ_MASK1_RD__ser3_data__BITNR 14
8834 #define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
8835 #define R_IRQ_MASK1_RD__ser2_data__BITNR 12
8836 #define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
8837 #define R_IRQ_MASK1_RD__ser1_data__BITNR 10
8838 #define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
8839 #define R_IRQ_MASK1_RD__ser0_data__BITNR 8
8840 #define R_IRQ_MASK1_RD__pa7__BITNR 7
8841 #define R_IRQ_MASK1_RD__pa6__BITNR 6
8842 #define R_IRQ_MASK1_RD__pa5__BITNR 5
8843 #define R_IRQ_MASK1_RD__pa4__BITNR 4
8844 #define R_IRQ_MASK1_RD__pa3__BITNR 3
8845 #define R_IRQ_MASK1_RD__pa2__BITNR 2
8846 #define R_IRQ_MASK1_RD__pa1__BITNR 1
8847 #define R_IRQ_MASK1_RD__pa0__BITNR 0
8848
8849 #define R_IRQ_MASK1_RD__sw_int7__sw_int7__VAL REG_VAL_ENUM
8850 #define R_IRQ_MASK1_RD__sw_int6__sw_int6__VAL REG_VAL_ENUM
8851 #define R_IRQ_MASK1_RD__sw_int5__sw_int5__VAL REG_VAL_ENUM
8852 #define R_IRQ_MASK1_RD__sw_int4__sw_int4__VAL REG_VAL_ENUM
8853 #define R_IRQ_MASK1_RD__sw_int3__sw_int3__VAL REG_VAL_ENUM
8854 #define R_IRQ_MASK1_RD__sw_int2__sw_int2__VAL REG_VAL_ENUM
8855 #define R_IRQ_MASK1_RD__sw_int1__sw_int1__VAL REG_VAL_ENUM
8856 #define R_IRQ_MASK1_RD__sw_int0__sw_int0__VAL REG_VAL_ENUM
8857 #define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
8858 #define R_IRQ_MASK1_RD__par1_peri__par1_peri__VAL REG_VAL_ENUM
8859 #define R_IRQ_MASK1_RD__par1_data__par1_data__VAL REG_VAL_ENUM
8860 #define R_IRQ_MASK1_RD__par1_ready__par1_ready__VAL REG_VAL_ENUM
8861 #define R_IRQ_MASK1_RD__scsi1__scsi1__VAL REG_VAL_ENUM
8862 #define R_IRQ_MASK1_RD__par1_ready__scsi1__VAL REG_VAL_ENUM
8863 #define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
8864 #define R_IRQ_MASK1_RD__ser3_data__ser3_data__VAL REG_VAL_ENUM
8865 #define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
8866 #define R_IRQ_MASK1_RD__ser2_data__ser2_data__VAL REG_VAL_ENUM
8867 #define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
8868 #define R_IRQ_MASK1_RD__ser1_data__ser1_data__VAL REG_VAL_ENUM
8869 #define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
8870 #define R_IRQ_MASK1_RD__ser0_data__ser0_data__VAL REG_VAL_ENUM
8871 #define R_IRQ_MASK1_RD__pa7__pa7__VAL REG_VAL_ENUM
8872 #define R_IRQ_MASK1_RD__pa6__pa6__VAL REG_VAL_ENUM
8873 #define R_IRQ_MASK1_RD__pa5__pa5__VAL REG_VAL_ENUM
8874 #define R_IRQ_MASK1_RD__pa4__pa4__VAL REG_VAL_ENUM
8875 #define R_IRQ_MASK1_RD__pa3__pa3__VAL REG_VAL_ENUM
8876 #define R_IRQ_MASK1_RD__pa2__pa2__VAL REG_VAL_ENUM
8877 #define R_IRQ_MASK1_RD__pa1__pa1__VAL REG_VAL_ENUM
8878 #define R_IRQ_MASK1_RD__pa0__pa0__VAL REG_VAL_ENUM
8879
8880 #define R_IRQ_MASK1_RD__sw_int7__sw_int7__active 1
8881 #define R_IRQ_MASK1_RD__sw_int7__sw_int7__inactive 0
8882 #define R_IRQ_MASK1_RD__sw_int6__sw_int6__active 1
8883 #define R_IRQ_MASK1_RD__sw_int6__sw_int6__inactive 0
8884 #define R_IRQ_MASK1_RD__sw_int5__sw_int5__active 1
8885 #define R_IRQ_MASK1_RD__sw_int5__sw_int5__inactive 0
8886 #define R_IRQ_MASK1_RD__sw_int4__sw_int4__active 1
8887 #define R_IRQ_MASK1_RD__sw_int4__sw_int4__inactive 0
8888 #define R_IRQ_MASK1_RD__sw_int3__sw_int3__active 1
8889 #define R_IRQ_MASK1_RD__sw_int3__sw_int3__inactive 0
8890 #define R_IRQ_MASK1_RD__sw_int2__sw_int2__active 1
8891 #define R_IRQ_MASK1_RD__sw_int2__sw_int2__inactive 0
8892 #define R_IRQ_MASK1_RD__sw_int1__sw_int1__active 1
8893 #define R_IRQ_MASK1_RD__sw_int1__sw_int1__inactive 0
8894 #define R_IRQ_MASK1_RD__sw_int0__sw_int0__active 1
8895 #define R_IRQ_MASK1_RD__sw_int0__sw_int0__inactive 0
8896 #define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__active 1
8897 #define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__inactive 0
8898 #define R_IRQ_MASK1_RD__par1_peri__par1_peri__active 1
8899 #define R_IRQ_MASK1_RD__par1_peri__par1_peri__inactive 0
8900 #define R_IRQ_MASK1_RD__par1_data__par1_data__active 1
8901 #define R_IRQ_MASK1_RD__par1_data__par1_data__inactive 0
8902 #define R_IRQ_MASK1_RD__par1_ready__par1_ready__active 1
8903 #define R_IRQ_MASK1_RD__par1_ready__par1_ready__inactive 0
8904 #define R_IRQ_MASK1_RD__scsi1__scsi1__active 1
8905 #define R_IRQ_MASK1_RD__scsi1__scsi1__inactive 0
8906 #define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__active 1
8907 #define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__inactive 0
8908 #define R_IRQ_MASK1_RD__ser3_data__ser3_data__active 1
8909 #define R_IRQ_MASK1_RD__ser3_data__ser3_data__inactive 0
8910 #define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__active 1
8911 #define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__inactive 0
8912 #define R_IRQ_MASK1_RD__ser2_data__ser2_data__active 1
8913 #define R_IRQ_MASK1_RD__ser2_data__ser2_data__inactive 0
8914 #define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__active 1
8915 #define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__inactive 0
8916 #define R_IRQ_MASK1_RD__ser1_data__ser1_data__active 1
8917 #define R_IRQ_MASK1_RD__ser1_data__ser1_data__inactive 0
8918 #define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__active 1
8919 #define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__inactive 0
8920 #define R_IRQ_MASK1_RD__ser0_data__ser0_data__active 1
8921 #define R_IRQ_MASK1_RD__ser0_data__ser0_data__inactive 0
8922 #define R_IRQ_MASK1_RD__pa7__pa7__active 1
8923 #define R_IRQ_MASK1_RD__pa7__pa7__inactive 0
8924 #define R_IRQ_MASK1_RD__pa6__pa6__active 1
8925 #define R_IRQ_MASK1_RD__pa6__pa6__inactive 0
8926 #define R_IRQ_MASK1_RD__pa5__pa5__active 1
8927 #define R_IRQ_MASK1_RD__pa5__pa5__inactive 0
8928 #define R_IRQ_MASK1_RD__pa4__pa4__active 1
8929 #define R_IRQ_MASK1_RD__pa4__pa4__inactive 0
8930 #define R_IRQ_MASK1_RD__pa3__pa3__active 1
8931 #define R_IRQ_MASK1_RD__pa3__pa3__inactive 0
8932 #define R_IRQ_MASK1_RD__pa2__pa2__active 1
8933 #define R_IRQ_MASK1_RD__pa2__pa2__inactive 0
8934 #define R_IRQ_MASK1_RD__pa1__pa1__active 1
8935 #define R_IRQ_MASK1_RD__pa1__pa1__inactive 0
8936 #define R_IRQ_MASK1_RD__pa0__pa0__active 1
8937 #define R_IRQ_MASK1_RD__pa0__pa0__inactive 0
8938
8939 #endif
8940
8941 /*
8942 * R_IRQ_MASK1_SET
8943 * - type: WO
8944 * - addr: 0xb00000cc
8945 * - group: Interrupt mask and status registers
8946 */
8947
8948 #if USE_GROUP__Interrupt_mask_and_status_registers
8949
8950 #define R_IRQ_MASK1_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000cc)
8951
8952 #ifndef REG_NO_SHADOW
8953 #define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_SET + 0))
8954 #define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_SET + 0))
8955 #else /* REG_NO_SHADOW */
8956 #define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
8957 #define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
8958 #endif /* REG_NO_SHADOW */
8959
8960 #define R_IRQ_MASK1_SET__STYPECAST REG_STYPECAST_UDWORD
8961 #define R_IRQ_MASK1_SET__SVAL REG_SVAL_ZERO
8962 #define R_IRQ_MASK1_SET__SVAL_I REG_SVAL_I_ZERO
8963 #define R_IRQ_MASK1_SET__TYPECAST REG_TYPECAST_UDWORD
8964 #define R_IRQ_MASK1_SET__TYPE (REG_UDWORD)
8965 #define R_IRQ_MASK1_SET__GET REG_GET_WO
8966 #define R_IRQ_MASK1_SET__IGET REG_IGET_WO
8967 #define R_IRQ_MASK1_SET__SET REG_SET_WO
8968 #define R_IRQ_MASK1_SET__ISET REG_ISET_WO
8969 #define R_IRQ_MASK1_SET__SET_VAL REG_SET_VAL_WO
8970 #define R_IRQ_MASK1_SET__EQL REG_EQL_WO
8971 #define R_IRQ_MASK1_SET__IEQL REG_IEQL_WO
8972 #define R_IRQ_MASK1_SET__RD REG_RD_WO
8973 #define R_IRQ_MASK1_SET__IRD REG_IRD_WO
8974 #define R_IRQ_MASK1_SET__WR REG_WR_WO
8975 #define R_IRQ_MASK1_SET__IWR REG_IWR_WO
8976
8977 #define R_IRQ_MASK1_SET__WRITE(addr,value) \
8978 (*(addr) = (value))
8979
8980 #define R_IRQ_MASK1_SET__sw_int7__sw_int7__MASK 0x80000000U
8981 #define R_IRQ_MASK1_SET__sw_int6__sw_int6__MASK 0x40000000U
8982 #define R_IRQ_MASK1_SET__sw_int5__sw_int5__MASK 0x20000000U
8983 #define R_IRQ_MASK1_SET__sw_int4__sw_int4__MASK 0x10000000U
8984 #define R_IRQ_MASK1_SET__sw_int3__sw_int3__MASK 0x08000000U
8985 #define R_IRQ_MASK1_SET__sw_int2__sw_int2__MASK 0x04000000U
8986 #define R_IRQ_MASK1_SET__sw_int1__sw_int1__MASK 0x02000000U
8987 #define R_IRQ_MASK1_SET__sw_int0__sw_int0__MASK 0x01000000U
8988 #define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
8989 #define R_IRQ_MASK1_SET__par1_peri__par1_peri__MASK 0x00040000U
8990 #define R_IRQ_MASK1_SET__par1_data__par1_data__MASK 0x00020000U
8991 #define R_IRQ_MASK1_SET__par1_ready__par1_ready__MASK 0x00010000U
8992 #define R_IRQ_MASK1_SET__scsi1__scsi1__MASK 0x00010000U
8993 #define R_IRQ_MASK1_SET__par1_ready__scsi1__MASK 0x00010000U
8994 #define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__MASK 0x00008000U
8995 #define R_IRQ_MASK1_SET__ser3_data__ser3_data__MASK 0x00004000U
8996 #define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__MASK 0x00002000U
8997 #define R_IRQ_MASK1_SET__ser2_data__ser2_data__MASK 0x00001000U
8998 #define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__MASK 0x00000800U
8999 #define R_IRQ_MASK1_SET__ser1_data__ser1_data__MASK 0x00000400U
9000 #define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__MASK 0x00000200U
9001 #define R_IRQ_MASK1_SET__ser0_data__ser0_data__MASK 0x00000100U
9002 #define R_IRQ_MASK1_SET__pa7__pa7__MASK 0x00000080U
9003 #define R_IRQ_MASK1_SET__pa6__pa6__MASK 0x00000040U
9004 #define R_IRQ_MASK1_SET__pa5__pa5__MASK 0x00000020U
9005 #define R_IRQ_MASK1_SET__pa4__pa4__MASK 0x00000010U
9006 #define R_IRQ_MASK1_SET__pa3__pa3__MASK 0x00000008U
9007 #define R_IRQ_MASK1_SET__pa2__pa2__MASK 0x00000004U
9008 #define R_IRQ_MASK1_SET__pa1__pa1__MASK 0x00000002U
9009 #define R_IRQ_MASK1_SET__pa0__pa0__MASK 0x00000001U
9010
9011 #define R_IRQ_MASK1_SET__sw_int7__MAX 0x1
9012 #define R_IRQ_MASK1_SET__sw_int6__MAX 0x1
9013 #define R_IRQ_MASK1_SET__sw_int5__MAX 0x1
9014 #define R_IRQ_MASK1_SET__sw_int4__MAX 0x1
9015 #define R_IRQ_MASK1_SET__sw_int3__MAX 0x1
9016 #define R_IRQ_MASK1_SET__sw_int2__MAX 0x1
9017 #define R_IRQ_MASK1_SET__sw_int1__MAX 0x1
9018 #define R_IRQ_MASK1_SET__sw_int0__MAX 0x1
9019 #define R_IRQ_MASK1_SET__par1_ecp_cmd__MAX 0x1
9020 #define R_IRQ_MASK1_SET__par1_peri__MAX 0x1
9021 #define R_IRQ_MASK1_SET__par1_data__MAX 0x1
9022 #define R_IRQ_MASK1_SET__par1_ready__MAX 0x1
9023 #define R_IRQ_MASK1_SET__scsi1__MAX 0x1
9024 #define R_IRQ_MASK1_SET__ser3_ready__MAX 0x1
9025 #define R_IRQ_MASK1_SET__ser3_data__MAX 0x1
9026 #define R_IRQ_MASK1_SET__ser2_ready__MAX 0x1
9027 #define R_IRQ_MASK1_SET__ser2_data__MAX 0x1
9028 #define R_IRQ_MASK1_SET__ser1_ready__MAX 0x1
9029 #define R_IRQ_MASK1_SET__ser1_data__MAX 0x1
9030 #define R_IRQ_MASK1_SET__ser0_ready__MAX 0x1
9031 #define R_IRQ_MASK1_SET__ser0_data__MAX 0x1
9032 #define R_IRQ_MASK1_SET__pa7__MAX 0x1
9033 #define R_IRQ_MASK1_SET__pa6__MAX 0x1
9034 #define R_IRQ_MASK1_SET__pa5__MAX 0x1
9035 #define R_IRQ_MASK1_SET__pa4__MAX 0x1
9036 #define R_IRQ_MASK1_SET__pa3__MAX 0x1
9037 #define R_IRQ_MASK1_SET__pa2__MAX 0x1
9038 #define R_IRQ_MASK1_SET__pa1__MAX 0x1
9039 #define R_IRQ_MASK1_SET__pa0__MAX 0x1
9040
9041 #define R_IRQ_MASK1_SET__sw_int7__MIN 0
9042 #define R_IRQ_MASK1_SET__sw_int6__MIN 0
9043 #define R_IRQ_MASK1_SET__sw_int5__MIN 0
9044 #define R_IRQ_MASK1_SET__sw_int4__MIN 0
9045 #define R_IRQ_MASK1_SET__sw_int3__MIN 0
9046 #define R_IRQ_MASK1_SET__sw_int2__MIN 0
9047 #define R_IRQ_MASK1_SET__sw_int1__MIN 0
9048 #define R_IRQ_MASK1_SET__sw_int0__MIN 0
9049 #define R_IRQ_MASK1_SET__par1_ecp_cmd__MIN 0
9050 #define R_IRQ_MASK1_SET__par1_peri__MIN 0
9051 #define R_IRQ_MASK1_SET__par1_data__MIN 0
9052 #define R_IRQ_MASK1_SET__par1_ready__MIN 0
9053 #define R_IRQ_MASK1_SET__scsi1__MIN 0
9054 #define R_IRQ_MASK1_SET__ser3_ready__MIN 0
9055 #define R_IRQ_MASK1_SET__ser3_data__MIN 0
9056 #define R_IRQ_MASK1_SET__ser2_ready__MIN 0
9057 #define R_IRQ_MASK1_SET__ser2_data__MIN 0
9058 #define R_IRQ_MASK1_SET__ser1_ready__MIN 0
9059 #define R_IRQ_MASK1_SET__ser1_data__MIN 0
9060 #define R_IRQ_MASK1_SET__ser0_ready__MIN 0
9061 #define R_IRQ_MASK1_SET__ser0_data__MIN 0
9062 #define R_IRQ_MASK1_SET__pa7__MIN 0
9063 #define R_IRQ_MASK1_SET__pa6__MIN 0
9064 #define R_IRQ_MASK1_SET__pa5__MIN 0
9065 #define R_IRQ_MASK1_SET__pa4__MIN 0
9066 #define R_IRQ_MASK1_SET__pa3__MIN 0
9067 #define R_IRQ_MASK1_SET__pa2__MIN 0
9068 #define R_IRQ_MASK1_SET__pa1__MIN 0
9069 #define R_IRQ_MASK1_SET__pa0__MIN 0
9070
9071 #define R_IRQ_MASK1_SET__sw_int7__BITNR 31
9072 #define R_IRQ_MASK1_SET__sw_int6__BITNR 30
9073 #define R_IRQ_MASK1_SET__sw_int5__BITNR 29
9074 #define R_IRQ_MASK1_SET__sw_int4__BITNR 28
9075 #define R_IRQ_MASK1_SET__sw_int3__BITNR 27
9076 #define R_IRQ_MASK1_SET__sw_int2__BITNR 26
9077 #define R_IRQ_MASK1_SET__sw_int1__BITNR 25
9078 #define R_IRQ_MASK1_SET__sw_int0__BITNR 24
9079 #define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
9080 #define R_IRQ_MASK1_SET__par1_peri__BITNR 18
9081 #define R_IRQ_MASK1_SET__par1_data__BITNR 17
9082 #define R_IRQ_MASK1_SET__par1_ready__BITNR 16
9083 #define R_IRQ_MASK1_SET__scsi1__BITNR 16
9084 #define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
9085 #define R_IRQ_MASK1_SET__ser3_data__BITNR 14
9086 #define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
9087 #define R_IRQ_MASK1_SET__ser2_data__BITNR 12
9088 #define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
9089 #define R_IRQ_MASK1_SET__ser1_data__BITNR 10
9090 #define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
9091 #define R_IRQ_MASK1_SET__ser0_data__BITNR 8
9092 #define R_IRQ_MASK1_SET__pa7__BITNR 7
9093 #define R_IRQ_MASK1_SET__pa6__BITNR 6
9094 #define R_IRQ_MASK1_SET__pa5__BITNR 5
9095 #define R_IRQ_MASK1_SET__pa4__BITNR 4
9096 #define R_IRQ_MASK1_SET__pa3__BITNR 3
9097 #define R_IRQ_MASK1_SET__pa2__BITNR 2
9098 #define R_IRQ_MASK1_SET__pa1__BITNR 1
9099 #define R_IRQ_MASK1_SET__pa0__BITNR 0
9100
9101 #define R_IRQ_MASK1_SET__sw_int7__sw_int7__VAL REG_VAL_ENUM
9102 #define R_IRQ_MASK1_SET__sw_int6__sw_int6__VAL REG_VAL_ENUM
9103 #define R_IRQ_MASK1_SET__sw_int5__sw_int5__VAL REG_VAL_ENUM
9104 #define R_IRQ_MASK1_SET__sw_int4__sw_int4__VAL REG_VAL_ENUM
9105 #define R_IRQ_MASK1_SET__sw_int3__sw_int3__VAL REG_VAL_ENUM
9106 #define R_IRQ_MASK1_SET__sw_int2__sw_int2__VAL REG_VAL_ENUM
9107 #define R_IRQ_MASK1_SET__sw_int1__sw_int1__VAL REG_VAL_ENUM
9108 #define R_IRQ_MASK1_SET__sw_int0__sw_int0__VAL REG_VAL_ENUM
9109 #define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
9110 #define R_IRQ_MASK1_SET__par1_peri__par1_peri__VAL REG_VAL_ENUM
9111 #define R_IRQ_MASK1_SET__par1_data__par1_data__VAL REG_VAL_ENUM
9112 #define R_IRQ_MASK1_SET__par1_ready__par1_ready__VAL REG_VAL_ENUM
9113 #define R_IRQ_MASK1_SET__scsi1__scsi1__VAL REG_VAL_ENUM
9114 #define R_IRQ_MASK1_SET__par1_ready__scsi1__VAL REG_VAL_ENUM
9115 #define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
9116 #define R_IRQ_MASK1_SET__ser3_data__ser3_data__VAL REG_VAL_ENUM
9117 #define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
9118 #define R_IRQ_MASK1_SET__ser2_data__ser2_data__VAL REG_VAL_ENUM
9119 #define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
9120 #define R_IRQ_MASK1_SET__ser1_data__ser1_data__VAL REG_VAL_ENUM
9121 #define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
9122 #define R_IRQ_MASK1_SET__ser0_data__ser0_data__VAL REG_VAL_ENUM
9123 #define R_IRQ_MASK1_SET__pa7__pa7__VAL REG_VAL_ENUM
9124 #define R_IRQ_MASK1_SET__pa6__pa6__VAL REG_VAL_ENUM
9125 #define R_IRQ_MASK1_SET__pa5__pa5__VAL REG_VAL_ENUM
9126 #define R_IRQ_MASK1_SET__pa4__pa4__VAL REG_VAL_ENUM
9127 #define R_IRQ_MASK1_SET__pa3__pa3__VAL REG_VAL_ENUM
9128 #define R_IRQ_MASK1_SET__pa2__pa2__VAL REG_VAL_ENUM
9129 #define R_IRQ_MASK1_SET__pa1__pa1__VAL REG_VAL_ENUM
9130 #define R_IRQ_MASK1_SET__pa0__pa0__VAL REG_VAL_ENUM
9131
9132 #define R_IRQ_MASK1_SET__sw_int7__sw_int7__nop 0
9133 #define R_IRQ_MASK1_SET__sw_int7__sw_int7__set 1
9134 #define R_IRQ_MASK1_SET__sw_int6__sw_int6__nop 0
9135 #define R_IRQ_MASK1_SET__sw_int6__sw_int6__set 1
9136 #define R_IRQ_MASK1_SET__sw_int5__sw_int5__nop 0
9137 #define R_IRQ_MASK1_SET__sw_int5__sw_int5__set 1
9138 #define R_IRQ_MASK1_SET__sw_int4__sw_int4__nop 0
9139 #define R_IRQ_MASK1_SET__sw_int4__sw_int4__set 1
9140 #define R_IRQ_MASK1_SET__sw_int3__sw_int3__nop 0
9141 #define R_IRQ_MASK1_SET__sw_int3__sw_int3__set 1
9142 #define R_IRQ_MASK1_SET__sw_int2__sw_int2__nop 0
9143 #define R_IRQ_MASK1_SET__sw_int2__sw_int2__set 1
9144 #define R_IRQ_MASK1_SET__sw_int1__sw_int1__nop 0
9145 #define R_IRQ_MASK1_SET__sw_int1__sw_int1__set 1
9146 #define R_IRQ_MASK1_SET__sw_int0__sw_int0__nop 0
9147 #define R_IRQ_MASK1_SET__sw_int0__sw_int0__set 1
9148 #define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__nop 0
9149 #define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__set 1
9150 #define R_IRQ_MASK1_SET__par1_peri__par1_peri__nop 0
9151 #define R_IRQ_MASK1_SET__par1_peri__par1_peri__set 1
9152 #define R_IRQ_MASK1_SET__par1_data__par1_data__nop 0
9153 #define R_IRQ_MASK1_SET__par1_data__par1_data__set 1
9154 #define R_IRQ_MASK1_SET__par1_ready__par1_ready__nop 0
9155 #define R_IRQ_MASK1_SET__par1_ready__par1_ready__set 1
9156 #define R_IRQ_MASK1_SET__scsi1__scsi1__nop 0
9157 #define R_IRQ_MASK1_SET__scsi1__scsi1__set 1
9158 #define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__nop 0
9159 #define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__set 1
9160 #define R_IRQ_MASK1_SET__ser3_data__ser3_data__nop 0
9161 #define R_IRQ_MASK1_SET__ser3_data__ser3_data__set 1
9162 #define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__nop 0
9163 #define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__set 1
9164 #define R_IRQ_MASK1_SET__ser2_data__ser2_data__nop 0
9165 #define R_IRQ_MASK1_SET__ser2_data__ser2_data__set 1
9166 #define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__nop 0
9167 #define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__set 1
9168 #define R_IRQ_MASK1_SET__ser1_data__ser1_data__nop 0
9169 #define R_IRQ_MASK1_SET__ser1_data__ser1_data__set 1
9170 #define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__nop 0
9171 #define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__set 1
9172 #define R_IRQ_MASK1_SET__ser0_data__ser0_data__nop 0
9173 #define R_IRQ_MASK1_SET__ser0_data__ser0_data__set 1
9174 #define R_IRQ_MASK1_SET__pa7__pa7__nop 0
9175 #define R_IRQ_MASK1_SET__pa7__pa7__set 1
9176 #define R_IRQ_MASK1_SET__pa6__pa6__nop 0
9177 #define R_IRQ_MASK1_SET__pa6__pa6__set 1
9178 #define R_IRQ_MASK1_SET__pa5__pa5__nop 0
9179 #define R_IRQ_MASK1_SET__pa5__pa5__set 1
9180 #define R_IRQ_MASK1_SET__pa4__pa4__nop 0
9181 #define R_IRQ_MASK1_SET__pa4__pa4__set 1
9182 #define R_IRQ_MASK1_SET__pa3__pa3__nop 0
9183 #define R_IRQ_MASK1_SET__pa3__pa3__set 1
9184 #define R_IRQ_MASK1_SET__pa2__pa2__nop 0
9185 #define R_IRQ_MASK1_SET__pa2__pa2__set 1
9186 #define R_IRQ_MASK1_SET__pa1__pa1__nop 0
9187 #define R_IRQ_MASK1_SET__pa1__pa1__set 1
9188 #define R_IRQ_MASK1_SET__pa0__pa0__nop 0
9189 #define R_IRQ_MASK1_SET__pa0__pa0__set 1
9190
9191 #endif
9192
9193 /*
9194 * R_IRQ_MASK2_CLR
9195 * - type: WO
9196 * - addr: 0xb00000d0
9197 * - group: Interrupt mask and status registers
9198 */
9199
9200 #if USE_GROUP__Interrupt_mask_and_status_registers
9201
9202 #define R_IRQ_MASK2_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d0)
9203
9204 #ifndef REG_NO_SHADOW
9205 #define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_CLR + 0))
9206 #define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_CLR + 0))
9207 #else /* REG_NO_SHADOW */
9208 #define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
9209 #define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
9210 #endif /* REG_NO_SHADOW */
9211
9212 #define R_IRQ_MASK2_CLR__STYPECAST REG_STYPECAST_UDWORD
9213 #define R_IRQ_MASK2_CLR__SVAL REG_SVAL_ZERO
9214 #define R_IRQ_MASK2_CLR__SVAL_I REG_SVAL_I_ZERO
9215 #define R_IRQ_MASK2_CLR__TYPECAST REG_TYPECAST_UDWORD
9216 #define R_IRQ_MASK2_CLR__TYPE (REG_UDWORD)
9217 #define R_IRQ_MASK2_CLR__GET REG_GET_WO
9218 #define R_IRQ_MASK2_CLR__IGET REG_IGET_WO
9219 #define R_IRQ_MASK2_CLR__SET REG_SET_WO
9220 #define R_IRQ_MASK2_CLR__ISET REG_ISET_WO
9221 #define R_IRQ_MASK2_CLR__SET_VAL REG_SET_VAL_WO
9222 #define R_IRQ_MASK2_CLR__EQL REG_EQL_WO
9223 #define R_IRQ_MASK2_CLR__IEQL REG_IEQL_WO
9224 #define R_IRQ_MASK2_CLR__RD REG_RD_WO
9225 #define R_IRQ_MASK2_CLR__IRD REG_IRD_WO
9226 #define R_IRQ_MASK2_CLR__WR REG_WR_WO
9227 #define R_IRQ_MASK2_CLR__IWR REG_IWR_WO
9228
9229 #define R_IRQ_MASK2_CLR__WRITE(addr,value) \
9230 (*(addr) = (value))
9231
9232 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
9233 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
9234 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
9235 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
9236 #define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__MASK 0x00080000U
9237 #define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__MASK 0x00040000U
9238 #define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__MASK 0x00020000U
9239 #define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__MASK 0x00010000U
9240 #define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__MASK 0x00008000U
9241 #define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__MASK 0x00004000U
9242 #define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__MASK 0x00002000U
9243 #define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__MASK 0x00001000U
9244 #define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__MASK 0x00000800U
9245 #define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__MASK 0x00000400U
9246 #define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__MASK 0x00000200U
9247 #define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__MASK 0x00000100U
9248 #define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__MASK 0x00000080U
9249 #define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__MASK 0x00000040U
9250 #define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__MASK 0x00000020U
9251 #define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__MASK 0x00000010U
9252 #define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__MASK 0x00000008U
9253 #define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__MASK 0x00000004U
9254 #define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__MASK 0x00000002U
9255 #define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__MASK 0x00000001U
9256
9257 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__MAX 0x1
9258 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__MAX 0x1
9259 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__MAX 0x1
9260 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__MAX 0x1
9261 #define R_IRQ_MASK2_CLR__dma9_eop__MAX 0x1
9262 #define R_IRQ_MASK2_CLR__dma9_descr__MAX 0x1
9263 #define R_IRQ_MASK2_CLR__dma8_eop__MAX 0x1
9264 #define R_IRQ_MASK2_CLR__dma8_descr__MAX 0x1
9265 #define R_IRQ_MASK2_CLR__dma7_eop__MAX 0x1
9266 #define R_IRQ_MASK2_CLR__dma7_descr__MAX 0x1
9267 #define R_IRQ_MASK2_CLR__dma6_eop__MAX 0x1
9268 #define R_IRQ_MASK2_CLR__dma6_descr__MAX 0x1
9269 #define R_IRQ_MASK2_CLR__dma5_eop__MAX 0x1
9270 #define R_IRQ_MASK2_CLR__dma5_descr__MAX 0x1
9271 #define R_IRQ_MASK2_CLR__dma4_eop__MAX 0x1
9272 #define R_IRQ_MASK2_CLR__dma4_descr__MAX 0x1
9273 #define R_IRQ_MASK2_CLR__dma3_eop__MAX 0x1
9274 #define R_IRQ_MASK2_CLR__dma3_descr__MAX 0x1
9275 #define R_IRQ_MASK2_CLR__dma2_eop__MAX 0x1
9276 #define R_IRQ_MASK2_CLR__dma2_descr__MAX 0x1
9277 #define R_IRQ_MASK2_CLR__dma1_eop__MAX 0x1
9278 #define R_IRQ_MASK2_CLR__dma1_descr__MAX 0x1
9279 #define R_IRQ_MASK2_CLR__dma0_eop__MAX 0x1
9280 #define R_IRQ_MASK2_CLR__dma0_descr__MAX 0x1
9281
9282 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__MIN 0
9283 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__MIN 0
9284 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__MIN 0
9285 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__MIN 0
9286 #define R_IRQ_MASK2_CLR__dma9_eop__MIN 0
9287 #define R_IRQ_MASK2_CLR__dma9_descr__MIN 0
9288 #define R_IRQ_MASK2_CLR__dma8_eop__MIN 0
9289 #define R_IRQ_MASK2_CLR__dma8_descr__MIN 0
9290 #define R_IRQ_MASK2_CLR__dma7_eop__MIN 0
9291 #define R_IRQ_MASK2_CLR__dma7_descr__MIN 0
9292 #define R_IRQ_MASK2_CLR__dma6_eop__MIN 0
9293 #define R_IRQ_MASK2_CLR__dma6_descr__MIN 0
9294 #define R_IRQ_MASK2_CLR__dma5_eop__MIN 0
9295 #define R_IRQ_MASK2_CLR__dma5_descr__MIN 0
9296 #define R_IRQ_MASK2_CLR__dma4_eop__MIN 0
9297 #define R_IRQ_MASK2_CLR__dma4_descr__MIN 0
9298 #define R_IRQ_MASK2_CLR__dma3_eop__MIN 0
9299 #define R_IRQ_MASK2_CLR__dma3_descr__MIN 0
9300 #define R_IRQ_MASK2_CLR__dma2_eop__MIN 0
9301 #define R_IRQ_MASK2_CLR__dma2_descr__MIN 0
9302 #define R_IRQ_MASK2_CLR__dma1_eop__MIN 0
9303 #define R_IRQ_MASK2_CLR__dma1_descr__MIN 0
9304 #define R_IRQ_MASK2_CLR__dma0_eop__MIN 0
9305 #define R_IRQ_MASK2_CLR__dma0_descr__MIN 0
9306
9307 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
9308 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
9309 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
9310 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
9311 #define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
9312 #define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
9313 #define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
9314 #define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
9315 #define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
9316 #define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
9317 #define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
9318 #define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
9319 #define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
9320 #define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
9321 #define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
9322 #define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
9323 #define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
9324 #define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
9325 #define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
9326 #define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
9327 #define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
9328 #define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
9329 #define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
9330 #define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
9331
9332 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
9333 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
9334 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
9335 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
9336 #define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
9337 #define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
9338 #define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
9339 #define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
9340 #define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
9341 #define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
9342 #define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
9343 #define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
9344 #define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
9345 #define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
9346 #define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
9347 #define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
9348 #define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
9349 #define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
9350 #define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
9351 #define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
9352 #define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
9353 #define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
9354 #define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
9355 #define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
9356
9357 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__clr 1
9358 #define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__nop 0
9359 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__clr 1
9360 #define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__nop 0
9361 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__clr 1
9362 #define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__nop 0
9363 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__clr 1
9364 #define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__nop 0
9365 #define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__clr 1
9366 #define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__nop 0
9367 #define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__clr 1
9368 #define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__nop 0
9369 #define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__clr 1
9370 #define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__nop 0
9371 #define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__clr 1
9372 #define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__nop 0
9373 #define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__clr 1
9374 #define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__nop 0
9375 #define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__clr 1
9376 #define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__nop 0
9377 #define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__clr 1
9378 #define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__nop 0
9379 #define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__clr 1
9380 #define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__nop 0
9381 #define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__clr 1
9382 #define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__nop 0
9383 #define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__clr 1
9384 #define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__nop 0
9385 #define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__clr 1
9386 #define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__nop 0
9387 #define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__clr 1
9388 #define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__nop 0
9389 #define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__clr 1
9390 #define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__nop 0
9391 #define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__clr 1
9392 #define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__nop 0
9393 #define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__clr 1
9394 #define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__nop 0
9395 #define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__clr 1
9396 #define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__nop 0
9397 #define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__clr 1
9398 #define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__nop 0
9399 #define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__clr 1
9400 #define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__nop 0
9401 #define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__clr 1
9402 #define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__nop 0
9403 #define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__clr 1
9404 #define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__nop 0
9405
9406 #endif
9407
9408 /*
9409 * R_IRQ_MASK2_RD
9410 * - type: RO
9411 * - addr: 0xb00000d0
9412 * - group: Interrupt mask and status registers
9413 */
9414
9415 #if USE_GROUP__Interrupt_mask_and_status_registers
9416
9417 #define R_IRQ_MASK2_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d0)
9418 #define R_IRQ_MASK2_RD__SVAL REG_SVAL_SHADOW
9419 #define R_IRQ_MASK2_RD__SVAL_I REG_SVAL_I_SHADOW
9420 #define R_IRQ_MASK2_RD__TYPECAST REG_TYPECAST_UDWORD
9421 #define R_IRQ_MASK2_RD__TYPE (REG_UDWORD)
9422 #define R_IRQ_MASK2_RD__GET REG_GET_RO
9423 #define R_IRQ_MASK2_RD__IGET REG_IGET_RO
9424 #define R_IRQ_MASK2_RD__SET REG_SET_RO
9425 #define R_IRQ_MASK2_RD__ISET REG_ISET_RO
9426 #define R_IRQ_MASK2_RD__SET_VAL REG_SET_VAL_RO
9427 #define R_IRQ_MASK2_RD__EQL REG_EQL_RO
9428 #define R_IRQ_MASK2_RD__IEQL REG_IEQL_RO
9429 #define R_IRQ_MASK2_RD__RD REG_RD_RO
9430 #define R_IRQ_MASK2_RD__IRD REG_IRD_RO
9431 #define R_IRQ_MASK2_RD__WR REG_WR_RO
9432 #define R_IRQ_MASK2_RD__IWR REG_IWR_RO
9433
9434 #define R_IRQ_MASK2_RD__READ(addr) \
9435 (*(addr))
9436
9437 #define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
9438 #define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
9439 #define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
9440 #define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
9441 #define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__MASK 0x00080000U
9442 #define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__MASK 0x00040000U
9443 #define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__MASK 0x00020000U
9444 #define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__MASK 0x00010000U
9445 #define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__MASK 0x00008000U
9446 #define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__MASK 0x00004000U
9447 #define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__MASK 0x00002000U
9448 #define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__MASK 0x00001000U
9449 #define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__MASK 0x00000800U
9450 #define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__MASK 0x00000400U
9451 #define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__MASK 0x00000200U
9452 #define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__MASK 0x00000100U
9453 #define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__MASK 0x00000080U
9454 #define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__MASK 0x00000040U
9455 #define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__MASK 0x00000020U
9456 #define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__MASK 0x00000010U
9457 #define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__MASK 0x00000008U
9458 #define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__MASK 0x00000004U
9459 #define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__MASK 0x00000002U
9460 #define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__MASK 0x00000001U
9461
9462 #define R_IRQ_MASK2_RD__dma8_sub3_descr__MAX 0x1
9463 #define R_IRQ_MASK2_RD__dma8_sub2_descr__MAX 0x1
9464 #define R_IRQ_MASK2_RD__dma8_sub1_descr__MAX 0x1
9465 #define R_IRQ_MASK2_RD__dma8_sub0_descr__MAX 0x1
9466 #define R_IRQ_MASK2_RD__dma9_eop__MAX 0x1
9467 #define R_IRQ_MASK2_RD__dma9_descr__MAX 0x1
9468 #define R_IRQ_MASK2_RD__dma8_eop__MAX 0x1
9469 #define R_IRQ_MASK2_RD__dma8_descr__MAX 0x1
9470 #define R_IRQ_MASK2_RD__dma7_eop__MAX 0x1
9471 #define R_IRQ_MASK2_RD__dma7_descr__MAX 0x1
9472 #define R_IRQ_MASK2_RD__dma6_eop__MAX 0x1
9473 #define R_IRQ_MASK2_RD__dma6_descr__MAX 0x1
9474 #define R_IRQ_MASK2_RD__dma5_eop__MAX 0x1
9475 #define R_IRQ_MASK2_RD__dma5_descr__MAX 0x1
9476 #define R_IRQ_MASK2_RD__dma4_eop__MAX 0x1
9477 #define R_IRQ_MASK2_RD__dma4_descr__MAX 0x1
9478 #define R_IRQ_MASK2_RD__dma3_eop__MAX 0x1
9479 #define R_IRQ_MASK2_RD__dma3_descr__MAX 0x1
9480 #define R_IRQ_MASK2_RD__dma2_eop__MAX 0x1
9481 #define R_IRQ_MASK2_RD__dma2_descr__MAX 0x1
9482 #define R_IRQ_MASK2_RD__dma1_eop__MAX 0x1
9483 #define R_IRQ_MASK2_RD__dma1_descr__MAX 0x1
9484 #define R_IRQ_MASK2_RD__dma0_eop__MAX 0x1
9485 #define R_IRQ_MASK2_RD__dma0_descr__MAX 0x1
9486
9487 #define R_IRQ_MASK2_RD__dma8_sub3_descr__MIN 0
9488 #define R_IRQ_MASK2_RD__dma8_sub2_descr__MIN 0
9489 #define R_IRQ_MASK2_RD__dma8_sub1_descr__MIN 0
9490 #define R_IRQ_MASK2_RD__dma8_sub0_descr__MIN 0
9491 #define R_IRQ_MASK2_RD__dma9_eop__MIN 0
9492 #define R_IRQ_MASK2_RD__dma9_descr__MIN 0
9493 #define R_IRQ_MASK2_RD__dma8_eop__MIN 0
9494 #define R_IRQ_MASK2_RD__dma8_descr__MIN 0
9495 #define R_IRQ_MASK2_RD__dma7_eop__MIN 0
9496 #define R_IRQ_MASK2_RD__dma7_descr__MIN 0
9497 #define R_IRQ_MASK2_RD__dma6_eop__MIN 0
9498 #define R_IRQ_MASK2_RD__dma6_descr__MIN 0
9499 #define R_IRQ_MASK2_RD__dma5_eop__MIN 0
9500 #define R_IRQ_MASK2_RD__dma5_descr__MIN 0
9501 #define R_IRQ_MASK2_RD__dma4_eop__MIN 0
9502 #define R_IRQ_MASK2_RD__dma4_descr__MIN 0
9503 #define R_IRQ_MASK2_RD__dma3_eop__MIN 0
9504 #define R_IRQ_MASK2_RD__dma3_descr__MIN 0
9505 #define R_IRQ_MASK2_RD__dma2_eop__MIN 0
9506 #define R_IRQ_MASK2_RD__dma2_descr__MIN 0
9507 #define R_IRQ_MASK2_RD__dma1_eop__MIN 0
9508 #define R_IRQ_MASK2_RD__dma1_descr__MIN 0
9509 #define R_IRQ_MASK2_RD__dma0_eop__MIN 0
9510 #define R_IRQ_MASK2_RD__dma0_descr__MIN 0
9511
9512 #define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
9513 #define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
9514 #define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
9515 #define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
9516 #define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
9517 #define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
9518 #define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
9519 #define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
9520 #define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
9521 #define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
9522 #define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
9523 #define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
9524 #define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
9525 #define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
9526 #define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
9527 #define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
9528 #define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
9529 #define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
9530 #define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
9531 #define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
9532 #define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
9533 #define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
9534 #define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
9535 #define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
9536
9537 #define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
9538 #define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
9539 #define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
9540 #define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
9541 #define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
9542 #define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
9543 #define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
9544 #define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
9545 #define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
9546 #define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
9547 #define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
9548 #define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
9549 #define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
9550 #define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
9551 #define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
9552 #define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
9553 #define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
9554 #define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
9555 #define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
9556 #define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
9557 #define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
9558 #define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
9559 #define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
9560 #define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
9561
9562 #define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__active 1
9563 #define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__inactive 0
9564 #define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__active 1
9565 #define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__inactive 0
9566 #define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__active 1
9567 #define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__inactive 0
9568 #define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__active 1
9569 #define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__inactive 0
9570 #define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__active 1
9571 #define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__inactive 0
9572 #define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__active 1
9573 #define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__inactive 0
9574 #define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__active 1
9575 #define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__inactive 0
9576 #define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__active 1
9577 #define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__inactive 0
9578 #define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__active 1
9579 #define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__inactive 0
9580 #define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__active 1
9581 #define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__inactive 0
9582 #define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__active 1
9583 #define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__inactive 0
9584 #define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__active 1
9585 #define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__inactive 0
9586 #define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__active 1
9587 #define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__inactive 0
9588 #define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__active 1
9589 #define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__inactive 0
9590 #define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__active 1
9591 #define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__inactive 0
9592 #define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__active 1
9593 #define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__inactive 0
9594 #define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__active 1
9595 #define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__inactive 0
9596 #define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__active 1
9597 #define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__inactive 0
9598 #define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__active 1
9599 #define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__inactive 0
9600 #define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__active 1
9601 #define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__inactive 0
9602 #define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__active 1
9603 #define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__inactive 0
9604 #define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__active 1
9605 #define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__inactive 0
9606 #define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__active 1
9607 #define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__inactive 0
9608 #define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__active 1
9609 #define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__inactive 0
9610
9611 #endif
9612
9613 /*
9614 * R_IRQ_MASK2_SET
9615 * - type: WO
9616 * - addr: 0xb00000d4
9617 * - group: Interrupt mask and status registers
9618 */
9619
9620 #if USE_GROUP__Interrupt_mask_and_status_registers
9621
9622 #define R_IRQ_MASK2_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000d4)
9623
9624 #ifndef REG_NO_SHADOW
9625 #define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_SET + 0))
9626 #define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_SET + 0))
9627 #else /* REG_NO_SHADOW */
9628 #define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
9629 #define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
9630 #endif /* REG_NO_SHADOW */
9631
9632 #define R_IRQ_MASK2_SET__STYPECAST REG_STYPECAST_UDWORD
9633 #define R_IRQ_MASK2_SET__SVAL REG_SVAL_ZERO
9634 #define R_IRQ_MASK2_SET__SVAL_I REG_SVAL_I_ZERO
9635 #define R_IRQ_MASK2_SET__TYPECAST REG_TYPECAST_UDWORD
9636 #define R_IRQ_MASK2_SET__TYPE (REG_UDWORD)
9637 #define R_IRQ_MASK2_SET__GET REG_GET_WO
9638 #define R_IRQ_MASK2_SET__IGET REG_IGET_WO
9639 #define R_IRQ_MASK2_SET__SET REG_SET_WO
9640 #define R_IRQ_MASK2_SET__ISET REG_ISET_WO
9641 #define R_IRQ_MASK2_SET__SET_VAL REG_SET_VAL_WO
9642 #define R_IRQ_MASK2_SET__EQL REG_EQL_WO
9643 #define R_IRQ_MASK2_SET__IEQL REG_IEQL_WO
9644 #define R_IRQ_MASK2_SET__RD REG_RD_WO
9645 #define R_IRQ_MASK2_SET__IRD REG_IRD_WO
9646 #define R_IRQ_MASK2_SET__WR REG_WR_WO
9647 #define R_IRQ_MASK2_SET__IWR REG_IWR_WO
9648
9649 #define R_IRQ_MASK2_SET__WRITE(addr,value) \
9650 (*(addr) = (value))
9651
9652 #define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
9653 #define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
9654 #define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
9655 #define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
9656 #define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__MASK 0x00080000U
9657 #define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__MASK 0x00040000U
9658 #define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__MASK 0x00020000U
9659 #define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__MASK 0x00010000U
9660 #define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__MASK 0x00008000U
9661 #define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__MASK 0x00004000U
9662 #define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__MASK 0x00002000U
9663 #define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__MASK 0x00001000U
9664 #define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__MASK 0x00000800U
9665 #define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__MASK 0x00000400U
9666 #define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__MASK 0x00000200U
9667 #define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__MASK 0x00000100U
9668 #define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__MASK 0x00000080U
9669 #define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__MASK 0x00000040U
9670 #define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__MASK 0x00000020U
9671 #define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__MASK 0x00000010U
9672 #define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__MASK 0x00000008U
9673 #define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__MASK 0x00000004U
9674 #define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__MASK 0x00000002U
9675 #define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__MASK 0x00000001U
9676
9677 #define R_IRQ_MASK2_SET__dma8_sub3_descr__MAX 0x1
9678 #define R_IRQ_MASK2_SET__dma8_sub2_descr__MAX 0x1
9679 #define R_IRQ_MASK2_SET__dma8_sub1_descr__MAX 0x1
9680 #define R_IRQ_MASK2_SET__dma8_sub0_descr__MAX 0x1
9681 #define R_IRQ_MASK2_SET__dma9_eop__MAX 0x1
9682 #define R_IRQ_MASK2_SET__dma9_descr__MAX 0x1
9683 #define R_IRQ_MASK2_SET__dma8_eop__MAX 0x1
9684 #define R_IRQ_MASK2_SET__dma8_descr__MAX 0x1
9685 #define R_IRQ_MASK2_SET__dma7_eop__MAX 0x1
9686 #define R_IRQ_MASK2_SET__dma7_descr__MAX 0x1
9687 #define R_IRQ_MASK2_SET__dma6_eop__MAX 0x1
9688 #define R_IRQ_MASK2_SET__dma6_descr__MAX 0x1
9689 #define R_IRQ_MASK2_SET__dma5_eop__MAX 0x1
9690 #define R_IRQ_MASK2_SET__dma5_descr__MAX 0x1
9691 #define R_IRQ_MASK2_SET__dma4_eop__MAX 0x1
9692 #define R_IRQ_MASK2_SET__dma4_descr__MAX 0x1
9693 #define R_IRQ_MASK2_SET__dma3_eop__MAX 0x1
9694 #define R_IRQ_MASK2_SET__dma3_descr__MAX 0x1
9695 #define R_IRQ_MASK2_SET__dma2_eop__MAX 0x1
9696 #define R_IRQ_MASK2_SET__dma2_descr__MAX 0x1
9697 #define R_IRQ_MASK2_SET__dma1_eop__MAX 0x1
9698 #define R_IRQ_MASK2_SET__dma1_descr__MAX 0x1
9699 #define R_IRQ_MASK2_SET__dma0_eop__MAX 0x1
9700 #define R_IRQ_MASK2_SET__dma0_descr__MAX 0x1
9701
9702 #define R_IRQ_MASK2_SET__dma8_sub3_descr__MIN 0
9703 #define R_IRQ_MASK2_SET__dma8_sub2_descr__MIN 0
9704 #define R_IRQ_MASK2_SET__dma8_sub1_descr__MIN 0
9705 #define R_IRQ_MASK2_SET__dma8_sub0_descr__MIN 0
9706 #define R_IRQ_MASK2_SET__dma9_eop__MIN 0
9707 #define R_IRQ_MASK2_SET__dma9_descr__MIN 0
9708 #define R_IRQ_MASK2_SET__dma8_eop__MIN 0
9709 #define R_IRQ_MASK2_SET__dma8_descr__MIN 0
9710 #define R_IRQ_MASK2_SET__dma7_eop__MIN 0
9711 #define R_IRQ_MASK2_SET__dma7_descr__MIN 0
9712 #define R_IRQ_MASK2_SET__dma6_eop__MIN 0
9713 #define R_IRQ_MASK2_SET__dma6_descr__MIN 0
9714 #define R_IRQ_MASK2_SET__dma5_eop__MIN 0
9715 #define R_IRQ_MASK2_SET__dma5_descr__MIN 0
9716 #define R_IRQ_MASK2_SET__dma4_eop__MIN 0
9717 #define R_IRQ_MASK2_SET__dma4_descr__MIN 0
9718 #define R_IRQ_MASK2_SET__dma3_eop__MIN 0
9719 #define R_IRQ_MASK2_SET__dma3_descr__MIN 0
9720 #define R_IRQ_MASK2_SET__dma2_eop__MIN 0
9721 #define R_IRQ_MASK2_SET__dma2_descr__MIN 0
9722 #define R_IRQ_MASK2_SET__dma1_eop__MIN 0
9723 #define R_IRQ_MASK2_SET__dma1_descr__MIN 0
9724 #define R_IRQ_MASK2_SET__dma0_eop__MIN 0
9725 #define R_IRQ_MASK2_SET__dma0_descr__MIN 0
9726
9727 #define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
9728 #define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
9729 #define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
9730 #define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
9731 #define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
9732 #define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
9733 #define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
9734 #define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
9735 #define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
9736 #define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
9737 #define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
9738 #define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
9739 #define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
9740 #define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
9741 #define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
9742 #define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
9743 #define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
9744 #define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
9745 #define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
9746 #define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
9747 #define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
9748 #define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
9749 #define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
9750 #define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
9751
9752 #define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
9753 #define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
9754 #define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
9755 #define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
9756 #define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
9757 #define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
9758 #define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
9759 #define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
9760 #define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
9761 #define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
9762 #define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
9763 #define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
9764 #define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
9765 #define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
9766 #define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
9767 #define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
9768 #define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
9769 #define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
9770 #define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
9771 #define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
9772 #define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
9773 #define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
9774 #define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
9775 #define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
9776
9777 #define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__nop 0
9778 #define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__set 1
9779 #define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__nop 0
9780 #define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__set 1
9781 #define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__nop 0
9782 #define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__set 1
9783 #define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__nop 0
9784 #define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__set 1
9785 #define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__nop 0
9786 #define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__set 1
9787 #define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__nop 0
9788 #define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__set 1
9789 #define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__nop 0
9790 #define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__set 1
9791 #define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__nop 0
9792 #define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__set 1
9793 #define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__nop 0
9794 #define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__set 1
9795 #define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__nop 0
9796 #define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__set 1
9797 #define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__nop 0
9798 #define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__set 1
9799 #define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__nop 0
9800 #define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__set 1
9801 #define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__nop 0
9802 #define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__set 1
9803 #define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__nop 0
9804 #define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__set 1
9805 #define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__nop 0
9806 #define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__set 1
9807 #define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__nop 0
9808 #define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__set 1
9809 #define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__nop 0
9810 #define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__set 1
9811 #define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__nop 0
9812 #define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__set 1
9813 #define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__nop 0
9814 #define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__set 1
9815 #define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__nop 0
9816 #define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__set 1
9817 #define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__nop 0
9818 #define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__set 1
9819 #define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__nop 0
9820 #define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__set 1
9821 #define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__nop 0
9822 #define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__set 1
9823 #define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__nop 0
9824 #define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__set 1
9825
9826 #endif
9827
9828 /*
9829 * R_IRQ_READ0
9830 * - type: RO
9831 * - addr: 0xb00000c4
9832 * - group: Interrupt mask and status registers
9833 */
9834
9835 #if USE_GROUP__Interrupt_mask_and_status_registers
9836
9837 #define R_IRQ_READ0__ADDR (REG_TYPECAST_UDWORD 0xb00000c4)
9838 #define R_IRQ_READ0__SVAL REG_SVAL_SHADOW
9839 #define R_IRQ_READ0__SVAL_I REG_SVAL_I_SHADOW
9840 #define R_IRQ_READ0__TYPECAST REG_TYPECAST_UDWORD
9841 #define R_IRQ_READ0__TYPE (REG_UDWORD)
9842 #define R_IRQ_READ0__GET REG_GET_RO
9843 #define R_IRQ_READ0__IGET REG_IGET_RO
9844 #define R_IRQ_READ0__SET REG_SET_RO
9845 #define R_IRQ_READ0__ISET REG_ISET_RO
9846 #define R_IRQ_READ0__SET_VAL REG_SET_VAL_RO
9847 #define R_IRQ_READ0__EQL REG_EQL_RO
9848 #define R_IRQ_READ0__IEQL REG_IEQL_RO
9849 #define R_IRQ_READ0__RD REG_RD_RO
9850 #define R_IRQ_READ0__IRD REG_IRD_RO
9851 #define R_IRQ_READ0__WR REG_WR_RO
9852 #define R_IRQ_READ0__IWR REG_IWR_RO
9853
9854 #define R_IRQ_READ0__READ(addr) \
9855 (*(addr))
9856
9857 #define R_IRQ_READ0__nmi_pin__nmi_pin__MASK 0x80000000U
9858 #define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
9859 #define R_IRQ_READ0__sqe_test_error__sqe_test_error__MASK 0x20000000U
9860 #define R_IRQ_READ0__carrier_loss__carrier_loss__MASK 0x10000000U
9861 #define R_IRQ_READ0__deferred__deferred__MASK 0x08000000U
9862 #define R_IRQ_READ0__late_col__late_col__MASK 0x04000000U
9863 #define R_IRQ_READ0__multiple_col__multiple_col__MASK 0x02000000U
9864 #define R_IRQ_READ0__single_col__single_col__MASK 0x01000000U
9865 #define R_IRQ_READ0__congestion__congestion__MASK 0x00800000U
9866 #define R_IRQ_READ0__oversize__oversize__MASK 0x00400000U
9867 #define R_IRQ_READ0__alignment_error__alignment_error__MASK 0x00200000U
9868 #define R_IRQ_READ0__crc_error__crc_error__MASK 0x00100000U
9869 #define R_IRQ_READ0__overrun__overrun__MASK 0x00080000U
9870 #define R_IRQ_READ0__underrun__underrun__MASK 0x00040000U
9871 #define R_IRQ_READ0__excessive_col__excessive_col__MASK 0x00020000U
9872 #define R_IRQ_READ0__mdio__mdio__MASK 0x00010000U
9873 #define R_IRQ_READ0__ata_drq3__ata_drq3__MASK 0x00008000U
9874 #define R_IRQ_READ0__ata_drq2__ata_drq2__MASK 0x00004000U
9875 #define R_IRQ_READ0__ata_drq1__ata_drq1__MASK 0x00002000U
9876 #define R_IRQ_READ0__ata_drq0__ata_drq0__MASK 0x00001000U
9877 #define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
9878 #define R_IRQ_READ0__ata_irq3__ata_irq3__MASK 0x00000800U
9879 #define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
9880 #define R_IRQ_READ0__par0_peri__par0_peri__MASK 0x00000400U
9881 #define R_IRQ_READ0__ata_irq2__ata_irq2__MASK 0x00000400U
9882 #define R_IRQ_READ0__par0_peri__ata_irq2__MASK 0x00000400U
9883 #define R_IRQ_READ0__par0_data__par0_data__MASK 0x00000200U
9884 #define R_IRQ_READ0__ata_irq1__ata_irq1__MASK 0x00000200U
9885 #define R_IRQ_READ0__par0_data__ata_irq1__MASK 0x00000200U
9886 #define R_IRQ_READ0__par0_ready__par0_ready__MASK 0x00000100U
9887 #define R_IRQ_READ0__ata_irq0__ata_irq0__MASK 0x00000100U
9888 #define R_IRQ_READ0__par0_ready__ata_irq0__MASK 0x00000100U
9889 #define R_IRQ_READ0__mio__mio__MASK 0x00000100U
9890 #define R_IRQ_READ0__par0_ready__mio__MASK 0x00000100U
9891 #define R_IRQ_READ0__scsi0__scsi0__MASK 0x00000100U
9892 #define R_IRQ_READ0__par0_ready__scsi0__MASK 0x00000100U
9893 #define R_IRQ_READ0__ata_dmaend__ata_dmaend__MASK 0x00000080U
9894 #define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
9895 #define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
9896 #define R_IRQ_READ0__ext_dma1__ext_dma1__MASK 0x00000008U
9897 #define R_IRQ_READ0__ext_dma0__ext_dma0__MASK 0x00000004U
9898 #define R_IRQ_READ0__timer1__timer1__MASK 0x00000002U
9899 #define R_IRQ_READ0__timer0__timer0__MASK 0x00000001U
9900
9901 #define R_IRQ_READ0__nmi_pin__MAX 0x1
9902 #define R_IRQ_READ0__watchdog_nmi__MAX 0x1
9903 #define R_IRQ_READ0__sqe_test_error__MAX 0x1
9904 #define R_IRQ_READ0__carrier_loss__MAX 0x1
9905 #define R_IRQ_READ0__deferred__MAX 0x1
9906 #define R_IRQ_READ0__late_col__MAX 0x1
9907 #define R_IRQ_READ0__multiple_col__MAX 0x1
9908 #define R_IRQ_READ0__single_col__MAX 0x1
9909 #define R_IRQ_READ0__congestion__MAX 0x1
9910 #define R_IRQ_READ0__oversize__MAX 0x1
9911 #define R_IRQ_READ0__alignment_error__MAX 0x1
9912 #define R_IRQ_READ0__crc_error__MAX 0x1
9913 #define R_IRQ_READ0__overrun__MAX 0x1
9914 #define R_IRQ_READ0__underrun__MAX 0x1
9915 #define R_IRQ_READ0__excessive_col__MAX 0x1
9916 #define R_IRQ_READ0__mdio__MAX 0x1
9917 #define R_IRQ_READ0__ata_drq3__MAX 0x1
9918 #define R_IRQ_READ0__ata_drq2__MAX 0x1
9919 #define R_IRQ_READ0__ata_drq1__MAX 0x1
9920 #define R_IRQ_READ0__ata_drq0__MAX 0x1
9921 #define R_IRQ_READ0__par0_ecp_cmd__MAX 0x1
9922 #define R_IRQ_READ0__ata_irq3__MAX 0x1
9923 #define R_IRQ_READ0__par0_peri__MAX 0x1
9924 #define R_IRQ_READ0__ata_irq2__MAX 0x1
9925 #define R_IRQ_READ0__par0_data__MAX 0x1
9926 #define R_IRQ_READ0__ata_irq1__MAX 0x1
9927 #define R_IRQ_READ0__par0_ready__MAX 0x1
9928 #define R_IRQ_READ0__ata_irq0__MAX 0x1
9929 #define R_IRQ_READ0__mio__MAX 0x1
9930 #define R_IRQ_READ0__scsi0__MAX 0x1
9931 #define R_IRQ_READ0__ata_dmaend__MAX 0x1
9932 #define R_IRQ_READ0__irq_ext_vector_nr__MAX 0x1
9933 #define R_IRQ_READ0__irq_int_vector_nr__MAX 0x1
9934 #define R_IRQ_READ0__ext_dma1__MAX 0x1
9935 #define R_IRQ_READ0__ext_dma0__MAX 0x1
9936 #define R_IRQ_READ0__timer1__MAX 0x1
9937 #define R_IRQ_READ0__timer0__MAX 0x1
9938
9939 #define R_IRQ_READ0__nmi_pin__MIN 0
9940 #define R_IRQ_READ0__watchdog_nmi__MIN 0
9941 #define R_IRQ_READ0__sqe_test_error__MIN 0
9942 #define R_IRQ_READ0__carrier_loss__MIN 0
9943 #define R_IRQ_READ0__deferred__MIN 0
9944 #define R_IRQ_READ0__late_col__MIN 0
9945 #define R_IRQ_READ0__multiple_col__MIN 0
9946 #define R_IRQ_READ0__single_col__MIN 0
9947 #define R_IRQ_READ0__congestion__MIN 0
9948 #define R_IRQ_READ0__oversize__MIN 0
9949 #define R_IRQ_READ0__alignment_error__MIN 0
9950 #define R_IRQ_READ0__crc_error__MIN 0
9951 #define R_IRQ_READ0__overrun__MIN 0
9952 #define R_IRQ_READ0__underrun__MIN 0
9953 #define R_IRQ_READ0__excessive_col__MIN 0
9954 #define R_IRQ_READ0__mdio__MIN 0
9955 #define R_IRQ_READ0__ata_drq3__MIN 0
9956 #define R_IRQ_READ0__ata_drq2__MIN 0
9957 #define R_IRQ_READ0__ata_drq1__MIN 0
9958 #define R_IRQ_READ0__ata_drq0__MIN 0
9959 #define R_IRQ_READ0__par0_ecp_cmd__MIN 0
9960 #define R_IRQ_READ0__ata_irq3__MIN 0
9961 #define R_IRQ_READ0__par0_peri__MIN 0
9962 #define R_IRQ_READ0__ata_irq2__MIN 0
9963 #define R_IRQ_READ0__par0_data__MIN 0
9964 #define R_IRQ_READ0__ata_irq1__MIN 0
9965 #define R_IRQ_READ0__par0_ready__MIN 0
9966 #define R_IRQ_READ0__ata_irq0__MIN 0
9967 #define R_IRQ_READ0__mio__MIN 0
9968 #define R_IRQ_READ0__scsi0__MIN 0
9969 #define R_IRQ_READ0__ata_dmaend__MIN 0
9970 #define R_IRQ_READ0__irq_ext_vector_nr__MIN 0
9971 #define R_IRQ_READ0__irq_int_vector_nr__MIN 0
9972 #define R_IRQ_READ0__ext_dma1__MIN 0
9973 #define R_IRQ_READ0__ext_dma0__MIN 0
9974 #define R_IRQ_READ0__timer1__MIN 0
9975 #define R_IRQ_READ0__timer0__MIN 0
9976
9977 #define R_IRQ_READ0__nmi_pin__BITNR 31
9978 #define R_IRQ_READ0__watchdog_nmi__BITNR 30
9979 #define R_IRQ_READ0__sqe_test_error__BITNR 29
9980 #define R_IRQ_READ0__carrier_loss__BITNR 28
9981 #define R_IRQ_READ0__deferred__BITNR 27
9982 #define R_IRQ_READ0__late_col__BITNR 26
9983 #define R_IRQ_READ0__multiple_col__BITNR 25
9984 #define R_IRQ_READ0__single_col__BITNR 24
9985 #define R_IRQ_READ0__congestion__BITNR 23
9986 #define R_IRQ_READ0__oversize__BITNR 22
9987 #define R_IRQ_READ0__alignment_error__BITNR 21
9988 #define R_IRQ_READ0__crc_error__BITNR 20
9989 #define R_IRQ_READ0__overrun__BITNR 19
9990 #define R_IRQ_READ0__underrun__BITNR 18
9991 #define R_IRQ_READ0__excessive_col__BITNR 17
9992 #define R_IRQ_READ0__mdio__BITNR 16
9993 #define R_IRQ_READ0__ata_drq3__BITNR 15
9994 #define R_IRQ_READ0__ata_drq2__BITNR 14
9995 #define R_IRQ_READ0__ata_drq1__BITNR 13
9996 #define R_IRQ_READ0__ata_drq0__BITNR 12
9997 #define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
9998 #define R_IRQ_READ0__ata_irq3__BITNR 11
9999 #define R_IRQ_READ0__par0_peri__BITNR 10
10000 #define R_IRQ_READ0__ata_irq2__BITNR 10
10001 #define R_IRQ_READ0__par0_data__BITNR 9
10002 #define R_IRQ_READ0__ata_irq1__BITNR 9
10003 #define R_IRQ_READ0__par0_ready__BITNR 8
10004 #define R_IRQ_READ0__ata_irq0__BITNR 8
10005 #define R_IRQ_READ0__mio__BITNR 8
10006 #define R_IRQ_READ0__scsi0__BITNR 8
10007 #define R_IRQ_READ0__ata_dmaend__BITNR 7
10008 #define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
10009 #define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
10010 #define R_IRQ_READ0__ext_dma1__BITNR 3
10011 #define R_IRQ_READ0__ext_dma0__BITNR 2
10012 #define R_IRQ_READ0__timer1__BITNR 1
10013 #define R_IRQ_READ0__timer0__BITNR 0
10014
10015 #define R_IRQ_READ0__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
10016 #define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
10017 #define R_IRQ_READ0__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
10018 #define R_IRQ_READ0__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
10019 #define R_IRQ_READ0__deferred__deferred__VAL REG_VAL_ENUM
10020 #define R_IRQ_READ0__late_col__late_col__VAL REG_VAL_ENUM
10021 #define R_IRQ_READ0__multiple_col__multiple_col__VAL REG_VAL_ENUM
10022 #define R_IRQ_READ0__single_col__single_col__VAL REG_VAL_ENUM
10023 #define R_IRQ_READ0__congestion__congestion__VAL REG_VAL_ENUM
10024 #define R_IRQ_READ0__oversize__oversize__VAL REG_VAL_ENUM
10025 #define R_IRQ_READ0__alignment_error__alignment_error__VAL REG_VAL_ENUM
10026 #define R_IRQ_READ0__crc_error__crc_error__VAL REG_VAL_ENUM
10027 #define R_IRQ_READ0__overrun__overrun__VAL REG_VAL_ENUM
10028 #define R_IRQ_READ0__underrun__underrun__VAL REG_VAL_ENUM
10029 #define R_IRQ_READ0__excessive_col__excessive_col__VAL REG_VAL_ENUM
10030 #define R_IRQ_READ0__mdio__mdio__VAL REG_VAL_ENUM
10031 #define R_IRQ_READ0__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
10032 #define R_IRQ_READ0__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
10033 #define R_IRQ_READ0__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
10034 #define R_IRQ_READ0__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
10035 #define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
10036 #define R_IRQ_READ0__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
10037 #define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
10038 #define R_IRQ_READ0__par0_peri__par0_peri__VAL REG_VAL_ENUM
10039 #define R_IRQ_READ0__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
10040 #define R_IRQ_READ0__par0_peri__ata_irq2__VAL REG_VAL_ENUM
10041 #define R_IRQ_READ0__par0_data__par0_data__VAL REG_VAL_ENUM
10042 #define R_IRQ_READ0__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
10043 #define R_IRQ_READ0__par0_data__ata_irq1__VAL REG_VAL_ENUM
10044 #define R_IRQ_READ0__par0_ready__par0_ready__VAL REG_VAL_ENUM
10045 #define R_IRQ_READ0__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
10046 #define R_IRQ_READ0__par0_ready__ata_irq0__VAL REG_VAL_ENUM
10047 #define R_IRQ_READ0__mio__mio__VAL REG_VAL_ENUM
10048 #define R_IRQ_READ0__par0_ready__mio__VAL REG_VAL_ENUM
10049 #define R_IRQ_READ0__scsi0__scsi0__VAL REG_VAL_ENUM
10050 #define R_IRQ_READ0__par0_ready__scsi0__VAL REG_VAL_ENUM
10051 #define R_IRQ_READ0__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
10052 #define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
10053 #define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
10054 #define R_IRQ_READ0__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
10055 #define R_IRQ_READ0__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
10056 #define R_IRQ_READ0__timer1__timer1__VAL REG_VAL_ENUM
10057 #define R_IRQ_READ0__timer0__timer0__VAL REG_VAL_ENUM
10058
10059 #define R_IRQ_READ0__nmi_pin__nmi_pin__active 1
10060 #define R_IRQ_READ0__nmi_pin__nmi_pin__inactive 0
10061 #define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__active 1
10062 #define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__inactive 0
10063 #define R_IRQ_READ0__sqe_test_error__sqe_test_error__active 1
10064 #define R_IRQ_READ0__sqe_test_error__sqe_test_error__inactive 0
10065 #define R_IRQ_READ0__carrier_loss__carrier_loss__active 1
10066 #define R_IRQ_READ0__carrier_loss__carrier_loss__inactive 0
10067 #define R_IRQ_READ0__deferred__deferred__active 1
10068 #define R_IRQ_READ0__deferred__deferred__inactive 0
10069 #define R_IRQ_READ0__late_col__late_col__active 1
10070 #define R_IRQ_READ0__late_col__late_col__inactive 0
10071 #define R_IRQ_READ0__multiple_col__multiple_col__active 1
10072 #define R_IRQ_READ0__multiple_col__multiple_col__inactive 0
10073 #define R_IRQ_READ0__single_col__single_col__active 1
10074 #define R_IRQ_READ0__single_col__single_col__inactive 0
10075 #define R_IRQ_READ0__congestion__congestion__active 1
10076 #define R_IRQ_READ0__congestion__congestion__inactive 0
10077 #define R_IRQ_READ0__oversize__oversize__active 1
10078 #define R_IRQ_READ0__oversize__oversize__inactive 0
10079 #define R_IRQ_READ0__alignment_error__alignment_error__active 1
10080 #define R_IRQ_READ0__alignment_error__alignment_error__inactive 0
10081 #define R_IRQ_READ0__crc_error__crc_error__active 1
10082 #define R_IRQ_READ0__crc_error__crc_error__inactive 0
10083 #define R_IRQ_READ0__overrun__overrun__active 1
10084 #define R_IRQ_READ0__overrun__overrun__inactive 0
10085 #define R_IRQ_READ0__underrun__underrun__active 1
10086 #define R_IRQ_READ0__underrun__underrun__inactive 0
10087 #define R_IRQ_READ0__excessive_col__excessive_col__active 1
10088 #define R_IRQ_READ0__excessive_col__excessive_col__inactive 0
10089 #define R_IRQ_READ0__mdio__mdio__active 1
10090 #define R_IRQ_READ0__mdio__mdio__inactive 0
10091 #define R_IRQ_READ0__ata_drq3__ata_drq3__active 1
10092 #define R_IRQ_READ0__ata_drq3__ata_drq3__inactive 0
10093 #define R_IRQ_READ0__ata_drq2__ata_drq2__active 1
10094 #define R_IRQ_READ0__ata_drq2__ata_drq2__inactive 0
10095 #define R_IRQ_READ0__ata_drq1__ata_drq1__active 1
10096 #define R_IRQ_READ0__ata_drq1__ata_drq1__inactive 0
10097 #define R_IRQ_READ0__ata_drq0__ata_drq0__active 1
10098 #define R_IRQ_READ0__ata_drq0__ata_drq0__inactive 0
10099 #define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__active 1
10100 #define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__inactive 0
10101 #define R_IRQ_READ0__ata_irq3__ata_irq3__active 1
10102 #define R_IRQ_READ0__ata_irq3__ata_irq3__inactive 0
10103 #define R_IRQ_READ0__par0_peri__par0_peri__active 1
10104 #define R_IRQ_READ0__par0_peri__par0_peri__inactive 0
10105 #define R_IRQ_READ0__ata_irq2__ata_irq2__active 1
10106 #define R_IRQ_READ0__ata_irq2__ata_irq2__inactive 0
10107 #define R_IRQ_READ0__par0_data__par0_data__active 1
10108 #define R_IRQ_READ0__par0_data__par0_data__inactive 0
10109 #define R_IRQ_READ0__ata_irq1__ata_irq1__active 1
10110 #define R_IRQ_READ0__ata_irq1__ata_irq1__inactive 0
10111 #define R_IRQ_READ0__par0_ready__par0_ready__active 1
10112 #define R_IRQ_READ0__par0_ready__par0_ready__inactive 0
10113 #define R_IRQ_READ0__ata_irq0__ata_irq0__active 1
10114 #define R_IRQ_READ0__ata_irq0__ata_irq0__inactive 0
10115 #define R_IRQ_READ0__mio__mio__active 1
10116 #define R_IRQ_READ0__mio__mio__inactive 0
10117 #define R_IRQ_READ0__scsi0__scsi0__active 1
10118 #define R_IRQ_READ0__scsi0__scsi0__inactive 0
10119 #define R_IRQ_READ0__ata_dmaend__ata_dmaend__active 1
10120 #define R_IRQ_READ0__ata_dmaend__ata_dmaend__inactive 0
10121 #define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__active 1
10122 #define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0
10123 #define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__active 1
10124 #define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__inactive 0
10125 #define R_IRQ_READ0__ext_dma1__ext_dma1__active 1
10126 #define R_IRQ_READ0__ext_dma1__ext_dma1__inactive 0
10127 #define R_IRQ_READ0__ext_dma0__ext_dma0__active 1
10128 #define R_IRQ_READ0__ext_dma0__ext_dma0__inactive 0
10129 #define R_IRQ_READ0__timer1__timer1__active 1
10130 #define R_IRQ_READ0__timer1__timer1__inactive 0
10131 #define R_IRQ_READ0__timer0__timer0__active 1
10132 #define R_IRQ_READ0__timer0__timer0__inactive 0
10133
10134 #endif
10135
10136 /*
10137 * R_IRQ_READ1
10138 * - type: RO
10139 * - addr: 0xb00000cc
10140 * - group: Interrupt mask and status registers
10141 */
10142
10143 #if USE_GROUP__Interrupt_mask_and_status_registers
10144
10145 #define R_IRQ_READ1__ADDR (REG_TYPECAST_UDWORD 0xb00000cc)
10146 #define R_IRQ_READ1__SVAL REG_SVAL_SHADOW
10147 #define R_IRQ_READ1__SVAL_I REG_SVAL_I_SHADOW
10148 #define R_IRQ_READ1__TYPECAST REG_TYPECAST_UDWORD
10149 #define R_IRQ_READ1__TYPE (REG_UDWORD)
10150 #define R_IRQ_READ1__GET REG_GET_RO
10151 #define R_IRQ_READ1__IGET REG_IGET_RO
10152 #define R_IRQ_READ1__SET REG_SET_RO
10153 #define R_IRQ_READ1__ISET REG_ISET_RO
10154 #define R_IRQ_READ1__SET_VAL REG_SET_VAL_RO
10155 #define R_IRQ_READ1__EQL REG_EQL_RO
10156 #define R_IRQ_READ1__IEQL REG_IEQL_RO
10157 #define R_IRQ_READ1__RD REG_RD_RO
10158 #define R_IRQ_READ1__IRD REG_IRD_RO
10159 #define R_IRQ_READ1__WR REG_WR_RO
10160 #define R_IRQ_READ1__IWR REG_IWR_RO
10161
10162 #define R_IRQ_READ1__READ(addr) \
10163 (*(addr))
10164
10165 #define R_IRQ_READ1__sw_int7__sw_int7__MASK 0x80000000U
10166 #define R_IRQ_READ1__sw_int6__sw_int6__MASK 0x40000000U
10167 #define R_IRQ_READ1__sw_int5__sw_int5__MASK 0x20000000U
10168 #define R_IRQ_READ1__sw_int4__sw_int4__MASK 0x10000000U
10169 #define R_IRQ_READ1__sw_int3__sw_int3__MASK 0x08000000U
10170 #define R_IRQ_READ1__sw_int2__sw_int2__MASK 0x04000000U
10171 #define R_IRQ_READ1__sw_int1__sw_int1__MASK 0x02000000U
10172 #define R_IRQ_READ1__sw_int0__sw_int0__MASK 0x01000000U
10173 #define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
10174 #define R_IRQ_READ1__par1_peri__par1_peri__MASK 0x00040000U
10175 #define R_IRQ_READ1__par1_data__par1_data__MASK 0x00020000U
10176 #define R_IRQ_READ1__par1_ready__par1_ready__MASK 0x00010000U
10177 #define R_IRQ_READ1__scsi1__scsi1__MASK 0x00010000U
10178 #define R_IRQ_READ1__par1_ready__scsi1__MASK 0x00010000U
10179 #define R_IRQ_READ1__ser3_ready__ser3_ready__MASK 0x00008000U
10180 #define R_IRQ_READ1__ser3_data__ser3_data__MASK 0x00004000U
10181 #define R_IRQ_READ1__ser2_ready__ser2_ready__MASK 0x00002000U
10182 #define R_IRQ_READ1__ser2_data__ser2_data__MASK 0x00001000U
10183 #define R_IRQ_READ1__ser1_ready__ser1_ready__MASK 0x00000800U
10184 #define R_IRQ_READ1__ser1_data__ser1_data__MASK 0x00000400U
10185 #define R_IRQ_READ1__ser0_ready__ser0_ready__MASK 0x00000200U
10186 #define R_IRQ_READ1__ser0_data__ser0_data__MASK 0x00000100U
10187 #define R_IRQ_READ1__pa7__pa7__MASK 0x00000080U
10188 #define R_IRQ_READ1__pa6__pa6__MASK 0x00000040U
10189 #define R_IRQ_READ1__pa5__pa5__MASK 0x00000020U
10190 #define R_IRQ_READ1__pa4__pa4__MASK 0x00000010U
10191 #define R_IRQ_READ1__pa3__pa3__MASK 0x00000008U
10192 #define R_IRQ_READ1__pa2__pa2__MASK 0x00000004U
10193 #define R_IRQ_READ1__pa1__pa1__MASK 0x00000002U
10194 #define R_IRQ_READ1__pa0__pa0__MASK 0x00000001U
10195
10196 #define R_IRQ_READ1__sw_int7__MAX 0x1
10197 #define R_IRQ_READ1__sw_int6__MAX 0x1
10198 #define R_IRQ_READ1__sw_int5__MAX 0x1
10199 #define R_IRQ_READ1__sw_int4__MAX 0x1
10200 #define R_IRQ_READ1__sw_int3__MAX 0x1
10201 #define R_IRQ_READ1__sw_int2__MAX 0x1
10202 #define R_IRQ_READ1__sw_int1__MAX 0x1
10203 #define R_IRQ_READ1__sw_int0__MAX 0x1
10204 #define R_IRQ_READ1__par1_ecp_cmd__MAX 0x1
10205 #define R_IRQ_READ1__par1_peri__MAX 0x1
10206 #define R_IRQ_READ1__par1_data__MAX 0x1
10207 #define R_IRQ_READ1__par1_ready__MAX 0x1
10208 #define R_IRQ_READ1__scsi1__MAX 0x1
10209 #define R_IRQ_READ1__ser3_ready__MAX 0x1
10210 #define R_IRQ_READ1__ser3_data__MAX 0x1
10211 #define R_IRQ_READ1__ser2_ready__MAX 0x1
10212 #define R_IRQ_READ1__ser2_data__MAX 0x1
10213 #define R_IRQ_READ1__ser1_ready__MAX 0x1
10214 #define R_IRQ_READ1__ser1_data__MAX 0x1
10215 #define R_IRQ_READ1__ser0_ready__MAX 0x1
10216 #define R_IRQ_READ1__ser0_data__MAX 0x1
10217 #define R_IRQ_READ1__pa7__MAX 0x1
10218 #define R_IRQ_READ1__pa6__MAX 0x1
10219 #define R_IRQ_READ1__pa5__MAX 0x1
10220 #define R_IRQ_READ1__pa4__MAX 0x1
10221 #define R_IRQ_READ1__pa3__MAX 0x1
10222 #define R_IRQ_READ1__pa2__MAX 0x1
10223 #define R_IRQ_READ1__pa1__MAX 0x1
10224 #define R_IRQ_READ1__pa0__MAX 0x1
10225
10226 #define R_IRQ_READ1__sw_int7__MIN 0
10227 #define R_IRQ_READ1__sw_int6__MIN 0
10228 #define R_IRQ_READ1__sw_int5__MIN 0
10229 #define R_IRQ_READ1__sw_int4__MIN 0
10230 #define R_IRQ_READ1__sw_int3__MIN 0
10231 #define R_IRQ_READ1__sw_int2__MIN 0
10232 #define R_IRQ_READ1__sw_int1__MIN 0
10233 #define R_IRQ_READ1__sw_int0__MIN 0
10234 #define R_IRQ_READ1__par1_ecp_cmd__MIN 0
10235 #define R_IRQ_READ1__par1_peri__MIN 0
10236 #define R_IRQ_READ1__par1_data__MIN 0
10237 #define R_IRQ_READ1__par1_ready__MIN 0
10238 #define R_IRQ_READ1__scsi1__MIN 0
10239 #define R_IRQ_READ1__ser3_ready__MIN 0
10240 #define R_IRQ_READ1__ser3_data__MIN 0
10241 #define R_IRQ_READ1__ser2_ready__MIN 0
10242 #define R_IRQ_READ1__ser2_data__MIN 0
10243 #define R_IRQ_READ1__ser1_ready__MIN 0
10244 #define R_IRQ_READ1__ser1_data__MIN 0
10245 #define R_IRQ_READ1__ser0_ready__MIN 0
10246 #define R_IRQ_READ1__ser0_data__MIN 0
10247 #define R_IRQ_READ1__pa7__MIN 0
10248 #define R_IRQ_READ1__pa6__MIN 0
10249 #define R_IRQ_READ1__pa5__MIN 0
10250 #define R_IRQ_READ1__pa4__MIN 0
10251 #define R_IRQ_READ1__pa3__MIN 0
10252 #define R_IRQ_READ1__pa2__MIN 0
10253 #define R_IRQ_READ1__pa1__MIN 0
10254 #define R_IRQ_READ1__pa0__MIN 0
10255
10256 #define R_IRQ_READ1__sw_int7__BITNR 31
10257 #define R_IRQ_READ1__sw_int6__BITNR 30
10258 #define R_IRQ_READ1__sw_int5__BITNR 29
10259 #define R_IRQ_READ1__sw_int4__BITNR 28
10260 #define R_IRQ_READ1__sw_int3__BITNR 27
10261 #define R_IRQ_READ1__sw_int2__BITNR 26
10262 #define R_IRQ_READ1__sw_int1__BITNR 25
10263 #define R_IRQ_READ1__sw_int0__BITNR 24
10264 #define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
10265 #define R_IRQ_READ1__par1_peri__BITNR 18
10266 #define R_IRQ_READ1__par1_data__BITNR 17
10267 #define R_IRQ_READ1__par1_ready__BITNR 16
10268 #define R_IRQ_READ1__scsi1__BITNR 16
10269 #define R_IRQ_READ1__ser3_ready__BITNR 15
10270 #define R_IRQ_READ1__ser3_data__BITNR 14
10271 #define R_IRQ_READ1__ser2_ready__BITNR 13
10272 #define R_IRQ_READ1__ser2_data__BITNR 12
10273 #define R_IRQ_READ1__ser1_ready__BITNR 11
10274 #define R_IRQ_READ1__ser1_data__BITNR 10
10275 #define R_IRQ_READ1__ser0_ready__BITNR 9
10276 #define R_IRQ_READ1__ser0_data__BITNR 8
10277 #define R_IRQ_READ1__pa7__BITNR 7
10278 #define R_IRQ_READ1__pa6__BITNR 6
10279 #define R_IRQ_READ1__pa5__BITNR 5
10280 #define R_IRQ_READ1__pa4__BITNR 4
10281 #define R_IRQ_READ1__pa3__BITNR 3
10282 #define R_IRQ_READ1__pa2__BITNR 2
10283 #define R_IRQ_READ1__pa1__BITNR 1
10284 #define R_IRQ_READ1__pa0__BITNR 0
10285
10286 #define R_IRQ_READ1__sw_int7__sw_int7__VAL REG_VAL_ENUM
10287 #define R_IRQ_READ1__sw_int6__sw_int6__VAL REG_VAL_ENUM
10288 #define R_IRQ_READ1__sw_int5__sw_int5__VAL REG_VAL_ENUM
10289 #define R_IRQ_READ1__sw_int4__sw_int4__VAL REG_VAL_ENUM
10290 #define R_IRQ_READ1__sw_int3__sw_int3__VAL REG_VAL_ENUM
10291 #define R_IRQ_READ1__sw_int2__sw_int2__VAL REG_VAL_ENUM
10292 #define R_IRQ_READ1__sw_int1__sw_int1__VAL REG_VAL_ENUM
10293 #define R_IRQ_READ1__sw_int0__sw_int0__VAL REG_VAL_ENUM
10294 #define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
10295 #define R_IRQ_READ1__par1_peri__par1_peri__VAL REG_VAL_ENUM
10296 #define R_IRQ_READ1__par1_data__par1_data__VAL REG_VAL_ENUM
10297 #define R_IRQ_READ1__par1_ready__par1_ready__VAL REG_VAL_ENUM
10298 #define R_IRQ_READ1__scsi1__scsi1__VAL REG_VAL_ENUM
10299 #define R_IRQ_READ1__par1_ready__scsi1__VAL REG_VAL_ENUM
10300 #define R_IRQ_READ1__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
10301 #define R_IRQ_READ1__ser3_data__ser3_data__VAL REG_VAL_ENUM
10302 #define R_IRQ_READ1__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
10303 #define R_IRQ_READ1__ser2_data__ser2_data__VAL REG_VAL_ENUM
10304 #define R_IRQ_READ1__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
10305 #define R_IRQ_READ1__ser1_data__ser1_data__VAL REG_VAL_ENUM
10306 #define R_IRQ_READ1__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
10307 #define R_IRQ_READ1__ser0_data__ser0_data__VAL REG_VAL_ENUM
10308 #define R_IRQ_READ1__pa7__pa7__VAL REG_VAL_ENUM
10309 #define R_IRQ_READ1__pa6__pa6__VAL REG_VAL_ENUM
10310 #define R_IRQ_READ1__pa5__pa5__VAL REG_VAL_ENUM
10311 #define R_IRQ_READ1__pa4__pa4__VAL REG_VAL_ENUM
10312 #define R_IRQ_READ1__pa3__pa3__VAL REG_VAL_ENUM
10313 #define R_IRQ_READ1__pa2__pa2__VAL REG_VAL_ENUM
10314 #define R_IRQ_READ1__pa1__pa1__VAL REG_VAL_ENUM
10315 #define R_IRQ_READ1__pa0__pa0__VAL REG_VAL_ENUM
10316
10317 #define R_IRQ_READ1__sw_int7__sw_int7__active 1
10318 #define R_IRQ_READ1__sw_int7__sw_int7__inactive 0
10319 #define R_IRQ_READ1__sw_int6__sw_int6__active 1
10320 #define R_IRQ_READ1__sw_int6__sw_int6__inactive 0
10321 #define R_IRQ_READ1__sw_int5__sw_int5__active 1
10322 #define R_IRQ_READ1__sw_int5__sw_int5__inactive 0
10323 #define R_IRQ_READ1__sw_int4__sw_int4__active 1
10324 #define R_IRQ_READ1__sw_int4__sw_int4__inactive 0
10325 #define R_IRQ_READ1__sw_int3__sw_int3__active 1
10326 #define R_IRQ_READ1__sw_int3__sw_int3__inactive 0
10327 #define R_IRQ_READ1__sw_int2__sw_int2__active 1
10328 #define R_IRQ_READ1__sw_int2__sw_int2__inactive 0
10329 #define R_IRQ_READ1__sw_int1__sw_int1__active 1
10330 #define R_IRQ_READ1__sw_int1__sw_int1__inactive 0
10331 #define R_IRQ_READ1__sw_int0__sw_int0__active 1
10332 #define R_IRQ_READ1__sw_int0__sw_int0__inactive 0
10333 #define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__active 1
10334 #define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__inactive 0
10335 #define R_IRQ_READ1__par1_peri__par1_peri__active 1
10336 #define R_IRQ_READ1__par1_peri__par1_peri__inactive 0
10337 #define R_IRQ_READ1__par1_data__par1_data__active 1
10338 #define R_IRQ_READ1__par1_data__par1_data__inactive 0
10339 #define R_IRQ_READ1__par1_ready__par1_ready__active 1
10340 #define R_IRQ_READ1__par1_ready__par1_ready__inactive 0
10341 #define R_IRQ_READ1__scsi1__scsi1__active 1
10342 #define R_IRQ_READ1__scsi1__scsi1__inactive 0
10343 #define R_IRQ_READ1__ser3_ready__ser3_ready__active 1
10344 #define R_IRQ_READ1__ser3_ready__ser3_ready__inactive 0
10345 #define R_IRQ_READ1__ser3_data__ser3_data__active 1
10346 #define R_IRQ_READ1__ser3_data__ser3_data__inactive 0
10347 #define R_IRQ_READ1__ser2_ready__ser2_ready__active 1
10348 #define R_IRQ_READ1__ser2_ready__ser2_ready__inactive 0
10349 #define R_IRQ_READ1__ser2_data__ser2_data__active 1
10350 #define R_IRQ_READ1__ser2_data__ser2_data__inactive 0
10351 #define R_IRQ_READ1__ser1_ready__ser1_ready__active 1
10352 #define R_IRQ_READ1__ser1_ready__ser1_ready__inactive 0
10353 #define R_IRQ_READ1__ser1_data__ser1_data__active 1
10354 #define R_IRQ_READ1__ser1_data__ser1_data__inactive 0
10355 #define R_IRQ_READ1__ser0_ready__ser0_ready__active 1
10356 #define R_IRQ_READ1__ser0_ready__ser0_ready__inactive 0
10357 #define R_IRQ_READ1__ser0_data__ser0_data__active 1
10358 #define R_IRQ_READ1__ser0_data__ser0_data__inactive 0
10359 #define R_IRQ_READ1__pa7__pa7__active 1
10360 #define R_IRQ_READ1__pa7__pa7__inactive 0
10361 #define R_IRQ_READ1__pa6__pa6__active 1
10362 #define R_IRQ_READ1__pa6__pa6__inactive 0
10363 #define R_IRQ_READ1__pa5__pa5__active 1
10364 #define R_IRQ_READ1__pa5__pa5__inactive 0
10365 #define R_IRQ_READ1__pa4__pa4__active 1
10366 #define R_IRQ_READ1__pa4__pa4__inactive 0
10367 #define R_IRQ_READ1__pa3__pa3__active 1
10368 #define R_IRQ_READ1__pa3__pa3__inactive 0
10369 #define R_IRQ_READ1__pa2__pa2__active 1
10370 #define R_IRQ_READ1__pa2__pa2__inactive 0
10371 #define R_IRQ_READ1__pa1__pa1__active 1
10372 #define R_IRQ_READ1__pa1__pa1__inactive 0
10373 #define R_IRQ_READ1__pa0__pa0__active 1
10374 #define R_IRQ_READ1__pa0__pa0__inactive 0
10375
10376 #endif
10377
10378 /*
10379 * R_IRQ_READ2
10380 * - type: RO
10381 * - addr: 0xb00000d4
10382 * - group: Interrupt mask and status registers
10383 */
10384
10385 #if USE_GROUP__Interrupt_mask_and_status_registers
10386
10387 #define R_IRQ_READ2__ADDR (REG_TYPECAST_UDWORD 0xb00000d4)
10388 #define R_IRQ_READ2__SVAL REG_SVAL_SHADOW
10389 #define R_IRQ_READ2__SVAL_I REG_SVAL_I_SHADOW
10390 #define R_IRQ_READ2__TYPECAST REG_TYPECAST_UDWORD
10391 #define R_IRQ_READ2__TYPE (REG_UDWORD)
10392 #define R_IRQ_READ2__GET REG_GET_RO
10393 #define R_IRQ_READ2__IGET REG_IGET_RO
10394 #define R_IRQ_READ2__SET REG_SET_RO
10395 #define R_IRQ_READ2__ISET REG_ISET_RO
10396 #define R_IRQ_READ2__SET_VAL REG_SET_VAL_RO
10397 #define R_IRQ_READ2__EQL REG_EQL_RO
10398 #define R_IRQ_READ2__IEQL REG_IEQL_RO
10399 #define R_IRQ_READ2__RD REG_RD_RO
10400 #define R_IRQ_READ2__IRD REG_IRD_RO
10401 #define R_IRQ_READ2__WR REG_WR_RO
10402 #define R_IRQ_READ2__IWR REG_IWR_RO
10403
10404 #define R_IRQ_READ2__READ(addr) \
10405 (*(addr))
10406
10407 #define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
10408 #define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
10409 #define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
10410 #define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
10411 #define R_IRQ_READ2__dma9_eop__dma9_eop__MASK 0x00080000U
10412 #define R_IRQ_READ2__dma9_descr__dma9_descr__MASK 0x00040000U
10413 #define R_IRQ_READ2__dma8_eop__dma8_eop__MASK 0x00020000U
10414 #define R_IRQ_READ2__dma8_descr__dma8_descr__MASK 0x00010000U
10415 #define R_IRQ_READ2__dma7_eop__dma7_eop__MASK 0x00008000U
10416 #define R_IRQ_READ2__dma7_descr__dma7_descr__MASK 0x00004000U
10417 #define R_IRQ_READ2__dma6_eop__dma6_eop__MASK 0x00002000U
10418 #define R_IRQ_READ2__dma6_descr__dma6_descr__MASK 0x00001000U
10419 #define R_IRQ_READ2__dma5_eop__dma5_eop__MASK 0x00000800U
10420 #define R_IRQ_READ2__dma5_descr__dma5_descr__MASK 0x00000400U
10421 #define R_IRQ_READ2__dma4_eop__dma4_eop__MASK 0x00000200U
10422 #define R_IRQ_READ2__dma4_descr__dma4_descr__MASK 0x00000100U
10423 #define R_IRQ_READ2__dma3_eop__dma3_eop__MASK 0x00000080U
10424 #define R_IRQ_READ2__dma3_descr__dma3_descr__MASK 0x00000040U
10425 #define R_IRQ_READ2__dma2_eop__dma2_eop__MASK 0x00000020U
10426 #define R_IRQ_READ2__dma2_descr__dma2_descr__MASK 0x00000010U
10427 #define R_IRQ_READ2__dma1_eop__dma1_eop__MASK 0x00000008U
10428 #define R_IRQ_READ2__dma1_descr__dma1_descr__MASK 0x00000004U
10429 #define R_IRQ_READ2__dma0_eop__dma0_eop__MASK 0x00000002U
10430 #define R_IRQ_READ2__dma0_descr__dma0_descr__MASK 0x00000001U
10431
10432 #define R_IRQ_READ2__dma8_sub3_descr__MAX 0x1
10433 #define R_IRQ_READ2__dma8_sub2_descr__MAX 0x1
10434 #define R_IRQ_READ2__dma8_sub1_descr__MAX 0x1
10435 #define R_IRQ_READ2__dma8_sub0_descr__MAX 0x1
10436 #define R_IRQ_READ2__dma9_eop__MAX 0x1
10437 #define R_IRQ_READ2__dma9_descr__MAX 0x1
10438 #define R_IRQ_READ2__dma8_eop__MAX 0x1
10439 #define R_IRQ_READ2__dma8_descr__MAX 0x1
10440 #define R_IRQ_READ2__dma7_eop__MAX 0x1
10441 #define R_IRQ_READ2__dma7_descr__MAX 0x1
10442 #define R_IRQ_READ2__dma6_eop__MAX 0x1
10443 #define R_IRQ_READ2__dma6_descr__MAX 0x1
10444 #define R_IRQ_READ2__dma5_eop__MAX 0x1
10445 #define R_IRQ_READ2__dma5_descr__MAX 0x1
10446 #define R_IRQ_READ2__dma4_eop__MAX 0x1
10447 #define R_IRQ_READ2__dma4_descr__MAX 0x1
10448 #define R_IRQ_READ2__dma3_eop__MAX 0x1
10449 #define R_IRQ_READ2__dma3_descr__MAX 0x1
10450 #define R_IRQ_READ2__dma2_eop__MAX 0x1
10451 #define R_IRQ_READ2__dma2_descr__MAX 0x1
10452 #define R_IRQ_READ2__dma1_eop__MAX 0x1
10453 #define R_IRQ_READ2__dma1_descr__MAX 0x1
10454 #define R_IRQ_READ2__dma0_eop__MAX 0x1
10455 #define R_IRQ_READ2__dma0_descr__MAX 0x1
10456
10457 #define R_IRQ_READ2__dma8_sub3_descr__MIN 0
10458 #define R_IRQ_READ2__dma8_sub2_descr__MIN 0
10459 #define R_IRQ_READ2__dma8_sub1_descr__MIN 0
10460 #define R_IRQ_READ2__dma8_sub0_descr__MIN 0
10461 #define R_IRQ_READ2__dma9_eop__MIN 0
10462 #define R_IRQ_READ2__dma9_descr__MIN 0
10463 #define R_IRQ_READ2__dma8_eop__MIN 0
10464 #define R_IRQ_READ2__dma8_descr__MIN 0
10465 #define R_IRQ_READ2__dma7_eop__MIN 0
10466 #define R_IRQ_READ2__dma7_descr__MIN 0
10467 #define R_IRQ_READ2__dma6_eop__MIN 0
10468 #define R_IRQ_READ2__dma6_descr__MIN 0
10469 #define R_IRQ_READ2__dma5_eop__MIN 0
10470 #define R_IRQ_READ2__dma5_descr__MIN 0
10471 #define R_IRQ_READ2__dma4_eop__MIN 0
10472 #define R_IRQ_READ2__dma4_descr__MIN 0
10473 #define R_IRQ_READ2__dma3_eop__MIN 0
10474 #define R_IRQ_READ2__dma3_descr__MIN 0
10475 #define R_IRQ_READ2__dma2_eop__MIN 0
10476 #define R_IRQ_READ2__dma2_descr__MIN 0
10477 #define R_IRQ_READ2__dma1_eop__MIN 0
10478 #define R_IRQ_READ2__dma1_descr__MIN 0
10479 #define R_IRQ_READ2__dma0_eop__MIN 0
10480 #define R_IRQ_READ2__dma0_descr__MIN 0
10481
10482 #define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
10483 #define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
10484 #define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
10485 #define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
10486 #define R_IRQ_READ2__dma9_eop__BITNR 19
10487 #define R_IRQ_READ2__dma9_descr__BITNR 18
10488 #define R_IRQ_READ2__dma8_eop__BITNR 17
10489 #define R_IRQ_READ2__dma8_descr__BITNR 16
10490 #define R_IRQ_READ2__dma7_eop__BITNR 15
10491 #define R_IRQ_READ2__dma7_descr__BITNR 14
10492 #define R_IRQ_READ2__dma6_eop__BITNR 13
10493 #define R_IRQ_READ2__dma6_descr__BITNR 12
10494 #define R_IRQ_READ2__dma5_eop__BITNR 11
10495 #define R_IRQ_READ2__dma5_descr__BITNR 10
10496 #define R_IRQ_READ2__dma4_eop__BITNR 9
10497 #define R_IRQ_READ2__dma4_descr__BITNR 8
10498 #define R_IRQ_READ2__dma3_eop__BITNR 7
10499 #define R_IRQ_READ2__dma3_descr__BITNR 6
10500 #define R_IRQ_READ2__dma2_eop__BITNR 5
10501 #define R_IRQ_READ2__dma2_descr__BITNR 4
10502 #define R_IRQ_READ2__dma1_eop__BITNR 3
10503 #define R_IRQ_READ2__dma1_descr__BITNR 2
10504 #define R_IRQ_READ2__dma0_eop__BITNR 1
10505 #define R_IRQ_READ2__dma0_descr__BITNR 0
10506
10507 #define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
10508 #define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
10509 #define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
10510 #define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
10511 #define R_IRQ_READ2__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
10512 #define R_IRQ_READ2__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
10513 #define R_IRQ_READ2__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
10514 #define R_IRQ_READ2__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
10515 #define R_IRQ_READ2__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
10516 #define R_IRQ_READ2__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
10517 #define R_IRQ_READ2__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
10518 #define R_IRQ_READ2__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
10519 #define R_IRQ_READ2__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
10520 #define R_IRQ_READ2__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
10521 #define R_IRQ_READ2__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
10522 #define R_IRQ_READ2__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
10523 #define R_IRQ_READ2__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
10524 #define R_IRQ_READ2__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
10525 #define R_IRQ_READ2__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
10526 #define R_IRQ_READ2__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
10527 #define R_IRQ_READ2__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
10528 #define R_IRQ_READ2__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
10529 #define R_IRQ_READ2__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
10530 #define R_IRQ_READ2__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
10531
10532 #define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__active 1
10533 #define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__inactive 0
10534 #define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__active 1
10535 #define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__inactive 0
10536 #define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__active 1
10537 #define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__inactive 0
10538 #define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__active 1
10539 #define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__inactive 0
10540 #define R_IRQ_READ2__dma9_eop__dma9_eop__active 1
10541 #define R_IRQ_READ2__dma9_eop__dma9_eop__inactive 0
10542 #define R_IRQ_READ2__dma9_descr__dma9_descr__active 1
10543 #define R_IRQ_READ2__dma9_descr__dma9_descr__inactive 0
10544 #define R_IRQ_READ2__dma8_eop__dma8_eop__active 1
10545 #define R_IRQ_READ2__dma8_eop__dma8_eop__inactive 0
10546 #define R_IRQ_READ2__dma8_descr__dma8_descr__active 1
10547 #define R_IRQ_READ2__dma8_descr__dma8_descr__inactive 0
10548 #define R_IRQ_READ2__dma7_eop__dma7_eop__active 1
10549 #define R_IRQ_READ2__dma7_eop__dma7_eop__inactive 0
10550 #define R_IRQ_READ2__dma7_descr__dma7_descr__active 1
10551 #define R_IRQ_READ2__dma7_descr__dma7_descr__inactive 0
10552 #define R_IRQ_READ2__dma6_eop__dma6_eop__active 1
10553 #define R_IRQ_READ2__dma6_eop__dma6_eop__inactive 0
10554 #define R_IRQ_READ2__dma6_descr__dma6_descr__active 1
10555 #define R_IRQ_READ2__dma6_descr__dma6_descr__inactive 0
10556 #define R_IRQ_READ2__dma5_eop__dma5_eop__active 1
10557 #define R_IRQ_READ2__dma5_eop__dma5_eop__inactive 0
10558 #define R_IRQ_READ2__dma5_descr__dma5_descr__active 1
10559 #define R_IRQ_READ2__dma5_descr__dma5_descr__inactive 0
10560 #define R_IRQ_READ2__dma4_eop__dma4_eop__active 1
10561 #define R_IRQ_READ2__dma4_eop__dma4_eop__inactive 0
10562 #define R_IRQ_READ2__dma4_descr__dma4_descr__active 1
10563 #define R_IRQ_READ2__dma4_descr__dma4_descr__inactive 0
10564 #define R_IRQ_READ2__dma3_eop__dma3_eop__active 1
10565 #define R_IRQ_READ2__dma3_eop__dma3_eop__inactive 0
10566 #define R_IRQ_READ2__dma3_descr__dma3_descr__active 1
10567 #define R_IRQ_READ2__dma3_descr__dma3_descr__inactive 0
10568 #define R_IRQ_READ2__dma2_eop__dma2_eop__active 1
10569 #define R_IRQ_READ2__dma2_eop__dma2_eop__inactive 0
10570 #define R_IRQ_READ2__dma2_descr__dma2_descr__active 1
10571 #define R_IRQ_READ2__dma2_descr__dma2_descr__inactive 0
10572 #define R_IRQ_READ2__dma1_eop__dma1_eop__active 1
10573 #define R_IRQ_READ2__dma1_eop__dma1_eop__inactive 0
10574 #define R_IRQ_READ2__dma1_descr__dma1_descr__active 1
10575 #define R_IRQ_READ2__dma1_descr__dma1_descr__inactive 0
10576 #define R_IRQ_READ2__dma0_eop__dma0_eop__active 1
10577 #define R_IRQ_READ2__dma0_eop__dma0_eop__inactive 0
10578 #define R_IRQ_READ2__dma0_descr__dma0_descr__active 1
10579 #define R_IRQ_READ2__dma0_descr__dma0_descr__inactive 0
10580
10581 #endif
10582
10583 /*
10584 * R_MMU_CAUSE
10585 * - type: RO
10586 * - addr: 0xb0000250
10587 * - group: MMU registers
10588 */
10589
10590 #if USE_GROUP__MMU_registers
10591
10592 #define R_MMU_CAUSE__ADDR (REG_TYPECAST_UDWORD 0xb0000250)
10593 #define R_MMU_CAUSE__SVAL REG_SVAL_SHADOW
10594 #define R_MMU_CAUSE__SVAL_I REG_SVAL_I_SHADOW
10595 #define R_MMU_CAUSE__TYPECAST REG_TYPECAST_UDWORD
10596 #define R_MMU_CAUSE__TYPE (REG_UDWORD)
10597 #define R_MMU_CAUSE__GET REG_GET_RO
10598 #define R_MMU_CAUSE__IGET REG_IGET_RO
10599 #define R_MMU_CAUSE__SET REG_SET_RO
10600 #define R_MMU_CAUSE__ISET REG_ISET_RO
10601 #define R_MMU_CAUSE__SET_VAL REG_SET_VAL_RO
10602 #define R_MMU_CAUSE__EQL REG_EQL_RO
10603 #define R_MMU_CAUSE__IEQL REG_IEQL_RO
10604 #define R_MMU_CAUSE__RD REG_RD_RO
10605 #define R_MMU_CAUSE__IRD REG_IRD_RO
10606 #define R_MMU_CAUSE__WR REG_WR_RO
10607 #define R_MMU_CAUSE__IWR REG_IWR_RO
10608
10609 #define R_MMU_CAUSE__READ(addr) \
10610 (*(addr))
10611
10612 #define R_MMU_CAUSE__vpn__vpn__MASK 0xffffe000U
10613 #define R_MMU_CAUSE__miss_excp__miss_excp__MASK 0x00001000U
10614 #define R_MMU_CAUSE__inv_excp__inv_excp__MASK 0x00000800U
10615 #define R_MMU_CAUSE__acc_excp__acc_excp__MASK 0x00000400U
10616 #define R_MMU_CAUSE__we_excp__we_excp__MASK 0x00000200U
10617 #define R_MMU_CAUSE__wr_rd__wr_rd__MASK 0x00000100U
10618 #define R_MMU_CAUSE__page_id__page_id__MASK 0x0000003fU
10619
10620 #define R_MMU_CAUSE__vpn__MAX 0x7ffff
10621 #define R_MMU_CAUSE__miss_excp__MAX 0x1
10622 #define R_MMU_CAUSE__inv_excp__MAX 0x1
10623 #define R_MMU_CAUSE__acc_excp__MAX 0x1
10624 #define R_MMU_CAUSE__we_excp__MAX 0x1
10625 #define R_MMU_CAUSE__wr_rd__MAX 0x1
10626 #define R_MMU_CAUSE__page_id__MAX 63
10627
10628 #define R_MMU_CAUSE__vpn__MIN 0
10629 #define R_MMU_CAUSE__miss_excp__MIN 0
10630 #define R_MMU_CAUSE__inv_excp__MIN 0
10631 #define R_MMU_CAUSE__acc_excp__MIN 0
10632 #define R_MMU_CAUSE__we_excp__MIN 0
10633 #define R_MMU_CAUSE__wr_rd__MIN 0
10634 #define R_MMU_CAUSE__page_id__MIN 0
10635
10636 #define R_MMU_CAUSE__vpn__BITNR 13
10637 #define R_MMU_CAUSE__miss_excp__BITNR 12
10638 #define R_MMU_CAUSE__inv_excp__BITNR 11
10639 #define R_MMU_CAUSE__acc_excp__BITNR 10
10640 #define R_MMU_CAUSE__we_excp__BITNR 9
10641 #define R_MMU_CAUSE__wr_rd__BITNR 8
10642 #define R_MMU_CAUSE__page_id__BITNR 0
10643
10644 #define R_MMU_CAUSE__vpn__vpn__VAL REG_VAL_VAL
10645 #define R_MMU_CAUSE__miss_excp__miss_excp__VAL REG_VAL_ENUM
10646 #define R_MMU_CAUSE__inv_excp__inv_excp__VAL REG_VAL_ENUM
10647 #define R_MMU_CAUSE__acc_excp__acc_excp__VAL REG_VAL_ENUM
10648 #define R_MMU_CAUSE__we_excp__we_excp__VAL REG_VAL_ENUM
10649 #define R_MMU_CAUSE__wr_rd__wr_rd__VAL REG_VAL_ENUM
10650 #define R_MMU_CAUSE__page_id__page_id__VAL REG_VAL_VAL
10651
10652 #define R_MMU_CAUSE__miss_excp__miss_excp__no 0
10653 #define R_MMU_CAUSE__miss_excp__miss_excp__yes 1
10654 #define R_MMU_CAUSE__inv_excp__inv_excp__no 0
10655 #define R_MMU_CAUSE__inv_excp__inv_excp__yes 1
10656 #define R_MMU_CAUSE__acc_excp__acc_excp__no 0
10657 #define R_MMU_CAUSE__acc_excp__acc_excp__yes 1
10658 #define R_MMU_CAUSE__we_excp__we_excp__no 0
10659 #define R_MMU_CAUSE__we_excp__we_excp__yes 1
10660 #define R_MMU_CAUSE__wr_rd__wr_rd__read 0
10661 #define R_MMU_CAUSE__wr_rd__wr_rd__write 1
10662
10663 #endif
10664
10665 /*
10666 * R_MMU_CONFIG
10667 * - type: WO
10668 * - addr: 0xb0000240
10669 * - group: MMU registers
10670 */
10671
10672 #if USE_GROUP__MMU_registers
10673
10674 #define R_MMU_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000240)
10675
10676 #ifndef REG_NO_SHADOW
10677 #define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2))
10678 #define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2))
10679 #else /* REG_NO_SHADOW */
10680 #define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
10681 #define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
10682 #endif /* REG_NO_SHADOW */
10683
10684 #define R_MMU_CONFIG__STYPECAST REG_STYPECAST_UDWORD
10685 #define R_MMU_CONFIG__SVAL REG_SVAL_SHADOW
10686 #define R_MMU_CONFIG__SVAL_I REG_SVAL_I_SHADOW
10687 #define R_MMU_CONFIG__TYPECAST REG_TYPECAST_UDWORD
10688 #define R_MMU_CONFIG__TYPE (REG_UDWORD)
10689 #define R_MMU_CONFIG__GET REG_GET_WO
10690 #define R_MMU_CONFIG__IGET REG_IGET_WO
10691 #define R_MMU_CONFIG__SET REG_SET_WO
10692 #define R_MMU_CONFIG__ISET REG_ISET_WO
10693 #define R_MMU_CONFIG__SET_VAL REG_SET_VAL_WO
10694 #define R_MMU_CONFIG__EQL REG_EQL_WO
10695 #define R_MMU_CONFIG__IEQL REG_IEQL_WO
10696 #define R_MMU_CONFIG__RD REG_RD_WO
10697 #define R_MMU_CONFIG__IRD REG_IRD_WO
10698 #define R_MMU_CONFIG__WR REG_WR_WO
10699 #define R_MMU_CONFIG__IWR REG_IWR_WO
10700
10701 #define R_MMU_CONFIG__WRITE(addr,value) \
10702 (*(addr) = (value))
10703
10704 #define R_MMU_CONFIG__mmu_enable__mmu_enable__MASK 0x80000000U
10705 #define R_MMU_CONFIG__inv_excp__inv_excp__MASK 0x00040000U
10706 #define R_MMU_CONFIG__acc_excp__acc_excp__MASK 0x00020000U
10707 #define R_MMU_CONFIG__we_excp__we_excp__MASK 0x00010000U
10708 #define R_MMU_CONFIG__seg_f__seg_f__MASK 0x00008000U
10709 #define R_MMU_CONFIG__seg_e__seg_e__MASK 0x00004000U
10710 #define R_MMU_CONFIG__seg_d__seg_d__MASK 0x00002000U
10711 #define R_MMU_CONFIG__seg_c__seg_c__MASK 0x00001000U
10712 #define R_MMU_CONFIG__seg_b__seg_b__MASK 0x00000800U
10713 #define R_MMU_CONFIG__seg_a__seg_a__MASK 0x00000400U
10714 #define R_MMU_CONFIG__seg_9__seg_9__MASK 0x00000200U
10715 #define R_MMU_CONFIG__seg_8__seg_8__MASK 0x00000100U
10716 #define R_MMU_CONFIG__seg_7__seg_7__MASK 0x00000080U
10717 #define R_MMU_CONFIG__seg_6__seg_6__MASK 0x00000040U
10718 #define R_MMU_CONFIG__seg_5__seg_5__MASK 0x00000020U
10719 #define R_MMU_CONFIG__seg_4__seg_4__MASK 0x00000010U
10720 #define R_MMU_CONFIG__seg_3__seg_3__MASK 0x00000008U
10721 #define R_MMU_CONFIG__seg_2__seg_2__MASK 0x00000004U
10722 #define R_MMU_CONFIG__seg_1__seg_1__MASK 0x00000002U
10723 #define R_MMU_CONFIG__seg_0__seg_0__MASK 0x00000001U
10724
10725 #define R_MMU_CONFIG__mmu_enable__MAX 0x1
10726 #define R_MMU_CONFIG__inv_excp__MAX 0x1
10727 #define R_MMU_CONFIG__acc_excp__MAX 0x1
10728 #define R_MMU_CONFIG__we_excp__MAX 0x1
10729 #define R_MMU_CONFIG__seg_f__MAX 0x1
10730 #define R_MMU_CONFIG__seg_e__MAX 0x1
10731 #define R_MMU_CONFIG__seg_d__MAX 0x1
10732 #define R_MMU_CONFIG__seg_c__MAX 0x1
10733 #define R_MMU_CONFIG__seg_b__MAX 0x1
10734 #define R_MMU_CONFIG__seg_a__MAX 0x1
10735 #define R_MMU_CONFIG__seg_9__MAX 0x1
10736 #define R_MMU_CONFIG__seg_8__MAX 0x1
10737 #define R_MMU_CONFIG__seg_7__MAX 0x1
10738 #define R_MMU_CONFIG__seg_6__MAX 0x1
10739 #define R_MMU_CONFIG__seg_5__MAX 0x1
10740 #define R_MMU_CONFIG__seg_4__MAX 0x1
10741 #define R_MMU_CONFIG__seg_3__MAX 0x1
10742 #define R_MMU_CONFIG__seg_2__MAX 0x1
10743 #define R_MMU_CONFIG__seg_1__MAX 0x1
10744 #define R_MMU_CONFIG__seg_0__MAX 0x1
10745
10746 #define R_MMU_CONFIG__mmu_enable__MIN 0
10747 #define R_MMU_CONFIG__inv_excp__MIN 0
10748 #define R_MMU_CONFIG__acc_excp__MIN 0
10749 #define R_MMU_CONFIG__we_excp__MIN 0
10750 #define R_MMU_CONFIG__seg_f__MIN 0
10751 #define R_MMU_CONFIG__seg_e__MIN 0
10752 #define R_MMU_CONFIG__seg_d__MIN 0
10753 #define R_MMU_CONFIG__seg_c__MIN 0
10754 #define R_MMU_CONFIG__seg_b__MIN 0
10755 #define R_MMU_CONFIG__seg_a__MIN 0
10756 #define R_MMU_CONFIG__seg_9__MIN 0
10757 #define R_MMU_CONFIG__seg_8__MIN 0
10758 #define R_MMU_CONFIG__seg_7__MIN 0
10759 #define R_MMU_CONFIG__seg_6__MIN 0
10760 #define R_MMU_CONFIG__seg_5__MIN 0
10761 #define R_MMU_CONFIG__seg_4__MIN 0
10762 #define R_MMU_CONFIG__seg_3__MIN 0
10763 #define R_MMU_CONFIG__seg_2__MIN 0
10764 #define R_MMU_CONFIG__seg_1__MIN 0
10765 #define R_MMU_CONFIG__seg_0__MIN 0
10766
10767 #define R_MMU_CONFIG__mmu_enable__BITNR 31
10768 #define R_MMU_CONFIG__inv_excp__BITNR 18
10769 #define R_MMU_CONFIG__acc_excp__BITNR 17
10770 #define R_MMU_CONFIG__we_excp__BITNR 16
10771 #define R_MMU_CONFIG__seg_f__BITNR 15
10772 #define R_MMU_CONFIG__seg_e__BITNR 14
10773 #define R_MMU_CONFIG__seg_d__BITNR 13
10774 #define R_MMU_CONFIG__seg_c__BITNR 12
10775 #define R_MMU_CONFIG__seg_b__BITNR 11
10776 #define R_MMU_CONFIG__seg_a__BITNR 10
10777 #define R_MMU_CONFIG__seg_9__BITNR 9
10778 #define R_MMU_CONFIG__seg_8__BITNR 8
10779 #define R_MMU_CONFIG__seg_7__BITNR 7
10780 #define R_MMU_CONFIG__seg_6__BITNR 6
10781 #define R_MMU_CONFIG__seg_5__BITNR 5
10782 #define R_MMU_CONFIG__seg_4__BITNR 4
10783 #define R_MMU_CONFIG__seg_3__BITNR 3
10784 #define R_MMU_CONFIG__seg_2__BITNR 2
10785 #define R_MMU_CONFIG__seg_1__BITNR 1
10786 #define R_MMU_CONFIG__seg_0__BITNR 0
10787
10788 #define R_MMU_CONFIG__mmu_enable__mmu_enable__VAL REG_VAL_ENUM
10789 #define R_MMU_CONFIG__inv_excp__inv_excp__VAL REG_VAL_ENUM
10790 #define R_MMU_CONFIG__acc_excp__acc_excp__VAL REG_VAL_ENUM
10791 #define R_MMU_CONFIG__we_excp__we_excp__VAL REG_VAL_ENUM
10792 #define R_MMU_CONFIG__seg_f__seg_f__VAL REG_VAL_ENUM
10793 #define R_MMU_CONFIG__seg_e__seg_e__VAL REG_VAL_ENUM
10794 #define R_MMU_CONFIG__seg_d__seg_d__VAL REG_VAL_ENUM
10795 #define R_MMU_CONFIG__seg_c__seg_c__VAL REG_VAL_ENUM
10796 #define R_MMU_CONFIG__seg_b__seg_b__VAL REG_VAL_ENUM
10797 #define R_MMU_CONFIG__seg_a__seg_a__VAL REG_VAL_ENUM
10798 #define R_MMU_CONFIG__seg_9__seg_9__VAL REG_VAL_ENUM
10799 #define R_MMU_CONFIG__seg_8__seg_8__VAL REG_VAL_ENUM
10800 #define R_MMU_CONFIG__seg_7__seg_7__VAL REG_VAL_ENUM
10801 #define R_MMU_CONFIG__seg_6__seg_6__VAL REG_VAL_ENUM
10802 #define R_MMU_CONFIG__seg_5__seg_5__VAL REG_VAL_ENUM
10803 #define R_MMU_CONFIG__seg_4__seg_4__VAL REG_VAL_ENUM
10804 #define R_MMU_CONFIG__seg_3__seg_3__VAL REG_VAL_ENUM
10805 #define R_MMU_CONFIG__seg_2__seg_2__VAL REG_VAL_ENUM
10806 #define R_MMU_CONFIG__seg_1__seg_1__VAL REG_VAL_ENUM
10807 #define R_MMU_CONFIG__seg_0__seg_0__VAL REG_VAL_ENUM
10808
10809 #define R_MMU_CONFIG__mmu_enable__mmu_enable__disable 0
10810 #define R_MMU_CONFIG__mmu_enable__mmu_enable__enable 1
10811 #define R_MMU_CONFIG__inv_excp__inv_excp__disable 0
10812 #define R_MMU_CONFIG__inv_excp__inv_excp__enable 1
10813 #define R_MMU_CONFIG__acc_excp__acc_excp__disable 0
10814 #define R_MMU_CONFIG__acc_excp__acc_excp__enable 1
10815 #define R_MMU_CONFIG__we_excp__we_excp__disable 0
10816 #define R_MMU_CONFIG__we_excp__we_excp__enable 1
10817 #define R_MMU_CONFIG__seg_f__seg_f__page 0
10818 #define R_MMU_CONFIG__seg_f__seg_f__seg 1
10819 #define R_MMU_CONFIG__seg_e__seg_e__page 0
10820 #define R_MMU_CONFIG__seg_e__seg_e__seg 1
10821 #define R_MMU_CONFIG__seg_d__seg_d__page 0
10822 #define R_MMU_CONFIG__seg_d__seg_d__seg 1
10823 #define R_MMU_CONFIG__seg_c__seg_c__page 0
10824 #define R_MMU_CONFIG__seg_c__seg_c__seg 1
10825 #define R_MMU_CONFIG__seg_b__seg_b__page 0
10826 #define R_MMU_CONFIG__seg_b__seg_b__seg 1
10827 #define R_MMU_CONFIG__seg_a__seg_a__page 0
10828 #define R_MMU_CONFIG__seg_a__seg_a__seg 1
10829 #define R_MMU_CONFIG__seg_9__seg_9__page 0
10830 #define R_MMU_CONFIG__seg_9__seg_9__seg 1
10831 #define R_MMU_CONFIG__seg_8__seg_8__page 0
10832 #define R_MMU_CONFIG__seg_8__seg_8__seg 1
10833 #define R_MMU_CONFIG__seg_7__seg_7__page 0
10834 #define R_MMU_CONFIG__seg_7__seg_7__seg 1
10835 #define R_MMU_CONFIG__seg_6__seg_6__page 0
10836 #define R_MMU_CONFIG__seg_6__seg_6__seg 1
10837 #define R_MMU_CONFIG__seg_5__seg_5__page 0
10838 #define R_MMU_CONFIG__seg_5__seg_5__seg 1
10839 #define R_MMU_CONFIG__seg_4__seg_4__page 0
10840 #define R_MMU_CONFIG__seg_4__seg_4__seg 1
10841 #define R_MMU_CONFIG__seg_3__seg_3__page 0
10842 #define R_MMU_CONFIG__seg_3__seg_3__seg 1
10843 #define R_MMU_CONFIG__seg_2__seg_2__page 0
10844 #define R_MMU_CONFIG__seg_2__seg_2__seg 1
10845 #define R_MMU_CONFIG__seg_1__seg_1__page 0
10846 #define R_MMU_CONFIG__seg_1__seg_1__seg 1
10847 #define R_MMU_CONFIG__seg_0__seg_0__page 0
10848 #define R_MMU_CONFIG__seg_0__seg_0__seg 1
10849
10850 #endif
10851
10852 /*
10853 * R_MMU_CONTEXT
10854 * - type: RW
10855 * - addr: 0xb000024c
10856 * - group: MMU registers
10857 */
10858
10859 #if USE_GROUP__MMU_registers
10860
10861 #define R_MMU_CONTEXT__ADDR (REG_TYPECAST_BYTE 0xb000024c)
10862 #define R_MMU_CONTEXT__SVAL REG_SVAL_SHADOW
10863 #define R_MMU_CONTEXT__SVAL_I REG_SVAL_I_SHADOW
10864 #define R_MMU_CONTEXT__TYPECAST REG_TYPECAST_BYTE
10865 #define R_MMU_CONTEXT__TYPE (REG_BYTE)
10866 #define R_MMU_CONTEXT__GET REG_GET_RW
10867 #define R_MMU_CONTEXT__IGET REG_IGET_RW
10868 #define R_MMU_CONTEXT__SET REG_SET_RW
10869 #define R_MMU_CONTEXT__ISET REG_ISET_RW
10870 #define R_MMU_CONTEXT__SET_VAL REG_SET_VAL_RW
10871 #define R_MMU_CONTEXT__EQL REG_EQL_RW
10872 #define R_MMU_CONTEXT__IEQL REG_IEQL_RW
10873 #define R_MMU_CONTEXT__RD REG_RD_RW
10874 #define R_MMU_CONTEXT__IRD REG_IRD_RW
10875 #define R_MMU_CONTEXT__WR REG_WR_RW
10876 #define R_MMU_CONTEXT__IWR REG_IWR_RW
10877
10878 #define R_MMU_CONTEXT__WRITE(addr,value) \
10879 (*(addr) = (value))
10880 #define R_MMU_CONTEXT__READ(addr) \
10881 (*(addr))
10882
10883 #define R_MMU_CONTEXT__page_id__page_id__MASK 0x0000003fU
10884
10885 #define R_MMU_CONTEXT__page_id__MAX 63
10886
10887 #define R_MMU_CONTEXT__page_id__MIN 0
10888
10889 #define R_MMU_CONTEXT__page_id__BITNR 0
10890
10891 #define R_MMU_CONTEXT__page_id__page_id__VAL REG_VAL_VAL
10892
10893
10894 #endif
10895
10896 /*
10897 * R_MMU_CTRL
10898 * - type: WO
10899 * - addr: 0xb0000242
10900 * - group: MMU registers
10901 */
10902
10903 #if USE_GROUP__MMU_registers
10904
10905 #define R_MMU_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000242)
10906
10907 #ifndef REG_NO_SHADOW
10908 #define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 0))
10909 #define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 0))
10910 #else /* REG_NO_SHADOW */
10911 #define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
10912 #define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
10913 #endif /* REG_NO_SHADOW */
10914
10915 #define R_MMU_CTRL__STYPECAST REG_STYPECAST_BYTE
10916 #define R_MMU_CTRL__SVAL REG_SVAL_SHADOW
10917 #define R_MMU_CTRL__SVAL_I REG_SVAL_I_SHADOW
10918 #define R_MMU_CTRL__TYPECAST REG_TYPECAST_BYTE
10919 #define R_MMU_CTRL__TYPE (REG_BYTE)
10920 #define R_MMU_CTRL__GET REG_GET_WO
10921 #define R_MMU_CTRL__IGET REG_IGET_WO
10922 #define R_MMU_CTRL__SET REG_SET_WO
10923 #define R_MMU_CTRL__ISET REG_ISET_WO
10924 #define R_MMU_CTRL__SET_VAL REG_SET_VAL_WO
10925 #define R_MMU_CTRL__EQL REG_EQL_WO
10926 #define R_MMU_CTRL__IEQL REG_IEQL_WO
10927 #define R_MMU_CTRL__RD REG_RD_WO
10928 #define R_MMU_CTRL__IRD REG_IRD_WO
10929 #define R_MMU_CTRL__WR REG_WR_WO
10930 #define R_MMU_CTRL__IWR REG_IWR_WO
10931
10932 #define R_MMU_CTRL__WRITE(addr,value) \
10933 (*(addr) = (value))
10934
10935 #define R_MMU_CTRL__inv_excp__inv_excp__MASK 0x00000004U
10936 #define R_MMU_CTRL__acc_excp__acc_excp__MASK 0x00000002U
10937 #define R_MMU_CTRL__we_excp__we_excp__MASK 0x00000001U
10938
10939 #define R_MMU_CTRL__inv_excp__MAX 0x1
10940 #define R_MMU_CTRL__acc_excp__MAX 0x1
10941 #define R_MMU_CTRL__we_excp__MAX 0x1
10942
10943 #define R_MMU_CTRL__inv_excp__MIN 0
10944 #define R_MMU_CTRL__acc_excp__MIN 0
10945 #define R_MMU_CTRL__we_excp__MIN 0
10946
10947 #define R_MMU_CTRL__inv_excp__BITNR 2
10948 #define R_MMU_CTRL__acc_excp__BITNR 1
10949 #define R_MMU_CTRL__we_excp__BITNR 0
10950
10951 #define R_MMU_CTRL__inv_excp__inv_excp__VAL REG_VAL_ENUM
10952 #define R_MMU_CTRL__acc_excp__acc_excp__VAL REG_VAL_ENUM
10953 #define R_MMU_CTRL__we_excp__we_excp__VAL REG_VAL_ENUM
10954
10955 #define R_MMU_CTRL__inv_excp__inv_excp__disable 0
10956 #define R_MMU_CTRL__inv_excp__inv_excp__enable 1
10957 #define R_MMU_CTRL__acc_excp__acc_excp__disable 0
10958 #define R_MMU_CTRL__acc_excp__acc_excp__enable 1
10959 #define R_MMU_CTRL__we_excp__we_excp__disable 0
10960 #define R_MMU_CTRL__we_excp__we_excp__enable 1
10961
10962 #endif
10963
10964 /*
10965 * R_MMU_ENABLE
10966 * - type: WO
10967 * - addr: 0xb0000243
10968 * - group: MMU registers
10969 */
10970
10971 #if USE_GROUP__MMU_registers
10972
10973 #define R_MMU_ENABLE__ADDR (REG_TYPECAST_BYTE 0xb0000243)
10974
10975 #ifndef REG_NO_SHADOW
10976 #define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 1))
10977 #define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 1))
10978 #else /* REG_NO_SHADOW */
10979 #define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
10980 #define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
10981 #endif /* REG_NO_SHADOW */
10982
10983 #define R_MMU_ENABLE__STYPECAST REG_STYPECAST_BYTE
10984 #define R_MMU_ENABLE__SVAL REG_SVAL_SHADOW
10985 #define R_MMU_ENABLE__SVAL_I REG_SVAL_I_SHADOW
10986 #define R_MMU_ENABLE__TYPECAST REG_TYPECAST_BYTE
10987 #define R_MMU_ENABLE__TYPE (REG_BYTE)
10988 #define R_MMU_ENABLE__GET REG_GET_WO
10989 #define R_MMU_ENABLE__IGET REG_IGET_WO
10990 #define R_MMU_ENABLE__SET REG_SET_WO
10991 #define R_MMU_ENABLE__ISET REG_ISET_WO
10992 #define R_MMU_ENABLE__SET_VAL REG_SET_VAL_WO
10993 #define R_MMU_ENABLE__EQL REG_EQL_WO
10994 #define R_MMU_ENABLE__IEQL REG_IEQL_WO
10995 #define R_MMU_ENABLE__RD REG_RD_WO
10996 #define R_MMU_ENABLE__IRD REG_IRD_WO
10997 #define R_MMU_ENABLE__WR REG_WR_WO
10998 #define R_MMU_ENABLE__IWR REG_IWR_WO
10999
11000 #define R_MMU_ENABLE__WRITE(addr,value) \
11001 (*(addr) = (value))
11002
11003 #define R_MMU_ENABLE__mmu_enable__mmu_enable__MASK 0x00000080U
11004
11005 #define R_MMU_ENABLE__mmu_enable__MAX 0x1
11006
11007 #define R_MMU_ENABLE__mmu_enable__MIN 0
11008
11009 #define R_MMU_ENABLE__mmu_enable__BITNR 7
11010
11011 #define R_MMU_ENABLE__mmu_enable__mmu_enable__VAL REG_VAL_ENUM
11012
11013 #define R_MMU_ENABLE__mmu_enable__mmu_enable__disable 0
11014 #define R_MMU_ENABLE__mmu_enable__mmu_enable__enable 1
11015
11016 #endif
11017
11018 /*
11019 * R_MMU_KBASE_HI
11020 * - type: WO
11021 * - addr: 0xb0000248
11022 * - group: MMU registers
11023 */
11024
11025 #if USE_GROUP__MMU_registers
11026
11027 #define R_MMU_KBASE_HI__ADDR (REG_TYPECAST_UDWORD 0xb0000248)
11028
11029 #ifndef REG_NO_SHADOW
11030 #define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_HI + 2))
11031 #define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_HI + 2))
11032 #else /* REG_NO_SHADOW */
11033 #define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11034 #define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11035 #endif /* REG_NO_SHADOW */
11036
11037 #define R_MMU_KBASE_HI__STYPECAST REG_STYPECAST_UDWORD
11038 #define R_MMU_KBASE_HI__SVAL REG_SVAL_SHADOW
11039 #define R_MMU_KBASE_HI__SVAL_I REG_SVAL_I_SHADOW
11040 #define R_MMU_KBASE_HI__TYPECAST REG_TYPECAST_UDWORD
11041 #define R_MMU_KBASE_HI__TYPE (REG_UDWORD)
11042 #define R_MMU_KBASE_HI__GET REG_GET_WO
11043 #define R_MMU_KBASE_HI__IGET REG_IGET_WO
11044 #define R_MMU_KBASE_HI__SET REG_SET_WO
11045 #define R_MMU_KBASE_HI__ISET REG_ISET_WO
11046 #define R_MMU_KBASE_HI__SET_VAL REG_SET_VAL_WO
11047 #define R_MMU_KBASE_HI__EQL REG_EQL_WO
11048 #define R_MMU_KBASE_HI__IEQL REG_IEQL_WO
11049 #define R_MMU_KBASE_HI__RD REG_RD_WO
11050 #define R_MMU_KBASE_HI__IRD REG_IRD_WO
11051 #define R_MMU_KBASE_HI__WR REG_WR_WO
11052 #define R_MMU_KBASE_HI__IWR REG_IWR_WO
11053
11054 #define R_MMU_KBASE_HI__WRITE(addr,value) \
11055 (*(addr) = (value))
11056
11057 #define R_MMU_KBASE_HI__base_f__base_f__MASK 0xf0000000U
11058 #define R_MMU_KBASE_HI__base_e__base_e__MASK 0x0f000000U
11059 #define R_MMU_KBASE_HI__base_d__base_d__MASK 0x00f00000U
11060 #define R_MMU_KBASE_HI__base_c__base_c__MASK 0x000f0000U
11061 #define R_MMU_KBASE_HI__base_b__base_b__MASK 0x0000f000U
11062 #define R_MMU_KBASE_HI__base_a__base_a__MASK 0x00000f00U
11063 #define R_MMU_KBASE_HI__base_9__base_9__MASK 0x000000f0U
11064 #define R_MMU_KBASE_HI__base_8__base_8__MASK 0x0000000fU
11065
11066 #define R_MMU_KBASE_HI__base_f__MAX 15
11067 #define R_MMU_KBASE_HI__base_e__MAX 15
11068 #define R_MMU_KBASE_HI__base_d__MAX 15
11069 #define R_MMU_KBASE_HI__base_c__MAX 15
11070 #define R_MMU_KBASE_HI__base_b__MAX 15
11071 #define R_MMU_KBASE_HI__base_a__MAX 15
11072 #define R_MMU_KBASE_HI__base_9__MAX 15
11073 #define R_MMU_KBASE_HI__base_8__MAX 15
11074
11075 #define R_MMU_KBASE_HI__base_f__MIN 0
11076 #define R_MMU_KBASE_HI__base_e__MIN 0
11077 #define R_MMU_KBASE_HI__base_d__MIN 0
11078 #define R_MMU_KBASE_HI__base_c__MIN 0
11079 #define R_MMU_KBASE_HI__base_b__MIN 0
11080 #define R_MMU_KBASE_HI__base_a__MIN 0
11081 #define R_MMU_KBASE_HI__base_9__MIN 0
11082 #define R_MMU_KBASE_HI__base_8__MIN 0
11083
11084 #define R_MMU_KBASE_HI__base_f__BITNR 28
11085 #define R_MMU_KBASE_HI__base_e__BITNR 24
11086 #define R_MMU_KBASE_HI__base_d__BITNR 20
11087 #define R_MMU_KBASE_HI__base_c__BITNR 16
11088 #define R_MMU_KBASE_HI__base_b__BITNR 12
11089 #define R_MMU_KBASE_HI__base_a__BITNR 8
11090 #define R_MMU_KBASE_HI__base_9__BITNR 4
11091 #define R_MMU_KBASE_HI__base_8__BITNR 0
11092
11093 #define R_MMU_KBASE_HI__base_f__base_f__VAL REG_VAL_VAL
11094 #define R_MMU_KBASE_HI__base_e__base_e__VAL REG_VAL_VAL
11095 #define R_MMU_KBASE_HI__base_d__base_d__VAL REG_VAL_VAL
11096 #define R_MMU_KBASE_HI__base_c__base_c__VAL REG_VAL_VAL
11097 #define R_MMU_KBASE_HI__base_b__base_b__VAL REG_VAL_VAL
11098 #define R_MMU_KBASE_HI__base_a__base_a__VAL REG_VAL_VAL
11099 #define R_MMU_KBASE_HI__base_9__base_9__VAL REG_VAL_VAL
11100 #define R_MMU_KBASE_HI__base_8__base_8__VAL REG_VAL_VAL
11101
11102
11103 #endif
11104
11105 /*
11106 * R_MMU_KBASE_LO
11107 * - type: WO
11108 * - addr: 0xb0000244
11109 * - group: MMU registers
11110 */
11111
11112 #if USE_GROUP__MMU_registers
11113
11114 #define R_MMU_KBASE_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000244)
11115
11116 #ifndef REG_NO_SHADOW
11117 #define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_LO + 2))
11118 #define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_LO + 2))
11119 #else /* REG_NO_SHADOW */
11120 #define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11121 #define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11122 #endif /* REG_NO_SHADOW */
11123
11124 #define R_MMU_KBASE_LO__STYPECAST REG_STYPECAST_UDWORD
11125 #define R_MMU_KBASE_LO__SVAL REG_SVAL_SHADOW
11126 #define R_MMU_KBASE_LO__SVAL_I REG_SVAL_I_SHADOW
11127 #define R_MMU_KBASE_LO__TYPECAST REG_TYPECAST_UDWORD
11128 #define R_MMU_KBASE_LO__TYPE (REG_UDWORD)
11129 #define R_MMU_KBASE_LO__GET REG_GET_WO
11130 #define R_MMU_KBASE_LO__IGET REG_IGET_WO
11131 #define R_MMU_KBASE_LO__SET REG_SET_WO
11132 #define R_MMU_KBASE_LO__ISET REG_ISET_WO
11133 #define R_MMU_KBASE_LO__SET_VAL REG_SET_VAL_WO
11134 #define R_MMU_KBASE_LO__EQL REG_EQL_WO
11135 #define R_MMU_KBASE_LO__IEQL REG_IEQL_WO
11136 #define R_MMU_KBASE_LO__RD REG_RD_WO
11137 #define R_MMU_KBASE_LO__IRD REG_IRD_WO
11138 #define R_MMU_KBASE_LO__WR REG_WR_WO
11139 #define R_MMU_KBASE_LO__IWR REG_IWR_WO
11140
11141 #define R_MMU_KBASE_LO__WRITE(addr,value) \
11142 (*(addr) = (value))
11143
11144 #define R_MMU_KBASE_LO__base_7__base_7__MASK 0xf0000000U
11145 #define R_MMU_KBASE_LO__base_6__base_6__MASK 0x0f000000U
11146 #define R_MMU_KBASE_LO__base_5__base_5__MASK 0x00f00000U
11147 #define R_MMU_KBASE_LO__base_4__base_4__MASK 0x000f0000U
11148 #define R_MMU_KBASE_LO__base_3__base_3__MASK 0x0000f000U
11149 #define R_MMU_KBASE_LO__base_2__base_2__MASK 0x00000f00U
11150 #define R_MMU_KBASE_LO__base_1__base_1__MASK 0x000000f0U
11151 #define R_MMU_KBASE_LO__base_0__base_0__MASK 0x0000000fU
11152
11153 #define R_MMU_KBASE_LO__base_7__MAX 15
11154 #define R_MMU_KBASE_LO__base_6__MAX 15
11155 #define R_MMU_KBASE_LO__base_5__MAX 15
11156 #define R_MMU_KBASE_LO__base_4__MAX 15
11157 #define R_MMU_KBASE_LO__base_3__MAX 15
11158 #define R_MMU_KBASE_LO__base_2__MAX 15
11159 #define R_MMU_KBASE_LO__base_1__MAX 15
11160 #define R_MMU_KBASE_LO__base_0__MAX 15
11161
11162 #define R_MMU_KBASE_LO__base_7__MIN 0
11163 #define R_MMU_KBASE_LO__base_6__MIN 0
11164 #define R_MMU_KBASE_LO__base_5__MIN 0
11165 #define R_MMU_KBASE_LO__base_4__MIN 0
11166 #define R_MMU_KBASE_LO__base_3__MIN 0
11167 #define R_MMU_KBASE_LO__base_2__MIN 0
11168 #define R_MMU_KBASE_LO__base_1__MIN 0
11169 #define R_MMU_KBASE_LO__base_0__MIN 0
11170
11171 #define R_MMU_KBASE_LO__base_7__BITNR 28
11172 #define R_MMU_KBASE_LO__base_6__BITNR 24
11173 #define R_MMU_KBASE_LO__base_5__BITNR 20
11174 #define R_MMU_KBASE_LO__base_4__BITNR 16
11175 #define R_MMU_KBASE_LO__base_3__BITNR 12
11176 #define R_MMU_KBASE_LO__base_2__BITNR 8
11177 #define R_MMU_KBASE_LO__base_1__BITNR 4
11178 #define R_MMU_KBASE_LO__base_0__BITNR 0
11179
11180 #define R_MMU_KBASE_LO__base_7__base_7__VAL REG_VAL_VAL
11181 #define R_MMU_KBASE_LO__base_6__base_6__VAL REG_VAL_VAL
11182 #define R_MMU_KBASE_LO__base_5__base_5__VAL REG_VAL_VAL
11183 #define R_MMU_KBASE_LO__base_4__base_4__VAL REG_VAL_VAL
11184 #define R_MMU_KBASE_LO__base_3__base_3__VAL REG_VAL_VAL
11185 #define R_MMU_KBASE_LO__base_2__base_2__VAL REG_VAL_VAL
11186 #define R_MMU_KBASE_LO__base_1__base_1__VAL REG_VAL_VAL
11187 #define R_MMU_KBASE_LO__base_0__base_0__VAL REG_VAL_VAL
11188
11189
11190 #endif
11191
11192 /*
11193 * R_MMU_KSEG
11194 * - type: WO
11195 * - addr: 0xb0000240
11196 * - group: MMU registers
11197 */
11198
11199 #if USE_GROUP__MMU_registers
11200
11201 #define R_MMU_KSEG__ADDR (REG_TYPECAST_UWORD 0xb0000240)
11202
11203 #ifndef REG_NO_SHADOW
11204 #define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2))
11205 #define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2))
11206 #else /* REG_NO_SHADOW */
11207 #define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
11208 #define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
11209 #endif /* REG_NO_SHADOW */
11210
11211 #define R_MMU_KSEG__STYPECAST REG_STYPECAST_UWORD
11212 #define R_MMU_KSEG__SVAL REG_SVAL_SHADOW
11213 #define R_MMU_KSEG__SVAL_I REG_SVAL_I_SHADOW
11214 #define R_MMU_KSEG__TYPECAST REG_TYPECAST_UWORD
11215 #define R_MMU_KSEG__TYPE (REG_UWORD)
11216 #define R_MMU_KSEG__GET REG_GET_WO
11217 #define R_MMU_KSEG__IGET REG_IGET_WO
11218 #define R_MMU_KSEG__SET REG_SET_WO
11219 #define R_MMU_KSEG__ISET REG_ISET_WO
11220 #define R_MMU_KSEG__SET_VAL REG_SET_VAL_WO
11221 #define R_MMU_KSEG__EQL REG_EQL_WO
11222 #define R_MMU_KSEG__IEQL REG_IEQL_WO
11223 #define R_MMU_KSEG__RD REG_RD_WO
11224 #define R_MMU_KSEG__IRD REG_IRD_WO
11225 #define R_MMU_KSEG__WR REG_WR_WO
11226 #define R_MMU_KSEG__IWR REG_IWR_WO
11227
11228 #define R_MMU_KSEG__WRITE(addr,value) \
11229 (*(addr) = (value))
11230
11231 #define R_MMU_KSEG__seg_f__seg_f__MASK 0x00008000U
11232 #define R_MMU_KSEG__seg_e__seg_e__MASK 0x00004000U
11233 #define R_MMU_KSEG__seg_d__seg_d__MASK 0x00002000U
11234 #define R_MMU_KSEG__seg_c__seg_c__MASK 0x00001000U
11235 #define R_MMU_KSEG__seg_b__seg_b__MASK 0x00000800U
11236 #define R_MMU_KSEG__seg_a__seg_a__MASK 0x00000400U
11237 #define R_MMU_KSEG__seg_9__seg_9__MASK 0x00000200U
11238 #define R_MMU_KSEG__seg_8__seg_8__MASK 0x00000100U
11239 #define R_MMU_KSEG__seg_7__seg_7__MASK 0x00000080U
11240 #define R_MMU_KSEG__seg_6__seg_6__MASK 0x00000040U
11241 #define R_MMU_KSEG__seg_5__seg_5__MASK 0x00000020U
11242 #define R_MMU_KSEG__seg_4__seg_4__MASK 0x00000010U
11243 #define R_MMU_KSEG__seg_3__seg_3__MASK 0x00000008U
11244 #define R_MMU_KSEG__seg_2__seg_2__MASK 0x00000004U
11245 #define R_MMU_KSEG__seg_1__seg_1__MASK 0x00000002U
11246 #define R_MMU_KSEG__seg_0__seg_0__MASK 0x00000001U
11247
11248 #define R_MMU_KSEG__seg_f__MAX 0x1
11249 #define R_MMU_KSEG__seg_e__MAX 0x1
11250 #define R_MMU_KSEG__seg_d__MAX 0x1
11251 #define R_MMU_KSEG__seg_c__MAX 0x1
11252 #define R_MMU_KSEG__seg_b__MAX 0x1
11253 #define R_MMU_KSEG__seg_a__MAX 0x1
11254 #define R_MMU_KSEG__seg_9__MAX 0x1
11255 #define R_MMU_KSEG__seg_8__MAX 0x1
11256 #define R_MMU_KSEG__seg_7__MAX 0x1
11257 #define R_MMU_KSEG__seg_6__MAX 0x1
11258 #define R_MMU_KSEG__seg_5__MAX 0x1
11259 #define R_MMU_KSEG__seg_4__MAX 0x1
11260 #define R_MMU_KSEG__seg_3__MAX 0x1
11261 #define R_MMU_KSEG__seg_2__MAX 0x1
11262 #define R_MMU_KSEG__seg_1__MAX 0x1
11263 #define R_MMU_KSEG__seg_0__MAX 0x1
11264
11265 #define R_MMU_KSEG__seg_f__MIN 0
11266 #define R_MMU_KSEG__seg_e__MIN 0
11267 #define R_MMU_KSEG__seg_d__MIN 0
11268 #define R_MMU_KSEG__seg_c__MIN 0
11269 #define R_MMU_KSEG__seg_b__MIN 0
11270 #define R_MMU_KSEG__seg_a__MIN 0
11271 #define R_MMU_KSEG__seg_9__MIN 0
11272 #define R_MMU_KSEG__seg_8__MIN 0
11273 #define R_MMU_KSEG__seg_7__MIN 0
11274 #define R_MMU_KSEG__seg_6__MIN 0
11275 #define R_MMU_KSEG__seg_5__MIN 0
11276 #define R_MMU_KSEG__seg_4__MIN 0
11277 #define R_MMU_KSEG__seg_3__MIN 0
11278 #define R_MMU_KSEG__seg_2__MIN 0
11279 #define R_MMU_KSEG__seg_1__MIN 0
11280 #define R_MMU_KSEG__seg_0__MIN 0
11281
11282 #define R_MMU_KSEG__seg_f__BITNR 15
11283 #define R_MMU_KSEG__seg_e__BITNR 14
11284 #define R_MMU_KSEG__seg_d__BITNR 13
11285 #define R_MMU_KSEG__seg_c__BITNR 12
11286 #define R_MMU_KSEG__seg_b__BITNR 11
11287 #define R_MMU_KSEG__seg_a__BITNR 10
11288 #define R_MMU_KSEG__seg_9__BITNR 9
11289 #define R_MMU_KSEG__seg_8__BITNR 8
11290 #define R_MMU_KSEG__seg_7__BITNR 7
11291 #define R_MMU_KSEG__seg_6__BITNR 6
11292 #define R_MMU_KSEG__seg_5__BITNR 5
11293 #define R_MMU_KSEG__seg_4__BITNR 4
11294 #define R_MMU_KSEG__seg_3__BITNR 3
11295 #define R_MMU_KSEG__seg_2__BITNR 2
11296 #define R_MMU_KSEG__seg_1__BITNR 1
11297 #define R_MMU_KSEG__seg_0__BITNR 0
11298
11299 #define R_MMU_KSEG__seg_f__seg_f__VAL REG_VAL_ENUM
11300 #define R_MMU_KSEG__seg_e__seg_e__VAL REG_VAL_ENUM
11301 #define R_MMU_KSEG__seg_d__seg_d__VAL REG_VAL_ENUM
11302 #define R_MMU_KSEG__seg_c__seg_c__VAL REG_VAL_ENUM
11303 #define R_MMU_KSEG__seg_b__seg_b__VAL REG_VAL_ENUM
11304 #define R_MMU_KSEG__seg_a__seg_a__VAL REG_VAL_ENUM
11305 #define R_MMU_KSEG__seg_9__seg_9__VAL REG_VAL_ENUM
11306 #define R_MMU_KSEG__seg_8__seg_8__VAL REG_VAL_ENUM
11307 #define R_MMU_KSEG__seg_7__seg_7__VAL REG_VAL_ENUM
11308 #define R_MMU_KSEG__seg_6__seg_6__VAL REG_VAL_ENUM
11309 #define R_MMU_KSEG__seg_5__seg_5__VAL REG_VAL_ENUM
11310 #define R_MMU_KSEG__seg_4__seg_4__VAL REG_VAL_ENUM
11311 #define R_MMU_KSEG__seg_3__seg_3__VAL REG_VAL_ENUM
11312 #define R_MMU_KSEG__seg_2__seg_2__VAL REG_VAL_ENUM
11313 #define R_MMU_KSEG__seg_1__seg_1__VAL REG_VAL_ENUM
11314 #define R_MMU_KSEG__seg_0__seg_0__VAL REG_VAL_ENUM
11315
11316 #define R_MMU_KSEG__seg_f__seg_f__page 0
11317 #define R_MMU_KSEG__seg_f__seg_f__seg 1
11318 #define R_MMU_KSEG__seg_e__seg_e__page 0
11319 #define R_MMU_KSEG__seg_e__seg_e__seg 1
11320 #define R_MMU_KSEG__seg_d__seg_d__page 0
11321 #define R_MMU_KSEG__seg_d__seg_d__seg 1
11322 #define R_MMU_KSEG__seg_c__seg_c__page 0
11323 #define R_MMU_KSEG__seg_c__seg_c__seg 1
11324 #define R_MMU_KSEG__seg_b__seg_b__page 0
11325 #define R_MMU_KSEG__seg_b__seg_b__seg 1
11326 #define R_MMU_KSEG__seg_a__seg_a__page 0
11327 #define R_MMU_KSEG__seg_a__seg_a__seg 1
11328 #define R_MMU_KSEG__seg_9__seg_9__page 0
11329 #define R_MMU_KSEG__seg_9__seg_9__seg 1
11330 #define R_MMU_KSEG__seg_8__seg_8__page 0
11331 #define R_MMU_KSEG__seg_8__seg_8__seg 1
11332 #define R_MMU_KSEG__seg_7__seg_7__page 0
11333 #define R_MMU_KSEG__seg_7__seg_7__seg 1
11334 #define R_MMU_KSEG__seg_6__seg_6__page 0
11335 #define R_MMU_KSEG__seg_6__seg_6__seg 1
11336 #define R_MMU_KSEG__seg_5__seg_5__page 0
11337 #define R_MMU_KSEG__seg_5__seg_5__seg 1
11338 #define R_MMU_KSEG__seg_4__seg_4__page 0
11339 #define R_MMU_KSEG__seg_4__seg_4__seg 1
11340 #define R_MMU_KSEG__seg_3__seg_3__page 0
11341 #define R_MMU_KSEG__seg_3__seg_3__seg 1
11342 #define R_MMU_KSEG__seg_2__seg_2__page 0
11343 #define R_MMU_KSEG__seg_2__seg_2__seg 1
11344 #define R_MMU_KSEG__seg_1__seg_1__page 0
11345 #define R_MMU_KSEG__seg_1__seg_1__seg 1
11346 #define R_MMU_KSEG__seg_0__seg_0__page 0
11347 #define R_MMU_KSEG__seg_0__seg_0__seg 1
11348
11349 #endif
11350
11351 /*
11352 * R_NETWORK_GA_0
11353 * - type: WO
11354 * - addr: 0xb000008c
11355 * - group: Network interface registers
11356 */
11357
11358 #if USE_GROUP__Network_interface_registers
11359
11360 #define R_NETWORK_GA_0__ADDR (REG_TYPECAST_UDWORD 0xb000008c)
11361
11362 #ifndef REG_NO_SHADOW
11363 #define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_0 + 0))
11364 #define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_0 + 0))
11365 #else /* REG_NO_SHADOW */
11366 #define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11367 #define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11368 #endif /* REG_NO_SHADOW */
11369
11370 #define R_NETWORK_GA_0__STYPECAST REG_STYPECAST_UDWORD
11371 #define R_NETWORK_GA_0__SVAL REG_SVAL_SHADOW
11372 #define R_NETWORK_GA_0__SVAL_I REG_SVAL_I_SHADOW
11373 #define R_NETWORK_GA_0__TYPECAST REG_TYPECAST_UDWORD
11374 #define R_NETWORK_GA_0__TYPE (REG_UDWORD)
11375 #define R_NETWORK_GA_0__GET REG_GET_WO
11376 #define R_NETWORK_GA_0__IGET REG_IGET_WO
11377 #define R_NETWORK_GA_0__SET REG_SET_WO
11378 #define R_NETWORK_GA_0__ISET REG_ISET_WO
11379 #define R_NETWORK_GA_0__SET_VAL REG_SET_VAL_WO
11380 #define R_NETWORK_GA_0__EQL REG_EQL_WO
11381 #define R_NETWORK_GA_0__IEQL REG_IEQL_WO
11382 #define R_NETWORK_GA_0__RD REG_RD_WO
11383 #define R_NETWORK_GA_0__IRD REG_IRD_WO
11384 #define R_NETWORK_GA_0__WR REG_WR_WO
11385 #define R_NETWORK_GA_0__IWR REG_IWR_WO
11386
11387 #define R_NETWORK_GA_0__WRITE(addr,value) \
11388 (*(addr) = (value))
11389
11390 #define R_NETWORK_GA_0__ga_low__ga_low__MASK 0xffffffffU
11391
11392 #define R_NETWORK_GA_0__ga_low__MAX 0xffffffff
11393
11394 #define R_NETWORK_GA_0__ga_low__MIN 0
11395
11396 #define R_NETWORK_GA_0__ga_low__BITNR 0
11397
11398 #define R_NETWORK_GA_0__ga_low__ga_low__VAL REG_VAL_VAL
11399
11400
11401 #endif
11402
11403 /*
11404 * R_NETWORK_GA_1
11405 * - type: WO
11406 * - addr: 0xb0000090
11407 * - group: Network interface registers
11408 */
11409
11410 #if USE_GROUP__Network_interface_registers
11411
11412 #define R_NETWORK_GA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000090)
11413
11414 #ifndef REG_NO_SHADOW
11415 #define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_1 + 0))
11416 #define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_1 + 0))
11417 #else /* REG_NO_SHADOW */
11418 #define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11419 #define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11420 #endif /* REG_NO_SHADOW */
11421
11422 #define R_NETWORK_GA_1__STYPECAST REG_STYPECAST_UDWORD
11423 #define R_NETWORK_GA_1__SVAL REG_SVAL_SHADOW
11424 #define R_NETWORK_GA_1__SVAL_I REG_SVAL_I_SHADOW
11425 #define R_NETWORK_GA_1__TYPECAST REG_TYPECAST_UDWORD
11426 #define R_NETWORK_GA_1__TYPE (REG_UDWORD)
11427 #define R_NETWORK_GA_1__GET REG_GET_WO
11428 #define R_NETWORK_GA_1__IGET REG_IGET_WO
11429 #define R_NETWORK_GA_1__SET REG_SET_WO
11430 #define R_NETWORK_GA_1__ISET REG_ISET_WO
11431 #define R_NETWORK_GA_1__SET_VAL REG_SET_VAL_WO
11432 #define R_NETWORK_GA_1__EQL REG_EQL_WO
11433 #define R_NETWORK_GA_1__IEQL REG_IEQL_WO
11434 #define R_NETWORK_GA_1__RD REG_RD_WO
11435 #define R_NETWORK_GA_1__IRD REG_IRD_WO
11436 #define R_NETWORK_GA_1__WR REG_WR_WO
11437 #define R_NETWORK_GA_1__IWR REG_IWR_WO
11438
11439 #define R_NETWORK_GA_1__WRITE(addr,value) \
11440 (*(addr) = (value))
11441
11442 #define R_NETWORK_GA_1__ga_high__ga_high__MASK 0xffffffffU
11443
11444 #define R_NETWORK_GA_1__ga_high__MAX 0xffffffff
11445
11446 #define R_NETWORK_GA_1__ga_high__MIN 0
11447
11448 #define R_NETWORK_GA_1__ga_high__BITNR 0
11449
11450 #define R_NETWORK_GA_1__ga_high__ga_high__VAL REG_VAL_VAL
11451
11452
11453 #endif
11454
11455 /*
11456 * R_NETWORK_GEN_CONFIG
11457 * - type: WO
11458 * - addr: 0xb0000098
11459 * - group: Network interface registers
11460 */
11461
11462 #if USE_GROUP__Network_interface_registers
11463
11464 #define R_NETWORK_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000098)
11465
11466 #ifndef REG_NO_SHADOW
11467 #define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GEN_CONFIG + 0))
11468 #define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GEN_CONFIG + 0))
11469 #else /* REG_NO_SHADOW */
11470 #define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11471 #define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11472 #endif /* REG_NO_SHADOW */
11473
11474 #define R_NETWORK_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD
11475 #define R_NETWORK_GEN_CONFIG__SVAL REG_SVAL_SHADOW
11476 #define R_NETWORK_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW
11477 #define R_NETWORK_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD
11478 #define R_NETWORK_GEN_CONFIG__TYPE (REG_UDWORD)
11479 #define R_NETWORK_GEN_CONFIG__GET REG_GET_WO
11480 #define R_NETWORK_GEN_CONFIG__IGET REG_IGET_WO
11481 #define R_NETWORK_GEN_CONFIG__SET REG_SET_WO
11482 #define R_NETWORK_GEN_CONFIG__ISET REG_ISET_WO
11483 #define R_NETWORK_GEN_CONFIG__SET_VAL REG_SET_VAL_WO
11484 #define R_NETWORK_GEN_CONFIG__EQL REG_EQL_WO
11485 #define R_NETWORK_GEN_CONFIG__IEQL REG_IEQL_WO
11486 #define R_NETWORK_GEN_CONFIG__RD REG_RD_WO
11487 #define R_NETWORK_GEN_CONFIG__IRD REG_IRD_WO
11488 #define R_NETWORK_GEN_CONFIG__WR REG_WR_WO
11489 #define R_NETWORK_GEN_CONFIG__IWR REG_IWR_WO
11490
11491 #define R_NETWORK_GEN_CONFIG__WRITE(addr,value) \
11492 (*(addr) = (value))
11493
11494 #define R_NETWORK_GEN_CONFIG__loopback__loopback__MASK 0x00000020U
11495 #define R_NETWORK_GEN_CONFIG__frame__frame__MASK 0x00000010U
11496 #define R_NETWORK_GEN_CONFIG__vg__vg__MASK 0x00000008U
11497 #define R_NETWORK_GEN_CONFIG__phy__phy__MASK 0x00000006U
11498 #define R_NETWORK_GEN_CONFIG__enable__enable__MASK 0x00000001U
11499
11500 #define R_NETWORK_GEN_CONFIG__loopback__MAX 0x1
11501 #define R_NETWORK_GEN_CONFIG__frame__MAX 0x1
11502 #define R_NETWORK_GEN_CONFIG__vg__MAX 0x1
11503 #define R_NETWORK_GEN_CONFIG__phy__MAX 0x3
11504 #define R_NETWORK_GEN_CONFIG__enable__MAX 0x1
11505
11506 #define R_NETWORK_GEN_CONFIG__loopback__MIN 0
11507 #define R_NETWORK_GEN_CONFIG__frame__MIN 0
11508 #define R_NETWORK_GEN_CONFIG__vg__MIN 0
11509 #define R_NETWORK_GEN_CONFIG__phy__MIN 0
11510 #define R_NETWORK_GEN_CONFIG__enable__MIN 0
11511
11512 #define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
11513 #define R_NETWORK_GEN_CONFIG__frame__BITNR 4
11514 #define R_NETWORK_GEN_CONFIG__vg__BITNR 3
11515 #define R_NETWORK_GEN_CONFIG__phy__BITNR 1
11516 #define R_NETWORK_GEN_CONFIG__enable__BITNR 0
11517
11518 #define R_NETWORK_GEN_CONFIG__loopback__loopback__VAL REG_VAL_ENUM
11519 #define R_NETWORK_GEN_CONFIG__frame__frame__VAL REG_VAL_ENUM
11520 #define R_NETWORK_GEN_CONFIG__vg__vg__VAL REG_VAL_ENUM
11521 #define R_NETWORK_GEN_CONFIG__phy__phy__VAL REG_VAL_ENUM
11522 #define R_NETWORK_GEN_CONFIG__enable__enable__VAL REG_VAL_ENUM
11523
11524 #define R_NETWORK_GEN_CONFIG__loopback__loopback__off 0
11525 #define R_NETWORK_GEN_CONFIG__loopback__loopback__on 1
11526 #define R_NETWORK_GEN_CONFIG__frame__frame__ether 0
11527 #define R_NETWORK_GEN_CONFIG__frame__frame__tokenr 1
11528 #define R_NETWORK_GEN_CONFIG__vg__vg__off 0
11529 #define R_NETWORK_GEN_CONFIG__vg__vg__on 1
11530 #define R_NETWORK_GEN_CONFIG__phy__phy__mii_clk 1
11531 #define R_NETWORK_GEN_CONFIG__phy__phy__mii_err 2
11532 #define R_NETWORK_GEN_CONFIG__phy__phy__mii_req 3
11533 #define R_NETWORK_GEN_CONFIG__phy__phy__sni 0
11534 #define R_NETWORK_GEN_CONFIG__enable__enable__off 0
11535 #define R_NETWORK_GEN_CONFIG__enable__enable__on 1
11536
11537 #endif
11538
11539 /*
11540 * R_NETWORK_MGM_CTRL
11541 * - type: WO
11542 * - addr: 0xb00000a0
11543 * - group: Network interface registers
11544 */
11545
11546 #if USE_GROUP__Network_interface_registers
11547
11548 #define R_NETWORK_MGM_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb00000a0)
11549
11550 #ifndef REG_NO_SHADOW
11551 #define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_MGM_CTRL + 0))
11552 #define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_MGM_CTRL + 0))
11553 #else /* REG_NO_SHADOW */
11554 #define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11555 #define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11556 #endif /* REG_NO_SHADOW */
11557
11558 #define R_NETWORK_MGM_CTRL__STYPECAST REG_STYPECAST_UDWORD
11559 #define R_NETWORK_MGM_CTRL__SVAL REG_SVAL_SHADOW
11560 #define R_NETWORK_MGM_CTRL__SVAL_I REG_SVAL_I_SHADOW
11561 #define R_NETWORK_MGM_CTRL__TYPECAST REG_TYPECAST_UDWORD
11562 #define R_NETWORK_MGM_CTRL__TYPE (REG_UDWORD)
11563 #define R_NETWORK_MGM_CTRL__GET REG_GET_WO
11564 #define R_NETWORK_MGM_CTRL__IGET REG_IGET_WO
11565 #define R_NETWORK_MGM_CTRL__SET REG_SET_WO
11566 #define R_NETWORK_MGM_CTRL__ISET REG_ISET_WO
11567 #define R_NETWORK_MGM_CTRL__SET_VAL REG_SET_VAL_WO
11568 #define R_NETWORK_MGM_CTRL__EQL REG_EQL_WO
11569 #define R_NETWORK_MGM_CTRL__IEQL REG_IEQL_WO
11570 #define R_NETWORK_MGM_CTRL__RD REG_RD_WO
11571 #define R_NETWORK_MGM_CTRL__IRD REG_IRD_WO
11572 #define R_NETWORK_MGM_CTRL__WR REG_WR_WO
11573 #define R_NETWORK_MGM_CTRL__IWR REG_IWR_WO
11574
11575 #define R_NETWORK_MGM_CTRL__WRITE(addr,value) \
11576 (*(addr) = (value))
11577
11578 #define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__MASK 0x000000f0U
11579 #define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__MASK 0x00000008U
11580 #define R_NETWORK_MGM_CTRL__mdck__mdck__MASK 0x00000004U
11581 #define R_NETWORK_MGM_CTRL__mdoe__mdoe__MASK 0x00000002U
11582 #define R_NETWORK_MGM_CTRL__mdio__mdio__MASK 0x00000001U
11583
11584 #define R_NETWORK_MGM_CTRL__txd_pins__MAX 0xf
11585 #define R_NETWORK_MGM_CTRL__txer_pin__MAX 0x1
11586 #define R_NETWORK_MGM_CTRL__mdck__MAX 0x1
11587 #define R_NETWORK_MGM_CTRL__mdoe__MAX 0x1
11588 #define R_NETWORK_MGM_CTRL__mdio__MAX 0x1
11589
11590 #define R_NETWORK_MGM_CTRL__txd_pins__MIN 0
11591 #define R_NETWORK_MGM_CTRL__txer_pin__MIN 0
11592 #define R_NETWORK_MGM_CTRL__mdck__MIN 0
11593 #define R_NETWORK_MGM_CTRL__mdoe__MIN 0
11594 #define R_NETWORK_MGM_CTRL__mdio__MIN 0
11595
11596 #define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
11597 #define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
11598 #define R_NETWORK_MGM_CTRL__mdck__BITNR 2
11599 #define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
11600 #define R_NETWORK_MGM_CTRL__mdio__BITNR 0
11601
11602 #define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__VAL REG_VAL_VAL
11603 #define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__VAL REG_VAL_VAL
11604 #define R_NETWORK_MGM_CTRL__mdck__mdck__VAL REG_VAL_VAL
11605 #define R_NETWORK_MGM_CTRL__mdoe__mdoe__VAL REG_VAL_ENUM
11606 #define R_NETWORK_MGM_CTRL__mdio__mdio__VAL REG_VAL_VAL
11607
11608 #define R_NETWORK_MGM_CTRL__mdoe__mdoe__disable 0
11609 #define R_NETWORK_MGM_CTRL__mdoe__mdoe__enable 1
11610
11611 #endif
11612
11613 /*
11614 * R_NETWORK_REC_CONFIG
11615 * - type: WO
11616 * - addr: 0xb0000094
11617 * - group: Network interface registers
11618 */
11619
11620 #if USE_GROUP__Network_interface_registers
11621
11622 #define R_NETWORK_REC_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000094)
11623
11624 #ifndef REG_NO_SHADOW
11625 #define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_REC_CONFIG + 0))
11626 #define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_REC_CONFIG + 0))
11627 #else /* REG_NO_SHADOW */
11628 #define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11629 #define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11630 #endif /* REG_NO_SHADOW */
11631
11632 #define R_NETWORK_REC_CONFIG__STYPECAST REG_STYPECAST_UDWORD
11633 #define R_NETWORK_REC_CONFIG__SVAL REG_SVAL_SHADOW
11634 #define R_NETWORK_REC_CONFIG__SVAL_I REG_SVAL_I_SHADOW
11635 #define R_NETWORK_REC_CONFIG__TYPECAST REG_TYPECAST_UDWORD
11636 #define R_NETWORK_REC_CONFIG__TYPE (REG_UDWORD)
11637 #define R_NETWORK_REC_CONFIG__GET REG_GET_WO
11638 #define R_NETWORK_REC_CONFIG__IGET REG_IGET_WO
11639 #define R_NETWORK_REC_CONFIG__SET REG_SET_WO
11640 #define R_NETWORK_REC_CONFIG__ISET REG_ISET_WO
11641 #define R_NETWORK_REC_CONFIG__SET_VAL REG_SET_VAL_WO
11642 #define R_NETWORK_REC_CONFIG__EQL REG_EQL_WO
11643 #define R_NETWORK_REC_CONFIG__IEQL REG_IEQL_WO
11644 #define R_NETWORK_REC_CONFIG__RD REG_RD_WO
11645 #define R_NETWORK_REC_CONFIG__IRD REG_IRD_WO
11646 #define R_NETWORK_REC_CONFIG__WR REG_WR_WO
11647 #define R_NETWORK_REC_CONFIG__IWR REG_IWR_WO
11648
11649 #define R_NETWORK_REC_CONFIG__WRITE(addr,value) \
11650 (*(addr) = (value))
11651
11652 #define R_NETWORK_REC_CONFIG__max_size__max_size__MASK 0x00000400U
11653 #define R_NETWORK_REC_CONFIG__duplex__duplex__MASK 0x00000200U
11654 #define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__MASK 0x00000100U
11655 #define R_NETWORK_REC_CONFIG__oversize__oversize__MASK 0x00000080U
11656 #define R_NETWORK_REC_CONFIG__undersize__undersize__MASK 0x00000040U
11657 #define R_NETWORK_REC_CONFIG__all_roots__all_roots__MASK 0x00000020U
11658 #define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__MASK 0x00000010U
11659 #define R_NETWORK_REC_CONFIG__broadcast__broadcast__MASK 0x00000008U
11660 #define R_NETWORK_REC_CONFIG__individual__individual__MASK 0x00000004U
11661 #define R_NETWORK_REC_CONFIG__ma1__ma1__MASK 0x00000002U
11662 #define R_NETWORK_REC_CONFIG__ma0__ma0__MASK 0x00000001U
11663
11664 #define R_NETWORK_REC_CONFIG__max_size__MAX 0x1
11665 #define R_NETWORK_REC_CONFIG__duplex__MAX 0x1
11666 #define R_NETWORK_REC_CONFIG__bad_crc__MAX 0x1
11667 #define R_NETWORK_REC_CONFIG__oversize__MAX 0x1
11668 #define R_NETWORK_REC_CONFIG__undersize__MAX 0x1
11669 #define R_NETWORK_REC_CONFIG__all_roots__MAX 0x1
11670 #define R_NETWORK_REC_CONFIG__tr_broadcast__MAX 0x1
11671 #define R_NETWORK_REC_CONFIG__broadcast__MAX 0x1
11672 #define R_NETWORK_REC_CONFIG__individual__MAX 0x1
11673 #define R_NETWORK_REC_CONFIG__ma1__MAX 0x1
11674 #define R_NETWORK_REC_CONFIG__ma0__MAX 0x1
11675
11676 #define R_NETWORK_REC_CONFIG__max_size__MIN 0
11677 #define R_NETWORK_REC_CONFIG__duplex__MIN 0
11678 #define R_NETWORK_REC_CONFIG__bad_crc__MIN 0
11679 #define R_NETWORK_REC_CONFIG__oversize__MIN 0
11680 #define R_NETWORK_REC_CONFIG__undersize__MIN 0
11681 #define R_NETWORK_REC_CONFIG__all_roots__MIN 0
11682 #define R_NETWORK_REC_CONFIG__tr_broadcast__MIN 0
11683 #define R_NETWORK_REC_CONFIG__broadcast__MIN 0
11684 #define R_NETWORK_REC_CONFIG__individual__MIN 0
11685 #define R_NETWORK_REC_CONFIG__ma1__MIN 0
11686 #define R_NETWORK_REC_CONFIG__ma0__MIN 0
11687
11688 #define R_NETWORK_REC_CONFIG__max_size__BITNR 10
11689 #define R_NETWORK_REC_CONFIG__duplex__BITNR 9
11690 #define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
11691 #define R_NETWORK_REC_CONFIG__oversize__BITNR 7
11692 #define R_NETWORK_REC_CONFIG__undersize__BITNR 6
11693 #define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
11694 #define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
11695 #define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
11696 #define R_NETWORK_REC_CONFIG__individual__BITNR 2
11697 #define R_NETWORK_REC_CONFIG__ma1__BITNR 1
11698 #define R_NETWORK_REC_CONFIG__ma0__BITNR 0
11699
11700 #define R_NETWORK_REC_CONFIG__max_size__max_size__VAL REG_VAL_ENUM
11701 #define R_NETWORK_REC_CONFIG__duplex__duplex__VAL REG_VAL_ENUM
11702 #define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__VAL REG_VAL_ENUM
11703 #define R_NETWORK_REC_CONFIG__oversize__oversize__VAL REG_VAL_ENUM
11704 #define R_NETWORK_REC_CONFIG__undersize__undersize__VAL REG_VAL_ENUM
11705 #define R_NETWORK_REC_CONFIG__all_roots__all_roots__VAL REG_VAL_ENUM
11706 #define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__VAL REG_VAL_ENUM
11707 #define R_NETWORK_REC_CONFIG__broadcast__broadcast__VAL REG_VAL_ENUM
11708 #define R_NETWORK_REC_CONFIG__individual__individual__VAL REG_VAL_ENUM
11709 #define R_NETWORK_REC_CONFIG__ma1__ma1__VAL REG_VAL_ENUM
11710 #define R_NETWORK_REC_CONFIG__ma0__ma0__VAL REG_VAL_ENUM
11711
11712 #define R_NETWORK_REC_CONFIG__max_size__max_size__size1518 0
11713 #define R_NETWORK_REC_CONFIG__max_size__max_size__size1522 1
11714 #define R_NETWORK_REC_CONFIG__duplex__duplex__full 1
11715 #define R_NETWORK_REC_CONFIG__duplex__duplex__half 0
11716 #define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__discard 0
11717 #define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__receive 1
11718 #define R_NETWORK_REC_CONFIG__oversize__oversize__discard 0
11719 #define R_NETWORK_REC_CONFIG__oversize__oversize__receive 1
11720 #define R_NETWORK_REC_CONFIG__undersize__undersize__discard 0
11721 #define R_NETWORK_REC_CONFIG__undersize__undersize__receive 1
11722 #define R_NETWORK_REC_CONFIG__all_roots__all_roots__discard 0
11723 #define R_NETWORK_REC_CONFIG__all_roots__all_roots__receive 1
11724 #define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__discard 0
11725 #define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__receive 1
11726 #define R_NETWORK_REC_CONFIG__broadcast__broadcast__discard 0
11727 #define R_NETWORK_REC_CONFIG__broadcast__broadcast__receive 1
11728 #define R_NETWORK_REC_CONFIG__individual__individual__discard 0
11729 #define R_NETWORK_REC_CONFIG__individual__individual__receive 1
11730 #define R_NETWORK_REC_CONFIG__ma1__ma1__disable 0
11731 #define R_NETWORK_REC_CONFIG__ma1__ma1__enable 1
11732 #define R_NETWORK_REC_CONFIG__ma0__ma0__disable 0
11733 #define R_NETWORK_REC_CONFIG__ma0__ma0__enable 1
11734
11735 #endif
11736
11737 /*
11738 * R_NETWORK_SA_0
11739 * - type: WO
11740 * - addr: 0xb0000080
11741 * - group: Network interface registers
11742 */
11743
11744 #if USE_GROUP__Network_interface_registers
11745
11746 #define R_NETWORK_SA_0__ADDR (REG_TYPECAST_UDWORD 0xb0000080)
11747
11748 #ifndef REG_NO_SHADOW
11749 #define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_0 + 0))
11750 #define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_0 + 0))
11751 #else /* REG_NO_SHADOW */
11752 #define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11753 #define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11754 #endif /* REG_NO_SHADOW */
11755
11756 #define R_NETWORK_SA_0__STYPECAST REG_STYPECAST_UDWORD
11757 #define R_NETWORK_SA_0__SVAL REG_SVAL_SHADOW
11758 #define R_NETWORK_SA_0__SVAL_I REG_SVAL_I_SHADOW
11759 #define R_NETWORK_SA_0__TYPECAST REG_TYPECAST_UDWORD
11760 #define R_NETWORK_SA_0__TYPE (REG_UDWORD)
11761 #define R_NETWORK_SA_0__GET REG_GET_WO
11762 #define R_NETWORK_SA_0__IGET REG_IGET_WO
11763 #define R_NETWORK_SA_0__SET REG_SET_WO
11764 #define R_NETWORK_SA_0__ISET REG_ISET_WO
11765 #define R_NETWORK_SA_0__SET_VAL REG_SET_VAL_WO
11766 #define R_NETWORK_SA_0__EQL REG_EQL_WO
11767 #define R_NETWORK_SA_0__IEQL REG_IEQL_WO
11768 #define R_NETWORK_SA_0__RD REG_RD_WO
11769 #define R_NETWORK_SA_0__IRD REG_IRD_WO
11770 #define R_NETWORK_SA_0__WR REG_WR_WO
11771 #define R_NETWORK_SA_0__IWR REG_IWR_WO
11772
11773 #define R_NETWORK_SA_0__WRITE(addr,value) \
11774 (*(addr) = (value))
11775
11776 #define R_NETWORK_SA_0__ma0_low__ma0_low__MASK 0xffffffffU
11777
11778 #define R_NETWORK_SA_0__ma0_low__MAX 0xffffffff
11779
11780 #define R_NETWORK_SA_0__ma0_low__MIN 0
11781
11782 #define R_NETWORK_SA_0__ma0_low__BITNR 0
11783
11784 #define R_NETWORK_SA_0__ma0_low__ma0_low__VAL REG_VAL_VAL
11785
11786
11787 #endif
11788
11789 /*
11790 * R_NETWORK_SA_1
11791 * - type: WO
11792 * - addr: 0xb0000084
11793 * - group: Network interface registers
11794 */
11795
11796 #if USE_GROUP__Network_interface_registers
11797
11798 #define R_NETWORK_SA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000084)
11799
11800 #ifndef REG_NO_SHADOW
11801 #define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_1 + 0))
11802 #define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_1 + 0))
11803 #else /* REG_NO_SHADOW */
11804 #define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11805 #define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11806 #endif /* REG_NO_SHADOW */
11807
11808 #define R_NETWORK_SA_1__STYPECAST REG_STYPECAST_UDWORD
11809 #define R_NETWORK_SA_1__SVAL REG_SVAL_SHADOW
11810 #define R_NETWORK_SA_1__SVAL_I REG_SVAL_I_SHADOW
11811 #define R_NETWORK_SA_1__TYPECAST REG_TYPECAST_UDWORD
11812 #define R_NETWORK_SA_1__TYPE (REG_UDWORD)
11813 #define R_NETWORK_SA_1__GET REG_GET_WO
11814 #define R_NETWORK_SA_1__IGET REG_IGET_WO
11815 #define R_NETWORK_SA_1__SET REG_SET_WO
11816 #define R_NETWORK_SA_1__ISET REG_ISET_WO
11817 #define R_NETWORK_SA_1__SET_VAL REG_SET_VAL_WO
11818 #define R_NETWORK_SA_1__EQL REG_EQL_WO
11819 #define R_NETWORK_SA_1__IEQL REG_IEQL_WO
11820 #define R_NETWORK_SA_1__RD REG_RD_WO
11821 #define R_NETWORK_SA_1__IRD REG_IRD_WO
11822 #define R_NETWORK_SA_1__WR REG_WR_WO
11823 #define R_NETWORK_SA_1__IWR REG_IWR_WO
11824
11825 #define R_NETWORK_SA_1__WRITE(addr,value) \
11826 (*(addr) = (value))
11827
11828 #define R_NETWORK_SA_1__ma1_low__ma1_low__MASK 0xffff0000U
11829 #define R_NETWORK_SA_1__ma0_high__ma0_high__MASK 0x0000ffffU
11830
11831 #define R_NETWORK_SA_1__ma1_low__MAX 0xffff
11832 #define R_NETWORK_SA_1__ma0_high__MAX 0xffff
11833
11834 #define R_NETWORK_SA_1__ma1_low__MIN 0
11835 #define R_NETWORK_SA_1__ma0_high__MIN 0
11836
11837 #define R_NETWORK_SA_1__ma1_low__BITNR 16
11838 #define R_NETWORK_SA_1__ma0_high__BITNR 0
11839
11840 #define R_NETWORK_SA_1__ma1_low__ma1_low__VAL REG_VAL_VAL
11841 #define R_NETWORK_SA_1__ma0_high__ma0_high__VAL REG_VAL_VAL
11842
11843
11844 #endif
11845
11846 /*
11847 * R_NETWORK_SA_2
11848 * - type: WO
11849 * - addr: 0xb0000088
11850 * - group: Network interface registers
11851 */
11852
11853 #if USE_GROUP__Network_interface_registers
11854
11855 #define R_NETWORK_SA_2__ADDR (REG_TYPECAST_UDWORD 0xb0000088)
11856
11857 #ifndef REG_NO_SHADOW
11858 #define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_2 + 0))
11859 #define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_2 + 0))
11860 #else /* REG_NO_SHADOW */
11861 #define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11862 #define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11863 #endif /* REG_NO_SHADOW */
11864
11865 #define R_NETWORK_SA_2__STYPECAST REG_STYPECAST_UDWORD
11866 #define R_NETWORK_SA_2__SVAL REG_SVAL_SHADOW
11867 #define R_NETWORK_SA_2__SVAL_I REG_SVAL_I_SHADOW
11868 #define R_NETWORK_SA_2__TYPECAST REG_TYPECAST_UDWORD
11869 #define R_NETWORK_SA_2__TYPE (REG_UDWORD)
11870 #define R_NETWORK_SA_2__GET REG_GET_WO
11871 #define R_NETWORK_SA_2__IGET REG_IGET_WO
11872 #define R_NETWORK_SA_2__SET REG_SET_WO
11873 #define R_NETWORK_SA_2__ISET REG_ISET_WO
11874 #define R_NETWORK_SA_2__SET_VAL REG_SET_VAL_WO
11875 #define R_NETWORK_SA_2__EQL REG_EQL_WO
11876 #define R_NETWORK_SA_2__IEQL REG_IEQL_WO
11877 #define R_NETWORK_SA_2__RD REG_RD_WO
11878 #define R_NETWORK_SA_2__IRD REG_IRD_WO
11879 #define R_NETWORK_SA_2__WR REG_WR_WO
11880 #define R_NETWORK_SA_2__IWR REG_IWR_WO
11881
11882 #define R_NETWORK_SA_2__WRITE(addr,value) \
11883 (*(addr) = (value))
11884
11885 #define R_NETWORK_SA_2__ma1_high__ma1_high__MASK 0xffffffffU
11886
11887 #define R_NETWORK_SA_2__ma1_high__MAX 0xffffffff
11888
11889 #define R_NETWORK_SA_2__ma1_high__MIN 0
11890
11891 #define R_NETWORK_SA_2__ma1_high__BITNR 0
11892
11893 #define R_NETWORK_SA_2__ma1_high__ma1_high__VAL REG_VAL_VAL
11894
11895
11896 #endif
11897
11898 /*
11899 * R_NETWORK_STAT
11900 * - type: RO
11901 * - addr: 0xb00000a0
11902 * - group: Network interface registers
11903 */
11904
11905 #if USE_GROUP__Network_interface_registers
11906
11907 #define R_NETWORK_STAT__ADDR (REG_TYPECAST_UDWORD 0xb00000a0)
11908 #define R_NETWORK_STAT__SVAL REG_SVAL_SHADOW
11909 #define R_NETWORK_STAT__SVAL_I REG_SVAL_I_SHADOW
11910 #define R_NETWORK_STAT__TYPECAST REG_TYPECAST_UDWORD
11911 #define R_NETWORK_STAT__TYPE (REG_UDWORD)
11912 #define R_NETWORK_STAT__GET REG_GET_RO
11913 #define R_NETWORK_STAT__IGET REG_IGET_RO
11914 #define R_NETWORK_STAT__SET REG_SET_RO
11915 #define R_NETWORK_STAT__ISET REG_ISET_RO
11916 #define R_NETWORK_STAT__SET_VAL REG_SET_VAL_RO
11917 #define R_NETWORK_STAT__EQL REG_EQL_RO
11918 #define R_NETWORK_STAT__IEQL REG_IEQL_RO
11919 #define R_NETWORK_STAT__RD REG_RD_RO
11920 #define R_NETWORK_STAT__IRD REG_IRD_RO
11921 #define R_NETWORK_STAT__WR REG_WR_RO
11922 #define R_NETWORK_STAT__IWR REG_IWR_RO
11923
11924 #define R_NETWORK_STAT__READ(addr) \
11925 (*(addr))
11926
11927 #define R_NETWORK_STAT__rxd_pins__rxd_pins__MASK 0x000000f0U
11928 #define R_NETWORK_STAT__rxer__rxer__MASK 0x00000008U
11929 #define R_NETWORK_STAT__underrun__underrun__MASK 0x00000004U
11930 #define R_NETWORK_STAT__exc_col__exc_col__MASK 0x00000002U
11931 #define R_NETWORK_STAT__mdio__mdio__MASK 0x00000001U
11932
11933 #define R_NETWORK_STAT__rxd_pins__MAX 0xf
11934 #define R_NETWORK_STAT__rxer__MAX 0x1
11935 #define R_NETWORK_STAT__underrun__MAX 0x1
11936 #define R_NETWORK_STAT__exc_col__MAX 0x1
11937 #define R_NETWORK_STAT__mdio__MAX 0x1
11938
11939 #define R_NETWORK_STAT__rxd_pins__MIN 0
11940 #define R_NETWORK_STAT__rxer__MIN 0
11941 #define R_NETWORK_STAT__underrun__MIN 0
11942 #define R_NETWORK_STAT__exc_col__MIN 0
11943 #define R_NETWORK_STAT__mdio__MIN 0
11944
11945 #define R_NETWORK_STAT__rxd_pins__BITNR 4
11946 #define R_NETWORK_STAT__rxer__BITNR 3
11947 #define R_NETWORK_STAT__underrun__BITNR 2
11948 #define R_NETWORK_STAT__exc_col__BITNR 1
11949 #define R_NETWORK_STAT__mdio__BITNR 0
11950
11951 #define R_NETWORK_STAT__rxd_pins__rxd_pins__VAL REG_VAL_VAL
11952 #define R_NETWORK_STAT__rxer__rxer__VAL REG_VAL_VAL
11953 #define R_NETWORK_STAT__underrun__underrun__VAL REG_VAL_ENUM
11954 #define R_NETWORK_STAT__exc_col__exc_col__VAL REG_VAL_ENUM
11955 #define R_NETWORK_STAT__mdio__mdio__VAL REG_VAL_VAL
11956
11957 #define R_NETWORK_STAT__underrun__underrun__no 0
11958 #define R_NETWORK_STAT__underrun__underrun__yes 1
11959 #define R_NETWORK_STAT__exc_col__exc_col__no 0
11960 #define R_NETWORK_STAT__exc_col__exc_col__yes 1
11961
11962 #endif
11963
11964 /*
11965 * R_NETWORK_TR_CTRL
11966 * - type: WO
11967 * - addr: 0xb000009c
11968 * - group: Network interface registers
11969 */
11970
11971 #if USE_GROUP__Network_interface_registers
11972
11973 #define R_NETWORK_TR_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb000009c)
11974
11975 #ifndef REG_NO_SHADOW
11976 #define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_TR_CTRL + 0))
11977 #define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_TR_CTRL + 0))
11978 #else /* REG_NO_SHADOW */
11979 #define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
11980 #define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
11981 #endif /* REG_NO_SHADOW */
11982
11983 #define R_NETWORK_TR_CTRL__STYPECAST REG_STYPECAST_UDWORD
11984 #define R_NETWORK_TR_CTRL__SVAL REG_SVAL_SHADOW
11985 #define R_NETWORK_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
11986 #define R_NETWORK_TR_CTRL__TYPECAST REG_TYPECAST_UDWORD
11987 #define R_NETWORK_TR_CTRL__TYPE (REG_UDWORD)
11988 #define R_NETWORK_TR_CTRL__GET REG_GET_WO
11989 #define R_NETWORK_TR_CTRL__IGET REG_IGET_WO
11990 #define R_NETWORK_TR_CTRL__SET REG_SET_WO
11991 #define R_NETWORK_TR_CTRL__ISET REG_ISET_WO
11992 #define R_NETWORK_TR_CTRL__SET_VAL REG_SET_VAL_WO
11993 #define R_NETWORK_TR_CTRL__EQL REG_EQL_WO
11994 #define R_NETWORK_TR_CTRL__IEQL REG_IEQL_WO
11995 #define R_NETWORK_TR_CTRL__RD REG_RD_WO
11996 #define R_NETWORK_TR_CTRL__IRD REG_IRD_WO
11997 #define R_NETWORK_TR_CTRL__WR REG_WR_WO
11998 #define R_NETWORK_TR_CTRL__IWR REG_IWR_WO
11999
12000 #define R_NETWORK_TR_CTRL__WRITE(addr,value) \
12001 (*(addr) = (value))
12002
12003 #define R_NETWORK_TR_CTRL__clr_error__clr_error__MASK 0x00000100U
12004 #define R_NETWORK_TR_CTRL__delay__delay__MASK 0x00000020U
12005 #define R_NETWORK_TR_CTRL__cancel__cancel__MASK 0x00000010U
12006 #define R_NETWORK_TR_CTRL__cd__cd__MASK 0x00000008U
12007 #define R_NETWORK_TR_CTRL__retry__retry__MASK 0x00000004U
12008 #define R_NETWORK_TR_CTRL__pad__pad__MASK 0x00000002U
12009 #define R_NETWORK_TR_CTRL__crc__crc__MASK 0x00000001U
12010
12011 #define R_NETWORK_TR_CTRL__clr_error__MAX 0x1
12012 #define R_NETWORK_TR_CTRL__delay__MAX 0x1
12013 #define R_NETWORK_TR_CTRL__cancel__MAX 0x1
12014 #define R_NETWORK_TR_CTRL__cd__MAX 0x1
12015 #define R_NETWORK_TR_CTRL__retry__MAX 0x1
12016 #define R_NETWORK_TR_CTRL__pad__MAX 0x1
12017 #define R_NETWORK_TR_CTRL__crc__MAX 0x1
12018
12019 #define R_NETWORK_TR_CTRL__clr_error__MIN 0
12020 #define R_NETWORK_TR_CTRL__delay__MIN 0
12021 #define R_NETWORK_TR_CTRL__cancel__MIN 0
12022 #define R_NETWORK_TR_CTRL__cd__MIN 0
12023 #define R_NETWORK_TR_CTRL__retry__MIN 0
12024 #define R_NETWORK_TR_CTRL__pad__MIN 0
12025 #define R_NETWORK_TR_CTRL__crc__MIN 0
12026
12027 #define R_NETWORK_TR_CTRL__clr_error__BITNR 8
12028 #define R_NETWORK_TR_CTRL__delay__BITNR 5
12029 #define R_NETWORK_TR_CTRL__cancel__BITNR 4
12030 #define R_NETWORK_TR_CTRL__cd__BITNR 3
12031 #define R_NETWORK_TR_CTRL__retry__BITNR 2
12032 #define R_NETWORK_TR_CTRL__pad__BITNR 1
12033 #define R_NETWORK_TR_CTRL__crc__BITNR 0
12034
12035 #define R_NETWORK_TR_CTRL__clr_error__clr_error__VAL REG_VAL_ENUM
12036 #define R_NETWORK_TR_CTRL__delay__delay__VAL REG_VAL_ENUM
12037 #define R_NETWORK_TR_CTRL__cancel__cancel__VAL REG_VAL_ENUM
12038 #define R_NETWORK_TR_CTRL__cd__cd__VAL REG_VAL_ENUM
12039 #define R_NETWORK_TR_CTRL__retry__retry__VAL REG_VAL_ENUM
12040 #define R_NETWORK_TR_CTRL__pad__pad__VAL REG_VAL_ENUM
12041 #define R_NETWORK_TR_CTRL__crc__crc__VAL REG_VAL_ENUM
12042
12043 #define R_NETWORK_TR_CTRL__clr_error__clr_error__clr 1
12044 #define R_NETWORK_TR_CTRL__clr_error__clr_error__nop 0
12045 #define R_NETWORK_TR_CTRL__delay__delay__d2us 1
12046 #define R_NETWORK_TR_CTRL__delay__delay__none 0
12047 #define R_NETWORK_TR_CTRL__cancel__cancel__do 1
12048 #define R_NETWORK_TR_CTRL__cancel__cancel__dont 0
12049 #define R_NETWORK_TR_CTRL__cd__cd__ack_col 0
12050 #define R_NETWORK_TR_CTRL__cd__cd__ack_crs 1
12051 #define R_NETWORK_TR_CTRL__cd__cd__disable 1
12052 #define R_NETWORK_TR_CTRL__cd__cd__enable 0
12053 #define R_NETWORK_TR_CTRL__retry__retry__disable 1
12054 #define R_NETWORK_TR_CTRL__retry__retry__enable 0
12055 #define R_NETWORK_TR_CTRL__pad__pad__disable 0
12056 #define R_NETWORK_TR_CTRL__pad__pad__enable 1
12057 #define R_NETWORK_TR_CTRL__crc__crc__disable 1
12058 #define R_NETWORK_TR_CTRL__crc__crc__enable 0
12059
12060 #endif
12061
12062 /*
12063 * R_PAR0_CONFIG
12064 * - type: WO
12065 * - addr: 0xb0000044
12066 * - group: Parallel printer port registers
12067 */
12068
12069 #if USE_GROUP__Parallel_printer_port_registers
12070
12071 #define R_PAR0_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
12072
12073 #ifndef REG_NO_SHADOW
12074 #define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
12075 #define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
12076 #else /* REG_NO_SHADOW */
12077 #define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
12078 #define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
12079 #endif /* REG_NO_SHADOW */
12080
12081 #define R_PAR0_CONFIG__STYPECAST REG_STYPECAST_UDWORD
12082 #define R_PAR0_CONFIG__SVAL REG_SVAL_SHADOW
12083 #define R_PAR0_CONFIG__SVAL_I REG_SVAL_I_SHADOW
12084 #define R_PAR0_CONFIG__TYPECAST REG_TYPECAST_UDWORD
12085 #define R_PAR0_CONFIG__TYPE (REG_UDWORD)
12086 #define R_PAR0_CONFIG__GET REG_GET_WO
12087 #define R_PAR0_CONFIG__IGET REG_IGET_WO
12088 #define R_PAR0_CONFIG__SET REG_SET_WO
12089 #define R_PAR0_CONFIG__ISET REG_ISET_WO
12090 #define R_PAR0_CONFIG__SET_VAL REG_SET_VAL_WO
12091 #define R_PAR0_CONFIG__EQL REG_EQL_WO
12092 #define R_PAR0_CONFIG__IEQL REG_IEQL_WO
12093 #define R_PAR0_CONFIG__RD REG_RD_WO
12094 #define R_PAR0_CONFIG__IRD REG_IRD_WO
12095 #define R_PAR0_CONFIG__WR REG_WR_WO
12096 #define R_PAR0_CONFIG__IWR REG_IWR_WO
12097
12098 #define R_PAR0_CONFIG__WRITE(addr,value) \
12099 (*(addr) = (value))
12100
12101 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
12102 #define R_PAR0_CONFIG__FIRST 0
12103 #define R_PAR0_CONFIG__IOFFSET 12
12104 #define R_PAR0_CONFIG__LAST 1
12105 #define R_PAR0_CONFIG__OFFSET 16
12106 #define R_PAR0_CONFIG__SOFFSET 12
12107 /* end */
12108
12109 #define R_PAR0_CONFIG__ioe__ioe__MASK 0x02000000U
12110 #define R_PAR0_CONFIG__iseli__iseli__MASK 0x01000000U
12111 #define R_PAR0_CONFIG__iautofd__iautofd__MASK 0x00800000U
12112 #define R_PAR0_CONFIG__istrb__istrb__MASK 0x00400000U
12113 #define R_PAR0_CONFIG__iinit__iinit__MASK 0x00200000U
12114 #define R_PAR0_CONFIG__iperr__iperr__MASK 0x00100000U
12115 #define R_PAR0_CONFIG__iack__iack__MASK 0x00080000U
12116 #define R_PAR0_CONFIG__ibusy__ibusy__MASK 0x00040000U
12117 #define R_PAR0_CONFIG__ifault__ifault__MASK 0x00020000U
12118 #define R_PAR0_CONFIG__isel__isel__MASK 0x00010000U
12119 #define R_PAR0_CONFIG__ext_mode__ext_mode__MASK 0x00000800U
12120 #define R_PAR0_CONFIG__wide__wide__MASK 0x00000400U
12121 #define R_PAR0_CONFIG__dma__dma__MASK 0x00000200U
12122 #define R_PAR0_CONFIG__rle_in__rle_in__MASK 0x00000100U
12123 #define R_PAR0_CONFIG__rle_out__rle_out__MASK 0x00000080U
12124 #define R_PAR0_CONFIG__enable__enable__MASK 0x00000040U
12125 #define R_PAR0_CONFIG__force__force__MASK 0x00000020U
12126 #define R_PAR0_CONFIG__ign_ack__ign_ack__MASK 0x00000010U
12127 #define R_PAR0_CONFIG__oe_ack__oe_ack__MASK 0x00000008U
12128 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U
12129 #define R_PAR0_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U
12130 #define R_PAR0_CONFIG__mode__mode__MASK 0x00000007U
12131
12132 #define R_PAR0_CONFIG__ioe__MAX 0x1
12133 #define R_PAR0_CONFIG__iseli__MAX 0x1
12134 #define R_PAR0_CONFIG__iautofd__MAX 0x1
12135 #define R_PAR0_CONFIG__istrb__MAX 0x1
12136 #define R_PAR0_CONFIG__iinit__MAX 0x1
12137 #define R_PAR0_CONFIG__iperr__MAX 0x1
12138 #define R_PAR0_CONFIG__iack__MAX 0x1
12139 #define R_PAR0_CONFIG__ibusy__MAX 0x1
12140 #define R_PAR0_CONFIG__ifault__MAX 0x1
12141 #define R_PAR0_CONFIG__isel__MAX 0x1
12142 #define R_PAR0_CONFIG__ext_mode__MAX 0x1
12143 #define R_PAR0_CONFIG__wide__MAX 0x1
12144 #define R_PAR0_CONFIG__dma__MAX 0x1
12145 #define R_PAR0_CONFIG__rle_in__MAX 0x1
12146 #define R_PAR0_CONFIG__rle_out__MAX 0x1
12147 #define R_PAR0_CONFIG__enable__MAX 0x1
12148 #define R_PAR0_CONFIG__force__MAX 0x1
12149 #define R_PAR0_CONFIG__ign_ack__MAX 0x1
12150 #define R_PAR0_CONFIG__oe_ack__MAX 0x1
12151 #define R_PAR0_CONFIG__epp_addr_data__MAX 0x1
12152 #define R_PAR0_CONFIG__mode__MAX 0x7
12153
12154 #define R_PAR0_CONFIG__ioe__MIN 0
12155 #define R_PAR0_CONFIG__iseli__MIN 0
12156 #define R_PAR0_CONFIG__iautofd__MIN 0
12157 #define R_PAR0_CONFIG__istrb__MIN 0
12158 #define R_PAR0_CONFIG__iinit__MIN 0
12159 #define R_PAR0_CONFIG__iperr__MIN 0
12160 #define R_PAR0_CONFIG__iack__MIN 0
12161 #define R_PAR0_CONFIG__ibusy__MIN 0
12162 #define R_PAR0_CONFIG__ifault__MIN 0
12163 #define R_PAR0_CONFIG__isel__MIN 0
12164 #define R_PAR0_CONFIG__ext_mode__MIN 0
12165 #define R_PAR0_CONFIG__wide__MIN 0
12166 #define R_PAR0_CONFIG__dma__MIN 0
12167 #define R_PAR0_CONFIG__rle_in__MIN 0
12168 #define R_PAR0_CONFIG__rle_out__MIN 0
12169 #define R_PAR0_CONFIG__enable__MIN 0
12170 #define R_PAR0_CONFIG__force__MIN 0
12171 #define R_PAR0_CONFIG__ign_ack__MIN 0
12172 #define R_PAR0_CONFIG__oe_ack__MIN 0
12173 #define R_PAR0_CONFIG__epp_addr_data__MIN 0
12174 #define R_PAR0_CONFIG__mode__MIN 0
12175
12176 #define R_PAR0_CONFIG__ioe__BITNR 25
12177 #define R_PAR0_CONFIG__iseli__BITNR 24
12178 #define R_PAR0_CONFIG__iautofd__BITNR 23
12179 #define R_PAR0_CONFIG__istrb__BITNR 22
12180 #define R_PAR0_CONFIG__iinit__BITNR 21
12181 #define R_PAR0_CONFIG__iperr__BITNR 20
12182 #define R_PAR0_CONFIG__iack__BITNR 19
12183 #define R_PAR0_CONFIG__ibusy__BITNR 18
12184 #define R_PAR0_CONFIG__ifault__BITNR 17
12185 #define R_PAR0_CONFIG__isel__BITNR 16
12186 #define R_PAR0_CONFIG__ext_mode__BITNR 11
12187 #define R_PAR0_CONFIG__wide__BITNR 10
12188 #define R_PAR0_CONFIG__dma__BITNR 9
12189 #define R_PAR0_CONFIG__rle_in__BITNR 8
12190 #define R_PAR0_CONFIG__rle_out__BITNR 7
12191 #define R_PAR0_CONFIG__enable__BITNR 6
12192 #define R_PAR0_CONFIG__force__BITNR 5
12193 #define R_PAR0_CONFIG__ign_ack__BITNR 4
12194 #define R_PAR0_CONFIG__oe_ack__BITNR 3
12195 #define R_PAR0_CONFIG__epp_addr_data__BITNR 3
12196 #define R_PAR0_CONFIG__mode__BITNR 0
12197
12198 #define R_PAR0_CONFIG__ioe__ioe__VAL REG_VAL_ENUM
12199 #define R_PAR0_CONFIG__iseli__iseli__VAL REG_VAL_ENUM
12200 #define R_PAR0_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM
12201 #define R_PAR0_CONFIG__istrb__istrb__VAL REG_VAL_ENUM
12202 #define R_PAR0_CONFIG__iinit__iinit__VAL REG_VAL_ENUM
12203 #define R_PAR0_CONFIG__iperr__iperr__VAL REG_VAL_ENUM
12204 #define R_PAR0_CONFIG__iack__iack__VAL REG_VAL_ENUM
12205 #define R_PAR0_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM
12206 #define R_PAR0_CONFIG__ifault__ifault__VAL REG_VAL_ENUM
12207 #define R_PAR0_CONFIG__isel__isel__VAL REG_VAL_ENUM
12208 #define R_PAR0_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM
12209 #define R_PAR0_CONFIG__wide__wide__VAL REG_VAL_ENUM
12210 #define R_PAR0_CONFIG__dma__dma__VAL REG_VAL_ENUM
12211 #define R_PAR0_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM
12212 #define R_PAR0_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM
12213 #define R_PAR0_CONFIG__enable__enable__VAL REG_VAL_ENUM
12214 #define R_PAR0_CONFIG__force__force__VAL REG_VAL_ENUM
12215 #define R_PAR0_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM
12216 #define R_PAR0_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM
12217 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM
12218 #define R_PAR0_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM
12219 #define R_PAR0_CONFIG__mode__mode__VAL REG_VAL_ENUM
12220
12221 #define R_PAR0_CONFIG__ioe__ioe__inv 1
12222 #define R_PAR0_CONFIG__ioe__ioe__noninv 0
12223 #define R_PAR0_CONFIG__iseli__iseli__inv 1
12224 #define R_PAR0_CONFIG__iseli__iseli__noninv 0
12225 #define R_PAR0_CONFIG__iautofd__iautofd__inv 1
12226 #define R_PAR0_CONFIG__iautofd__iautofd__noninv 0
12227 #define R_PAR0_CONFIG__istrb__istrb__inv 1
12228 #define R_PAR0_CONFIG__istrb__istrb__noninv 0
12229 #define R_PAR0_CONFIG__iinit__iinit__inv 1
12230 #define R_PAR0_CONFIG__iinit__iinit__noninv 0
12231 #define R_PAR0_CONFIG__iperr__iperr__inv 1
12232 #define R_PAR0_CONFIG__iperr__iperr__noninv 0
12233 #define R_PAR0_CONFIG__iack__iack__inv 1
12234 #define R_PAR0_CONFIG__iack__iack__noninv 0
12235 #define R_PAR0_CONFIG__ibusy__ibusy__inv 1
12236 #define R_PAR0_CONFIG__ibusy__ibusy__noninv 0
12237 #define R_PAR0_CONFIG__ifault__ifault__inv 1
12238 #define R_PAR0_CONFIG__ifault__ifault__noninv 0
12239 #define R_PAR0_CONFIG__isel__isel__inv 1
12240 #define R_PAR0_CONFIG__isel__isel__noninv 0
12241 #define R_PAR0_CONFIG__ext_mode__ext_mode__disable 0
12242 #define R_PAR0_CONFIG__ext_mode__ext_mode__enable 1
12243 #define R_PAR0_CONFIG__wide__wide__disable 0
12244 #define R_PAR0_CONFIG__wide__wide__enable 1
12245 #define R_PAR0_CONFIG__dma__dma__disable 0
12246 #define R_PAR0_CONFIG__dma__dma__enable 1
12247 #define R_PAR0_CONFIG__rle_in__rle_in__disable 0
12248 #define R_PAR0_CONFIG__rle_in__rle_in__enable 1
12249 #define R_PAR0_CONFIG__rle_out__rle_out__disable 0
12250 #define R_PAR0_CONFIG__rle_out__rle_out__enable 1
12251 #define R_PAR0_CONFIG__enable__enable__on 1
12252 #define R_PAR0_CONFIG__enable__enable__reset 0
12253 #define R_PAR0_CONFIG__force__force__off 0
12254 #define R_PAR0_CONFIG__force__force__on 1
12255 #define R_PAR0_CONFIG__ign_ack__ign_ack__ignore 1
12256 #define R_PAR0_CONFIG__ign_ack__ign_ack__wait 0
12257 #define R_PAR0_CONFIG__oe_ack__oe_ack__dont_wait 0
12258 #define R_PAR0_CONFIG__oe_ack__oe_ack__epp_addr 1
12259 #define R_PAR0_CONFIG__oe_ack__oe_ack__epp_data 0
12260 #define R_PAR0_CONFIG__oe_ack__oe_ack__wait_oe 1
12261 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0
12262 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1
12263 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_data 0
12264 #define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1
12265 #define R_PAR0_CONFIG__mode__mode__byte 4
12266 #define R_PAR0_CONFIG__mode__mode__centronics 1
12267 #define R_PAR0_CONFIG__mode__mode__ecp_fwd 5
12268 #define R_PAR0_CONFIG__mode__mode__ecp_rev 6
12269 #define R_PAR0_CONFIG__mode__mode__epp_rd 0
12270 #define R_PAR0_CONFIG__mode__mode__epp_wr1 5
12271 #define R_PAR0_CONFIG__mode__mode__epp_wr2 6
12272 #define R_PAR0_CONFIG__mode__mode__epp_wr3 7
12273 #define R_PAR0_CONFIG__mode__mode__fastbyte 2
12274 #define R_PAR0_CONFIG__mode__mode__manual 0
12275 #define R_PAR0_CONFIG__mode__mode__nibble 3
12276 #define R_PAR0_CONFIG__mode__mode__off 7
12277
12278 #endif
12279
12280 /*
12281 * R_PAR0_CTRL
12282 * - type: WO
12283 * - addr: 0xb0000042
12284 * - group: Parallel printer port registers
12285 */
12286
12287 #if USE_GROUP__Parallel_printer_port_registers
12288
12289 #define R_PAR0_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000042)
12290
12291 #ifndef REG_NO_SHADOW
12292 #define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2))
12293 #define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2))
12294 #else /* REG_NO_SHADOW */
12295 #define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
12296 #define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
12297 #endif /* REG_NO_SHADOW */
12298
12299 #define R_PAR0_CTRL__STYPECAST REG_STYPECAST_BYTE
12300 #define R_PAR0_CTRL__SVAL REG_SVAL_SHADOW
12301 #define R_PAR0_CTRL__SVAL_I REG_SVAL_I_SHADOW
12302 #define R_PAR0_CTRL__TYPECAST REG_TYPECAST_BYTE
12303 #define R_PAR0_CTRL__TYPE (REG_BYTE)
12304 #define R_PAR0_CTRL__GET REG_GET_WO
12305 #define R_PAR0_CTRL__IGET REG_IGET_WO
12306 #define R_PAR0_CTRL__SET REG_SET_WO
12307 #define R_PAR0_CTRL__ISET REG_ISET_WO
12308 #define R_PAR0_CTRL__SET_VAL REG_SET_VAL_WO
12309 #define R_PAR0_CTRL__EQL REG_EQL_WO
12310 #define R_PAR0_CTRL__IEQL REG_IEQL_WO
12311 #define R_PAR0_CTRL__RD REG_RD_WO
12312 #define R_PAR0_CTRL__IRD REG_IRD_WO
12313 #define R_PAR0_CTRL__WR REG_WR_WO
12314 #define R_PAR0_CTRL__IWR REG_IWR_WO
12315
12316 #define R_PAR0_CTRL__WRITE(addr,value) \
12317 (*(addr) = (value))
12318
12319 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
12320 #define R_PAR0_CTRL__FIRST 0
12321 #define R_PAR0_CTRL__IOFFSET 12
12322 #define R_PAR0_CTRL__LAST 1
12323 #define R_PAR0_CTRL__OFFSET 16
12324 #define R_PAR0_CTRL__SOFFSET 12
12325 /* end */
12326
12327 #define R_PAR0_CTRL__ctrl__ctrl__MASK 0x0000001fU
12328
12329 #define R_PAR0_CTRL__ctrl__MAX 31
12330
12331 #define R_PAR0_CTRL__ctrl__MIN 0
12332
12333 #define R_PAR0_CTRL__ctrl__BITNR 0
12334
12335 #define R_PAR0_CTRL__ctrl__ctrl__VAL REG_VAL_VAL
12336
12337
12338 #endif
12339
12340 /*
12341 * R_PAR0_CTRL_DATA
12342 * - type: WO
12343 * - addr: 0xb0000040
12344 * - group: Parallel printer port registers
12345 */
12346
12347 #if USE_GROUP__Parallel_printer_port_registers
12348
12349 #define R_PAR0_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
12350
12351 #ifndef REG_NO_SHADOW
12352 #define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
12353 #define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
12354 #else /* REG_NO_SHADOW */
12355 #define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
12356 #define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
12357 #endif /* REG_NO_SHADOW */
12358
12359 #define R_PAR0_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
12360 #define R_PAR0_CTRL_DATA__SVAL REG_SVAL_SHADOW
12361 #define R_PAR0_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
12362 #define R_PAR0_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
12363 #define R_PAR0_CTRL_DATA__TYPE (REG_UDWORD)
12364 #define R_PAR0_CTRL_DATA__GET REG_GET_WO
12365 #define R_PAR0_CTRL_DATA__IGET REG_IGET_WO
12366 #define R_PAR0_CTRL_DATA__SET REG_SET_WO
12367 #define R_PAR0_CTRL_DATA__ISET REG_ISET_WO
12368 #define R_PAR0_CTRL_DATA__SET_VAL REG_SET_VAL_WO
12369 #define R_PAR0_CTRL_DATA__EQL REG_EQL_WO
12370 #define R_PAR0_CTRL_DATA__IEQL REG_IEQL_WO
12371 #define R_PAR0_CTRL_DATA__RD REG_RD_WO
12372 #define R_PAR0_CTRL_DATA__IRD REG_IRD_WO
12373 #define R_PAR0_CTRL_DATA__WR REG_WR_WO
12374 #define R_PAR0_CTRL_DATA__IWR REG_IWR_WO
12375
12376 #define R_PAR0_CTRL_DATA__WRITE(addr,value) \
12377 (*(addr) = (value))
12378
12379 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
12380 #define R_PAR0_CTRL_DATA__FIRST 0
12381 #define R_PAR0_CTRL_DATA__IOFFSET 12
12382 #define R_PAR0_CTRL_DATA__LAST 1
12383 #define R_PAR0_CTRL_DATA__OFFSET 16
12384 #define R_PAR0_CTRL_DATA__SOFFSET 12
12385 /* end */
12386
12387 #define R_PAR0_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U
12388 #define R_PAR0_CTRL_DATA__oe__oe__MASK 0x00100000U
12389 #define R_PAR0_CTRL_DATA__seli__seli__MASK 0x00080000U
12390 #define R_PAR0_CTRL_DATA__autofd__autofd__MASK 0x00040000U
12391 #define R_PAR0_CTRL_DATA__strb__strb__MASK 0x00020000U
12392 #define R_PAR0_CTRL_DATA__init__init__MASK 0x00010000U
12393 #define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
12394 #define R_PAR0_CTRL_DATA__data__data__MASK 0x000000ffU
12395
12396 #define R_PAR0_CTRL_DATA__peri_int__MAX 0x1
12397 #define R_PAR0_CTRL_DATA__oe__MAX 0x1
12398 #define R_PAR0_CTRL_DATA__seli__MAX 0x1
12399 #define R_PAR0_CTRL_DATA__autofd__MAX 0x1
12400 #define R_PAR0_CTRL_DATA__strb__MAX 0x1
12401 #define R_PAR0_CTRL_DATA__init__MAX 0x1
12402 #define R_PAR0_CTRL_DATA__ecp_cmd__MAX 0x1
12403 #define R_PAR0_CTRL_DATA__data__MAX 0xff
12404
12405 #define R_PAR0_CTRL_DATA__peri_int__MIN 0
12406 #define R_PAR0_CTRL_DATA__oe__MIN 0
12407 #define R_PAR0_CTRL_DATA__seli__MIN 0
12408 #define R_PAR0_CTRL_DATA__autofd__MIN 0
12409 #define R_PAR0_CTRL_DATA__strb__MIN 0
12410 #define R_PAR0_CTRL_DATA__init__MIN 0
12411 #define R_PAR0_CTRL_DATA__ecp_cmd__MIN 0
12412 #define R_PAR0_CTRL_DATA__data__MIN 0
12413
12414 #define R_PAR0_CTRL_DATA__peri_int__BITNR 24
12415 #define R_PAR0_CTRL_DATA__oe__BITNR 20
12416 #define R_PAR0_CTRL_DATA__seli__BITNR 19
12417 #define R_PAR0_CTRL_DATA__autofd__BITNR 18
12418 #define R_PAR0_CTRL_DATA__strb__BITNR 17
12419 #define R_PAR0_CTRL_DATA__init__BITNR 16
12420 #define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
12421 #define R_PAR0_CTRL_DATA__data__BITNR 0
12422
12423 #define R_PAR0_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM
12424 #define R_PAR0_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM
12425 #define R_PAR0_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM
12426 #define R_PAR0_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM
12427 #define R_PAR0_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM
12428 #define R_PAR0_CTRL_DATA__init__init__VAL REG_VAL_ENUM
12429 #define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
12430 #define R_PAR0_CTRL_DATA__data__data__VAL REG_VAL_VAL
12431
12432 #define R_PAR0_CTRL_DATA__peri_int__peri_int__ack 1
12433 #define R_PAR0_CTRL_DATA__peri_int__peri_int__nop 0
12434 #define R_PAR0_CTRL_DATA__oe__oe__disable 0
12435 #define R_PAR0_CTRL_DATA__oe__oe__enable 1
12436 #define R_PAR0_CTRL_DATA__seli__seli__active 1
12437 #define R_PAR0_CTRL_DATA__seli__seli__inactive 0
12438 #define R_PAR0_CTRL_DATA__autofd__autofd__active 1
12439 #define R_PAR0_CTRL_DATA__autofd__autofd__inactive 0
12440 #define R_PAR0_CTRL_DATA__strb__strb__active 1
12441 #define R_PAR0_CTRL_DATA__strb__strb__inactive 0
12442 #define R_PAR0_CTRL_DATA__init__init__active 1
12443 #define R_PAR0_CTRL_DATA__init__init__inactive 0
12444 #define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__command 1
12445 #define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__data 0
12446
12447 #endif
12448
12449 /*
12450 * R_PAR0_DELAY
12451 * - type: WO
12452 * - addr: 0xb0000048
12453 * - group: Parallel printer port registers
12454 */
12455
12456 #if USE_GROUP__Parallel_printer_port_registers
12457
12458 #define R_PAR0_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
12459
12460 #ifndef REG_NO_SHADOW
12461 #define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR0_DELAY + 0))
12462 #define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR0_DELAY + 0))
12463 #else /* REG_NO_SHADOW */
12464 #define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
12465 #define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
12466 #endif /* REG_NO_SHADOW */
12467
12468 #define R_PAR0_DELAY__STYPECAST REG_STYPECAST_UDWORD
12469 #define R_PAR0_DELAY__SVAL REG_SVAL_SHADOW
12470 #define R_PAR0_DELAY__SVAL_I REG_SVAL_I_SHADOW
12471 #define R_PAR0_DELAY__TYPECAST REG_TYPECAST_UDWORD
12472 #define R_PAR0_DELAY__TYPE (REG_UDWORD)
12473 #define R_PAR0_DELAY__GET REG_GET_WO
12474 #define R_PAR0_DELAY__IGET REG_IGET_WO
12475 #define R_PAR0_DELAY__SET REG_SET_WO
12476 #define R_PAR0_DELAY__ISET REG_ISET_WO
12477 #define R_PAR0_DELAY__SET_VAL REG_SET_VAL_WO
12478 #define R_PAR0_DELAY__EQL REG_EQL_WO
12479 #define R_PAR0_DELAY__IEQL REG_IEQL_WO
12480 #define R_PAR0_DELAY__RD REG_RD_WO
12481 #define R_PAR0_DELAY__IRD REG_IRD_WO
12482 #define R_PAR0_DELAY__WR REG_WR_WO
12483 #define R_PAR0_DELAY__IWR REG_IWR_WO
12484
12485 #define R_PAR0_DELAY__WRITE(addr,value) \
12486 (*(addr) = (value))
12487
12488 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
12489 #define R_PAR0_DELAY__FIRST 0
12490 #define R_PAR0_DELAY__IOFFSET 12
12491 #define R_PAR0_DELAY__LAST 1
12492 #define R_PAR0_DELAY__OFFSET 16
12493 #define R_PAR0_DELAY__SOFFSET 12
12494 /* end */
12495
12496 #define R_PAR0_DELAY__fine_hold__fine_hold__MASK 0x00e00000U
12497 #define R_PAR0_DELAY__hold__hold__MASK 0x001f0000U
12498 #define R_PAR0_DELAY__fine_strb__fine_strb__MASK 0x0000e000U
12499 #define R_PAR0_DELAY__strobe__strobe__MASK 0x00001f00U
12500 #define R_PAR0_DELAY__fine_setup__fine_setup__MASK 0x000000e0U
12501 #define R_PAR0_DELAY__setup__setup__MASK 0x0000001fU
12502
12503 #define R_PAR0_DELAY__fine_hold__MAX 0x7
12504 #define R_PAR0_DELAY__hold__MAX 0x1f
12505 #define R_PAR0_DELAY__fine_strb__MAX 0x7
12506 #define R_PAR0_DELAY__strobe__MAX 0x1f
12507 #define R_PAR0_DELAY__fine_setup__MAX 0x7
12508 #define R_PAR0_DELAY__setup__MAX 0x1f
12509
12510 #define R_PAR0_DELAY__fine_hold__MIN 0
12511 #define R_PAR0_DELAY__hold__MIN 0
12512 #define R_PAR0_DELAY__fine_strb__MIN 0
12513 #define R_PAR0_DELAY__strobe__MIN 0
12514 #define R_PAR0_DELAY__fine_setup__MIN 0
12515 #define R_PAR0_DELAY__setup__MIN 0
12516
12517 #define R_PAR0_DELAY__fine_hold__BITNR 21
12518 #define R_PAR0_DELAY__hold__BITNR 16
12519 #define R_PAR0_DELAY__fine_strb__BITNR 13
12520 #define R_PAR0_DELAY__strobe__BITNR 8
12521 #define R_PAR0_DELAY__fine_setup__BITNR 5
12522 #define R_PAR0_DELAY__setup__BITNR 0
12523
12524 #define R_PAR0_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL
12525 #define R_PAR0_DELAY__hold__hold__VAL REG_VAL_VAL
12526 #define R_PAR0_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL
12527 #define R_PAR0_DELAY__strobe__strobe__VAL REG_VAL_VAL
12528 #define R_PAR0_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL
12529 #define R_PAR0_DELAY__setup__setup__VAL REG_VAL_VAL
12530
12531
12532 #endif
12533
12534 /*
12535 * R_PAR0_STATUS
12536 * - type: RO
12537 * - addr: 0xb0000042
12538 * - group: Parallel printer port registers
12539 */
12540
12541 #if USE_GROUP__Parallel_printer_port_registers
12542
12543 #define R_PAR0_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000042)
12544 #define R_PAR0_STATUS__SVAL REG_SVAL_SHADOW
12545 #define R_PAR0_STATUS__SVAL_I REG_SVAL_I_SHADOW
12546 #define R_PAR0_STATUS__TYPECAST REG_TYPECAST_UWORD
12547 #define R_PAR0_STATUS__TYPE (REG_UWORD)
12548 #define R_PAR0_STATUS__GET REG_GET_RO
12549 #define R_PAR0_STATUS__IGET REG_IGET_RO
12550 #define R_PAR0_STATUS__SET REG_SET_RO
12551 #define R_PAR0_STATUS__ISET REG_ISET_RO
12552 #define R_PAR0_STATUS__SET_VAL REG_SET_VAL_RO
12553 #define R_PAR0_STATUS__EQL REG_EQL_RO
12554 #define R_PAR0_STATUS__IEQL REG_IEQL_RO
12555 #define R_PAR0_STATUS__RD REG_RD_RO
12556 #define R_PAR0_STATUS__IRD REG_IRD_RO
12557 #define R_PAR0_STATUS__WR REG_WR_RO
12558 #define R_PAR0_STATUS__IWR REG_IWR_RO
12559
12560 #define R_PAR0_STATUS__READ(addr) \
12561 (*(addr))
12562
12563 #define R_PAR0_STATUS__mode__mode__MASK 0x0000e000U
12564 #define R_PAR0_STATUS__perr__perr__MASK 0x00001000U
12565 #define R_PAR0_STATUS__ack__ack__MASK 0x00000800U
12566 #define R_PAR0_STATUS__busy__busy__MASK 0x00000400U
12567 #define R_PAR0_STATUS__fault__fault__MASK 0x00000200U
12568 #define R_PAR0_STATUS__sel__sel__MASK 0x00000100U
12569 #define R_PAR0_STATUS__ext_mode__ext_mode__MASK 0x00000080U
12570 #define R_PAR0_STATUS__ecp_16__ecp_16__MASK 0x00000040U
12571 #define R_PAR0_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U
12572 #define R_PAR0_STATUS__dav__dav__MASK 0x00000001U
12573
12574 #define R_PAR0_STATUS__mode__MAX 0x7
12575 #define R_PAR0_STATUS__perr__MAX 0x1
12576 #define R_PAR0_STATUS__ack__MAX 0x1
12577 #define R_PAR0_STATUS__busy__MAX 0x1
12578 #define R_PAR0_STATUS__fault__MAX 0x1
12579 #define R_PAR0_STATUS__sel__MAX 0x1
12580 #define R_PAR0_STATUS__ext_mode__MAX 0x1
12581 #define R_PAR0_STATUS__ecp_16__MAX 0x1
12582 #define R_PAR0_STATUS__tr_rdy__MAX 0x1
12583 #define R_PAR0_STATUS__dav__MAX 0x1
12584
12585 #define R_PAR0_STATUS__mode__MIN 0
12586 #define R_PAR0_STATUS__perr__MIN 0
12587 #define R_PAR0_STATUS__ack__MIN 0
12588 #define R_PAR0_STATUS__busy__MIN 0
12589 #define R_PAR0_STATUS__fault__MIN 0
12590 #define R_PAR0_STATUS__sel__MIN 0
12591 #define R_PAR0_STATUS__ext_mode__MIN 0
12592 #define R_PAR0_STATUS__ecp_16__MIN 0
12593 #define R_PAR0_STATUS__tr_rdy__MIN 0
12594 #define R_PAR0_STATUS__dav__MIN 0
12595
12596 #define R_PAR0_STATUS__mode__BITNR 13
12597 #define R_PAR0_STATUS__perr__BITNR 12
12598 #define R_PAR0_STATUS__ack__BITNR 11
12599 #define R_PAR0_STATUS__busy__BITNR 10
12600 #define R_PAR0_STATUS__fault__BITNR 9
12601 #define R_PAR0_STATUS__sel__BITNR 8
12602 #define R_PAR0_STATUS__ext_mode__BITNR 7
12603 #define R_PAR0_STATUS__ecp_16__BITNR 6
12604 #define R_PAR0_STATUS__tr_rdy__BITNR 1
12605 #define R_PAR0_STATUS__dav__BITNR 0
12606
12607 #define R_PAR0_STATUS__mode__mode__VAL REG_VAL_ENUM
12608 #define R_PAR0_STATUS__perr__perr__VAL REG_VAL_ENUM
12609 #define R_PAR0_STATUS__ack__ack__VAL REG_VAL_ENUM
12610 #define R_PAR0_STATUS__busy__busy__VAL REG_VAL_ENUM
12611 #define R_PAR0_STATUS__fault__fault__VAL REG_VAL_ENUM
12612 #define R_PAR0_STATUS__sel__sel__VAL REG_VAL_ENUM
12613 #define R_PAR0_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM
12614 #define R_PAR0_STATUS__ecp_16__ecp_16__VAL REG_VAL_ENUM
12615 #define R_PAR0_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
12616 #define R_PAR0_STATUS__dav__dav__VAL REG_VAL_ENUM
12617
12618 #define R_PAR0_STATUS__mode__mode__byte 4
12619 #define R_PAR0_STATUS__mode__mode__centronics 1
12620 #define R_PAR0_STATUS__mode__mode__ecp_fwd 5
12621 #define R_PAR0_STATUS__mode__mode__ecp_rev 6
12622 #define R_PAR0_STATUS__mode__mode__epp_rd 0
12623 #define R_PAR0_STATUS__mode__mode__epp_wr1 5
12624 #define R_PAR0_STATUS__mode__mode__epp_wr2 6
12625 #define R_PAR0_STATUS__mode__mode__epp_wr3 7
12626 #define R_PAR0_STATUS__mode__mode__fastbyte 2
12627 #define R_PAR0_STATUS__mode__mode__manual 0
12628 #define R_PAR0_STATUS__mode__mode__nibble 3
12629 #define R_PAR0_STATUS__mode__mode__off 7
12630 #define R_PAR0_STATUS__perr__perr__active 1
12631 #define R_PAR0_STATUS__perr__perr__inactive 0
12632 #define R_PAR0_STATUS__ack__ack__active 0
12633 #define R_PAR0_STATUS__ack__ack__inactive 1
12634 #define R_PAR0_STATUS__busy__busy__active 1
12635 #define R_PAR0_STATUS__busy__busy__inactive 0
12636 #define R_PAR0_STATUS__fault__fault__active 0
12637 #define R_PAR0_STATUS__fault__fault__inactive 1
12638 #define R_PAR0_STATUS__sel__sel__active 1
12639 #define R_PAR0_STATUS__sel__sel__inactive 0
12640 #define R_PAR0_STATUS__ext_mode__ext_mode__disable 0
12641 #define R_PAR0_STATUS__ext_mode__ext_mode__enable 1
12642 #define R_PAR0_STATUS__ecp_16__ecp_16__active 1
12643 #define R_PAR0_STATUS__ecp_16__ecp_16__inactive 0
12644 #define R_PAR0_STATUS__tr_rdy__tr_rdy__busy 0
12645 #define R_PAR0_STATUS__tr_rdy__tr_rdy__ready 1
12646 #define R_PAR0_STATUS__dav__dav__data 1
12647 #define R_PAR0_STATUS__dav__dav__nodata 0
12648
12649 #endif
12650
12651 /*
12652 * R_PAR0_STATUS_DATA
12653 * - type: RO
12654 * - addr: 0xb0000040
12655 * - group: Parallel printer port registers
12656 */
12657
12658 #if USE_GROUP__Parallel_printer_port_registers
12659
12660 #define R_PAR0_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
12661 #define R_PAR0_STATUS_DATA__SVAL REG_SVAL_SHADOW
12662 #define R_PAR0_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
12663 #define R_PAR0_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
12664 #define R_PAR0_STATUS_DATA__TYPE (REG_UDWORD)
12665 #define R_PAR0_STATUS_DATA__GET REG_GET_RO
12666 #define R_PAR0_STATUS_DATA__IGET REG_IGET_RO
12667 #define R_PAR0_STATUS_DATA__SET REG_SET_RO
12668 #define R_PAR0_STATUS_DATA__ISET REG_ISET_RO
12669 #define R_PAR0_STATUS_DATA__SET_VAL REG_SET_VAL_RO
12670 #define R_PAR0_STATUS_DATA__EQL REG_EQL_RO
12671 #define R_PAR0_STATUS_DATA__IEQL REG_IEQL_RO
12672 #define R_PAR0_STATUS_DATA__RD REG_RD_RO
12673 #define R_PAR0_STATUS_DATA__IRD REG_IRD_RO
12674 #define R_PAR0_STATUS_DATA__WR REG_WR_RO
12675 #define R_PAR0_STATUS_DATA__IWR REG_IWR_RO
12676
12677 #define R_PAR0_STATUS_DATA__READ(addr) \
12678 (*(addr))
12679
12680 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
12681 #define R_PAR0_STATUS_DATA__FIRST 0
12682 #define R_PAR0_STATUS_DATA__LAST 1
12683 #define R_PAR0_STATUS_DATA__OFFSET 16
12684 /* end */
12685
12686 #define R_PAR0_STATUS_DATA__mode__mode__MASK 0xe0000000U
12687 #define R_PAR0_STATUS_DATA__perr__perr__MASK 0x10000000U
12688 #define R_PAR0_STATUS_DATA__ack__ack__MASK 0x08000000U
12689 #define R_PAR0_STATUS_DATA__busy__busy__MASK 0x04000000U
12690 #define R_PAR0_STATUS_DATA__fault__fault__MASK 0x02000000U
12691 #define R_PAR0_STATUS_DATA__sel__sel__MASK 0x01000000U
12692 #define R_PAR0_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U
12693 #define R_PAR0_STATUS_DATA__ecp_16__ecp_16__MASK 0x00400000U
12694 #define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
12695 #define R_PAR0_STATUS_DATA__dav__dav__MASK 0x00010000U
12696 #define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
12697 #define R_PAR0_STATUS_DATA__data__data__MASK 0x000000ffU
12698
12699 #define R_PAR0_STATUS_DATA__mode__MAX 0x7
12700 #define R_PAR0_STATUS_DATA__perr__MAX 0x1
12701 #define R_PAR0_STATUS_DATA__ack__MAX 0x1
12702 #define R_PAR0_STATUS_DATA__busy__MAX 0x1
12703 #define R_PAR0_STATUS_DATA__fault__MAX 0x1
12704 #define R_PAR0_STATUS_DATA__sel__MAX 0x1
12705 #define R_PAR0_STATUS_DATA__ext_mode__MAX 0x1
12706 #define R_PAR0_STATUS_DATA__ecp_16__MAX 0x1
12707 #define R_PAR0_STATUS_DATA__tr_rdy__MAX 0x1
12708 #define R_PAR0_STATUS_DATA__dav__MAX 0x1
12709 #define R_PAR0_STATUS_DATA__ecp_cmd__MAX 0x1
12710 #define R_PAR0_STATUS_DATA__data__MAX 0xff
12711
12712 #define R_PAR0_STATUS_DATA__mode__MIN 0
12713 #define R_PAR0_STATUS_DATA__perr__MIN 0
12714 #define R_PAR0_STATUS_DATA__ack__MIN 0
12715 #define R_PAR0_STATUS_DATA__busy__MIN 0
12716 #define R_PAR0_STATUS_DATA__fault__MIN 0
12717 #define R_PAR0_STATUS_DATA__sel__MIN 0
12718 #define R_PAR0_STATUS_DATA__ext_mode__MIN 0
12719 #define R_PAR0_STATUS_DATA__ecp_16__MIN 0
12720 #define R_PAR0_STATUS_DATA__tr_rdy__MIN 0
12721 #define R_PAR0_STATUS_DATA__dav__MIN 0
12722 #define R_PAR0_STATUS_DATA__ecp_cmd__MIN 0
12723 #define R_PAR0_STATUS_DATA__data__MIN 0
12724
12725 #define R_PAR0_STATUS_DATA__mode__BITNR 29
12726 #define R_PAR0_STATUS_DATA__perr__BITNR 28
12727 #define R_PAR0_STATUS_DATA__ack__BITNR 27
12728 #define R_PAR0_STATUS_DATA__busy__BITNR 26
12729 #define R_PAR0_STATUS_DATA__fault__BITNR 25
12730 #define R_PAR0_STATUS_DATA__sel__BITNR 24
12731 #define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
12732 #define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
12733 #define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
12734 #define R_PAR0_STATUS_DATA__dav__BITNR 16
12735 #define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
12736 #define R_PAR0_STATUS_DATA__data__BITNR 0
12737
12738 #define R_PAR0_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM
12739 #define R_PAR0_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM
12740 #define R_PAR0_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM
12741 #define R_PAR0_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
12742 #define R_PAR0_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM
12743 #define R_PAR0_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM
12744 #define R_PAR0_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM
12745 #define R_PAR0_STATUS_DATA__ecp_16__ecp_16__VAL REG_VAL_ENUM
12746 #define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
12747 #define R_PAR0_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
12748 #define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
12749 #define R_PAR0_STATUS_DATA__data__data__VAL REG_VAL_VAL
12750
12751 #define R_PAR0_STATUS_DATA__mode__mode__byte 4
12752 #define R_PAR0_STATUS_DATA__mode__mode__centronics 1
12753 #define R_PAR0_STATUS_DATA__mode__mode__ecp_fwd 5
12754 #define R_PAR0_STATUS_DATA__mode__mode__ecp_rev 6
12755 #define R_PAR0_STATUS_DATA__mode__mode__epp_rd 0
12756 #define R_PAR0_STATUS_DATA__mode__mode__epp_wr1 5
12757 #define R_PAR0_STATUS_DATA__mode__mode__epp_wr2 6
12758 #define R_PAR0_STATUS_DATA__mode__mode__epp_wr3 7
12759 #define R_PAR0_STATUS_DATA__mode__mode__fastbyte 2
12760 #define R_PAR0_STATUS_DATA__mode__mode__manual 0
12761 #define R_PAR0_STATUS_DATA__mode__mode__nibble 3
12762 #define R_PAR0_STATUS_DATA__mode__mode__off 7
12763 #define R_PAR0_STATUS_DATA__perr__perr__active 1
12764 #define R_PAR0_STATUS_DATA__perr__perr__inactive 0
12765 #define R_PAR0_STATUS_DATA__ack__ack__active 0
12766 #define R_PAR0_STATUS_DATA__ack__ack__inactive 1
12767 #define R_PAR0_STATUS_DATA__busy__busy__active 1
12768 #define R_PAR0_STATUS_DATA__busy__busy__inactive 0
12769 #define R_PAR0_STATUS_DATA__fault__fault__active 0
12770 #define R_PAR0_STATUS_DATA__fault__fault__inactive 1
12771 #define R_PAR0_STATUS_DATA__sel__sel__active 1
12772 #define R_PAR0_STATUS_DATA__sel__sel__inactive 0
12773 #define R_PAR0_STATUS_DATA__ext_mode__ext_mode__disable 0
12774 #define R_PAR0_STATUS_DATA__ext_mode__ext_mode__enable 1
12775 #define R_PAR0_STATUS_DATA__ecp_16__ecp_16__active 1
12776 #define R_PAR0_STATUS_DATA__ecp_16__ecp_16__inactive 0
12777 #define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__busy 0
12778 #define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__ready 1
12779 #define R_PAR0_STATUS_DATA__dav__dav__data 1
12780 #define R_PAR0_STATUS_DATA__dav__dav__nodata 0
12781 #define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__command 1
12782 #define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__data 0
12783
12784 #endif
12785
12786 /*
12787 * R_PAR1_CONFIG
12788 * - type: WO
12789 * - addr: 0xb0000054
12790 * - group: Parallel printer port registers
12791 */
12792
12793 #if USE_GROUP__Parallel_printer_port_registers
12794
12795 #define R_PAR1_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000054)
12796
12797 #ifndef REG_NO_SHADOW
12798 #define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0))
12799 #define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0))
12800 #else /* REG_NO_SHADOW */
12801 #define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
12802 #define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
12803 #endif /* REG_NO_SHADOW */
12804
12805 #define R_PAR1_CONFIG__STYPECAST REG_STYPECAST_UDWORD
12806 #define R_PAR1_CONFIG__SVAL REG_SVAL_SHADOW
12807 #define R_PAR1_CONFIG__SVAL_I REG_SVAL_I_SHADOW
12808 #define R_PAR1_CONFIG__TYPECAST REG_TYPECAST_UDWORD
12809 #define R_PAR1_CONFIG__TYPE (REG_UDWORD)
12810 #define R_PAR1_CONFIG__GET REG_GET_WO
12811 #define R_PAR1_CONFIG__IGET REG_IGET_WO
12812 #define R_PAR1_CONFIG__SET REG_SET_WO
12813 #define R_PAR1_CONFIG__ISET REG_ISET_WO
12814 #define R_PAR1_CONFIG__SET_VAL REG_SET_VAL_WO
12815 #define R_PAR1_CONFIG__EQL REG_EQL_WO
12816 #define R_PAR1_CONFIG__IEQL REG_IEQL_WO
12817 #define R_PAR1_CONFIG__RD REG_RD_WO
12818 #define R_PAR1_CONFIG__IRD REG_IRD_WO
12819 #define R_PAR1_CONFIG__WR REG_WR_WO
12820 #define R_PAR1_CONFIG__IWR REG_IWR_WO
12821
12822 #define R_PAR1_CONFIG__WRITE(addr,value) \
12823 (*(addr) = (value))
12824
12825 #define R_PAR1_CONFIG__ioe__ioe__MASK 0x02000000U
12826 #define R_PAR1_CONFIG__iseli__iseli__MASK 0x01000000U
12827 #define R_PAR1_CONFIG__iautofd__iautofd__MASK 0x00800000U
12828 #define R_PAR1_CONFIG__istrb__istrb__MASK 0x00400000U
12829 #define R_PAR1_CONFIG__iinit__iinit__MASK 0x00200000U
12830 #define R_PAR1_CONFIG__iperr__iperr__MASK 0x00100000U
12831 #define R_PAR1_CONFIG__iack__iack__MASK 0x00080000U
12832 #define R_PAR1_CONFIG__ibusy__ibusy__MASK 0x00040000U
12833 #define R_PAR1_CONFIG__ifault__ifault__MASK 0x00020000U
12834 #define R_PAR1_CONFIG__isel__isel__MASK 0x00010000U
12835 #define R_PAR1_CONFIG__ext_mode__ext_mode__MASK 0x00000800U
12836 #define R_PAR1_CONFIG__dma__dma__MASK 0x00000200U
12837 #define R_PAR1_CONFIG__rle_in__rle_in__MASK 0x00000100U
12838 #define R_PAR1_CONFIG__rle_out__rle_out__MASK 0x00000080U
12839 #define R_PAR1_CONFIG__enable__enable__MASK 0x00000040U
12840 #define R_PAR1_CONFIG__force__force__MASK 0x00000020U
12841 #define R_PAR1_CONFIG__ign_ack__ign_ack__MASK 0x00000010U
12842 #define R_PAR1_CONFIG__oe_ack__oe_ack__MASK 0x00000008U
12843 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U
12844 #define R_PAR1_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U
12845 #define R_PAR1_CONFIG__mode__mode__MASK 0x00000007U
12846
12847 #define R_PAR1_CONFIG__ioe__MAX 0x1
12848 #define R_PAR1_CONFIG__iseli__MAX 0x1
12849 #define R_PAR1_CONFIG__iautofd__MAX 0x1
12850 #define R_PAR1_CONFIG__istrb__MAX 0x1
12851 #define R_PAR1_CONFIG__iinit__MAX 0x1
12852 #define R_PAR1_CONFIG__iperr__MAX 0x1
12853 #define R_PAR1_CONFIG__iack__MAX 0x1
12854 #define R_PAR1_CONFIG__ibusy__MAX 0x1
12855 #define R_PAR1_CONFIG__ifault__MAX 0x1
12856 #define R_PAR1_CONFIG__isel__MAX 0x1
12857 #define R_PAR1_CONFIG__ext_mode__MAX 0x1
12858 #define R_PAR1_CONFIG__dma__MAX 0x1
12859 #define R_PAR1_CONFIG__rle_in__MAX 0x1
12860 #define R_PAR1_CONFIG__rle_out__MAX 0x1
12861 #define R_PAR1_CONFIG__enable__MAX 0x1
12862 #define R_PAR1_CONFIG__force__MAX 0x1
12863 #define R_PAR1_CONFIG__ign_ack__MAX 0x1
12864 #define R_PAR1_CONFIG__oe_ack__MAX 0x1
12865 #define R_PAR1_CONFIG__epp_addr_data__MAX 0x1
12866 #define R_PAR1_CONFIG__mode__MAX 0x7
12867
12868 #define R_PAR1_CONFIG__ioe__MIN 0
12869 #define R_PAR1_CONFIG__iseli__MIN 0
12870 #define R_PAR1_CONFIG__iautofd__MIN 0
12871 #define R_PAR1_CONFIG__istrb__MIN 0
12872 #define R_PAR1_CONFIG__iinit__MIN 0
12873 #define R_PAR1_CONFIG__iperr__MIN 0
12874 #define R_PAR1_CONFIG__iack__MIN 0
12875 #define R_PAR1_CONFIG__ibusy__MIN 0
12876 #define R_PAR1_CONFIG__ifault__MIN 0
12877 #define R_PAR1_CONFIG__isel__MIN 0
12878 #define R_PAR1_CONFIG__ext_mode__MIN 0
12879 #define R_PAR1_CONFIG__dma__MIN 0
12880 #define R_PAR1_CONFIG__rle_in__MIN 0
12881 #define R_PAR1_CONFIG__rle_out__MIN 0
12882 #define R_PAR1_CONFIG__enable__MIN 0
12883 #define R_PAR1_CONFIG__force__MIN 0
12884 #define R_PAR1_CONFIG__ign_ack__MIN 0
12885 #define R_PAR1_CONFIG__oe_ack__MIN 0
12886 #define R_PAR1_CONFIG__epp_addr_data__MIN 0
12887 #define R_PAR1_CONFIG__mode__MIN 0
12888
12889 #define R_PAR1_CONFIG__ioe__BITNR 25
12890 #define R_PAR1_CONFIG__iseli__BITNR 24
12891 #define R_PAR1_CONFIG__iautofd__BITNR 23
12892 #define R_PAR1_CONFIG__istrb__BITNR 22
12893 #define R_PAR1_CONFIG__iinit__BITNR 21
12894 #define R_PAR1_CONFIG__iperr__BITNR 20
12895 #define R_PAR1_CONFIG__iack__BITNR 19
12896 #define R_PAR1_CONFIG__ibusy__BITNR 18
12897 #define R_PAR1_CONFIG__ifault__BITNR 17
12898 #define R_PAR1_CONFIG__isel__BITNR 16
12899 #define R_PAR1_CONFIG__ext_mode__BITNR 11
12900 #define R_PAR1_CONFIG__dma__BITNR 9
12901 #define R_PAR1_CONFIG__rle_in__BITNR 8
12902 #define R_PAR1_CONFIG__rle_out__BITNR 7
12903 #define R_PAR1_CONFIG__enable__BITNR 6
12904 #define R_PAR1_CONFIG__force__BITNR 5
12905 #define R_PAR1_CONFIG__ign_ack__BITNR 4
12906 #define R_PAR1_CONFIG__oe_ack__BITNR 3
12907 #define R_PAR1_CONFIG__epp_addr_data__BITNR 3
12908 #define R_PAR1_CONFIG__mode__BITNR 0
12909
12910 #define R_PAR1_CONFIG__ioe__ioe__VAL REG_VAL_ENUM
12911 #define R_PAR1_CONFIG__iseli__iseli__VAL REG_VAL_ENUM
12912 #define R_PAR1_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM
12913 #define R_PAR1_CONFIG__istrb__istrb__VAL REG_VAL_ENUM
12914 #define R_PAR1_CONFIG__iinit__iinit__VAL REG_VAL_ENUM
12915 #define R_PAR1_CONFIG__iperr__iperr__VAL REG_VAL_ENUM
12916 #define R_PAR1_CONFIG__iack__iack__VAL REG_VAL_ENUM
12917 #define R_PAR1_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM
12918 #define R_PAR1_CONFIG__ifault__ifault__VAL REG_VAL_ENUM
12919 #define R_PAR1_CONFIG__isel__isel__VAL REG_VAL_ENUM
12920 #define R_PAR1_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM
12921 #define R_PAR1_CONFIG__dma__dma__VAL REG_VAL_ENUM
12922 #define R_PAR1_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM
12923 #define R_PAR1_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM
12924 #define R_PAR1_CONFIG__enable__enable__VAL REG_VAL_ENUM
12925 #define R_PAR1_CONFIG__force__force__VAL REG_VAL_ENUM
12926 #define R_PAR1_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM
12927 #define R_PAR1_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM
12928 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM
12929 #define R_PAR1_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM
12930 #define R_PAR1_CONFIG__mode__mode__VAL REG_VAL_ENUM
12931
12932 #define R_PAR1_CONFIG__ioe__ioe__inv 1
12933 #define R_PAR1_CONFIG__ioe__ioe__noninv 0
12934 #define R_PAR1_CONFIG__iseli__iseli__inv 1
12935 #define R_PAR1_CONFIG__iseli__iseli__noninv 0
12936 #define R_PAR1_CONFIG__iautofd__iautofd__inv 1
12937 #define R_PAR1_CONFIG__iautofd__iautofd__noninv 0
12938 #define R_PAR1_CONFIG__istrb__istrb__inv 1
12939 #define R_PAR1_CONFIG__istrb__istrb__noninv 0
12940 #define R_PAR1_CONFIG__iinit__iinit__inv 1
12941 #define R_PAR1_CONFIG__iinit__iinit__noninv 0
12942 #define R_PAR1_CONFIG__iperr__iperr__inv 1
12943 #define R_PAR1_CONFIG__iperr__iperr__noninv 0
12944 #define R_PAR1_CONFIG__iack__iack__inv 1
12945 #define R_PAR1_CONFIG__iack__iack__noninv 0
12946 #define R_PAR1_CONFIG__ibusy__ibusy__inv 1
12947 #define R_PAR1_CONFIG__ibusy__ibusy__noninv 0
12948 #define R_PAR1_CONFIG__ifault__ifault__inv 1
12949 #define R_PAR1_CONFIG__ifault__ifault__noninv 0
12950 #define R_PAR1_CONFIG__isel__isel__inv 1
12951 #define R_PAR1_CONFIG__isel__isel__noninv 0
12952 #define R_PAR1_CONFIG__ext_mode__ext_mode__disable 0
12953 #define R_PAR1_CONFIG__ext_mode__ext_mode__enable 1
12954 #define R_PAR1_CONFIG__dma__dma__disable 0
12955 #define R_PAR1_CONFIG__dma__dma__enable 1
12956 #define R_PAR1_CONFIG__rle_in__rle_in__disable 0
12957 #define R_PAR1_CONFIG__rle_in__rle_in__enable 1
12958 #define R_PAR1_CONFIG__rle_out__rle_out__disable 0
12959 #define R_PAR1_CONFIG__rle_out__rle_out__enable 1
12960 #define R_PAR1_CONFIG__enable__enable__on 1
12961 #define R_PAR1_CONFIG__enable__enable__reset 0
12962 #define R_PAR1_CONFIG__force__force__off 0
12963 #define R_PAR1_CONFIG__force__force__on 1
12964 #define R_PAR1_CONFIG__ign_ack__ign_ack__ignore 1
12965 #define R_PAR1_CONFIG__ign_ack__ign_ack__wait 0
12966 #define R_PAR1_CONFIG__oe_ack__oe_ack__dont_wait 0
12967 #define R_PAR1_CONFIG__oe_ack__oe_ack__epp_addr 1
12968 #define R_PAR1_CONFIG__oe_ack__oe_ack__epp_data 0
12969 #define R_PAR1_CONFIG__oe_ack__oe_ack__wait_oe 1
12970 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0
12971 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1
12972 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_data 0
12973 #define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1
12974 #define R_PAR1_CONFIG__mode__mode__byte 4
12975 #define R_PAR1_CONFIG__mode__mode__centronics 1
12976 #define R_PAR1_CONFIG__mode__mode__ecp_fwd 5
12977 #define R_PAR1_CONFIG__mode__mode__ecp_rev 6
12978 #define R_PAR1_CONFIG__mode__mode__epp_rd 0
12979 #define R_PAR1_CONFIG__mode__mode__epp_wr1 5
12980 #define R_PAR1_CONFIG__mode__mode__epp_wr2 6
12981 #define R_PAR1_CONFIG__mode__mode__epp_wr3 7
12982 #define R_PAR1_CONFIG__mode__mode__fastbyte 2
12983 #define R_PAR1_CONFIG__mode__mode__manual 0
12984 #define R_PAR1_CONFIG__mode__mode__nibble 3
12985 #define R_PAR1_CONFIG__mode__mode__off 7
12986
12987 #endif
12988
12989 /*
12990 * R_PAR1_CTRL
12991 * - type: WO
12992 * - addr: 0xb0000052
12993 * - group: Parallel printer port registers
12994 */
12995
12996 #if USE_GROUP__Parallel_printer_port_registers
12997
12998 #define R_PAR1_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000052)
12999
13000 #ifndef REG_NO_SHADOW
13001 #define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
13002 #define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
13003 #else /* REG_NO_SHADOW */
13004 #define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
13005 #define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
13006 #endif /* REG_NO_SHADOW */
13007
13008 #define R_PAR1_CTRL__STYPECAST REG_STYPECAST_BYTE
13009 #define R_PAR1_CTRL__SVAL REG_SVAL_SHADOW
13010 #define R_PAR1_CTRL__SVAL_I REG_SVAL_I_SHADOW
13011 #define R_PAR1_CTRL__TYPECAST REG_TYPECAST_BYTE
13012 #define R_PAR1_CTRL__TYPE (REG_BYTE)
13013 #define R_PAR1_CTRL__GET REG_GET_WO
13014 #define R_PAR1_CTRL__IGET REG_IGET_WO
13015 #define R_PAR1_CTRL__SET REG_SET_WO
13016 #define R_PAR1_CTRL__ISET REG_ISET_WO
13017 #define R_PAR1_CTRL__SET_VAL REG_SET_VAL_WO
13018 #define R_PAR1_CTRL__EQL REG_EQL_WO
13019 #define R_PAR1_CTRL__IEQL REG_IEQL_WO
13020 #define R_PAR1_CTRL__RD REG_RD_WO
13021 #define R_PAR1_CTRL__IRD REG_IRD_WO
13022 #define R_PAR1_CTRL__WR REG_WR_WO
13023 #define R_PAR1_CTRL__IWR REG_IWR_WO
13024
13025 #define R_PAR1_CTRL__WRITE(addr,value) \
13026 (*(addr) = (value))
13027
13028 #define R_PAR1_CTRL__ctrl__ctrl__MASK 0x0000001fU
13029
13030 #define R_PAR1_CTRL__ctrl__MAX 31
13031
13032 #define R_PAR1_CTRL__ctrl__MIN 0
13033
13034 #define R_PAR1_CTRL__ctrl__BITNR 0
13035
13036 #define R_PAR1_CTRL__ctrl__ctrl__VAL REG_VAL_VAL
13037
13038
13039 #endif
13040
13041 /*
13042 * R_PAR1_CTRL_DATA
13043 * - type: WO
13044 * - addr: 0xb0000050
13045 * - group: Parallel printer port registers
13046 */
13047
13048 #if USE_GROUP__Parallel_printer_port_registers
13049
13050 #define R_PAR1_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
13051
13052 #ifndef REG_NO_SHADOW
13053 #define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
13054 #define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
13055 #else /* REG_NO_SHADOW */
13056 #define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
13057 #define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
13058 #endif /* REG_NO_SHADOW */
13059
13060 #define R_PAR1_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
13061 #define R_PAR1_CTRL_DATA__SVAL REG_SVAL_SHADOW
13062 #define R_PAR1_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
13063 #define R_PAR1_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
13064 #define R_PAR1_CTRL_DATA__TYPE (REG_UDWORD)
13065 #define R_PAR1_CTRL_DATA__GET REG_GET_WO
13066 #define R_PAR1_CTRL_DATA__IGET REG_IGET_WO
13067 #define R_PAR1_CTRL_DATA__SET REG_SET_WO
13068 #define R_PAR1_CTRL_DATA__ISET REG_ISET_WO
13069 #define R_PAR1_CTRL_DATA__SET_VAL REG_SET_VAL_WO
13070 #define R_PAR1_CTRL_DATA__EQL REG_EQL_WO
13071 #define R_PAR1_CTRL_DATA__IEQL REG_IEQL_WO
13072 #define R_PAR1_CTRL_DATA__RD REG_RD_WO
13073 #define R_PAR1_CTRL_DATA__IRD REG_IRD_WO
13074 #define R_PAR1_CTRL_DATA__WR REG_WR_WO
13075 #define R_PAR1_CTRL_DATA__IWR REG_IWR_WO
13076
13077 #define R_PAR1_CTRL_DATA__WRITE(addr,value) \
13078 (*(addr) = (value))
13079
13080 #define R_PAR1_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U
13081 #define R_PAR1_CTRL_DATA__oe__oe__MASK 0x00100000U
13082 #define R_PAR1_CTRL_DATA__seli__seli__MASK 0x00080000U
13083 #define R_PAR1_CTRL_DATA__autofd__autofd__MASK 0x00040000U
13084 #define R_PAR1_CTRL_DATA__strb__strb__MASK 0x00020000U
13085 #define R_PAR1_CTRL_DATA__init__init__MASK 0x00010000U
13086 #define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
13087 #define R_PAR1_CTRL_DATA__data__data__MASK 0x000000ffU
13088
13089 #define R_PAR1_CTRL_DATA__peri_int__MAX 0x1
13090 #define R_PAR1_CTRL_DATA__oe__MAX 0x1
13091 #define R_PAR1_CTRL_DATA__seli__MAX 0x1
13092 #define R_PAR1_CTRL_DATA__autofd__MAX 0x1
13093 #define R_PAR1_CTRL_DATA__strb__MAX 0x1
13094 #define R_PAR1_CTRL_DATA__init__MAX 0x1
13095 #define R_PAR1_CTRL_DATA__ecp_cmd__MAX 0x1
13096 #define R_PAR1_CTRL_DATA__data__MAX 0xff
13097
13098 #define R_PAR1_CTRL_DATA__peri_int__MIN 0
13099 #define R_PAR1_CTRL_DATA__oe__MIN 0
13100 #define R_PAR1_CTRL_DATA__seli__MIN 0
13101 #define R_PAR1_CTRL_DATA__autofd__MIN 0
13102 #define R_PAR1_CTRL_DATA__strb__MIN 0
13103 #define R_PAR1_CTRL_DATA__init__MIN 0
13104 #define R_PAR1_CTRL_DATA__ecp_cmd__MIN 0
13105 #define R_PAR1_CTRL_DATA__data__MIN 0
13106
13107 #define R_PAR1_CTRL_DATA__peri_int__BITNR 24
13108 #define R_PAR1_CTRL_DATA__oe__BITNR 20
13109 #define R_PAR1_CTRL_DATA__seli__BITNR 19
13110 #define R_PAR1_CTRL_DATA__autofd__BITNR 18
13111 #define R_PAR1_CTRL_DATA__strb__BITNR 17
13112 #define R_PAR1_CTRL_DATA__init__BITNR 16
13113 #define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
13114 #define R_PAR1_CTRL_DATA__data__BITNR 0
13115
13116 #define R_PAR1_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM
13117 #define R_PAR1_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM
13118 #define R_PAR1_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM
13119 #define R_PAR1_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM
13120 #define R_PAR1_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM
13121 #define R_PAR1_CTRL_DATA__init__init__VAL REG_VAL_ENUM
13122 #define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
13123 #define R_PAR1_CTRL_DATA__data__data__VAL REG_VAL_VAL
13124
13125 #define R_PAR1_CTRL_DATA__peri_int__peri_int__ack 1
13126 #define R_PAR1_CTRL_DATA__peri_int__peri_int__nop 0
13127 #define R_PAR1_CTRL_DATA__oe__oe__disable 0
13128 #define R_PAR1_CTRL_DATA__oe__oe__enable 1
13129 #define R_PAR1_CTRL_DATA__seli__seli__active 1
13130 #define R_PAR1_CTRL_DATA__seli__seli__inactive 0
13131 #define R_PAR1_CTRL_DATA__autofd__autofd__active 1
13132 #define R_PAR1_CTRL_DATA__autofd__autofd__inactive 0
13133 #define R_PAR1_CTRL_DATA__strb__strb__active 1
13134 #define R_PAR1_CTRL_DATA__strb__strb__inactive 0
13135 #define R_PAR1_CTRL_DATA__init__init__active 1
13136 #define R_PAR1_CTRL_DATA__init__init__inactive 0
13137 #define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__command 1
13138 #define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__data 0
13139
13140 #endif
13141
13142 /*
13143 * R_PAR1_DELAY
13144 * - type: WO
13145 * - addr: 0xb0000058
13146 * - group: Parallel printer port registers
13147 */
13148
13149 #if USE_GROUP__Parallel_printer_port_registers
13150
13151 #define R_PAR1_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000058)
13152
13153 #ifndef REG_NO_SHADOW
13154 #define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_DELAY + 0))
13155 #define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_DELAY + 0))
13156 #else /* REG_NO_SHADOW */
13157 #define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
13158 #define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
13159 #endif /* REG_NO_SHADOW */
13160
13161 #define R_PAR1_DELAY__STYPECAST REG_STYPECAST_UDWORD
13162 #define R_PAR1_DELAY__SVAL REG_SVAL_SHADOW
13163 #define R_PAR1_DELAY__SVAL_I REG_SVAL_I_SHADOW
13164 #define R_PAR1_DELAY__TYPECAST REG_TYPECAST_UDWORD
13165 #define R_PAR1_DELAY__TYPE (REG_UDWORD)
13166 #define R_PAR1_DELAY__GET REG_GET_WO
13167 #define R_PAR1_DELAY__IGET REG_IGET_WO
13168 #define R_PAR1_DELAY__SET REG_SET_WO
13169 #define R_PAR1_DELAY__ISET REG_ISET_WO
13170 #define R_PAR1_DELAY__SET_VAL REG_SET_VAL_WO
13171 #define R_PAR1_DELAY__EQL REG_EQL_WO
13172 #define R_PAR1_DELAY__IEQL REG_IEQL_WO
13173 #define R_PAR1_DELAY__RD REG_RD_WO
13174 #define R_PAR1_DELAY__IRD REG_IRD_WO
13175 #define R_PAR1_DELAY__WR REG_WR_WO
13176 #define R_PAR1_DELAY__IWR REG_IWR_WO
13177
13178 #define R_PAR1_DELAY__WRITE(addr,value) \
13179 (*(addr) = (value))
13180
13181 #define R_PAR1_DELAY__fine_hold__fine_hold__MASK 0x00e00000U
13182 #define R_PAR1_DELAY__hold__hold__MASK 0x001f0000U
13183 #define R_PAR1_DELAY__fine_strb__fine_strb__MASK 0x0000e000U
13184 #define R_PAR1_DELAY__strobe__strobe__MASK 0x00001f00U
13185 #define R_PAR1_DELAY__fine_setup__fine_setup__MASK 0x000000e0U
13186 #define R_PAR1_DELAY__setup__setup__MASK 0x0000001fU
13187
13188 #define R_PAR1_DELAY__fine_hold__MAX 0x7
13189 #define R_PAR1_DELAY__hold__MAX 0x1f
13190 #define R_PAR1_DELAY__fine_strb__MAX 0x7
13191 #define R_PAR1_DELAY__strobe__MAX 0x1f
13192 #define R_PAR1_DELAY__fine_setup__MAX 0x7
13193 #define R_PAR1_DELAY__setup__MAX 0x1f
13194
13195 #define R_PAR1_DELAY__fine_hold__MIN 0
13196 #define R_PAR1_DELAY__hold__MIN 0
13197 #define R_PAR1_DELAY__fine_strb__MIN 0
13198 #define R_PAR1_DELAY__strobe__MIN 0
13199 #define R_PAR1_DELAY__fine_setup__MIN 0
13200 #define R_PAR1_DELAY__setup__MIN 0
13201
13202 #define R_PAR1_DELAY__fine_hold__BITNR 21
13203 #define R_PAR1_DELAY__hold__BITNR 16
13204 #define R_PAR1_DELAY__fine_strb__BITNR 13
13205 #define R_PAR1_DELAY__strobe__BITNR 8
13206 #define R_PAR1_DELAY__fine_setup__BITNR 5
13207 #define R_PAR1_DELAY__setup__BITNR 0
13208
13209 #define R_PAR1_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL
13210 #define R_PAR1_DELAY__hold__hold__VAL REG_VAL_VAL
13211 #define R_PAR1_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL
13212 #define R_PAR1_DELAY__strobe__strobe__VAL REG_VAL_VAL
13213 #define R_PAR1_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL
13214 #define R_PAR1_DELAY__setup__setup__VAL REG_VAL_VAL
13215
13216
13217 #endif
13218
13219 /*
13220 * R_PAR1_STATUS
13221 * - type: RO
13222 * - addr: 0xb0000052
13223 * - group: Parallel printer port registers
13224 */
13225
13226 #if USE_GROUP__Parallel_printer_port_registers
13227
13228 #define R_PAR1_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000052)
13229 #define R_PAR1_STATUS__SVAL REG_SVAL_SHADOW
13230 #define R_PAR1_STATUS__SVAL_I REG_SVAL_I_SHADOW
13231 #define R_PAR1_STATUS__TYPECAST REG_TYPECAST_UWORD
13232 #define R_PAR1_STATUS__TYPE (REG_UWORD)
13233 #define R_PAR1_STATUS__GET REG_GET_RO
13234 #define R_PAR1_STATUS__IGET REG_IGET_RO
13235 #define R_PAR1_STATUS__SET REG_SET_RO
13236 #define R_PAR1_STATUS__ISET REG_ISET_RO
13237 #define R_PAR1_STATUS__SET_VAL REG_SET_VAL_RO
13238 #define R_PAR1_STATUS__EQL REG_EQL_RO
13239 #define R_PAR1_STATUS__IEQL REG_IEQL_RO
13240 #define R_PAR1_STATUS__RD REG_RD_RO
13241 #define R_PAR1_STATUS__IRD REG_IRD_RO
13242 #define R_PAR1_STATUS__WR REG_WR_RO
13243 #define R_PAR1_STATUS__IWR REG_IWR_RO
13244
13245 #define R_PAR1_STATUS__READ(addr) \
13246 (*(addr))
13247
13248 #define R_PAR1_STATUS__mode__mode__MASK 0x0000e000U
13249 #define R_PAR1_STATUS__perr__perr__MASK 0x00001000U
13250 #define R_PAR1_STATUS__ack__ack__MASK 0x00000800U
13251 #define R_PAR1_STATUS__busy__busy__MASK 0x00000400U
13252 #define R_PAR1_STATUS__fault__fault__MASK 0x00000200U
13253 #define R_PAR1_STATUS__sel__sel__MASK 0x00000100U
13254 #define R_PAR1_STATUS__ext_mode__ext_mode__MASK 0x00000080U
13255 #define R_PAR1_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U
13256 #define R_PAR1_STATUS__dav__dav__MASK 0x00000001U
13257
13258 #define R_PAR1_STATUS__mode__MAX 0x7
13259 #define R_PAR1_STATUS__perr__MAX 0x1
13260 #define R_PAR1_STATUS__ack__MAX 0x1
13261 #define R_PAR1_STATUS__busy__MAX 0x1
13262 #define R_PAR1_STATUS__fault__MAX 0x1
13263 #define R_PAR1_STATUS__sel__MAX 0x1
13264 #define R_PAR1_STATUS__ext_mode__MAX 0x1
13265 #define R_PAR1_STATUS__tr_rdy__MAX 0x1
13266 #define R_PAR1_STATUS__dav__MAX 0x1
13267
13268 #define R_PAR1_STATUS__mode__MIN 0
13269 #define R_PAR1_STATUS__perr__MIN 0
13270 #define R_PAR1_STATUS__ack__MIN 0
13271 #define R_PAR1_STATUS__busy__MIN 0
13272 #define R_PAR1_STATUS__fault__MIN 0
13273 #define R_PAR1_STATUS__sel__MIN 0
13274 #define R_PAR1_STATUS__ext_mode__MIN 0
13275 #define R_PAR1_STATUS__tr_rdy__MIN 0
13276 #define R_PAR1_STATUS__dav__MIN 0
13277
13278 #define R_PAR1_STATUS__mode__BITNR 13
13279 #define R_PAR1_STATUS__perr__BITNR 12
13280 #define R_PAR1_STATUS__ack__BITNR 11
13281 #define R_PAR1_STATUS__busy__BITNR 10
13282 #define R_PAR1_STATUS__fault__BITNR 9
13283 #define R_PAR1_STATUS__sel__BITNR 8
13284 #define R_PAR1_STATUS__ext_mode__BITNR 7
13285 #define R_PAR1_STATUS__tr_rdy__BITNR 1
13286 #define R_PAR1_STATUS__dav__BITNR 0
13287
13288 #define R_PAR1_STATUS__mode__mode__VAL REG_VAL_ENUM
13289 #define R_PAR1_STATUS__perr__perr__VAL REG_VAL_ENUM
13290 #define R_PAR1_STATUS__ack__ack__VAL REG_VAL_ENUM
13291 #define R_PAR1_STATUS__busy__busy__VAL REG_VAL_ENUM
13292 #define R_PAR1_STATUS__fault__fault__VAL REG_VAL_ENUM
13293 #define R_PAR1_STATUS__sel__sel__VAL REG_VAL_ENUM
13294 #define R_PAR1_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM
13295 #define R_PAR1_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
13296 #define R_PAR1_STATUS__dav__dav__VAL REG_VAL_ENUM
13297
13298 #define R_PAR1_STATUS__mode__mode__byte 4
13299 #define R_PAR1_STATUS__mode__mode__centronics 1
13300 #define R_PAR1_STATUS__mode__mode__ecp_fwd 5
13301 #define R_PAR1_STATUS__mode__mode__ecp_rev 6
13302 #define R_PAR1_STATUS__mode__mode__epp_rd 0
13303 #define R_PAR1_STATUS__mode__mode__epp_wr1 5
13304 #define R_PAR1_STATUS__mode__mode__epp_wr2 6
13305 #define R_PAR1_STATUS__mode__mode__epp_wr3 7
13306 #define R_PAR1_STATUS__mode__mode__fastbyte 2
13307 #define R_PAR1_STATUS__mode__mode__manual 0
13308 #define R_PAR1_STATUS__mode__mode__nibble 3
13309 #define R_PAR1_STATUS__mode__mode__off 7
13310 #define R_PAR1_STATUS__perr__perr__active 1
13311 #define R_PAR1_STATUS__perr__perr__inactive 0
13312 #define R_PAR1_STATUS__ack__ack__active 0
13313 #define R_PAR1_STATUS__ack__ack__inactive 1
13314 #define R_PAR1_STATUS__busy__busy__active 1
13315 #define R_PAR1_STATUS__busy__busy__inactive 0
13316 #define R_PAR1_STATUS__fault__fault__active 0
13317 #define R_PAR1_STATUS__fault__fault__inactive 1
13318 #define R_PAR1_STATUS__sel__sel__active 1
13319 #define R_PAR1_STATUS__sel__sel__inactive 0
13320 #define R_PAR1_STATUS__ext_mode__ext_mode__disable 0
13321 #define R_PAR1_STATUS__ext_mode__ext_mode__enable 1
13322 #define R_PAR1_STATUS__tr_rdy__tr_rdy__busy 0
13323 #define R_PAR1_STATUS__tr_rdy__tr_rdy__ready 1
13324 #define R_PAR1_STATUS__dav__dav__data 1
13325 #define R_PAR1_STATUS__dav__dav__nodata 0
13326
13327 #endif
13328
13329 /*
13330 * R_PAR1_STATUS_DATA
13331 * - type: RO
13332 * - addr: 0xb0000050
13333 * - group: Parallel printer port registers
13334 */
13335
13336 #if USE_GROUP__Parallel_printer_port_registers
13337
13338 #define R_PAR1_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
13339 #define R_PAR1_STATUS_DATA__SVAL REG_SVAL_SHADOW
13340 #define R_PAR1_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
13341 #define R_PAR1_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
13342 #define R_PAR1_STATUS_DATA__TYPE (REG_UDWORD)
13343 #define R_PAR1_STATUS_DATA__GET REG_GET_RO
13344 #define R_PAR1_STATUS_DATA__IGET REG_IGET_RO
13345 #define R_PAR1_STATUS_DATA__SET REG_SET_RO
13346 #define R_PAR1_STATUS_DATA__ISET REG_ISET_RO
13347 #define R_PAR1_STATUS_DATA__SET_VAL REG_SET_VAL_RO
13348 #define R_PAR1_STATUS_DATA__EQL REG_EQL_RO
13349 #define R_PAR1_STATUS_DATA__IEQL REG_IEQL_RO
13350 #define R_PAR1_STATUS_DATA__RD REG_RD_RO
13351 #define R_PAR1_STATUS_DATA__IRD REG_IRD_RO
13352 #define R_PAR1_STATUS_DATA__WR REG_WR_RO
13353 #define R_PAR1_STATUS_DATA__IWR REG_IWR_RO
13354
13355 #define R_PAR1_STATUS_DATA__READ(addr) \
13356 (*(addr))
13357
13358 #define R_PAR1_STATUS_DATA__mode__mode__MASK 0xe0000000U
13359 #define R_PAR1_STATUS_DATA__perr__perr__MASK 0x10000000U
13360 #define R_PAR1_STATUS_DATA__ack__ack__MASK 0x08000000U
13361 #define R_PAR1_STATUS_DATA__busy__busy__MASK 0x04000000U
13362 #define R_PAR1_STATUS_DATA__fault__fault__MASK 0x02000000U
13363 #define R_PAR1_STATUS_DATA__sel__sel__MASK 0x01000000U
13364 #define R_PAR1_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U
13365 #define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
13366 #define R_PAR1_STATUS_DATA__dav__dav__MASK 0x00010000U
13367 #define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
13368 #define R_PAR1_STATUS_DATA__data__data__MASK 0x000000ffU
13369
13370 #define R_PAR1_STATUS_DATA__mode__MAX 0x7
13371 #define R_PAR1_STATUS_DATA__perr__MAX 0x1
13372 #define R_PAR1_STATUS_DATA__ack__MAX 0x1
13373 #define R_PAR1_STATUS_DATA__busy__MAX 0x1
13374 #define R_PAR1_STATUS_DATA__fault__MAX 0x1
13375 #define R_PAR1_STATUS_DATA__sel__MAX 0x1
13376 #define R_PAR1_STATUS_DATA__ext_mode__MAX 0x1
13377 #define R_PAR1_STATUS_DATA__tr_rdy__MAX 0x1
13378 #define R_PAR1_STATUS_DATA__dav__MAX 0x1
13379 #define R_PAR1_STATUS_DATA__ecp_cmd__MAX 0x1
13380 #define R_PAR1_STATUS_DATA__data__MAX 0xff
13381
13382 #define R_PAR1_STATUS_DATA__mode__MIN 0
13383 #define R_PAR1_STATUS_DATA__perr__MIN 0
13384 #define R_PAR1_STATUS_DATA__ack__MIN 0
13385 #define R_PAR1_STATUS_DATA__busy__MIN 0
13386 #define R_PAR1_STATUS_DATA__fault__MIN 0
13387 #define R_PAR1_STATUS_DATA__sel__MIN 0
13388 #define R_PAR1_STATUS_DATA__ext_mode__MIN 0
13389 #define R_PAR1_STATUS_DATA__tr_rdy__MIN 0
13390 #define R_PAR1_STATUS_DATA__dav__MIN 0
13391 #define R_PAR1_STATUS_DATA__ecp_cmd__MIN 0
13392 #define R_PAR1_STATUS_DATA__data__MIN 0
13393
13394 #define R_PAR1_STATUS_DATA__mode__BITNR 29
13395 #define R_PAR1_STATUS_DATA__perr__BITNR 28
13396 #define R_PAR1_STATUS_DATA__ack__BITNR 27
13397 #define R_PAR1_STATUS_DATA__busy__BITNR 26
13398 #define R_PAR1_STATUS_DATA__fault__BITNR 25
13399 #define R_PAR1_STATUS_DATA__sel__BITNR 24
13400 #define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
13401 #define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
13402 #define R_PAR1_STATUS_DATA__dav__BITNR 16
13403 #define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
13404 #define R_PAR1_STATUS_DATA__data__BITNR 0
13405
13406 #define R_PAR1_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM
13407 #define R_PAR1_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM
13408 #define R_PAR1_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM
13409 #define R_PAR1_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
13410 #define R_PAR1_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM
13411 #define R_PAR1_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM
13412 #define R_PAR1_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM
13413 #define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
13414 #define R_PAR1_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
13415 #define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
13416 #define R_PAR1_STATUS_DATA__data__data__VAL REG_VAL_VAL
13417
13418 #define R_PAR1_STATUS_DATA__mode__mode__byte 4
13419 #define R_PAR1_STATUS_DATA__mode__mode__centronics 1
13420 #define R_PAR1_STATUS_DATA__mode__mode__ecp_fwd 5
13421 #define R_PAR1_STATUS_DATA__mode__mode__ecp_rev 6
13422 #define R_PAR1_STATUS_DATA__mode__mode__epp_rd 0
13423 #define R_PAR1_STATUS_DATA__mode__mode__epp_wr1 5
13424 #define R_PAR1_STATUS_DATA__mode__mode__epp_wr2 6
13425 #define R_PAR1_STATUS_DATA__mode__mode__epp_wr3 7
13426 #define R_PAR1_STATUS_DATA__mode__mode__fastbyte 2
13427 #define R_PAR1_STATUS_DATA__mode__mode__manual 0
13428 #define R_PAR1_STATUS_DATA__mode__mode__nibble 3
13429 #define R_PAR1_STATUS_DATA__mode__mode__off 7
13430 #define R_PAR1_STATUS_DATA__perr__perr__active 1
13431 #define R_PAR1_STATUS_DATA__perr__perr__inactive 0
13432 #define R_PAR1_STATUS_DATA__ack__ack__active 0
13433 #define R_PAR1_STATUS_DATA__ack__ack__inactive 1
13434 #define R_PAR1_STATUS_DATA__busy__busy__active 1
13435 #define R_PAR1_STATUS_DATA__busy__busy__inactive 0
13436 #define R_PAR1_STATUS_DATA__fault__fault__active 0
13437 #define R_PAR1_STATUS_DATA__fault__fault__inactive 1
13438 #define R_PAR1_STATUS_DATA__sel__sel__active 1
13439 #define R_PAR1_STATUS_DATA__sel__sel__inactive 0
13440 #define R_PAR1_STATUS_DATA__ext_mode__ext_mode__disable 0
13441 #define R_PAR1_STATUS_DATA__ext_mode__ext_mode__enable 1
13442 #define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__busy 0
13443 #define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__ready 1
13444 #define R_PAR1_STATUS_DATA__dav__dav__data 1
13445 #define R_PAR1_STATUS_DATA__dav__dav__nodata 0
13446 #define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__command 1
13447 #define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__data 0
13448
13449 #endif
13450
13451 /*
13452 * R_PAR_ECP16_DATA
13453 * - type: RW
13454 * - addr: 0xb0000040
13455 * - group: Parallel printer port registers
13456 */
13457
13458 #if USE_GROUP__Parallel_printer_port_registers
13459
13460 #define R_PAR_ECP16_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040)
13461 #define R_PAR_ECP16_DATA__SVAL REG_SVAL_SHADOW
13462 #define R_PAR_ECP16_DATA__SVAL_I REG_SVAL_I_SHADOW
13463 #define R_PAR_ECP16_DATA__TYPECAST REG_TYPECAST_UWORD
13464 #define R_PAR_ECP16_DATA__TYPE (REG_UWORD)
13465 #define R_PAR_ECP16_DATA__GET REG_GET_RW
13466 #define R_PAR_ECP16_DATA__IGET REG_IGET_RW
13467 #define R_PAR_ECP16_DATA__SET REG_SET_RW
13468 #define R_PAR_ECP16_DATA__ISET REG_ISET_RW
13469 #define R_PAR_ECP16_DATA__SET_VAL REG_SET_VAL_RW
13470 #define R_PAR_ECP16_DATA__EQL REG_EQL_RW
13471 #define R_PAR_ECP16_DATA__IEQL REG_IEQL_RW
13472 #define R_PAR_ECP16_DATA__RD REG_RD_RW
13473 #define R_PAR_ECP16_DATA__IRD REG_IRD_RW
13474 #define R_PAR_ECP16_DATA__WR REG_WR_RW
13475 #define R_PAR_ECP16_DATA__IWR REG_IWR_RW
13476
13477 #define R_PAR_ECP16_DATA__WRITE(addr,value) \
13478 (*(addr) = (value))
13479 #define R_PAR_ECP16_DATA__READ(addr) \
13480 (*(addr))
13481
13482 #define R_PAR_ECP16_DATA__data__data__MASK 0x0000ffffU
13483
13484 #define R_PAR_ECP16_DATA__data__MAX 0xffff
13485
13486 #define R_PAR_ECP16_DATA__data__MIN 0
13487
13488 #define R_PAR_ECP16_DATA__data__BITNR 0
13489
13490 #define R_PAR_ECP16_DATA__data__data__VAL REG_VAL_VAL
13491
13492
13493 #endif
13494
13495 /*
13496 * R_PHY_COUNTERS
13497 * - type: RO
13498 * - addr: 0xb00000ac
13499 * - group: Network interface registers
13500 */
13501
13502 #if USE_GROUP__Network_interface_registers
13503
13504 #define R_PHY_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000ac)
13505 #define R_PHY_COUNTERS__SVAL REG_SVAL_SHADOW
13506 #define R_PHY_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
13507 #define R_PHY_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
13508 #define R_PHY_COUNTERS__TYPE (REG_UDWORD)
13509 #define R_PHY_COUNTERS__GET REG_GET_RO
13510 #define R_PHY_COUNTERS__IGET REG_IGET_RO
13511 #define R_PHY_COUNTERS__SET REG_SET_RO
13512 #define R_PHY_COUNTERS__ISET REG_ISET_RO
13513 #define R_PHY_COUNTERS__SET_VAL REG_SET_VAL_RO
13514 #define R_PHY_COUNTERS__EQL REG_EQL_RO
13515 #define R_PHY_COUNTERS__IEQL REG_IEQL_RO
13516 #define R_PHY_COUNTERS__RD REG_RD_RO
13517 #define R_PHY_COUNTERS__IRD REG_IRD_RO
13518 #define R_PHY_COUNTERS__WR REG_WR_RO
13519 #define R_PHY_COUNTERS__IWR REG_IWR_RO
13520
13521 #define R_PHY_COUNTERS__READ(addr) \
13522 (*(addr))
13523
13524 #define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__MASK 0x0000ff00U
13525 #define R_PHY_COUNTERS__carrier_loss__carrier_loss__MASK 0x000000ffU
13526
13527 #define R_PHY_COUNTERS__sqe_test_error__MAX 0xff
13528 #define R_PHY_COUNTERS__carrier_loss__MAX 0xff
13529
13530 #define R_PHY_COUNTERS__sqe_test_error__MIN 0
13531 #define R_PHY_COUNTERS__carrier_loss__MIN 0
13532
13533 #define R_PHY_COUNTERS__sqe_test_error__BITNR 8
13534 #define R_PHY_COUNTERS__carrier_loss__BITNR 0
13535
13536 #define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__VAL REG_VAL_VAL
13537 #define R_PHY_COUNTERS__carrier_loss__carrier_loss__VAL REG_VAL_VAL
13538
13539
13540 #endif
13541
13542 /*
13543 * R_PORT_G_DATA
13544 * - type: RW
13545 * - addr: 0xb0000028
13546 * - group: General config registers
13547 */
13548
13549 #if USE_GROUP__General_config_registers
13550
13551 #define R_PORT_G_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000028)
13552 #define R_PORT_G_DATA__SVAL REG_SVAL_SHADOW
13553 #define R_PORT_G_DATA__SVAL_I REG_SVAL_I_SHADOW
13554 #define R_PORT_G_DATA__TYPECAST REG_TYPECAST_UDWORD
13555 #define R_PORT_G_DATA__TYPE (REG_UDWORD)
13556 #define R_PORT_G_DATA__GET REG_GET_RW
13557 #define R_PORT_G_DATA__IGET REG_IGET_RW
13558 #define R_PORT_G_DATA__SET REG_SET_RW
13559 #define R_PORT_G_DATA__ISET REG_ISET_RW
13560 #define R_PORT_G_DATA__SET_VAL REG_SET_VAL_RW
13561 #define R_PORT_G_DATA__EQL REG_EQL_RW
13562 #define R_PORT_G_DATA__IEQL REG_IEQL_RW
13563 #define R_PORT_G_DATA__RD REG_RD_RW
13564 #define R_PORT_G_DATA__IRD REG_IRD_RW
13565 #define R_PORT_G_DATA__WR REG_WR_RW
13566 #define R_PORT_G_DATA__IWR REG_IWR_RW
13567
13568 #define R_PORT_G_DATA__WRITE(addr,value) \
13569 (*(addr) = (value))
13570 #define R_PORT_G_DATA__READ(addr) \
13571 (*(addr))
13572
13573 #define R_PORT_G_DATA__data__data__MASK 0xffffffffU
13574
13575 #define R_PORT_G_DATA__data__MAX 0xffffffff
13576
13577 #define R_PORT_G_DATA__data__MIN 0
13578
13579 #define R_PORT_G_DATA__data__BITNR 0
13580
13581 #define R_PORT_G_DATA__data__data__VAL REG_VAL_VAL
13582
13583
13584 #endif
13585
13586 /*
13587 * R_PORT_PA_DATA
13588 * - type: WO
13589 * - addr: 0xb0000030
13590 * - group: General port configuration registers
13591 */
13592
13593 #if USE_GROUP__General_port_configuration_registers
13594
13595 #define R_PORT_PA_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000030)
13596
13597 #ifndef REG_NO_SHADOW
13598 #define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 0))
13599 #define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 0))
13600 #else /* REG_NO_SHADOW */
13601 #define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
13602 #define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
13603 #endif /* REG_NO_SHADOW */
13604
13605 #define R_PORT_PA_DATA__STYPECAST REG_STYPECAST_BYTE
13606 #define R_PORT_PA_DATA__SVAL REG_SVAL_SHADOW
13607 #define R_PORT_PA_DATA__SVAL_I REG_SVAL_I_SHADOW
13608 #define R_PORT_PA_DATA__TYPECAST REG_TYPECAST_BYTE
13609 #define R_PORT_PA_DATA__TYPE (REG_BYTE)
13610 #define R_PORT_PA_DATA__GET REG_GET_WO
13611 #define R_PORT_PA_DATA__IGET REG_IGET_WO
13612 #define R_PORT_PA_DATA__SET REG_SET_WO
13613 #define R_PORT_PA_DATA__ISET REG_ISET_WO
13614 #define R_PORT_PA_DATA__SET_VAL REG_SET_VAL_WO
13615 #define R_PORT_PA_DATA__EQL REG_EQL_WO
13616 #define R_PORT_PA_DATA__IEQL REG_IEQL_WO
13617 #define R_PORT_PA_DATA__RD REG_RD_WO
13618 #define R_PORT_PA_DATA__IRD REG_IRD_WO
13619 #define R_PORT_PA_DATA__WR REG_WR_WO
13620 #define R_PORT_PA_DATA__IWR REG_IWR_WO
13621
13622 #define R_PORT_PA_DATA__WRITE(addr,value) \
13623 (*(addr) = (value))
13624
13625 #define R_PORT_PA_DATA__data_out__data_out__MASK 0x000000ffU
13626
13627 #define R_PORT_PA_DATA__data_out__MAX 255
13628
13629 #define R_PORT_PA_DATA__data_out__MIN 0
13630
13631 #define R_PORT_PA_DATA__data_out__BITNR 0
13632
13633 #define R_PORT_PA_DATA__data_out__data_out__VAL REG_VAL_VAL
13634
13635
13636 #endif
13637
13638 /*
13639 * R_PORT_PA_DIR
13640 * - type: WO
13641 * - addr: 0xb0000031
13642 * - group: General port configuration registers
13643 */
13644
13645 #if USE_GROUP__General_port_configuration_registers
13646
13647 #define R_PORT_PA_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000031)
13648
13649 #ifndef REG_NO_SHADOW
13650 #define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 1))
13651 #define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 1))
13652 #else /* REG_NO_SHADOW */
13653 #define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
13654 #define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
13655 #endif /* REG_NO_SHADOW */
13656
13657 #define R_PORT_PA_DIR__STYPECAST REG_STYPECAST_BYTE
13658 #define R_PORT_PA_DIR__SVAL REG_SVAL_SHADOW
13659 #define R_PORT_PA_DIR__SVAL_I REG_SVAL_I_SHADOW
13660 #define R_PORT_PA_DIR__TYPECAST REG_TYPECAST_BYTE
13661 #define R_PORT_PA_DIR__TYPE (REG_BYTE)
13662 #define R_PORT_PA_DIR__GET REG_GET_WO
13663 #define R_PORT_PA_DIR__IGET REG_IGET_WO
13664 #define R_PORT_PA_DIR__SET REG_SET_WO
13665 #define R_PORT_PA_DIR__ISET REG_ISET_WO
13666 #define R_PORT_PA_DIR__SET_VAL REG_SET_VAL_WO
13667 #define R_PORT_PA_DIR__EQL REG_EQL_WO
13668 #define R_PORT_PA_DIR__IEQL REG_IEQL_WO
13669 #define R_PORT_PA_DIR__RD REG_RD_WO
13670 #define R_PORT_PA_DIR__IRD REG_IRD_WO
13671 #define R_PORT_PA_DIR__WR REG_WR_WO
13672 #define R_PORT_PA_DIR__IWR REG_IWR_WO
13673
13674 #define R_PORT_PA_DIR__WRITE(addr,value) \
13675 (*(addr) = (value))
13676
13677 #define R_PORT_PA_DIR__dir7__dir7__MASK 0x00000080U
13678 #define R_PORT_PA_DIR__dir6__dir6__MASK 0x00000040U
13679 #define R_PORT_PA_DIR__dir5__dir5__MASK 0x00000020U
13680 #define R_PORT_PA_DIR__dir4__dir4__MASK 0x00000010U
13681 #define R_PORT_PA_DIR__dir3__dir3__MASK 0x00000008U
13682 #define R_PORT_PA_DIR__dir2__dir2__MASK 0x00000004U
13683 #define R_PORT_PA_DIR__dir1__dir1__MASK 0x00000002U
13684 #define R_PORT_PA_DIR__dir0__dir0__MASK 0x00000001U
13685
13686 #define R_PORT_PA_DIR__dir7__MAX 0x1
13687 #define R_PORT_PA_DIR__dir6__MAX 0x1
13688 #define R_PORT_PA_DIR__dir5__MAX 0x1
13689 #define R_PORT_PA_DIR__dir4__MAX 0x1
13690 #define R_PORT_PA_DIR__dir3__MAX 0x1
13691 #define R_PORT_PA_DIR__dir2__MAX 0x1
13692 #define R_PORT_PA_DIR__dir1__MAX 0x1
13693 #define R_PORT_PA_DIR__dir0__MAX 0x1
13694
13695 #define R_PORT_PA_DIR__dir7__MIN 0
13696 #define R_PORT_PA_DIR__dir6__MIN 0
13697 #define R_PORT_PA_DIR__dir5__MIN 0
13698 #define R_PORT_PA_DIR__dir4__MIN 0
13699 #define R_PORT_PA_DIR__dir3__MIN 0
13700 #define R_PORT_PA_DIR__dir2__MIN 0
13701 #define R_PORT_PA_DIR__dir1__MIN 0
13702 #define R_PORT_PA_DIR__dir0__MIN 0
13703
13704 #define R_PORT_PA_DIR__dir7__BITNR 7
13705 #define R_PORT_PA_DIR__dir6__BITNR 6
13706 #define R_PORT_PA_DIR__dir5__BITNR 5
13707 #define R_PORT_PA_DIR__dir4__BITNR 4
13708 #define R_PORT_PA_DIR__dir3__BITNR 3
13709 #define R_PORT_PA_DIR__dir2__BITNR 2
13710 #define R_PORT_PA_DIR__dir1__BITNR 1
13711 #define R_PORT_PA_DIR__dir0__BITNR 0
13712
13713 #define R_PORT_PA_DIR__dir7__dir7__VAL REG_VAL_ENUM
13714 #define R_PORT_PA_DIR__dir6__dir6__VAL REG_VAL_ENUM
13715 #define R_PORT_PA_DIR__dir5__dir5__VAL REG_VAL_ENUM
13716 #define R_PORT_PA_DIR__dir4__dir4__VAL REG_VAL_ENUM
13717 #define R_PORT_PA_DIR__dir3__dir3__VAL REG_VAL_ENUM
13718 #define R_PORT_PA_DIR__dir2__dir2__VAL REG_VAL_ENUM
13719 #define R_PORT_PA_DIR__dir1__dir1__VAL REG_VAL_ENUM
13720 #define R_PORT_PA_DIR__dir0__dir0__VAL REG_VAL_ENUM
13721
13722 #define R_PORT_PA_DIR__dir7__dir7__input 0
13723 #define R_PORT_PA_DIR__dir7__dir7__output 1
13724 #define R_PORT_PA_DIR__dir6__dir6__input 0
13725 #define R_PORT_PA_DIR__dir6__dir6__output 1
13726 #define R_PORT_PA_DIR__dir5__dir5__input 0
13727 #define R_PORT_PA_DIR__dir5__dir5__output 1
13728 #define R_PORT_PA_DIR__dir4__dir4__input 0
13729 #define R_PORT_PA_DIR__dir4__dir4__output 1
13730 #define R_PORT_PA_DIR__dir3__dir3__input 0
13731 #define R_PORT_PA_DIR__dir3__dir3__output 1
13732 #define R_PORT_PA_DIR__dir2__dir2__input 0
13733 #define R_PORT_PA_DIR__dir2__dir2__output 1
13734 #define R_PORT_PA_DIR__dir1__dir1__input 0
13735 #define R_PORT_PA_DIR__dir1__dir1__output 1
13736 #define R_PORT_PA_DIR__dir0__dir0__input 0
13737 #define R_PORT_PA_DIR__dir0__dir0__output 1
13738
13739 #endif
13740
13741 /*
13742 * R_PORT_PA_READ
13743 * - type: RO
13744 * - addr: 0xb0000030
13745 * - group: General port configuration registers
13746 */
13747
13748 #if USE_GROUP__General_port_configuration_registers
13749
13750 #define R_PORT_PA_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000030)
13751 #define R_PORT_PA_READ__SVAL REG_SVAL_SHADOW
13752 #define R_PORT_PA_READ__SVAL_I REG_SVAL_I_SHADOW
13753 #define R_PORT_PA_READ__TYPECAST REG_TYPECAST_UDWORD
13754 #define R_PORT_PA_READ__TYPE (REG_UDWORD)
13755 #define R_PORT_PA_READ__GET REG_GET_RO
13756 #define R_PORT_PA_READ__IGET REG_IGET_RO
13757 #define R_PORT_PA_READ__SET REG_SET_RO
13758 #define R_PORT_PA_READ__ISET REG_ISET_RO
13759 #define R_PORT_PA_READ__SET_VAL REG_SET_VAL_RO
13760 #define R_PORT_PA_READ__EQL REG_EQL_RO
13761 #define R_PORT_PA_READ__IEQL REG_IEQL_RO
13762 #define R_PORT_PA_READ__RD REG_RD_RO
13763 #define R_PORT_PA_READ__IRD REG_IRD_RO
13764 #define R_PORT_PA_READ__WR REG_WR_RO
13765 #define R_PORT_PA_READ__IWR REG_IWR_RO
13766
13767 #define R_PORT_PA_READ__READ(addr) \
13768 (*(addr))
13769
13770 #define R_PORT_PA_READ__data_in__data_in__MASK 0x000000ffU
13771
13772 #define R_PORT_PA_READ__data_in__MAX 255
13773
13774 #define R_PORT_PA_READ__data_in__MIN 0
13775
13776 #define R_PORT_PA_READ__data_in__BITNR 0
13777
13778 #define R_PORT_PA_READ__data_in__data_in__VAL REG_VAL_VAL
13779
13780
13781 #endif
13782
13783 /*
13784 * R_PORT_PA_SET
13785 * - type: WO
13786 * - addr: 0xb0000030
13787 * - group: General port configuration registers
13788 */
13789
13790 #if USE_GROUP__General_port_configuration_registers
13791
13792 #define R_PORT_PA_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000030)
13793
13794 #ifndef REG_NO_SHADOW
13795 #define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PA_SET + 0))
13796 #define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PA_SET + 0))
13797 #else /* REG_NO_SHADOW */
13798 #define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
13799 #define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
13800 #endif /* REG_NO_SHADOW */
13801
13802 #define R_PORT_PA_SET__STYPECAST REG_STYPECAST_UDWORD
13803 #define R_PORT_PA_SET__SVAL REG_SVAL_SHADOW
13804 #define R_PORT_PA_SET__SVAL_I REG_SVAL_I_SHADOW
13805 #define R_PORT_PA_SET__TYPECAST REG_TYPECAST_UDWORD
13806 #define R_PORT_PA_SET__TYPE (REG_UDWORD)
13807 #define R_PORT_PA_SET__GET REG_GET_WO
13808 #define R_PORT_PA_SET__IGET REG_IGET_WO
13809 #define R_PORT_PA_SET__SET REG_SET_WO
13810 #define R_PORT_PA_SET__ISET REG_ISET_WO
13811 #define R_PORT_PA_SET__SET_VAL REG_SET_VAL_WO
13812 #define R_PORT_PA_SET__EQL REG_EQL_WO
13813 #define R_PORT_PA_SET__IEQL REG_IEQL_WO
13814 #define R_PORT_PA_SET__RD REG_RD_WO
13815 #define R_PORT_PA_SET__IRD REG_IRD_WO
13816 #define R_PORT_PA_SET__WR REG_WR_WO
13817 #define R_PORT_PA_SET__IWR REG_IWR_WO
13818
13819 #define R_PORT_PA_SET__WRITE(addr,value) \
13820 (*(addr) = (value))
13821
13822 #define R_PORT_PA_SET__dir7__dir7__MASK 0x00008000U
13823 #define R_PORT_PA_SET__dir6__dir6__MASK 0x00004000U
13824 #define R_PORT_PA_SET__dir5__dir5__MASK 0x00002000U
13825 #define R_PORT_PA_SET__dir4__dir4__MASK 0x00001000U
13826 #define R_PORT_PA_SET__dir3__dir3__MASK 0x00000800U
13827 #define R_PORT_PA_SET__dir2__dir2__MASK 0x00000400U
13828 #define R_PORT_PA_SET__dir1__dir1__MASK 0x00000200U
13829 #define R_PORT_PA_SET__dir0__dir0__MASK 0x00000100U
13830 #define R_PORT_PA_SET__data_out__data_out__MASK 0x000000ffU
13831
13832 #define R_PORT_PA_SET__dir7__MAX 0x1
13833 #define R_PORT_PA_SET__dir6__MAX 0x1
13834 #define R_PORT_PA_SET__dir5__MAX 0x1
13835 #define R_PORT_PA_SET__dir4__MAX 0x1
13836 #define R_PORT_PA_SET__dir3__MAX 0x1
13837 #define R_PORT_PA_SET__dir2__MAX 0x1
13838 #define R_PORT_PA_SET__dir1__MAX 0x1
13839 #define R_PORT_PA_SET__dir0__MAX 0x1
13840 #define R_PORT_PA_SET__data_out__MAX 255
13841
13842 #define R_PORT_PA_SET__dir7__MIN 0
13843 #define R_PORT_PA_SET__dir6__MIN 0
13844 #define R_PORT_PA_SET__dir5__MIN 0
13845 #define R_PORT_PA_SET__dir4__MIN 0
13846 #define R_PORT_PA_SET__dir3__MIN 0
13847 #define R_PORT_PA_SET__dir2__MIN 0
13848 #define R_PORT_PA_SET__dir1__MIN 0
13849 #define R_PORT_PA_SET__dir0__MIN 0
13850 #define R_PORT_PA_SET__data_out__MIN 0
13851
13852 #define R_PORT_PA_SET__dir7__BITNR 15
13853 #define R_PORT_PA_SET__dir6__BITNR 14
13854 #define R_PORT_PA_SET__dir5__BITNR 13
13855 #define R_PORT_PA_SET__dir4__BITNR 12
13856 #define R_PORT_PA_SET__dir3__BITNR 11
13857 #define R_PORT_PA_SET__dir2__BITNR 10
13858 #define R_PORT_PA_SET__dir1__BITNR 9
13859 #define R_PORT_PA_SET__dir0__BITNR 8
13860 #define R_PORT_PA_SET__data_out__BITNR 0
13861
13862 #define R_PORT_PA_SET__dir7__dir7__VAL REG_VAL_ENUM
13863 #define R_PORT_PA_SET__dir6__dir6__VAL REG_VAL_ENUM
13864 #define R_PORT_PA_SET__dir5__dir5__VAL REG_VAL_ENUM
13865 #define R_PORT_PA_SET__dir4__dir4__VAL REG_VAL_ENUM
13866 #define R_PORT_PA_SET__dir3__dir3__VAL REG_VAL_ENUM
13867 #define R_PORT_PA_SET__dir2__dir2__VAL REG_VAL_ENUM
13868 #define R_PORT_PA_SET__dir1__dir1__VAL REG_VAL_ENUM
13869 #define R_PORT_PA_SET__dir0__dir0__VAL REG_VAL_ENUM
13870 #define R_PORT_PA_SET__data_out__data_out__VAL REG_VAL_VAL
13871
13872 #define R_PORT_PA_SET__dir7__dir7__input 0
13873 #define R_PORT_PA_SET__dir7__dir7__output 1
13874 #define R_PORT_PA_SET__dir6__dir6__input 0
13875 #define R_PORT_PA_SET__dir6__dir6__output 1
13876 #define R_PORT_PA_SET__dir5__dir5__input 0
13877 #define R_PORT_PA_SET__dir5__dir5__output 1
13878 #define R_PORT_PA_SET__dir4__dir4__input 0
13879 #define R_PORT_PA_SET__dir4__dir4__output 1
13880 #define R_PORT_PA_SET__dir3__dir3__input 0
13881 #define R_PORT_PA_SET__dir3__dir3__output 1
13882 #define R_PORT_PA_SET__dir2__dir2__input 0
13883 #define R_PORT_PA_SET__dir2__dir2__output 1
13884 #define R_PORT_PA_SET__dir1__dir1__input 0
13885 #define R_PORT_PA_SET__dir1__dir1__output 1
13886 #define R_PORT_PA_SET__dir0__dir0__input 0
13887 #define R_PORT_PA_SET__dir0__dir0__output 1
13888
13889 #endif
13890
13891 /*
13892 * R_PORT_PB_CONFIG
13893 * - type: WO
13894 * - addr: 0xb000003a
13895 * - group: General port configuration registers
13896 */
13897
13898 #if USE_GROUP__General_port_configuration_registers
13899
13900 #define R_PORT_PB_CONFIG__ADDR (REG_TYPECAST_BYTE 0xb000003a)
13901
13902 #ifndef REG_NO_SHADOW
13903 #define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 2))
13904 #define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 2))
13905 #else /* REG_NO_SHADOW */
13906 #define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
13907 #define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
13908 #endif /* REG_NO_SHADOW */
13909
13910 #define R_PORT_PB_CONFIG__STYPECAST REG_STYPECAST_BYTE
13911 #define R_PORT_PB_CONFIG__SVAL REG_SVAL_SHADOW
13912 #define R_PORT_PB_CONFIG__SVAL_I REG_SVAL_I_SHADOW
13913 #define R_PORT_PB_CONFIG__TYPECAST REG_TYPECAST_BYTE
13914 #define R_PORT_PB_CONFIG__TYPE (REG_BYTE)
13915 #define R_PORT_PB_CONFIG__GET REG_GET_WO
13916 #define R_PORT_PB_CONFIG__IGET REG_IGET_WO
13917 #define R_PORT_PB_CONFIG__SET REG_SET_WO
13918 #define R_PORT_PB_CONFIG__ISET REG_ISET_WO
13919 #define R_PORT_PB_CONFIG__SET_VAL REG_SET_VAL_WO
13920 #define R_PORT_PB_CONFIG__EQL REG_EQL_WO
13921 #define R_PORT_PB_CONFIG__IEQL REG_IEQL_WO
13922 #define R_PORT_PB_CONFIG__RD REG_RD_WO
13923 #define R_PORT_PB_CONFIG__IRD REG_IRD_WO
13924 #define R_PORT_PB_CONFIG__WR REG_WR_WO
13925 #define R_PORT_PB_CONFIG__IWR REG_IWR_WO
13926
13927 #define R_PORT_PB_CONFIG__WRITE(addr,value) \
13928 (*(addr) = (value))
13929
13930 #define R_PORT_PB_CONFIG__cs7__cs7__MASK 0x00000080U
13931 #define R_PORT_PB_CONFIG__cs6__cs6__MASK 0x00000040U
13932 #define R_PORT_PB_CONFIG__cs5__cs5__MASK 0x00000020U
13933 #define R_PORT_PB_CONFIG__cs4__cs4__MASK 0x00000010U
13934 #define R_PORT_PB_CONFIG__cs3__cs3__MASK 0x00000008U
13935 #define R_PORT_PB_CONFIG__cs2__cs2__MASK 0x00000004U
13936 #define R_PORT_PB_CONFIG__scsi1__scsi1__MASK 0x00000002U
13937 #define R_PORT_PB_CONFIG__scsi0__scsi0__MASK 0x00000001U
13938
13939 #define R_PORT_PB_CONFIG__cs7__MAX 0x1
13940 #define R_PORT_PB_CONFIG__cs6__MAX 0x1
13941 #define R_PORT_PB_CONFIG__cs5__MAX 0x1
13942 #define R_PORT_PB_CONFIG__cs4__MAX 0x1
13943 #define R_PORT_PB_CONFIG__cs3__MAX 0x1
13944 #define R_PORT_PB_CONFIG__cs2__MAX 0x1
13945 #define R_PORT_PB_CONFIG__scsi1__MAX 0x1
13946 #define R_PORT_PB_CONFIG__scsi0__MAX 0x1
13947
13948 #define R_PORT_PB_CONFIG__cs7__MIN 0
13949 #define R_PORT_PB_CONFIG__cs6__MIN 0
13950 #define R_PORT_PB_CONFIG__cs5__MIN 0
13951 #define R_PORT_PB_CONFIG__cs4__MIN 0
13952 #define R_PORT_PB_CONFIG__cs3__MIN 0
13953 #define R_PORT_PB_CONFIG__cs2__MIN 0
13954 #define R_PORT_PB_CONFIG__scsi1__MIN 0
13955 #define R_PORT_PB_CONFIG__scsi0__MIN 0
13956
13957 #define R_PORT_PB_CONFIG__cs7__BITNR 7
13958 #define R_PORT_PB_CONFIG__cs6__BITNR 6
13959 #define R_PORT_PB_CONFIG__cs5__BITNR 5
13960 #define R_PORT_PB_CONFIG__cs4__BITNR 4
13961 #define R_PORT_PB_CONFIG__cs3__BITNR 3
13962 #define R_PORT_PB_CONFIG__cs2__BITNR 2
13963 #define R_PORT_PB_CONFIG__scsi1__BITNR 1
13964 #define R_PORT_PB_CONFIG__scsi0__BITNR 0
13965
13966 #define R_PORT_PB_CONFIG__cs7__cs7__VAL REG_VAL_ENUM
13967 #define R_PORT_PB_CONFIG__cs6__cs6__VAL REG_VAL_ENUM
13968 #define R_PORT_PB_CONFIG__cs5__cs5__VAL REG_VAL_ENUM
13969 #define R_PORT_PB_CONFIG__cs4__cs4__VAL REG_VAL_ENUM
13970 #define R_PORT_PB_CONFIG__cs3__cs3__VAL REG_VAL_ENUM
13971 #define R_PORT_PB_CONFIG__cs2__cs2__VAL REG_VAL_ENUM
13972 #define R_PORT_PB_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM
13973 #define R_PORT_PB_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM
13974
13975 #define R_PORT_PB_CONFIG__cs7__cs7__cs 1
13976 #define R_PORT_PB_CONFIG__cs7__cs7__port 0
13977 #define R_PORT_PB_CONFIG__cs6__cs6__cs 1
13978 #define R_PORT_PB_CONFIG__cs6__cs6__port 0
13979 #define R_PORT_PB_CONFIG__cs5__cs5__cs 1
13980 #define R_PORT_PB_CONFIG__cs5__cs5__port 0
13981 #define R_PORT_PB_CONFIG__cs4__cs4__cs 1
13982 #define R_PORT_PB_CONFIG__cs4__cs4__port 0
13983 #define R_PORT_PB_CONFIG__cs3__cs3__cs 1
13984 #define R_PORT_PB_CONFIG__cs3__cs3__port 0
13985 #define R_PORT_PB_CONFIG__cs2__cs2__cs 1
13986 #define R_PORT_PB_CONFIG__cs2__cs2__port 0
13987 #define R_PORT_PB_CONFIG__scsi1__scsi1__enph 1
13988 #define R_PORT_PB_CONFIG__scsi1__scsi1__port_cs 0
13989 #define R_PORT_PB_CONFIG__scsi0__scsi0__enph 1
13990 #define R_PORT_PB_CONFIG__scsi0__scsi0__port_cs 0
13991
13992 #endif
13993
13994 /*
13995 * R_PORT_PB_DATA
13996 * - type: WO
13997 * - addr: 0xb0000038
13998 * - group: General port configuration registers
13999 */
14000
14001 #if USE_GROUP__General_port_configuration_registers
14002
14003 #define R_PORT_PB_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000038)
14004
14005 #ifndef REG_NO_SHADOW
14006 #define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 0))
14007 #define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 0))
14008 #else /* REG_NO_SHADOW */
14009 #define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
14010 #define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
14011 #endif /* REG_NO_SHADOW */
14012
14013 #define R_PORT_PB_DATA__STYPECAST REG_STYPECAST_BYTE
14014 #define R_PORT_PB_DATA__SVAL REG_SVAL_SHADOW
14015 #define R_PORT_PB_DATA__SVAL_I REG_SVAL_I_SHADOW
14016 #define R_PORT_PB_DATA__TYPECAST REG_TYPECAST_BYTE
14017 #define R_PORT_PB_DATA__TYPE (REG_BYTE)
14018 #define R_PORT_PB_DATA__GET REG_GET_WO
14019 #define R_PORT_PB_DATA__IGET REG_IGET_WO
14020 #define R_PORT_PB_DATA__SET REG_SET_WO
14021 #define R_PORT_PB_DATA__ISET REG_ISET_WO
14022 #define R_PORT_PB_DATA__SET_VAL REG_SET_VAL_WO
14023 #define R_PORT_PB_DATA__EQL REG_EQL_WO
14024 #define R_PORT_PB_DATA__IEQL REG_IEQL_WO
14025 #define R_PORT_PB_DATA__RD REG_RD_WO
14026 #define R_PORT_PB_DATA__IRD REG_IRD_WO
14027 #define R_PORT_PB_DATA__WR REG_WR_WO
14028 #define R_PORT_PB_DATA__IWR REG_IWR_WO
14029
14030 #define R_PORT_PB_DATA__WRITE(addr,value) \
14031 (*(addr) = (value))
14032
14033 #define R_PORT_PB_DATA__data_out__data_out__MASK 0x000000ffU
14034
14035 #define R_PORT_PB_DATA__data_out__MAX 255
14036
14037 #define R_PORT_PB_DATA__data_out__MIN 0
14038
14039 #define R_PORT_PB_DATA__data_out__BITNR 0
14040
14041 #define R_PORT_PB_DATA__data_out__data_out__VAL REG_VAL_VAL
14042
14043
14044 #endif
14045
14046 /*
14047 * R_PORT_PB_DIR
14048 * - type: WO
14049 * - addr: 0xb0000039
14050 * - group: General port configuration registers
14051 */
14052
14053 #if USE_GROUP__General_port_configuration_registers
14054
14055 #define R_PORT_PB_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000039)
14056
14057 #ifndef REG_NO_SHADOW
14058 #define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 1))
14059 #define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 1))
14060 #else /* REG_NO_SHADOW */
14061 #define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
14062 #define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
14063 #endif /* REG_NO_SHADOW */
14064
14065 #define R_PORT_PB_DIR__STYPECAST REG_STYPECAST_BYTE
14066 #define R_PORT_PB_DIR__SVAL REG_SVAL_SHADOW
14067 #define R_PORT_PB_DIR__SVAL_I REG_SVAL_I_SHADOW
14068 #define R_PORT_PB_DIR__TYPECAST REG_TYPECAST_BYTE
14069 #define R_PORT_PB_DIR__TYPE (REG_BYTE)
14070 #define R_PORT_PB_DIR__GET REG_GET_WO
14071 #define R_PORT_PB_DIR__IGET REG_IGET_WO
14072 #define R_PORT_PB_DIR__SET REG_SET_WO
14073 #define R_PORT_PB_DIR__ISET REG_ISET_WO
14074 #define R_PORT_PB_DIR__SET_VAL REG_SET_VAL_WO
14075 #define R_PORT_PB_DIR__EQL REG_EQL_WO
14076 #define R_PORT_PB_DIR__IEQL REG_IEQL_WO
14077 #define R_PORT_PB_DIR__RD REG_RD_WO
14078 #define R_PORT_PB_DIR__IRD REG_IRD_WO
14079 #define R_PORT_PB_DIR__WR REG_WR_WO
14080 #define R_PORT_PB_DIR__IWR REG_IWR_WO
14081
14082 #define R_PORT_PB_DIR__WRITE(addr,value) \
14083 (*(addr) = (value))
14084
14085 #define R_PORT_PB_DIR__dir7__dir7__MASK 0x00000080U
14086 #define R_PORT_PB_DIR__dir6__dir6__MASK 0x00000040U
14087 #define R_PORT_PB_DIR__dir5__dir5__MASK 0x00000020U
14088 #define R_PORT_PB_DIR__dir4__dir4__MASK 0x00000010U
14089 #define R_PORT_PB_DIR__dir3__dir3__MASK 0x00000008U
14090 #define R_PORT_PB_DIR__dir2__dir2__MASK 0x00000004U
14091 #define R_PORT_PB_DIR__dir1__dir1__MASK 0x00000002U
14092 #define R_PORT_PB_DIR__dir0__dir0__MASK 0x00000001U
14093
14094 #define R_PORT_PB_DIR__dir7__MAX 0x1
14095 #define R_PORT_PB_DIR__dir6__MAX 0x1
14096 #define R_PORT_PB_DIR__dir5__MAX 0x1
14097 #define R_PORT_PB_DIR__dir4__MAX 0x1
14098 #define R_PORT_PB_DIR__dir3__MAX 0x1
14099 #define R_PORT_PB_DIR__dir2__MAX 0x1
14100 #define R_PORT_PB_DIR__dir1__MAX 0x1
14101 #define R_PORT_PB_DIR__dir0__MAX 0x1
14102
14103 #define R_PORT_PB_DIR__dir7__MIN 0
14104 #define R_PORT_PB_DIR__dir6__MIN 0
14105 #define R_PORT_PB_DIR__dir5__MIN 0
14106 #define R_PORT_PB_DIR__dir4__MIN 0
14107 #define R_PORT_PB_DIR__dir3__MIN 0
14108 #define R_PORT_PB_DIR__dir2__MIN 0
14109 #define R_PORT_PB_DIR__dir1__MIN 0
14110 #define R_PORT_PB_DIR__dir0__MIN 0
14111
14112 #define R_PORT_PB_DIR__dir7__BITNR 7
14113 #define R_PORT_PB_DIR__dir6__BITNR 6
14114 #define R_PORT_PB_DIR__dir5__BITNR 5
14115 #define R_PORT_PB_DIR__dir4__BITNR 4
14116 #define R_PORT_PB_DIR__dir3__BITNR 3
14117 #define R_PORT_PB_DIR__dir2__BITNR 2
14118 #define R_PORT_PB_DIR__dir1__BITNR 1
14119 #define R_PORT_PB_DIR__dir0__BITNR 0
14120
14121 #define R_PORT_PB_DIR__dir7__dir7__VAL REG_VAL_ENUM
14122 #define R_PORT_PB_DIR__dir6__dir6__VAL REG_VAL_ENUM
14123 #define R_PORT_PB_DIR__dir5__dir5__VAL REG_VAL_ENUM
14124 #define R_PORT_PB_DIR__dir4__dir4__VAL REG_VAL_ENUM
14125 #define R_PORT_PB_DIR__dir3__dir3__VAL REG_VAL_ENUM
14126 #define R_PORT_PB_DIR__dir2__dir2__VAL REG_VAL_ENUM
14127 #define R_PORT_PB_DIR__dir1__dir1__VAL REG_VAL_ENUM
14128 #define R_PORT_PB_DIR__dir0__dir0__VAL REG_VAL_ENUM
14129
14130 #define R_PORT_PB_DIR__dir7__dir7__input 0
14131 #define R_PORT_PB_DIR__dir7__dir7__output 1
14132 #define R_PORT_PB_DIR__dir6__dir6__input 0
14133 #define R_PORT_PB_DIR__dir6__dir6__output 1
14134 #define R_PORT_PB_DIR__dir5__dir5__input 0
14135 #define R_PORT_PB_DIR__dir5__dir5__output 1
14136 #define R_PORT_PB_DIR__dir4__dir4__input 0
14137 #define R_PORT_PB_DIR__dir4__dir4__output 1
14138 #define R_PORT_PB_DIR__dir3__dir3__input 0
14139 #define R_PORT_PB_DIR__dir3__dir3__output 1
14140 #define R_PORT_PB_DIR__dir2__dir2__input 0
14141 #define R_PORT_PB_DIR__dir2__dir2__output 1
14142 #define R_PORT_PB_DIR__dir1__dir1__input 0
14143 #define R_PORT_PB_DIR__dir1__dir1__output 1
14144 #define R_PORT_PB_DIR__dir0__dir0__input 0
14145 #define R_PORT_PB_DIR__dir0__dir0__output 1
14146
14147 #endif
14148
14149 /*
14150 * R_PORT_PB_I2C
14151 * - type: WO
14152 * - addr: 0xb000003b
14153 * - group: General port configuration registers
14154 */
14155
14156 #if USE_GROUP__General_port_configuration_registers
14157
14158 #define R_PORT_PB_I2C__ADDR (REG_TYPECAST_BYTE 0xb000003b)
14159
14160 #ifndef REG_NO_SHADOW
14161 #define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 3))
14162 #define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 3))
14163 #else /* REG_NO_SHADOW */
14164 #define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
14165 #define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
14166 #endif /* REG_NO_SHADOW */
14167
14168 #define R_PORT_PB_I2C__STYPECAST REG_STYPECAST_BYTE
14169 #define R_PORT_PB_I2C__SVAL REG_SVAL_SHADOW
14170 #define R_PORT_PB_I2C__SVAL_I REG_SVAL_I_SHADOW
14171 #define R_PORT_PB_I2C__TYPECAST REG_TYPECAST_BYTE
14172 #define R_PORT_PB_I2C__TYPE (REG_BYTE)
14173 #define R_PORT_PB_I2C__GET REG_GET_WO
14174 #define R_PORT_PB_I2C__IGET REG_IGET_WO
14175 #define R_PORT_PB_I2C__SET REG_SET_WO
14176 #define R_PORT_PB_I2C__ISET REG_ISET_WO
14177 #define R_PORT_PB_I2C__SET_VAL REG_SET_VAL_WO
14178 #define R_PORT_PB_I2C__EQL REG_EQL_WO
14179 #define R_PORT_PB_I2C__IEQL REG_IEQL_WO
14180 #define R_PORT_PB_I2C__RD REG_RD_WO
14181 #define R_PORT_PB_I2C__IRD REG_IRD_WO
14182 #define R_PORT_PB_I2C__WR REG_WR_WO
14183 #define R_PORT_PB_I2C__IWR REG_IWR_WO
14184
14185 #define R_PORT_PB_I2C__WRITE(addr,value) \
14186 (*(addr) = (value))
14187
14188 #define R_PORT_PB_I2C__syncser3__syncser3__MASK 0x00000020U
14189 #define R_PORT_PB_I2C__syncser1__syncser1__MASK 0x00000010U
14190 #define R_PORT_PB_I2C__i2c_en__i2c_en__MASK 0x00000008U
14191 #define R_PORT_PB_I2C__i2c_d__i2c_d__MASK 0x00000004U
14192 #define R_PORT_PB_I2C__i2c_clk__i2c_clk__MASK 0x00000002U
14193 #define R_PORT_PB_I2C__i2c_oe___i2c_oe___MASK 0x00000001U
14194
14195 #define R_PORT_PB_I2C__syncser3__MAX 0x1
14196 #define R_PORT_PB_I2C__syncser1__MAX 0x1
14197 #define R_PORT_PB_I2C__i2c_en__MAX 0x1
14198 #define R_PORT_PB_I2C__i2c_d__MAX 1
14199 #define R_PORT_PB_I2C__i2c_clk__MAX 1
14200 #define R_PORT_PB_I2C__i2c_oe___MAX 0x1
14201
14202 #define R_PORT_PB_I2C__syncser3__MIN 0
14203 #define R_PORT_PB_I2C__syncser1__MIN 0
14204 #define R_PORT_PB_I2C__i2c_en__MIN 0
14205 #define R_PORT_PB_I2C__i2c_d__MIN 0
14206 #define R_PORT_PB_I2C__i2c_clk__MIN 0
14207 #define R_PORT_PB_I2C__i2c_oe___MIN 0
14208
14209 #define R_PORT_PB_I2C__syncser3__BITNR 5
14210 #define R_PORT_PB_I2C__syncser1__BITNR 4
14211 #define R_PORT_PB_I2C__i2c_en__BITNR 3
14212 #define R_PORT_PB_I2C__i2c_d__BITNR 2
14213 #define R_PORT_PB_I2C__i2c_clk__BITNR 1
14214 #define R_PORT_PB_I2C__i2c_oe___BITNR 0
14215
14216 #define R_PORT_PB_I2C__syncser3__syncser3__VAL REG_VAL_ENUM
14217 #define R_PORT_PB_I2C__syncser1__syncser1__VAL REG_VAL_ENUM
14218 #define R_PORT_PB_I2C__i2c_en__i2c_en__VAL REG_VAL_ENUM
14219 #define R_PORT_PB_I2C__i2c_d__i2c_d__VAL REG_VAL_VAL
14220 #define R_PORT_PB_I2C__i2c_clk__i2c_clk__VAL REG_VAL_VAL
14221 #define R_PORT_PB_I2C__i2c_oe___i2c_oe___VAL REG_VAL_ENUM
14222
14223 #define R_PORT_PB_I2C__syncser3__syncser3__port_cs 0
14224 #define R_PORT_PB_I2C__syncser3__syncser3__ss3extra 1
14225 #define R_PORT_PB_I2C__syncser1__syncser1__port_cs 0
14226 #define R_PORT_PB_I2C__syncser1__syncser1__ss1extra 1
14227 #define R_PORT_PB_I2C__i2c_en__i2c_en__off 0
14228 #define R_PORT_PB_I2C__i2c_en__i2c_en__on 1
14229 #define R_PORT_PB_I2C__i2c_oe___i2c_oe___disable 1
14230 #define R_PORT_PB_I2C__i2c_oe___i2c_oe___enable 0
14231
14232 #endif
14233
14234 /*
14235 * R_PORT_PB_READ
14236 * - type: RO
14237 * - addr: 0xb0000038
14238 * - group: General port configuration registers
14239 */
14240
14241 #if USE_GROUP__General_port_configuration_registers
14242
14243 #define R_PORT_PB_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000038)
14244 #define R_PORT_PB_READ__SVAL REG_SVAL_SHADOW
14245 #define R_PORT_PB_READ__SVAL_I REG_SVAL_I_SHADOW
14246 #define R_PORT_PB_READ__TYPECAST REG_TYPECAST_UDWORD
14247 #define R_PORT_PB_READ__TYPE (REG_UDWORD)
14248 #define R_PORT_PB_READ__GET REG_GET_RO
14249 #define R_PORT_PB_READ__IGET REG_IGET_RO
14250 #define R_PORT_PB_READ__SET REG_SET_RO
14251 #define R_PORT_PB_READ__ISET REG_ISET_RO
14252 #define R_PORT_PB_READ__SET_VAL REG_SET_VAL_RO
14253 #define R_PORT_PB_READ__EQL REG_EQL_RO
14254 #define R_PORT_PB_READ__IEQL REG_IEQL_RO
14255 #define R_PORT_PB_READ__RD REG_RD_RO
14256 #define R_PORT_PB_READ__IRD REG_IRD_RO
14257 #define R_PORT_PB_READ__WR REG_WR_RO
14258 #define R_PORT_PB_READ__IWR REG_IWR_RO
14259
14260 #define R_PORT_PB_READ__READ(addr) \
14261 (*(addr))
14262
14263 #define R_PORT_PB_READ__data_in__data_in__MASK 0x000000ffU
14264
14265 #define R_PORT_PB_READ__data_in__MAX 255
14266
14267 #define R_PORT_PB_READ__data_in__MIN 0
14268
14269 #define R_PORT_PB_READ__data_in__BITNR 0
14270
14271 #define R_PORT_PB_READ__data_in__data_in__VAL REG_VAL_VAL
14272
14273
14274 #endif
14275
14276 /*
14277 * R_PORT_PB_SET
14278 * - type: WO
14279 * - addr: 0xb0000038
14280 * - group: General port configuration registers
14281 */
14282
14283 #if USE_GROUP__General_port_configuration_registers
14284
14285 #define R_PORT_PB_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000038)
14286
14287 #ifndef REG_NO_SHADOW
14288 #define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PB_SET + 0))
14289 #define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PB_SET + 0))
14290 #else /* REG_NO_SHADOW */
14291 #define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
14292 #define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
14293 #endif /* REG_NO_SHADOW */
14294
14295 #define R_PORT_PB_SET__STYPECAST REG_STYPECAST_UDWORD
14296 #define R_PORT_PB_SET__SVAL REG_SVAL_SHADOW
14297 #define R_PORT_PB_SET__SVAL_I REG_SVAL_I_SHADOW
14298 #define R_PORT_PB_SET__TYPECAST REG_TYPECAST_UDWORD
14299 #define R_PORT_PB_SET__TYPE (REG_UDWORD)
14300 #define R_PORT_PB_SET__GET REG_GET_WO
14301 #define R_PORT_PB_SET__IGET REG_IGET_WO
14302 #define R_PORT_PB_SET__SET REG_SET_WO
14303 #define R_PORT_PB_SET__ISET REG_ISET_WO
14304 #define R_PORT_PB_SET__SET_VAL REG_SET_VAL_WO
14305 #define R_PORT_PB_SET__EQL REG_EQL_WO
14306 #define R_PORT_PB_SET__IEQL REG_IEQL_WO
14307 #define R_PORT_PB_SET__RD REG_RD_WO
14308 #define R_PORT_PB_SET__IRD REG_IRD_WO
14309 #define R_PORT_PB_SET__WR REG_WR_WO
14310 #define R_PORT_PB_SET__IWR REG_IWR_WO
14311
14312 #define R_PORT_PB_SET__WRITE(addr,value) \
14313 (*(addr) = (value))
14314
14315 #define R_PORT_PB_SET__syncser3__syncser3__MASK 0x20000000U
14316 #define R_PORT_PB_SET__syncser1__syncser1__MASK 0x10000000U
14317 #define R_PORT_PB_SET__i2c_en__i2c_en__MASK 0x08000000U
14318 #define R_PORT_PB_SET__i2c_d__i2c_d__MASK 0x04000000U
14319 #define R_PORT_PB_SET__i2c_clk__i2c_clk__MASK 0x02000000U
14320 #define R_PORT_PB_SET__i2c_oe___i2c_oe___MASK 0x01000000U
14321 #define R_PORT_PB_SET__cs7__cs7__MASK 0x00800000U
14322 #define R_PORT_PB_SET__cs6__cs6__MASK 0x00400000U
14323 #define R_PORT_PB_SET__cs5__cs5__MASK 0x00200000U
14324 #define R_PORT_PB_SET__cs4__cs4__MASK 0x00100000U
14325 #define R_PORT_PB_SET__cs3__cs3__MASK 0x00080000U
14326 #define R_PORT_PB_SET__cs2__cs2__MASK 0x00040000U
14327 #define R_PORT_PB_SET__scsi1__scsi1__MASK 0x00020000U
14328 #define R_PORT_PB_SET__scsi0__scsi0__MASK 0x00010000U
14329 #define R_PORT_PB_SET__dir7__dir7__MASK 0x00008000U
14330 #define R_PORT_PB_SET__dir6__dir6__MASK 0x00004000U
14331 #define R_PORT_PB_SET__dir5__dir5__MASK 0x00002000U
14332 #define R_PORT_PB_SET__dir4__dir4__MASK 0x00001000U
14333 #define R_PORT_PB_SET__dir3__dir3__MASK 0x00000800U
14334 #define R_PORT_PB_SET__dir2__dir2__MASK 0x00000400U
14335 #define R_PORT_PB_SET__dir1__dir1__MASK 0x00000200U
14336 #define R_PORT_PB_SET__dir0__dir0__MASK 0x00000100U
14337 #define R_PORT_PB_SET__data_out__data_out__MASK 0x000000ffU
14338
14339 #define R_PORT_PB_SET__syncser3__MAX 0x1
14340 #define R_PORT_PB_SET__syncser1__MAX 0x1
14341 #define R_PORT_PB_SET__i2c_en__MAX 0x1
14342 #define R_PORT_PB_SET__i2c_d__MAX 1
14343 #define R_PORT_PB_SET__i2c_clk__MAX 1
14344 #define R_PORT_PB_SET__i2c_oe___MAX 0x1
14345 #define R_PORT_PB_SET__cs7__MAX 0x1
14346 #define R_PORT_PB_SET__cs6__MAX 0x1
14347 #define R_PORT_PB_SET__cs5__MAX 0x1
14348 #define R_PORT_PB_SET__cs4__MAX 0x1
14349 #define R_PORT_PB_SET__cs3__MAX 0x1
14350 #define R_PORT_PB_SET__cs2__MAX 0x1
14351 #define R_PORT_PB_SET__scsi1__MAX 0x1
14352 #define R_PORT_PB_SET__scsi0__MAX 0x1
14353 #define R_PORT_PB_SET__dir7__MAX 0x1
14354 #define R_PORT_PB_SET__dir6__MAX 0x1
14355 #define R_PORT_PB_SET__dir5__MAX 0x1
14356 #define R_PORT_PB_SET__dir4__MAX 0x1
14357 #define R_PORT_PB_SET__dir3__MAX 0x1
14358 #define R_PORT_PB_SET__dir2__MAX 0x1
14359 #define R_PORT_PB_SET__dir1__MAX 0x1
14360 #define R_PORT_PB_SET__dir0__MAX 0x1
14361 #define R_PORT_PB_SET__data_out__MAX 255
14362
14363 #define R_PORT_PB_SET__syncser3__MIN 0
14364 #define R_PORT_PB_SET__syncser1__MIN 0
14365 #define R_PORT_PB_SET__i2c_en__MIN 0
14366 #define R_PORT_PB_SET__i2c_d__MIN 0
14367 #define R_PORT_PB_SET__i2c_clk__MIN 0
14368 #define R_PORT_PB_SET__i2c_oe___MIN 0
14369 #define R_PORT_PB_SET__cs7__MIN 0
14370 #define R_PORT_PB_SET__cs6__MIN 0
14371 #define R_PORT_PB_SET__cs5__MIN 0
14372 #define R_PORT_PB_SET__cs4__MIN 0
14373 #define R_PORT_PB_SET__cs3__MIN 0
14374 #define R_PORT_PB_SET__cs2__MIN 0
14375 #define R_PORT_PB_SET__scsi1__MIN 0
14376 #define R_PORT_PB_SET__scsi0__MIN 0
14377 #define R_PORT_PB_SET__dir7__MIN 0
14378 #define R_PORT_PB_SET__dir6__MIN 0
14379 #define R_PORT_PB_SET__dir5__MIN 0
14380 #define R_PORT_PB_SET__dir4__MIN 0
14381 #define R_PORT_PB_SET__dir3__MIN 0
14382 #define R_PORT_PB_SET__dir2__MIN 0
14383 #define R_PORT_PB_SET__dir1__MIN 0
14384 #define R_PORT_PB_SET__dir0__MIN 0
14385 #define R_PORT_PB_SET__data_out__MIN 0
14386
14387 #define R_PORT_PB_SET__syncser3__BITNR 29
14388 #define R_PORT_PB_SET__syncser1__BITNR 28
14389 #define R_PORT_PB_SET__i2c_en__BITNR 27
14390 #define R_PORT_PB_SET__i2c_d__BITNR 26
14391 #define R_PORT_PB_SET__i2c_clk__BITNR 25
14392 #define R_PORT_PB_SET__i2c_oe___BITNR 24
14393 #define R_PORT_PB_SET__cs7__BITNR 23
14394 #define R_PORT_PB_SET__cs6__BITNR 22
14395 #define R_PORT_PB_SET__cs5__BITNR 21
14396 #define R_PORT_PB_SET__cs4__BITNR 20
14397 #define R_PORT_PB_SET__cs3__BITNR 19
14398 #define R_PORT_PB_SET__cs2__BITNR 18
14399 #define R_PORT_PB_SET__scsi1__BITNR 17
14400 #define R_PORT_PB_SET__scsi0__BITNR 16
14401 #define R_PORT_PB_SET__dir7__BITNR 15
14402 #define R_PORT_PB_SET__dir6__BITNR 14
14403 #define R_PORT_PB_SET__dir5__BITNR 13
14404 #define R_PORT_PB_SET__dir4__BITNR 12
14405 #define R_PORT_PB_SET__dir3__BITNR 11
14406 #define R_PORT_PB_SET__dir2__BITNR 10
14407 #define R_PORT_PB_SET__dir1__BITNR 9
14408 #define R_PORT_PB_SET__dir0__BITNR 8
14409 #define R_PORT_PB_SET__data_out__BITNR 0
14410
14411 #define R_PORT_PB_SET__syncser3__syncser3__VAL REG_VAL_ENUM
14412 #define R_PORT_PB_SET__syncser1__syncser1__VAL REG_VAL_ENUM
14413 #define R_PORT_PB_SET__i2c_en__i2c_en__VAL REG_VAL_ENUM
14414 #define R_PORT_PB_SET__i2c_d__i2c_d__VAL REG_VAL_VAL
14415 #define R_PORT_PB_SET__i2c_clk__i2c_clk__VAL REG_VAL_VAL
14416 #define R_PORT_PB_SET__i2c_oe___i2c_oe___VAL REG_VAL_ENUM
14417 #define R_PORT_PB_SET__cs7__cs7__VAL REG_VAL_ENUM
14418 #define R_PORT_PB_SET__cs6__cs6__VAL REG_VAL_ENUM
14419 #define R_PORT_PB_SET__cs5__cs5__VAL REG_VAL_ENUM
14420 #define R_PORT_PB_SET__cs4__cs4__VAL REG_VAL_ENUM
14421 #define R_PORT_PB_SET__cs3__cs3__VAL REG_VAL_ENUM
14422 #define R_PORT_PB_SET__cs2__cs2__VAL REG_VAL_ENUM
14423 #define R_PORT_PB_SET__scsi1__scsi1__VAL REG_VAL_ENUM
14424 #define R_PORT_PB_SET__scsi0__scsi0__VAL REG_VAL_ENUM
14425 #define R_PORT_PB_SET__dir7__dir7__VAL REG_VAL_ENUM
14426 #define R_PORT_PB_SET__dir6__dir6__VAL REG_VAL_ENUM
14427 #define R_PORT_PB_SET__dir5__dir5__VAL REG_VAL_ENUM
14428 #define R_PORT_PB_SET__dir4__dir4__VAL REG_VAL_ENUM
14429 #define R_PORT_PB_SET__dir3__dir3__VAL REG_VAL_ENUM
14430 #define R_PORT_PB_SET__dir2__dir2__VAL REG_VAL_ENUM
14431 #define R_PORT_PB_SET__dir1__dir1__VAL REG_VAL_ENUM
14432 #define R_PORT_PB_SET__dir0__dir0__VAL REG_VAL_ENUM
14433 #define R_PORT_PB_SET__data_out__data_out__VAL REG_VAL_VAL
14434
14435 #define R_PORT_PB_SET__syncser3__syncser3__port_cs 0
14436 #define R_PORT_PB_SET__syncser3__syncser3__ss3extra 1
14437 #define R_PORT_PB_SET__syncser1__syncser1__port_cs 0
14438 #define R_PORT_PB_SET__syncser1__syncser1__ss1extra 1
14439 #define R_PORT_PB_SET__i2c_en__i2c_en__off 0
14440 #define R_PORT_PB_SET__i2c_en__i2c_en__on 1
14441 #define R_PORT_PB_SET__i2c_oe___i2c_oe___disable 1
14442 #define R_PORT_PB_SET__i2c_oe___i2c_oe___enable 0
14443 #define R_PORT_PB_SET__cs7__cs7__cs 1
14444 #define R_PORT_PB_SET__cs7__cs7__port 0
14445 #define R_PORT_PB_SET__cs6__cs6__cs 1
14446 #define R_PORT_PB_SET__cs6__cs6__port 0
14447 #define R_PORT_PB_SET__cs5__cs5__cs 1
14448 #define R_PORT_PB_SET__cs5__cs5__port 0
14449 #define R_PORT_PB_SET__cs4__cs4__cs 1
14450 #define R_PORT_PB_SET__cs4__cs4__port 0
14451 #define R_PORT_PB_SET__cs3__cs3__cs 1
14452 #define R_PORT_PB_SET__cs3__cs3__port 0
14453 #define R_PORT_PB_SET__cs2__cs2__cs 1
14454 #define R_PORT_PB_SET__cs2__cs2__port 0
14455 #define R_PORT_PB_SET__scsi1__scsi1__enph 1
14456 #define R_PORT_PB_SET__scsi1__scsi1__port_cs 0
14457 #define R_PORT_PB_SET__scsi0__scsi0__enph 1
14458 #define R_PORT_PB_SET__scsi0__scsi0__port_cs 0
14459 #define R_PORT_PB_SET__dir7__dir7__input 0
14460 #define R_PORT_PB_SET__dir7__dir7__output 1
14461 #define R_PORT_PB_SET__dir6__dir6__input 0
14462 #define R_PORT_PB_SET__dir6__dir6__output 1
14463 #define R_PORT_PB_SET__dir5__dir5__input 0
14464 #define R_PORT_PB_SET__dir5__dir5__output 1
14465 #define R_PORT_PB_SET__dir4__dir4__input 0
14466 #define R_PORT_PB_SET__dir4__dir4__output 1
14467 #define R_PORT_PB_SET__dir3__dir3__input 0
14468 #define R_PORT_PB_SET__dir3__dir3__output 1
14469 #define R_PORT_PB_SET__dir2__dir2__input 0
14470 #define R_PORT_PB_SET__dir2__dir2__output 1
14471 #define R_PORT_PB_SET__dir1__dir1__input 0
14472 #define R_PORT_PB_SET__dir1__dir1__output 1
14473 #define R_PORT_PB_SET__dir0__dir0__input 0
14474 #define R_PORT_PB_SET__dir0__dir0__output 1
14475
14476 #endif
14477
14478 /*
14479 * R_PRESCALE_STATUS
14480 * - type: RO
14481 * - addr: 0xb00000f0
14482 * - group: Timer registers
14483 */
14484
14485 #if USE_GROUP__Timer_registers
14486
14487 #define R_PRESCALE_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb00000f0)
14488 #define R_PRESCALE_STATUS__SVAL REG_SVAL_SHADOW
14489 #define R_PRESCALE_STATUS__SVAL_I REG_SVAL_I_SHADOW
14490 #define R_PRESCALE_STATUS__TYPECAST REG_TYPECAST_UDWORD
14491 #define R_PRESCALE_STATUS__TYPE (REG_UDWORD)
14492 #define R_PRESCALE_STATUS__GET REG_GET_RO
14493 #define R_PRESCALE_STATUS__IGET REG_IGET_RO
14494 #define R_PRESCALE_STATUS__SET REG_SET_RO
14495 #define R_PRESCALE_STATUS__ISET REG_ISET_RO
14496 #define R_PRESCALE_STATUS__SET_VAL REG_SET_VAL_RO
14497 #define R_PRESCALE_STATUS__EQL REG_EQL_RO
14498 #define R_PRESCALE_STATUS__IEQL REG_IEQL_RO
14499 #define R_PRESCALE_STATUS__RD REG_RD_RO
14500 #define R_PRESCALE_STATUS__IRD REG_IRD_RO
14501 #define R_PRESCALE_STATUS__WR REG_WR_RO
14502 #define R_PRESCALE_STATUS__IWR REG_IWR_RO
14503
14504 #define R_PRESCALE_STATUS__READ(addr) \
14505 (*(addr))
14506
14507 #define R_PRESCALE_STATUS__ser_status__ser_status__MASK 0xffff0000U
14508 #define R_PRESCALE_STATUS__tim_status__tim_status__MASK 0x0000ffffU
14509
14510 #define R_PRESCALE_STATUS__ser_status__MAX 0xffff
14511 #define R_PRESCALE_STATUS__tim_status__MAX 0xffff
14512
14513 #define R_PRESCALE_STATUS__ser_status__MIN 0
14514 #define R_PRESCALE_STATUS__tim_status__MIN 0
14515
14516 #define R_PRESCALE_STATUS__ser_status__BITNR 16
14517 #define R_PRESCALE_STATUS__tim_status__BITNR 0
14518
14519 #define R_PRESCALE_STATUS__ser_status__ser_status__VAL REG_VAL_VAL
14520 #define R_PRESCALE_STATUS__tim_status__tim_status__VAL REG_VAL_VAL
14521
14522
14523 #endif
14524
14525 /*
14526 * R_REC_COUNTERS
14527 * - type: RO
14528 * - addr: 0xb00000a4
14529 * - group: Network interface registers
14530 */
14531
14532 #if USE_GROUP__Network_interface_registers
14533
14534 #define R_REC_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a4)
14535 #define R_REC_COUNTERS__SVAL REG_SVAL_SHADOW
14536 #define R_REC_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
14537 #define R_REC_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
14538 #define R_REC_COUNTERS__TYPE (REG_UDWORD)
14539 #define R_REC_COUNTERS__GET REG_GET_RO
14540 #define R_REC_COUNTERS__IGET REG_IGET_RO
14541 #define R_REC_COUNTERS__SET REG_SET_RO
14542 #define R_REC_COUNTERS__ISET REG_ISET_RO
14543 #define R_REC_COUNTERS__SET_VAL REG_SET_VAL_RO
14544 #define R_REC_COUNTERS__EQL REG_EQL_RO
14545 #define R_REC_COUNTERS__IEQL REG_IEQL_RO
14546 #define R_REC_COUNTERS__RD REG_RD_RO
14547 #define R_REC_COUNTERS__IRD REG_IRD_RO
14548 #define R_REC_COUNTERS__WR REG_WR_RO
14549 #define R_REC_COUNTERS__IWR REG_IWR_RO
14550
14551 #define R_REC_COUNTERS__READ(addr) \
14552 (*(addr))
14553
14554 #define R_REC_COUNTERS__congestion__congestion__MASK 0xff000000U
14555 #define R_REC_COUNTERS__oversize__oversize__MASK 0x00ff0000U
14556 #define R_REC_COUNTERS__alignment_error__alignment_error__MASK 0x0000ff00U
14557 #define R_REC_COUNTERS__crc_error__crc_error__MASK 0x000000ffU
14558
14559 #define R_REC_COUNTERS__congestion__MAX 0xff
14560 #define R_REC_COUNTERS__oversize__MAX 0xff
14561 #define R_REC_COUNTERS__alignment_error__MAX 0xff
14562 #define R_REC_COUNTERS__crc_error__MAX 0xff
14563
14564 #define R_REC_COUNTERS__congestion__MIN 0
14565 #define R_REC_COUNTERS__oversize__MIN 0
14566 #define R_REC_COUNTERS__alignment_error__MIN 0
14567 #define R_REC_COUNTERS__crc_error__MIN 0
14568
14569 #define R_REC_COUNTERS__congestion__BITNR 24
14570 #define R_REC_COUNTERS__oversize__BITNR 16
14571 #define R_REC_COUNTERS__alignment_error__BITNR 8
14572 #define R_REC_COUNTERS__crc_error__BITNR 0
14573
14574 #define R_REC_COUNTERS__congestion__congestion__VAL REG_VAL_VAL
14575 #define R_REC_COUNTERS__oversize__oversize__VAL REG_VAL_VAL
14576 #define R_REC_COUNTERS__alignment_error__alignment_error__VAL REG_VAL_VAL
14577 #define R_REC_COUNTERS__crc_error__crc_error__VAL REG_VAL_VAL
14578
14579
14580 #endif
14581
14582 /*
14583 * R_SCSI0_CMD
14584 * - type: WO
14585 * - addr: 0xb0000042
14586 * - group: SCSI registers
14587 */
14588
14589 #if USE_GROUP__SCSI_registers
14590
14591 #define R_SCSI0_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000042)
14592
14593 #ifndef REG_NO_SHADOW
14594 #define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2))
14595 #define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2))
14596 #else /* REG_NO_SHADOW */
14597 #define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
14598 #define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
14599 #endif /* REG_NO_SHADOW */
14600
14601 #define R_SCSI0_CMD__STYPECAST REG_STYPECAST_BYTE
14602 #define R_SCSI0_CMD__SVAL REG_SVAL_SHADOW
14603 #define R_SCSI0_CMD__SVAL_I REG_SVAL_I_SHADOW
14604 #define R_SCSI0_CMD__TYPECAST REG_TYPECAST_BYTE
14605 #define R_SCSI0_CMD__TYPE (REG_BYTE)
14606 #define R_SCSI0_CMD__GET REG_GET_WO
14607 #define R_SCSI0_CMD__IGET REG_IGET_WO
14608 #define R_SCSI0_CMD__SET REG_SET_WO
14609 #define R_SCSI0_CMD__ISET REG_ISET_WO
14610 #define R_SCSI0_CMD__SET_VAL REG_SET_VAL_WO
14611 #define R_SCSI0_CMD__EQL REG_EQL_WO
14612 #define R_SCSI0_CMD__IEQL REG_IEQL_WO
14613 #define R_SCSI0_CMD__RD REG_RD_WO
14614 #define R_SCSI0_CMD__IRD REG_IRD_WO
14615 #define R_SCSI0_CMD__WR REG_WR_WO
14616 #define R_SCSI0_CMD__IWR REG_IWR_WO
14617
14618 #define R_SCSI0_CMD__WRITE(addr,value) \
14619 (*(addr) = (value))
14620
14621 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
14622 #define R_SCSI0_CMD__FIRST 0
14623 #define R_SCSI0_CMD__IOFFSET 12
14624 #define R_SCSI0_CMD__LAST 1
14625 #define R_SCSI0_CMD__OFFSET 16
14626 #define R_SCSI0_CMD__SOFFSET 12
14627 /* end */
14628
14629 #define R_SCSI0_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U
14630 #define R_SCSI0_CMD__command__command__MASK 0x0000000fU
14631
14632 #define R_SCSI0_CMD__asynch_setup__MAX 0xf
14633 #define R_SCSI0_CMD__command__MAX 0xf
14634
14635 #define R_SCSI0_CMD__asynch_setup__MIN 0
14636 #define R_SCSI0_CMD__command__MIN 0
14637
14638 #define R_SCSI0_CMD__asynch_setup__BITNR 4
14639 #define R_SCSI0_CMD__command__BITNR 0
14640
14641 #define R_SCSI0_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL
14642 #define R_SCSI0_CMD__command__command__VAL REG_VAL_ENUM
14643
14644 #define R_SCSI0_CMD__command__command__arb_only 6
14645 #define R_SCSI0_CMD__command__command__full_din_1 0
14646 #define R_SCSI0_CMD__command__command__full_din_3 8
14647 #define R_SCSI0_CMD__command__command__full_dout_1 1
14648 #define R_SCSI0_CMD__command__command__full_dout_3 9
14649 #define R_SCSI0_CMD__command__command__full_stat_1 2
14650 #define R_SCSI0_CMD__command__command__full_stat_3 10
14651 #define R_SCSI0_CMD__command__command__man_data_in 11
14652 #define R_SCSI0_CMD__command__command__man_data_out 12
14653 #define R_SCSI0_CMD__command__command__man_rat 13
14654 #define R_SCSI0_CMD__command__command__resel_din 3
14655 #define R_SCSI0_CMD__command__command__resel_dout 4
14656 #define R_SCSI0_CMD__command__command__resel_stat 5
14657
14658 #endif
14659
14660 /*
14661 * R_SCSI0_CMD_DATA
14662 * - type: WO
14663 * - addr: 0xb0000040
14664 * - group: SCSI registers
14665 */
14666
14667 #if USE_GROUP__SCSI_registers
14668
14669 #define R_SCSI0_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
14670
14671 #ifndef REG_NO_SHADOW
14672 #define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
14673 #define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
14674 #else /* REG_NO_SHADOW */
14675 #define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
14676 #define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
14677 #endif /* REG_NO_SHADOW */
14678
14679 #define R_SCSI0_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD
14680 #define R_SCSI0_CMD_DATA__SVAL REG_SVAL_SHADOW
14681 #define R_SCSI0_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW
14682 #define R_SCSI0_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD
14683 #define R_SCSI0_CMD_DATA__TYPE (REG_UDWORD)
14684 #define R_SCSI0_CMD_DATA__GET REG_GET_WO
14685 #define R_SCSI0_CMD_DATA__IGET REG_IGET_WO
14686 #define R_SCSI0_CMD_DATA__SET REG_SET_WO
14687 #define R_SCSI0_CMD_DATA__ISET REG_ISET_WO
14688 #define R_SCSI0_CMD_DATA__SET_VAL REG_SET_VAL_WO
14689 #define R_SCSI0_CMD_DATA__EQL REG_EQL_WO
14690 #define R_SCSI0_CMD_DATA__IEQL REG_IEQL_WO
14691 #define R_SCSI0_CMD_DATA__RD REG_RD_WO
14692 #define R_SCSI0_CMD_DATA__IRD REG_IRD_WO
14693 #define R_SCSI0_CMD_DATA__WR REG_WR_WO
14694 #define R_SCSI0_CMD_DATA__IWR REG_IWR_WO
14695
14696 #define R_SCSI0_CMD_DATA__WRITE(addr,value) \
14697 (*(addr) = (value))
14698
14699 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
14700 #define R_SCSI0_CMD_DATA__FIRST 0
14701 #define R_SCSI0_CMD_DATA__IOFFSET 12
14702 #define R_SCSI0_CMD_DATA__LAST 1
14703 #define R_SCSI0_CMD_DATA__OFFSET 16
14704 #define R_SCSI0_CMD_DATA__SOFFSET 12
14705 /* end */
14706
14707 #define R_SCSI0_CMD_DATA__parity_in__parity_in__MASK 0x04000000U
14708 #define R_SCSI0_CMD_DATA__skip__skip__MASK 0x02000000U
14709 #define R_SCSI0_CMD_DATA__clr_status__clr_status__MASK 0x01000000U
14710 #define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U
14711 #define R_SCSI0_CMD_DATA__command__command__MASK 0x000f0000U
14712 #define R_SCSI0_CMD_DATA__data_out__data_out__MASK 0x0000ffffU
14713
14714 #define R_SCSI0_CMD_DATA__parity_in__MAX 0x1
14715 #define R_SCSI0_CMD_DATA__skip__MAX 0x1
14716 #define R_SCSI0_CMD_DATA__clr_status__MAX 0x1
14717 #define R_SCSI0_CMD_DATA__asynch_setup__MAX 0xf
14718 #define R_SCSI0_CMD_DATA__command__MAX 0xf
14719 #define R_SCSI0_CMD_DATA__data_out__MAX 0xffff
14720
14721 #define R_SCSI0_CMD_DATA__parity_in__MIN 0
14722 #define R_SCSI0_CMD_DATA__skip__MIN 0
14723 #define R_SCSI0_CMD_DATA__clr_status__MIN 0
14724 #define R_SCSI0_CMD_DATA__asynch_setup__MIN 0
14725 #define R_SCSI0_CMD_DATA__command__MIN 0
14726 #define R_SCSI0_CMD_DATA__data_out__MIN 0
14727
14728 #define R_SCSI0_CMD_DATA__parity_in__BITNR 26
14729 #define R_SCSI0_CMD_DATA__skip__BITNR 25
14730 #define R_SCSI0_CMD_DATA__clr_status__BITNR 24
14731 #define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
14732 #define R_SCSI0_CMD_DATA__command__BITNR 16
14733 #define R_SCSI0_CMD_DATA__data_out__BITNR 0
14734
14735 #define R_SCSI0_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM
14736 #define R_SCSI0_CMD_DATA__skip__skip__VAL REG_VAL_ENUM
14737 #define R_SCSI0_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM
14738 #define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL
14739 #define R_SCSI0_CMD_DATA__command__command__VAL REG_VAL_ENUM
14740 #define R_SCSI0_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL
14741
14742 #define R_SCSI0_CMD_DATA__parity_in__parity_in__off 1
14743 #define R_SCSI0_CMD_DATA__parity_in__parity_in__on 0
14744 #define R_SCSI0_CMD_DATA__skip__skip__off 0
14745 #define R_SCSI0_CMD_DATA__skip__skip__on 1
14746 #define R_SCSI0_CMD_DATA__clr_status__clr_status__nop 0
14747 #define R_SCSI0_CMD_DATA__clr_status__clr_status__yes 1
14748 #define R_SCSI0_CMD_DATA__command__command__arb_only 6
14749 #define R_SCSI0_CMD_DATA__command__command__full_din_1 0
14750 #define R_SCSI0_CMD_DATA__command__command__full_din_3 8
14751 #define R_SCSI0_CMD_DATA__command__command__full_dout_1 1
14752 #define R_SCSI0_CMD_DATA__command__command__full_dout_3 9
14753 #define R_SCSI0_CMD_DATA__command__command__full_stat_1 2
14754 #define R_SCSI0_CMD_DATA__command__command__full_stat_3 10
14755 #define R_SCSI0_CMD_DATA__command__command__man_data_in 11
14756 #define R_SCSI0_CMD_DATA__command__command__man_data_out 12
14757 #define R_SCSI0_CMD_DATA__command__command__man_rat 13
14758 #define R_SCSI0_CMD_DATA__command__command__resel_din 3
14759 #define R_SCSI0_CMD_DATA__command__command__resel_dout 4
14760 #define R_SCSI0_CMD_DATA__command__command__resel_stat 5
14761
14762 #endif
14763
14764 /*
14765 * R_SCSI0_CTRL
14766 * - type: WO
14767 * - addr: 0xb0000044
14768 * - group: SCSI registers
14769 */
14770
14771 #if USE_GROUP__SCSI_registers
14772
14773 #define R_SCSI0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
14774
14775 #ifndef REG_NO_SHADOW
14776 #define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
14777 #define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
14778 #else /* REG_NO_SHADOW */
14779 #define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
14780 #define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
14781 #endif /* REG_NO_SHADOW */
14782
14783 #define R_SCSI0_CTRL__STYPECAST REG_STYPECAST_UDWORD
14784 #define R_SCSI0_CTRL__SVAL REG_SVAL_SHADOW
14785 #define R_SCSI0_CTRL__SVAL_I REG_SVAL_I_SHADOW
14786 #define R_SCSI0_CTRL__TYPECAST REG_TYPECAST_UDWORD
14787 #define R_SCSI0_CTRL__TYPE (REG_UDWORD)
14788 #define R_SCSI0_CTRL__GET REG_GET_WO
14789 #define R_SCSI0_CTRL__IGET REG_IGET_WO
14790 #define R_SCSI0_CTRL__SET REG_SET_WO
14791 #define R_SCSI0_CTRL__ISET REG_ISET_WO
14792 #define R_SCSI0_CTRL__SET_VAL REG_SET_VAL_WO
14793 #define R_SCSI0_CTRL__EQL REG_EQL_WO
14794 #define R_SCSI0_CTRL__IEQL REG_IEQL_WO
14795 #define R_SCSI0_CTRL__RD REG_RD_WO
14796 #define R_SCSI0_CTRL__IRD REG_IRD_WO
14797 #define R_SCSI0_CTRL__WR REG_WR_WO
14798 #define R_SCSI0_CTRL__IWR REG_IWR_WO
14799
14800 #define R_SCSI0_CTRL__WRITE(addr,value) \
14801 (*(addr) = (value))
14802
14803 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
14804 #define R_SCSI0_CTRL__FIRST 0
14805 #define R_SCSI0_CTRL__IOFFSET 12
14806 #define R_SCSI0_CTRL__LAST 1
14807 #define R_SCSI0_CTRL__OFFSET 16
14808 #define R_SCSI0_CTRL__SOFFSET 12
14809 /* end */
14810
14811 #define R_SCSI0_CTRL__id_type__id_type__MASK 0x80000000U
14812 #define R_SCSI0_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U
14813 #define R_SCSI0_CTRL__synch_per__synch_per__MASK 0x00ff0000U
14814 #define R_SCSI0_CTRL__rst__rst__MASK 0x00008000U
14815 #define R_SCSI0_CTRL__atn__atn__MASK 0x00004000U
14816 #define R_SCSI0_CTRL__my_id__my_id__MASK 0x00001e00U
14817 #define R_SCSI0_CTRL__target_id__target_id__MASK 0x000000f0U
14818 #define R_SCSI0_CTRL__fast_20__fast_20__MASK 0x00000008U
14819 #define R_SCSI0_CTRL__bus_width__bus_width__MASK 0x00000004U
14820 #define R_SCSI0_CTRL__synch__synch__MASK 0x00000002U
14821 #define R_SCSI0_CTRL__enable__enable__MASK 0x00000001U
14822
14823 #define R_SCSI0_CTRL__id_type__MAX 0x1
14824 #define R_SCSI0_CTRL__sel_timeout__MAX 0x7f
14825 #define R_SCSI0_CTRL__synch_per__MAX 0xff
14826 #define R_SCSI0_CTRL__rst__MAX 0x1
14827 #define R_SCSI0_CTRL__atn__MAX 0x1
14828 #define R_SCSI0_CTRL__my_id__MAX 0xf
14829 #define R_SCSI0_CTRL__target_id__MAX 0xf
14830 #define R_SCSI0_CTRL__fast_20__MAX 0x1
14831 #define R_SCSI0_CTRL__bus_width__MAX 0x1
14832 #define R_SCSI0_CTRL__synch__MAX 0x1
14833 #define R_SCSI0_CTRL__enable__MAX 0x1
14834
14835 #define R_SCSI0_CTRL__id_type__MIN 0
14836 #define R_SCSI0_CTRL__sel_timeout__MIN 0
14837 #define R_SCSI0_CTRL__synch_per__MIN 0
14838 #define R_SCSI0_CTRL__rst__MIN 0
14839 #define R_SCSI0_CTRL__atn__MIN 0
14840 #define R_SCSI0_CTRL__my_id__MIN 0
14841 #define R_SCSI0_CTRL__target_id__MIN 0
14842 #define R_SCSI0_CTRL__fast_20__MIN 0
14843 #define R_SCSI0_CTRL__bus_width__MIN 0
14844 #define R_SCSI0_CTRL__synch__MIN 0
14845 #define R_SCSI0_CTRL__enable__MIN 0
14846
14847 #define R_SCSI0_CTRL__id_type__BITNR 31
14848 #define R_SCSI0_CTRL__sel_timeout__BITNR 24
14849 #define R_SCSI0_CTRL__synch_per__BITNR 16
14850 #define R_SCSI0_CTRL__rst__BITNR 15
14851 #define R_SCSI0_CTRL__atn__BITNR 14
14852 #define R_SCSI0_CTRL__my_id__BITNR 9
14853 #define R_SCSI0_CTRL__target_id__BITNR 4
14854 #define R_SCSI0_CTRL__fast_20__BITNR 3
14855 #define R_SCSI0_CTRL__bus_width__BITNR 2
14856 #define R_SCSI0_CTRL__synch__BITNR 1
14857 #define R_SCSI0_CTRL__enable__BITNR 0
14858
14859 #define R_SCSI0_CTRL__id_type__id_type__VAL REG_VAL_ENUM
14860 #define R_SCSI0_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL
14861 #define R_SCSI0_CTRL__synch_per__synch_per__VAL REG_VAL_VAL
14862 #define R_SCSI0_CTRL__rst__rst__VAL REG_VAL_ENUM
14863 #define R_SCSI0_CTRL__atn__atn__VAL REG_VAL_ENUM
14864 #define R_SCSI0_CTRL__my_id__my_id__VAL REG_VAL_VAL
14865 #define R_SCSI0_CTRL__target_id__target_id__VAL REG_VAL_VAL
14866 #define R_SCSI0_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM
14867 #define R_SCSI0_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM
14868 #define R_SCSI0_CTRL__synch__synch__VAL REG_VAL_ENUM
14869 #define R_SCSI0_CTRL__enable__enable__VAL REG_VAL_ENUM
14870
14871 #define R_SCSI0_CTRL__id_type__id_type__hardware 0
14872 #define R_SCSI0_CTRL__id_type__id_type__software 1
14873 #define R_SCSI0_CTRL__rst__rst__no 0
14874 #define R_SCSI0_CTRL__rst__rst__yes 1
14875 #define R_SCSI0_CTRL__atn__atn__no 0
14876 #define R_SCSI0_CTRL__atn__atn__yes 1
14877 #define R_SCSI0_CTRL__fast_20__fast_20__no 0
14878 #define R_SCSI0_CTRL__fast_20__fast_20__yes 1
14879 #define R_SCSI0_CTRL__bus_width__bus_width__narrow 0
14880 #define R_SCSI0_CTRL__bus_width__bus_width__wide 1
14881 #define R_SCSI0_CTRL__synch__synch__asynch 0
14882 #define R_SCSI0_CTRL__synch__synch__synch 1
14883 #define R_SCSI0_CTRL__enable__enable__off 0
14884 #define R_SCSI0_CTRL__enable__enable__on 1
14885
14886 #endif
14887
14888 /*
14889 * R_SCSI0_DATA
14890 * - type: WO
14891 * - addr: 0xb0000040
14892 * - group: SCSI registers
14893 */
14894
14895 #if USE_GROUP__SCSI_registers
14896
14897 #define R_SCSI0_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040)
14898
14899 #ifndef REG_NO_SHADOW
14900 #define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
14901 #define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
14902 #else /* REG_NO_SHADOW */
14903 #define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
14904 #define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
14905 #endif /* REG_NO_SHADOW */
14906
14907 #define R_SCSI0_DATA__STYPECAST REG_STYPECAST_UWORD
14908 #define R_SCSI0_DATA__SVAL REG_SVAL_SHADOW
14909 #define R_SCSI0_DATA__SVAL_I REG_SVAL_I_SHADOW
14910 #define R_SCSI0_DATA__TYPECAST REG_TYPECAST_UWORD
14911 #define R_SCSI0_DATA__TYPE (REG_UWORD)
14912 #define R_SCSI0_DATA__GET REG_GET_WO
14913 #define R_SCSI0_DATA__IGET REG_IGET_WO
14914 #define R_SCSI0_DATA__SET REG_SET_WO
14915 #define R_SCSI0_DATA__ISET REG_ISET_WO
14916 #define R_SCSI0_DATA__SET_VAL REG_SET_VAL_WO
14917 #define R_SCSI0_DATA__EQL REG_EQL_WO
14918 #define R_SCSI0_DATA__IEQL REG_IEQL_WO
14919 #define R_SCSI0_DATA__RD REG_RD_WO
14920 #define R_SCSI0_DATA__IRD REG_IRD_WO
14921 #define R_SCSI0_DATA__WR REG_WR_WO
14922 #define R_SCSI0_DATA__IWR REG_IWR_WO
14923
14924 #define R_SCSI0_DATA__WRITE(addr,value) \
14925 (*(addr) = (value))
14926
14927 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
14928 #define R_SCSI0_DATA__FIRST 0
14929 #define R_SCSI0_DATA__IOFFSET 12
14930 #define R_SCSI0_DATA__LAST 1
14931 #define R_SCSI0_DATA__OFFSET 16
14932 #define R_SCSI0_DATA__SOFFSET 12
14933 /* end */
14934
14935 #define R_SCSI0_DATA__data_out__data_out__MASK 0x0000ffffU
14936
14937 #define R_SCSI0_DATA__data_out__MAX 0xffff
14938
14939 #define R_SCSI0_DATA__data_out__MIN 0
14940
14941 #define R_SCSI0_DATA__data_out__BITNR 0
14942
14943 #define R_SCSI0_DATA__data_out__data_out__VAL REG_VAL_VAL
14944
14945
14946 #endif
14947
14948 /*
14949 * R_SCSI0_DATA_IN
14950 * - type: RO
14951 * - addr: 0xb0000040
14952 * - group: SCSI registers
14953 */
14954
14955 #if USE_GROUP__SCSI_registers
14956
14957 #define R_SCSI0_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000040)
14958 #define R_SCSI0_DATA_IN__SVAL REG_SVAL_SHADOW
14959 #define R_SCSI0_DATA_IN__SVAL_I REG_SVAL_I_SHADOW
14960 #define R_SCSI0_DATA_IN__TYPECAST REG_TYPECAST_UWORD
14961 #define R_SCSI0_DATA_IN__TYPE (REG_UWORD)
14962 #define R_SCSI0_DATA_IN__GET REG_GET_RO
14963 #define R_SCSI0_DATA_IN__IGET REG_IGET_RO
14964 #define R_SCSI0_DATA_IN__SET REG_SET_RO
14965 #define R_SCSI0_DATA_IN__ISET REG_ISET_RO
14966 #define R_SCSI0_DATA_IN__SET_VAL REG_SET_VAL_RO
14967 #define R_SCSI0_DATA_IN__EQL REG_EQL_RO
14968 #define R_SCSI0_DATA_IN__IEQL REG_IEQL_RO
14969 #define R_SCSI0_DATA_IN__RD REG_RD_RO
14970 #define R_SCSI0_DATA_IN__IRD REG_IRD_RO
14971 #define R_SCSI0_DATA_IN__WR REG_WR_RO
14972 #define R_SCSI0_DATA_IN__IWR REG_IWR_RO
14973
14974 #define R_SCSI0_DATA_IN__READ(addr) \
14975 (*(addr))
14976
14977 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
14978 #define R_SCSI0_DATA_IN__FIRST 0
14979 #define R_SCSI0_DATA_IN__LAST 1
14980 #define R_SCSI0_DATA_IN__OFFSET 16
14981 /* end */
14982
14983 #define R_SCSI0_DATA_IN__data_in__data_in__MASK 0x0000ffffU
14984
14985 #define R_SCSI0_DATA_IN__data_in__MAX 0xffff
14986
14987 #define R_SCSI0_DATA_IN__data_in__MIN 0
14988
14989 #define R_SCSI0_DATA_IN__data_in__BITNR 0
14990
14991 #define R_SCSI0_DATA_IN__data_in__data_in__VAL REG_VAL_VAL
14992
14993
14994 #endif
14995
14996 /*
14997 * R_SCSI0_STATUS
14998 * - type: RO
14999 * - addr: 0xb0000048
15000 * - group: SCSI registers
15001 */
15002
15003 #if USE_GROUP__SCSI_registers
15004
15005 #define R_SCSI0_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
15006 #define R_SCSI0_STATUS__SVAL REG_SVAL_SHADOW
15007 #define R_SCSI0_STATUS__SVAL_I REG_SVAL_I_SHADOW
15008 #define R_SCSI0_STATUS__TYPECAST REG_TYPECAST_UDWORD
15009 #define R_SCSI0_STATUS__TYPE (REG_UDWORD)
15010 #define R_SCSI0_STATUS__GET REG_GET_RO
15011 #define R_SCSI0_STATUS__IGET REG_IGET_RO
15012 #define R_SCSI0_STATUS__SET REG_SET_RO
15013 #define R_SCSI0_STATUS__ISET REG_ISET_RO
15014 #define R_SCSI0_STATUS__SET_VAL REG_SET_VAL_RO
15015 #define R_SCSI0_STATUS__EQL REG_EQL_RO
15016 #define R_SCSI0_STATUS__IEQL REG_IEQL_RO
15017 #define R_SCSI0_STATUS__RD REG_RD_RO
15018 #define R_SCSI0_STATUS__IRD REG_IRD_RO
15019 #define R_SCSI0_STATUS__WR REG_WR_RO
15020 #define R_SCSI0_STATUS__IWR REG_IWR_RO
15021
15022 #define R_SCSI0_STATUS__READ(addr) \
15023 (*(addr))
15024
15025 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
15026 #define R_SCSI0_STATUS__FIRST 0
15027 #define R_SCSI0_STATUS__LAST 1
15028 #define R_SCSI0_STATUS__OFFSET 16
15029 /* end */
15030
15031 #define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U
15032 #define R_SCSI0_STATUS__tst_resel__tst_resel__MASK 0x00400000U
15033 #define R_SCSI0_STATUS__parity_error__parity_error__MASK 0x00200000U
15034 #define R_SCSI0_STATUS__bus_reset__bus_reset__MASK 0x00100000U
15035 #define R_SCSI0_STATUS__resel_target__resel_target__MASK 0x00078000U
15036 #define R_SCSI0_STATUS__resel__resel__MASK 0x00004000U
15037 #define R_SCSI0_STATUS__curr_phase__curr_phase__MASK 0x00003800U
15038 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U
15039 #define R_SCSI0_STATUS__valid_status__valid_status__MASK 0x00000020U
15040 #define R_SCSI0_STATUS__seq_status__seq_status__MASK 0x0000001fU
15041
15042 #define R_SCSI0_STATUS__tst_arb_won__MAX 0x1
15043 #define R_SCSI0_STATUS__tst_resel__MAX 0x1
15044 #define R_SCSI0_STATUS__parity_error__MAX 0x1
15045 #define R_SCSI0_STATUS__bus_reset__MAX 0x1
15046 #define R_SCSI0_STATUS__resel_target__MAX 0xf
15047 #define R_SCSI0_STATUS__resel__MAX 0x1
15048 #define R_SCSI0_STATUS__curr_phase__MAX 0x7
15049 #define R_SCSI0_STATUS__last_seq_step__MAX 0x1f
15050 #define R_SCSI0_STATUS__valid_status__MAX 0x1
15051 #define R_SCSI0_STATUS__seq_status__MAX 0x1f
15052
15053 #define R_SCSI0_STATUS__tst_arb_won__MIN 0
15054 #define R_SCSI0_STATUS__tst_resel__MIN 0
15055 #define R_SCSI0_STATUS__parity_error__MIN 0
15056 #define R_SCSI0_STATUS__bus_reset__MIN 0
15057 #define R_SCSI0_STATUS__resel_target__MIN 0
15058 #define R_SCSI0_STATUS__resel__MIN 0
15059 #define R_SCSI0_STATUS__curr_phase__MIN 0
15060 #define R_SCSI0_STATUS__last_seq_step__MIN 0
15061 #define R_SCSI0_STATUS__valid_status__MIN 0
15062 #define R_SCSI0_STATUS__seq_status__MIN 0
15063
15064 #define R_SCSI0_STATUS__tst_arb_won__BITNR 23
15065 #define R_SCSI0_STATUS__tst_resel__BITNR 22
15066 #define R_SCSI0_STATUS__parity_error__BITNR 21
15067 #define R_SCSI0_STATUS__bus_reset__BITNR 20
15068 #define R_SCSI0_STATUS__resel_target__BITNR 15
15069 #define R_SCSI0_STATUS__resel__BITNR 14
15070 #define R_SCSI0_STATUS__curr_phase__BITNR 11
15071 #define R_SCSI0_STATUS__last_seq_step__BITNR 6
15072 #define R_SCSI0_STATUS__valid_status__BITNR 5
15073 #define R_SCSI0_STATUS__seq_status__BITNR 0
15074
15075 #define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL
15076 #define R_SCSI0_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL
15077 #define R_SCSI0_STATUS__parity_error__parity_error__VAL REG_VAL_VAL
15078 #define R_SCSI0_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM
15079 #define R_SCSI0_STATUS__resel_target__resel_target__VAL REG_VAL_VAL
15080 #define R_SCSI0_STATUS__resel__resel__VAL REG_VAL_ENUM
15081 #define R_SCSI0_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM
15082 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM
15083 #define R_SCSI0_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM
15084 #define R_SCSI0_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM
15085
15086 #define R_SCSI0_STATUS__bus_reset__bus_reset__no 0
15087 #define R_SCSI0_STATUS__bus_reset__bus_reset__yes 1
15088 #define R_SCSI0_STATUS__resel__resel__no 0
15089 #define R_SCSI0_STATUS__resel__resel__yes 1
15090 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_command 2
15091 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_in 5
15092 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_out 4
15093 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_in 7
15094 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_out 6
15095 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_resel 1
15096 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_status 3
15097 #define R_SCSI0_STATUS__curr_phase__curr_phase__ph_undef 0
15098 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_answer 3
15099 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_arbitrate 8
15100 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_din 9
15101 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25
15102 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11
15103 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_bus_free 24
15104 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_cc 31
15105 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr 27
15106 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23
15107 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_good 14
15108 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual 28
15109 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18
15110 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_req 10
15111 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_1 2
15112 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_2 6
15113 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_3 22
15114 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_resel_req 29
15115 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7
15116 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din 13
15117 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12
15118 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5
15119 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1
15120 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout 0
15121 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4
15122 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30
15123 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transfer_done 15
15124 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20
15125 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21
15126 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17
15127 #define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16
15128 #define R_SCSI0_STATUS__valid_status__valid_status__no 0
15129 #define R_SCSI0_STATUS__valid_status__valid_status__yes 1
15130 #define R_SCSI0_STATUS__seq_status__seq_status__info_arb_lost 4
15131 #define R_SCSI0_STATUS__seq_status__seq_status__info_bus_free 13
15132 #define R_SCSI0_STATUS__seq_status__seq_status__info_bus_reset 11
15133 #define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_bf 12
15134 #define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_op 7
15135 #define R_SCSI0_STATUS__seq_status__seq_status__info_parity_error 1
15136 #define R_SCSI0_STATUS__seq_status__seq_status__info_rec_recvd 8
15137 #define R_SCSI0_STATUS__seq_status__seq_status__info_reselected 9
15138 #define R_SCSI0_STATUS__seq_status__seq_status__info_sel_timeout 5
15139 #define R_SCSI0_STATUS__seq_status__seq_status__info_seq_complete 0
15140 #define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_bf 6
15141 #define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_ph_change 3
15142 #define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_msg_in 2
15143 #define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_status 10
15144
15145 #endif
15146
15147 /*
15148 * R_SCSI0_STATUS_CTRL
15149 * - type: WO
15150 * - addr: 0xb0000043
15151 * - group: SCSI registers
15152 */
15153
15154 #if USE_GROUP__SCSI_registers
15155
15156 #define R_SCSI0_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000043)
15157
15158 #ifndef REG_NO_SHADOW
15159 #define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 3))
15160 #define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 3))
15161 #else /* REG_NO_SHADOW */
15162 #define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
15163 #define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
15164 #endif /* REG_NO_SHADOW */
15165
15166 #define R_SCSI0_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE
15167 #define R_SCSI0_STATUS_CTRL__SVAL REG_SVAL_SHADOW
15168 #define R_SCSI0_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW
15169 #define R_SCSI0_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE
15170 #define R_SCSI0_STATUS_CTRL__TYPE (REG_BYTE)
15171 #define R_SCSI0_STATUS_CTRL__GET REG_GET_WO
15172 #define R_SCSI0_STATUS_CTRL__IGET REG_IGET_WO
15173 #define R_SCSI0_STATUS_CTRL__SET REG_SET_WO
15174 #define R_SCSI0_STATUS_CTRL__ISET REG_ISET_WO
15175 #define R_SCSI0_STATUS_CTRL__SET_VAL REG_SET_VAL_WO
15176 #define R_SCSI0_STATUS_CTRL__EQL REG_EQL_WO
15177 #define R_SCSI0_STATUS_CTRL__IEQL REG_IEQL_WO
15178 #define R_SCSI0_STATUS_CTRL__RD REG_RD_WO
15179 #define R_SCSI0_STATUS_CTRL__IRD REG_IRD_WO
15180 #define R_SCSI0_STATUS_CTRL__WR REG_WR_WO
15181 #define R_SCSI0_STATUS_CTRL__IWR REG_IWR_WO
15182
15183 #define R_SCSI0_STATUS_CTRL__WRITE(addr,value) \
15184 (*(addr) = (value))
15185
15186 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
15187 #define R_SCSI0_STATUS_CTRL__FIRST 0
15188 #define R_SCSI0_STATUS_CTRL__IOFFSET 12
15189 #define R_SCSI0_STATUS_CTRL__LAST 1
15190 #define R_SCSI0_STATUS_CTRL__OFFSET 16
15191 #define R_SCSI0_STATUS_CTRL__SOFFSET 12
15192 /* end */
15193
15194 #define R_SCSI0_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U
15195 #define R_SCSI0_STATUS_CTRL__skip__skip__MASK 0x00000002U
15196 #define R_SCSI0_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U
15197
15198 #define R_SCSI0_STATUS_CTRL__parity_in__MAX 0x1
15199 #define R_SCSI0_STATUS_CTRL__skip__MAX 0x1
15200 #define R_SCSI0_STATUS_CTRL__clr_status__MAX 0x1
15201
15202 #define R_SCSI0_STATUS_CTRL__parity_in__MIN 0
15203 #define R_SCSI0_STATUS_CTRL__skip__MIN 0
15204 #define R_SCSI0_STATUS_CTRL__clr_status__MIN 0
15205
15206 #define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
15207 #define R_SCSI0_STATUS_CTRL__skip__BITNR 1
15208 #define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
15209
15210 #define R_SCSI0_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM
15211 #define R_SCSI0_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM
15212 #define R_SCSI0_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM
15213
15214 #define R_SCSI0_STATUS_CTRL__parity_in__parity_in__off 1
15215 #define R_SCSI0_STATUS_CTRL__parity_in__parity_in__on 0
15216 #define R_SCSI0_STATUS_CTRL__skip__skip__off 0
15217 #define R_SCSI0_STATUS_CTRL__skip__skip__on 1
15218 #define R_SCSI0_STATUS_CTRL__clr_status__clr_status__nop 0
15219 #define R_SCSI0_STATUS_CTRL__clr_status__clr_status__yes 1
15220
15221 #endif
15222
15223 /*
15224 * R_SCSI1_CMD
15225 * - type: WO
15226 * - addr: 0xb0000052
15227 * - group: SCSI registers
15228 */
15229
15230 #if USE_GROUP__SCSI_registers
15231
15232 #define R_SCSI1_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000052)
15233
15234 #ifndef REG_NO_SHADOW
15235 #define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
15236 #define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
15237 #else /* REG_NO_SHADOW */
15238 #define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
15239 #define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
15240 #endif /* REG_NO_SHADOW */
15241
15242 #define R_SCSI1_CMD__STYPECAST REG_STYPECAST_BYTE
15243 #define R_SCSI1_CMD__SVAL REG_SVAL_SHADOW
15244 #define R_SCSI1_CMD__SVAL_I REG_SVAL_I_SHADOW
15245 #define R_SCSI1_CMD__TYPECAST REG_TYPECAST_BYTE
15246 #define R_SCSI1_CMD__TYPE (REG_BYTE)
15247 #define R_SCSI1_CMD__GET REG_GET_WO
15248 #define R_SCSI1_CMD__IGET REG_IGET_WO
15249 #define R_SCSI1_CMD__SET REG_SET_WO
15250 #define R_SCSI1_CMD__ISET REG_ISET_WO
15251 #define R_SCSI1_CMD__SET_VAL REG_SET_VAL_WO
15252 #define R_SCSI1_CMD__EQL REG_EQL_WO
15253 #define R_SCSI1_CMD__IEQL REG_IEQL_WO
15254 #define R_SCSI1_CMD__RD REG_RD_WO
15255 #define R_SCSI1_CMD__IRD REG_IRD_WO
15256 #define R_SCSI1_CMD__WR REG_WR_WO
15257 #define R_SCSI1_CMD__IWR REG_IWR_WO
15258
15259 #define R_SCSI1_CMD__WRITE(addr,value) \
15260 (*(addr) = (value))
15261
15262 #define R_SCSI1_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U
15263 #define R_SCSI1_CMD__command__command__MASK 0x0000000fU
15264
15265 #define R_SCSI1_CMD__asynch_setup__MAX 0xf
15266 #define R_SCSI1_CMD__command__MAX 0xf
15267
15268 #define R_SCSI1_CMD__asynch_setup__MIN 0
15269 #define R_SCSI1_CMD__command__MIN 0
15270
15271 #define R_SCSI1_CMD__asynch_setup__BITNR 4
15272 #define R_SCSI1_CMD__command__BITNR 0
15273
15274 #define R_SCSI1_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL
15275 #define R_SCSI1_CMD__command__command__VAL REG_VAL_ENUM
15276
15277 #define R_SCSI1_CMD__command__command__arb_only 6
15278 #define R_SCSI1_CMD__command__command__full_din_1 0
15279 #define R_SCSI1_CMD__command__command__full_din_3 8
15280 #define R_SCSI1_CMD__command__command__full_dout_1 1
15281 #define R_SCSI1_CMD__command__command__full_dout_3 9
15282 #define R_SCSI1_CMD__command__command__full_stat_1 2
15283 #define R_SCSI1_CMD__command__command__full_stat_3 10
15284 #define R_SCSI1_CMD__command__command__man_data_in 11
15285 #define R_SCSI1_CMD__command__command__man_data_out 12
15286 #define R_SCSI1_CMD__command__command__man_rat 13
15287 #define R_SCSI1_CMD__command__command__resel_din 3
15288 #define R_SCSI1_CMD__command__command__resel_dout 4
15289 #define R_SCSI1_CMD__command__command__resel_stat 5
15290
15291 #endif
15292
15293 /*
15294 * R_SCSI1_CMD_DATA
15295 * - type: WO
15296 * - addr: 0xb0000050
15297 * - group: SCSI registers
15298 */
15299
15300 #if USE_GROUP__SCSI_registers
15301
15302 #define R_SCSI1_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
15303
15304 #ifndef REG_NO_SHADOW
15305 #define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
15306 #define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
15307 #else /* REG_NO_SHADOW */
15308 #define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
15309 #define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
15310 #endif /* REG_NO_SHADOW */
15311
15312 #define R_SCSI1_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD
15313 #define R_SCSI1_CMD_DATA__SVAL REG_SVAL_SHADOW
15314 #define R_SCSI1_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW
15315 #define R_SCSI1_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD
15316 #define R_SCSI1_CMD_DATA__TYPE (REG_UDWORD)
15317 #define R_SCSI1_CMD_DATA__GET REG_GET_WO
15318 #define R_SCSI1_CMD_DATA__IGET REG_IGET_WO
15319 #define R_SCSI1_CMD_DATA__SET REG_SET_WO
15320 #define R_SCSI1_CMD_DATA__ISET REG_ISET_WO
15321 #define R_SCSI1_CMD_DATA__SET_VAL REG_SET_VAL_WO
15322 #define R_SCSI1_CMD_DATA__EQL REG_EQL_WO
15323 #define R_SCSI1_CMD_DATA__IEQL REG_IEQL_WO
15324 #define R_SCSI1_CMD_DATA__RD REG_RD_WO
15325 #define R_SCSI1_CMD_DATA__IRD REG_IRD_WO
15326 #define R_SCSI1_CMD_DATA__WR REG_WR_WO
15327 #define R_SCSI1_CMD_DATA__IWR REG_IWR_WO
15328
15329 #define R_SCSI1_CMD_DATA__WRITE(addr,value) \
15330 (*(addr) = (value))
15331
15332 #define R_SCSI1_CMD_DATA__parity_in__parity_in__MASK 0x04000000U
15333 #define R_SCSI1_CMD_DATA__skip__skip__MASK 0x02000000U
15334 #define R_SCSI1_CMD_DATA__clr_status__clr_status__MASK 0x01000000U
15335 #define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U
15336 #define R_SCSI1_CMD_DATA__command__command__MASK 0x000f0000U
15337 #define R_SCSI1_CMD_DATA__data_out__data_out__MASK 0x0000ffffU
15338
15339 #define R_SCSI1_CMD_DATA__parity_in__MAX 0x1
15340 #define R_SCSI1_CMD_DATA__skip__MAX 0x1
15341 #define R_SCSI1_CMD_DATA__clr_status__MAX 0x1
15342 #define R_SCSI1_CMD_DATA__asynch_setup__MAX 0xf
15343 #define R_SCSI1_CMD_DATA__command__MAX 0xf
15344 #define R_SCSI1_CMD_DATA__data_out__MAX 0xffff
15345
15346 #define R_SCSI1_CMD_DATA__parity_in__MIN 0
15347 #define R_SCSI1_CMD_DATA__skip__MIN 0
15348 #define R_SCSI1_CMD_DATA__clr_status__MIN 0
15349 #define R_SCSI1_CMD_DATA__asynch_setup__MIN 0
15350 #define R_SCSI1_CMD_DATA__command__MIN 0
15351 #define R_SCSI1_CMD_DATA__data_out__MIN 0
15352
15353 #define R_SCSI1_CMD_DATA__parity_in__BITNR 26
15354 #define R_SCSI1_CMD_DATA__skip__BITNR 25
15355 #define R_SCSI1_CMD_DATA__clr_status__BITNR 24
15356 #define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
15357 #define R_SCSI1_CMD_DATA__command__BITNR 16
15358 #define R_SCSI1_CMD_DATA__data_out__BITNR 0
15359
15360 #define R_SCSI1_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM
15361 #define R_SCSI1_CMD_DATA__skip__skip__VAL REG_VAL_ENUM
15362 #define R_SCSI1_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM
15363 #define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL
15364 #define R_SCSI1_CMD_DATA__command__command__VAL REG_VAL_ENUM
15365 #define R_SCSI1_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL
15366
15367 #define R_SCSI1_CMD_DATA__parity_in__parity_in__off 1
15368 #define R_SCSI1_CMD_DATA__parity_in__parity_in__on 0
15369 #define R_SCSI1_CMD_DATA__skip__skip__off 0
15370 #define R_SCSI1_CMD_DATA__skip__skip__on 1
15371 #define R_SCSI1_CMD_DATA__clr_status__clr_status__nop 0
15372 #define R_SCSI1_CMD_DATA__clr_status__clr_status__yes 1
15373 #define R_SCSI1_CMD_DATA__command__command__arb_only 6
15374 #define R_SCSI1_CMD_DATA__command__command__full_din_1 0
15375 #define R_SCSI1_CMD_DATA__command__command__full_din_3 8
15376 #define R_SCSI1_CMD_DATA__command__command__full_dout_1 1
15377 #define R_SCSI1_CMD_DATA__command__command__full_dout_3 9
15378 #define R_SCSI1_CMD_DATA__command__command__full_stat_1 2
15379 #define R_SCSI1_CMD_DATA__command__command__full_stat_3 10
15380 #define R_SCSI1_CMD_DATA__command__command__man_data_in 11
15381 #define R_SCSI1_CMD_DATA__command__command__man_data_out 12
15382 #define R_SCSI1_CMD_DATA__command__command__man_rat 13
15383 #define R_SCSI1_CMD_DATA__command__command__resel_din 3
15384 #define R_SCSI1_CMD_DATA__command__command__resel_dout 4
15385 #define R_SCSI1_CMD_DATA__command__command__resel_stat 5
15386
15387 #endif
15388
15389 /*
15390 * R_SCSI1_CTRL
15391 * - type: WO
15392 * - addr: 0xb0000054
15393 * - group: SCSI registers
15394 */
15395
15396 #if USE_GROUP__SCSI_registers
15397
15398 #define R_SCSI1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000054)
15399
15400 #ifndef REG_NO_SHADOW
15401 #define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0))
15402 #define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0))
15403 #else /* REG_NO_SHADOW */
15404 #define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
15405 #define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
15406 #endif /* REG_NO_SHADOW */
15407
15408 #define R_SCSI1_CTRL__STYPECAST REG_STYPECAST_UDWORD
15409 #define R_SCSI1_CTRL__SVAL REG_SVAL_SHADOW
15410 #define R_SCSI1_CTRL__SVAL_I REG_SVAL_I_SHADOW
15411 #define R_SCSI1_CTRL__TYPECAST REG_TYPECAST_UDWORD
15412 #define R_SCSI1_CTRL__TYPE (REG_UDWORD)
15413 #define R_SCSI1_CTRL__GET REG_GET_WO
15414 #define R_SCSI1_CTRL__IGET REG_IGET_WO
15415 #define R_SCSI1_CTRL__SET REG_SET_WO
15416 #define R_SCSI1_CTRL__ISET REG_ISET_WO
15417 #define R_SCSI1_CTRL__SET_VAL REG_SET_VAL_WO
15418 #define R_SCSI1_CTRL__EQL REG_EQL_WO
15419 #define R_SCSI1_CTRL__IEQL REG_IEQL_WO
15420 #define R_SCSI1_CTRL__RD REG_RD_WO
15421 #define R_SCSI1_CTRL__IRD REG_IRD_WO
15422 #define R_SCSI1_CTRL__WR REG_WR_WO
15423 #define R_SCSI1_CTRL__IWR REG_IWR_WO
15424
15425 #define R_SCSI1_CTRL__WRITE(addr,value) \
15426 (*(addr) = (value))
15427
15428 #define R_SCSI1_CTRL__id_type__id_type__MASK 0x80000000U
15429 #define R_SCSI1_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U
15430 #define R_SCSI1_CTRL__synch_per__synch_per__MASK 0x00ff0000U
15431 #define R_SCSI1_CTRL__rst__rst__MASK 0x00008000U
15432 #define R_SCSI1_CTRL__atn__atn__MASK 0x00004000U
15433 #define R_SCSI1_CTRL__my_id__my_id__MASK 0x00001e00U
15434 #define R_SCSI1_CTRL__target_id__target_id__MASK 0x000000f0U
15435 #define R_SCSI1_CTRL__fast_20__fast_20__MASK 0x00000008U
15436 #define R_SCSI1_CTRL__bus_width__bus_width__MASK 0x00000004U
15437 #define R_SCSI1_CTRL__synch__synch__MASK 0x00000002U
15438 #define R_SCSI1_CTRL__enable__enable__MASK 0x00000001U
15439
15440 #define R_SCSI1_CTRL__id_type__MAX 0x1
15441 #define R_SCSI1_CTRL__sel_timeout__MAX 0x7f
15442 #define R_SCSI1_CTRL__synch_per__MAX 0xff
15443 #define R_SCSI1_CTRL__rst__MAX 0x1
15444 #define R_SCSI1_CTRL__atn__MAX 0x1
15445 #define R_SCSI1_CTRL__my_id__MAX 0xf
15446 #define R_SCSI1_CTRL__target_id__MAX 0xf
15447 #define R_SCSI1_CTRL__fast_20__MAX 0x1
15448 #define R_SCSI1_CTRL__bus_width__MAX 0x1
15449 #define R_SCSI1_CTRL__synch__MAX 0x1
15450 #define R_SCSI1_CTRL__enable__MAX 0x1
15451
15452 #define R_SCSI1_CTRL__id_type__MIN 0
15453 #define R_SCSI1_CTRL__sel_timeout__MIN 0
15454 #define R_SCSI1_CTRL__synch_per__MIN 0
15455 #define R_SCSI1_CTRL__rst__MIN 0
15456 #define R_SCSI1_CTRL__atn__MIN 0
15457 #define R_SCSI1_CTRL__my_id__MIN 0
15458 #define R_SCSI1_CTRL__target_id__MIN 0
15459 #define R_SCSI1_CTRL__fast_20__MIN 0
15460 #define R_SCSI1_CTRL__bus_width__MIN 0
15461 #define R_SCSI1_CTRL__synch__MIN 0
15462 #define R_SCSI1_CTRL__enable__MIN 0
15463
15464 #define R_SCSI1_CTRL__id_type__BITNR 31
15465 #define R_SCSI1_CTRL__sel_timeout__BITNR 24
15466 #define R_SCSI1_CTRL__synch_per__BITNR 16
15467 #define R_SCSI1_CTRL__rst__BITNR 15
15468 #define R_SCSI1_CTRL__atn__BITNR 14
15469 #define R_SCSI1_CTRL__my_id__BITNR 9
15470 #define R_SCSI1_CTRL__target_id__BITNR 4
15471 #define R_SCSI1_CTRL__fast_20__BITNR 3
15472 #define R_SCSI1_CTRL__bus_width__BITNR 2
15473 #define R_SCSI1_CTRL__synch__BITNR 1
15474 #define R_SCSI1_CTRL__enable__BITNR 0
15475
15476 #define R_SCSI1_CTRL__id_type__id_type__VAL REG_VAL_ENUM
15477 #define R_SCSI1_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL
15478 #define R_SCSI1_CTRL__synch_per__synch_per__VAL REG_VAL_VAL
15479 #define R_SCSI1_CTRL__rst__rst__VAL REG_VAL_ENUM
15480 #define R_SCSI1_CTRL__atn__atn__VAL REG_VAL_ENUM
15481 #define R_SCSI1_CTRL__my_id__my_id__VAL REG_VAL_VAL
15482 #define R_SCSI1_CTRL__target_id__target_id__VAL REG_VAL_VAL
15483 #define R_SCSI1_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM
15484 #define R_SCSI1_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM
15485 #define R_SCSI1_CTRL__synch__synch__VAL REG_VAL_ENUM
15486 #define R_SCSI1_CTRL__enable__enable__VAL REG_VAL_ENUM
15487
15488 #define R_SCSI1_CTRL__id_type__id_type__hardware 0
15489 #define R_SCSI1_CTRL__id_type__id_type__software 1
15490 #define R_SCSI1_CTRL__rst__rst__no 0
15491 #define R_SCSI1_CTRL__rst__rst__yes 1
15492 #define R_SCSI1_CTRL__atn__atn__no 0
15493 #define R_SCSI1_CTRL__atn__atn__yes 1
15494 #define R_SCSI1_CTRL__fast_20__fast_20__no 0
15495 #define R_SCSI1_CTRL__fast_20__fast_20__yes 1
15496 #define R_SCSI1_CTRL__bus_width__bus_width__narrow 0
15497 #define R_SCSI1_CTRL__bus_width__bus_width__wide 1
15498 #define R_SCSI1_CTRL__synch__synch__asynch 0
15499 #define R_SCSI1_CTRL__synch__synch__synch 1
15500 #define R_SCSI1_CTRL__enable__enable__off 0
15501 #define R_SCSI1_CTRL__enable__enable__on 1
15502
15503 #endif
15504
15505 /*
15506 * R_SCSI1_DATA
15507 * - type: WO
15508 * - addr: 0xb0000050
15509 * - group: SCSI registers
15510 */
15511
15512 #if USE_GROUP__SCSI_registers
15513
15514 #define R_SCSI1_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000050)
15515
15516 #ifndef REG_NO_SHADOW
15517 #define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
15518 #define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
15519 #else /* REG_NO_SHADOW */
15520 #define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
15521 #define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
15522 #endif /* REG_NO_SHADOW */
15523
15524 #define R_SCSI1_DATA__STYPECAST REG_STYPECAST_UWORD
15525 #define R_SCSI1_DATA__SVAL REG_SVAL_SHADOW
15526 #define R_SCSI1_DATA__SVAL_I REG_SVAL_I_SHADOW
15527 #define R_SCSI1_DATA__TYPECAST REG_TYPECAST_UWORD
15528 #define R_SCSI1_DATA__TYPE (REG_UWORD)
15529 #define R_SCSI1_DATA__GET REG_GET_WO
15530 #define R_SCSI1_DATA__IGET REG_IGET_WO
15531 #define R_SCSI1_DATA__SET REG_SET_WO
15532 #define R_SCSI1_DATA__ISET REG_ISET_WO
15533 #define R_SCSI1_DATA__SET_VAL REG_SET_VAL_WO
15534 #define R_SCSI1_DATA__EQL REG_EQL_WO
15535 #define R_SCSI1_DATA__IEQL REG_IEQL_WO
15536 #define R_SCSI1_DATA__RD REG_RD_WO
15537 #define R_SCSI1_DATA__IRD REG_IRD_WO
15538 #define R_SCSI1_DATA__WR REG_WR_WO
15539 #define R_SCSI1_DATA__IWR REG_IWR_WO
15540
15541 #define R_SCSI1_DATA__WRITE(addr,value) \
15542 (*(addr) = (value))
15543
15544 #define R_SCSI1_DATA__data_out__data_out__MASK 0x0000ffffU
15545
15546 #define R_SCSI1_DATA__data_out__MAX 0xffff
15547
15548 #define R_SCSI1_DATA__data_out__MIN 0
15549
15550 #define R_SCSI1_DATA__data_out__BITNR 0
15551
15552 #define R_SCSI1_DATA__data_out__data_out__VAL REG_VAL_VAL
15553
15554
15555 #endif
15556
15557 /*
15558 * R_SCSI1_DATA_IN
15559 * - type: RO
15560 * - addr: 0xb0000050
15561 * - group: SCSI registers
15562 */
15563
15564 #if USE_GROUP__SCSI_registers
15565
15566 #define R_SCSI1_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000050)
15567 #define R_SCSI1_DATA_IN__SVAL REG_SVAL_SHADOW
15568 #define R_SCSI1_DATA_IN__SVAL_I REG_SVAL_I_SHADOW
15569 #define R_SCSI1_DATA_IN__TYPECAST REG_TYPECAST_UWORD
15570 #define R_SCSI1_DATA_IN__TYPE (REG_UWORD)
15571 #define R_SCSI1_DATA_IN__GET REG_GET_RO
15572 #define R_SCSI1_DATA_IN__IGET REG_IGET_RO
15573 #define R_SCSI1_DATA_IN__SET REG_SET_RO
15574 #define R_SCSI1_DATA_IN__ISET REG_ISET_RO
15575 #define R_SCSI1_DATA_IN__SET_VAL REG_SET_VAL_RO
15576 #define R_SCSI1_DATA_IN__EQL REG_EQL_RO
15577 #define R_SCSI1_DATA_IN__IEQL REG_IEQL_RO
15578 #define R_SCSI1_DATA_IN__RD REG_RD_RO
15579 #define R_SCSI1_DATA_IN__IRD REG_IRD_RO
15580 #define R_SCSI1_DATA_IN__WR REG_WR_RO
15581 #define R_SCSI1_DATA_IN__IWR REG_IWR_RO
15582
15583 #define R_SCSI1_DATA_IN__READ(addr) \
15584 (*(addr))
15585
15586 #define R_SCSI1_DATA_IN__data_in__data_in__MASK 0x0000ffffU
15587
15588 #define R_SCSI1_DATA_IN__data_in__MAX 0xffff
15589
15590 #define R_SCSI1_DATA_IN__data_in__MIN 0
15591
15592 #define R_SCSI1_DATA_IN__data_in__BITNR 0
15593
15594 #define R_SCSI1_DATA_IN__data_in__data_in__VAL REG_VAL_VAL
15595
15596
15597 #endif
15598
15599 /*
15600 * R_SCSI1_STATUS
15601 * - type: RO
15602 * - addr: 0xb0000058
15603 * - group: SCSI registers
15604 */
15605
15606 #if USE_GROUP__SCSI_registers
15607
15608 #define R_SCSI1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000058)
15609 #define R_SCSI1_STATUS__SVAL REG_SVAL_SHADOW
15610 #define R_SCSI1_STATUS__SVAL_I REG_SVAL_I_SHADOW
15611 #define R_SCSI1_STATUS__TYPECAST REG_TYPECAST_UDWORD
15612 #define R_SCSI1_STATUS__TYPE (REG_UDWORD)
15613 #define R_SCSI1_STATUS__GET REG_GET_RO
15614 #define R_SCSI1_STATUS__IGET REG_IGET_RO
15615 #define R_SCSI1_STATUS__SET REG_SET_RO
15616 #define R_SCSI1_STATUS__ISET REG_ISET_RO
15617 #define R_SCSI1_STATUS__SET_VAL REG_SET_VAL_RO
15618 #define R_SCSI1_STATUS__EQL REG_EQL_RO
15619 #define R_SCSI1_STATUS__IEQL REG_IEQL_RO
15620 #define R_SCSI1_STATUS__RD REG_RD_RO
15621 #define R_SCSI1_STATUS__IRD REG_IRD_RO
15622 #define R_SCSI1_STATUS__WR REG_WR_RO
15623 #define R_SCSI1_STATUS__IWR REG_IWR_RO
15624
15625 #define R_SCSI1_STATUS__READ(addr) \
15626 (*(addr))
15627
15628 #define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U
15629 #define R_SCSI1_STATUS__tst_resel__tst_resel__MASK 0x00400000U
15630 #define R_SCSI1_STATUS__parity_error__parity_error__MASK 0x00200000U
15631 #define R_SCSI1_STATUS__bus_reset__bus_reset__MASK 0x00100000U
15632 #define R_SCSI1_STATUS__resel_target__resel_target__MASK 0x00078000U
15633 #define R_SCSI1_STATUS__resel__resel__MASK 0x00004000U
15634 #define R_SCSI1_STATUS__curr_phase__curr_phase__MASK 0x00003800U
15635 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U
15636 #define R_SCSI1_STATUS__valid_status__valid_status__MASK 0x00000020U
15637 #define R_SCSI1_STATUS__seq_status__seq_status__MASK 0x0000001fU
15638
15639 #define R_SCSI1_STATUS__tst_arb_won__MAX 0x1
15640 #define R_SCSI1_STATUS__tst_resel__MAX 0x1
15641 #define R_SCSI1_STATUS__parity_error__MAX 0x1
15642 #define R_SCSI1_STATUS__bus_reset__MAX 0x1
15643 #define R_SCSI1_STATUS__resel_target__MAX 0xf
15644 #define R_SCSI1_STATUS__resel__MAX 0x1
15645 #define R_SCSI1_STATUS__curr_phase__MAX 0x7
15646 #define R_SCSI1_STATUS__last_seq_step__MAX 0x1f
15647 #define R_SCSI1_STATUS__valid_status__MAX 0x1
15648 #define R_SCSI1_STATUS__seq_status__MAX 0x1f
15649
15650 #define R_SCSI1_STATUS__tst_arb_won__MIN 0
15651 #define R_SCSI1_STATUS__tst_resel__MIN 0
15652 #define R_SCSI1_STATUS__parity_error__MIN 0
15653 #define R_SCSI1_STATUS__bus_reset__MIN 0
15654 #define R_SCSI1_STATUS__resel_target__MIN 0
15655 #define R_SCSI1_STATUS__resel__MIN 0
15656 #define R_SCSI1_STATUS__curr_phase__MIN 0
15657 #define R_SCSI1_STATUS__last_seq_step__MIN 0
15658 #define R_SCSI1_STATUS__valid_status__MIN 0
15659 #define R_SCSI1_STATUS__seq_status__MIN 0
15660
15661 #define R_SCSI1_STATUS__tst_arb_won__BITNR 23
15662 #define R_SCSI1_STATUS__tst_resel__BITNR 22
15663 #define R_SCSI1_STATUS__parity_error__BITNR 21
15664 #define R_SCSI1_STATUS__bus_reset__BITNR 20
15665 #define R_SCSI1_STATUS__resel_target__BITNR 15
15666 #define R_SCSI1_STATUS__resel__BITNR 14
15667 #define R_SCSI1_STATUS__curr_phase__BITNR 11
15668 #define R_SCSI1_STATUS__last_seq_step__BITNR 6
15669 #define R_SCSI1_STATUS__valid_status__BITNR 5
15670 #define R_SCSI1_STATUS__seq_status__BITNR 0
15671
15672 #define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL
15673 #define R_SCSI1_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL
15674 #define R_SCSI1_STATUS__parity_error__parity_error__VAL REG_VAL_VAL
15675 #define R_SCSI1_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM
15676 #define R_SCSI1_STATUS__resel_target__resel_target__VAL REG_VAL_VAL
15677 #define R_SCSI1_STATUS__resel__resel__VAL REG_VAL_ENUM
15678 #define R_SCSI1_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM
15679 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM
15680 #define R_SCSI1_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM
15681 #define R_SCSI1_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM
15682
15683 #define R_SCSI1_STATUS__bus_reset__bus_reset__no 0
15684 #define R_SCSI1_STATUS__bus_reset__bus_reset__yes 1
15685 #define R_SCSI1_STATUS__resel__resel__no 0
15686 #define R_SCSI1_STATUS__resel__resel__yes 1
15687 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_command 2
15688 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_in 5
15689 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_out 4
15690 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_in 7
15691 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_out 6
15692 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_resel 1
15693 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_status 3
15694 #define R_SCSI1_STATUS__curr_phase__curr_phase__ph_undef 0
15695 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_answer 3
15696 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_arbitrate 8
15697 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_din 9
15698 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25
15699 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11
15700 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_bus_free 24
15701 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_cc 31
15702 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr 27
15703 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23
15704 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_good 14
15705 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual 28
15706 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18
15707 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_req 10
15708 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_1 2
15709 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_2 6
15710 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_3 22
15711 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_resel_req 29
15712 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7
15713 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din 13
15714 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12
15715 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5
15716 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1
15717 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout 0
15718 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4
15719 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30
15720 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transfer_done 15
15721 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20
15722 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21
15723 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17
15724 #define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16
15725 #define R_SCSI1_STATUS__valid_status__valid_status__no 0
15726 #define R_SCSI1_STATUS__valid_status__valid_status__yes 1
15727 #define R_SCSI1_STATUS__seq_status__seq_status__info_arb_lost 4
15728 #define R_SCSI1_STATUS__seq_status__seq_status__info_bus_free 13
15729 #define R_SCSI1_STATUS__seq_status__seq_status__info_bus_reset 11
15730 #define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_bf 12
15731 #define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_op 7
15732 #define R_SCSI1_STATUS__seq_status__seq_status__info_parity_error 1
15733 #define R_SCSI1_STATUS__seq_status__seq_status__info_rec_recvd 8
15734 #define R_SCSI1_STATUS__seq_status__seq_status__info_reselected 9
15735 #define R_SCSI1_STATUS__seq_status__seq_status__info_sel_timeout 5
15736 #define R_SCSI1_STATUS__seq_status__seq_status__info_seq_complete 0
15737 #define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_bf 6
15738 #define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_ph_change 3
15739 #define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_msg_in 2
15740 #define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_status 10
15741
15742 #endif
15743
15744 /*
15745 * R_SCSI1_STATUS_CTRL
15746 * - type: WO
15747 * - addr: 0xb0000053
15748 * - group: SCSI registers
15749 */
15750
15751 #if USE_GROUP__SCSI_registers
15752
15753 #define R_SCSI1_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000053)
15754
15755 #ifndef REG_NO_SHADOW
15756 #define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 3))
15757 #define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 3))
15758 #else /* REG_NO_SHADOW */
15759 #define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
15760 #define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
15761 #endif /* REG_NO_SHADOW */
15762
15763 #define R_SCSI1_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE
15764 #define R_SCSI1_STATUS_CTRL__SVAL REG_SVAL_SHADOW
15765 #define R_SCSI1_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW
15766 #define R_SCSI1_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE
15767 #define R_SCSI1_STATUS_CTRL__TYPE (REG_BYTE)
15768 #define R_SCSI1_STATUS_CTRL__GET REG_GET_WO
15769 #define R_SCSI1_STATUS_CTRL__IGET REG_IGET_WO
15770 #define R_SCSI1_STATUS_CTRL__SET REG_SET_WO
15771 #define R_SCSI1_STATUS_CTRL__ISET REG_ISET_WO
15772 #define R_SCSI1_STATUS_CTRL__SET_VAL REG_SET_VAL_WO
15773 #define R_SCSI1_STATUS_CTRL__EQL REG_EQL_WO
15774 #define R_SCSI1_STATUS_CTRL__IEQL REG_IEQL_WO
15775 #define R_SCSI1_STATUS_CTRL__RD REG_RD_WO
15776 #define R_SCSI1_STATUS_CTRL__IRD REG_IRD_WO
15777 #define R_SCSI1_STATUS_CTRL__WR REG_WR_WO
15778 #define R_SCSI1_STATUS_CTRL__IWR REG_IWR_WO
15779
15780 #define R_SCSI1_STATUS_CTRL__WRITE(addr,value) \
15781 (*(addr) = (value))
15782
15783 #define R_SCSI1_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U
15784 #define R_SCSI1_STATUS_CTRL__skip__skip__MASK 0x00000002U
15785 #define R_SCSI1_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U
15786
15787 #define R_SCSI1_STATUS_CTRL__parity_in__MAX 0x1
15788 #define R_SCSI1_STATUS_CTRL__skip__MAX 0x1
15789 #define R_SCSI1_STATUS_CTRL__clr_status__MAX 0x1
15790
15791 #define R_SCSI1_STATUS_CTRL__parity_in__MIN 0
15792 #define R_SCSI1_STATUS_CTRL__skip__MIN 0
15793 #define R_SCSI1_STATUS_CTRL__clr_status__MIN 0
15794
15795 #define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
15796 #define R_SCSI1_STATUS_CTRL__skip__BITNR 1
15797 #define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
15798
15799 #define R_SCSI1_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM
15800 #define R_SCSI1_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM
15801 #define R_SCSI1_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM
15802
15803 #define R_SCSI1_STATUS_CTRL__parity_in__parity_in__off 1
15804 #define R_SCSI1_STATUS_CTRL__parity_in__parity_in__on 0
15805 #define R_SCSI1_STATUS_CTRL__skip__skip__off 0
15806 #define R_SCSI1_STATUS_CTRL__skip__skip__on 1
15807 #define R_SCSI1_STATUS_CTRL__clr_status__clr_status__nop 0
15808 #define R_SCSI1_STATUS_CTRL__clr_status__clr_status__yes 1
15809
15810 #endif
15811
15812 /*
15813 * R_SDRAM_CONFIG
15814 * - type: WO
15815 * - addr: 0xb000000c
15816 * - group: Bus interface configuration registers
15817 */
15818
15819 #if USE_GROUP__Bus_interface_configuration_registers
15820
15821 #define R_SDRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c)
15822
15823 #ifndef REG_NO_SHADOW
15824 #define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0))
15825 #define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0))
15826 #else /* REG_NO_SHADOW */
15827 #define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
15828 #define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
15829 #endif /* REG_NO_SHADOW */
15830
15831 #define R_SDRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
15832 #define R_SDRAM_CONFIG__SVAL REG_SVAL_SHADOW
15833 #define R_SDRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
15834 #define R_SDRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
15835 #define R_SDRAM_CONFIG__TYPE (REG_UDWORD)
15836 #define R_SDRAM_CONFIG__GET REG_GET_WO
15837 #define R_SDRAM_CONFIG__IGET REG_IGET_WO
15838 #define R_SDRAM_CONFIG__SET REG_SET_WO
15839 #define R_SDRAM_CONFIG__ISET REG_ISET_WO
15840 #define R_SDRAM_CONFIG__SET_VAL REG_SET_VAL_WO
15841 #define R_SDRAM_CONFIG__EQL REG_EQL_WO
15842 #define R_SDRAM_CONFIG__IEQL REG_IEQL_WO
15843 #define R_SDRAM_CONFIG__RD REG_RD_WO
15844 #define R_SDRAM_CONFIG__IRD REG_IRD_WO
15845 #define R_SDRAM_CONFIG__WR REG_WR_WO
15846 #define R_SDRAM_CONFIG__IWR REG_IWR_WO
15847
15848 #define R_SDRAM_CONFIG__WRITE(addr,value) \
15849 (*(addr) = (value))
15850
15851 #define R_SDRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U
15852 #define R_SDRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U
15853 #define R_SDRAM_CONFIG__sh1__sh1__MASK 0x38000000U
15854 #define R_SDRAM_CONFIG__sh0__sh0__MASK 0x07000000U
15855 #define R_SDRAM_CONFIG__w__w__MASK 0x00800000U
15856 #define R_SDRAM_CONFIG__type1__type1__MASK 0x00400000U
15857 #define R_SDRAM_CONFIG__type0__type0__MASK 0x00200000U
15858 #define R_SDRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U
15859 #define R_SDRAM_CONFIG__ca1__ca1__MASK 0x0000e000U
15860 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__MASK 0x00001f00U
15861 #define R_SDRAM_CONFIG__ca0__ca0__MASK 0x000000e0U
15862 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__MASK 0x0000001fU
15863
15864 #define R_SDRAM_CONFIG__wmm1__MAX 0x1
15865 #define R_SDRAM_CONFIG__wmm0__MAX 0x1
15866 #define R_SDRAM_CONFIG__sh1__MAX 7
15867 #define R_SDRAM_CONFIG__sh0__MAX 7
15868 #define R_SDRAM_CONFIG__w__MAX 0x1
15869 #define R_SDRAM_CONFIG__type1__MAX 0x1
15870 #define R_SDRAM_CONFIG__type0__MAX 0x1
15871 #define R_SDRAM_CONFIG__group_sel__MAX 0x1f
15872 #define R_SDRAM_CONFIG__ca1__MAX 7
15873 #define R_SDRAM_CONFIG__bank_sel1__MAX 0x1f
15874 #define R_SDRAM_CONFIG__ca0__MAX 7
15875 #define R_SDRAM_CONFIG__bank_sel0__MAX 0x1f
15876
15877 #define R_SDRAM_CONFIG__wmm1__MIN 0
15878 #define R_SDRAM_CONFIG__wmm0__MIN 0
15879 #define R_SDRAM_CONFIG__sh1__MIN 0
15880 #define R_SDRAM_CONFIG__sh0__MIN 0
15881 #define R_SDRAM_CONFIG__w__MIN 0
15882 #define R_SDRAM_CONFIG__type1__MIN 0
15883 #define R_SDRAM_CONFIG__type0__MIN 0
15884 #define R_SDRAM_CONFIG__group_sel__MIN 0
15885 #define R_SDRAM_CONFIG__ca1__MIN 0
15886 #define R_SDRAM_CONFIG__bank_sel1__MIN 0
15887 #define R_SDRAM_CONFIG__ca0__MIN 0
15888 #define R_SDRAM_CONFIG__bank_sel0__MIN 0
15889
15890 #define R_SDRAM_CONFIG__wmm1__BITNR 31
15891 #define R_SDRAM_CONFIG__wmm0__BITNR 30
15892 #define R_SDRAM_CONFIG__sh1__BITNR 27
15893 #define R_SDRAM_CONFIG__sh0__BITNR 24
15894 #define R_SDRAM_CONFIG__w__BITNR 23
15895 #define R_SDRAM_CONFIG__type1__BITNR 22
15896 #define R_SDRAM_CONFIG__type0__BITNR 21
15897 #define R_SDRAM_CONFIG__group_sel__BITNR 16
15898 #define R_SDRAM_CONFIG__ca1__BITNR 13
15899 #define R_SDRAM_CONFIG__bank_sel1__BITNR 8
15900 #define R_SDRAM_CONFIG__ca0__BITNR 5
15901 #define R_SDRAM_CONFIG__bank_sel0__BITNR 0
15902
15903 #define R_SDRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM
15904 #define R_SDRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM
15905 #define R_SDRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL
15906 #define R_SDRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL
15907 #define R_SDRAM_CONFIG__w__w__VAL REG_VAL_ENUM
15908 #define R_SDRAM_CONFIG__type1__type1__VAL REG_VAL_ENUM
15909 #define R_SDRAM_CONFIG__type0__type0__VAL REG_VAL_ENUM
15910 #define R_SDRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM
15911 #define R_SDRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL
15912 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__VAL REG_VAL_ENUM
15913 #define R_SDRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL
15914 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__VAL REG_VAL_ENUM
15915
15916 #define R_SDRAM_CONFIG__wmm1__wmm1__norm 0
15917 #define R_SDRAM_CONFIG__wmm1__wmm1__wmm 1
15918 #define R_SDRAM_CONFIG__wmm0__wmm0__norm 0
15919 #define R_SDRAM_CONFIG__wmm0__wmm0__wmm 1
15920 #define R_SDRAM_CONFIG__w__w__bw16 0
15921 #define R_SDRAM_CONFIG__w__w__bw32 1
15922 #define R_SDRAM_CONFIG__type1__type1__bank2 0
15923 #define R_SDRAM_CONFIG__type1__type1__bank4 1
15924 #define R_SDRAM_CONFIG__type0__type0__bank2 0
15925 #define R_SDRAM_CONFIG__type0__type0__bank4 1
15926 #define R_SDRAM_CONFIG__group_sel__group_sel__bit10 10
15927 #define R_SDRAM_CONFIG__group_sel__group_sel__bit11 11
15928 #define R_SDRAM_CONFIG__group_sel__group_sel__bit12 12
15929 #define R_SDRAM_CONFIG__group_sel__group_sel__bit13 13
15930 #define R_SDRAM_CONFIG__group_sel__group_sel__bit14 14
15931 #define R_SDRAM_CONFIG__group_sel__group_sel__bit15 15
15932 #define R_SDRAM_CONFIG__group_sel__group_sel__bit16 16
15933 #define R_SDRAM_CONFIG__group_sel__group_sel__bit17 17
15934 #define R_SDRAM_CONFIG__group_sel__group_sel__bit18 18
15935 #define R_SDRAM_CONFIG__group_sel__group_sel__bit19 19
15936 #define R_SDRAM_CONFIG__group_sel__group_sel__bit20 20
15937 #define R_SDRAM_CONFIG__group_sel__group_sel__bit21 21
15938 #define R_SDRAM_CONFIG__group_sel__group_sel__bit22 22
15939 #define R_SDRAM_CONFIG__group_sel__group_sel__bit23 23
15940 #define R_SDRAM_CONFIG__group_sel__group_sel__bit24 24
15941 #define R_SDRAM_CONFIG__group_sel__group_sel__bit25 25
15942 #define R_SDRAM_CONFIG__group_sel__group_sel__bit26 26
15943 #define R_SDRAM_CONFIG__group_sel__group_sel__bit27 27
15944 #define R_SDRAM_CONFIG__group_sel__group_sel__bit28 28
15945 #define R_SDRAM_CONFIG__group_sel__group_sel__bit29 29
15946 #define R_SDRAM_CONFIG__group_sel__group_sel__bit9 9
15947 #define R_SDRAM_CONFIG__group_sel__group_sel__grp0 0
15948 #define R_SDRAM_CONFIG__group_sel__group_sel__grp1 1
15949 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit10 10
15950 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit11 11
15951 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit12 12
15952 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit13 13
15953 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit14 14
15954 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit15 15
15955 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit16 16
15956 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit17 17
15957 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit18 18
15958 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit19 19
15959 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit20 20
15960 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit21 21
15961 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit22 22
15962 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit23 23
15963 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit24 24
15964 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit25 25
15965 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit26 26
15966 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit27 27
15967 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit28 28
15968 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit29 29
15969 #define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit9 9
15970 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit10 10
15971 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit11 11
15972 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit12 12
15973 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit13 13
15974 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit14 14
15975 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit15 15
15976 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit16 16
15977 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit17 17
15978 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit18 18
15979 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit19 19
15980 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit20 20
15981 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit21 21
15982 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit22 22
15983 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit23 23
15984 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit24 24
15985 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit25 25
15986 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit26 26
15987 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit27 27
15988 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit28 28
15989 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit29 29
15990 #define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit9 9
15991
15992 #endif
15993
15994 /*
15995 * R_SDRAM_TIMING
15996 * - type: WO
15997 * - addr: 0xb0000008
15998 * - group: Bus interface configuration registers
15999 */
16000
16001 #if USE_GROUP__Bus_interface_configuration_registers
16002
16003 #define R_SDRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008)
16004
16005 #ifndef REG_NO_SHADOW
16006 #define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0))
16007 #define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0))
16008 #else /* REG_NO_SHADOW */
16009 #define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
16010 #define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
16011 #endif /* REG_NO_SHADOW */
16012
16013 #define R_SDRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD
16014 #define R_SDRAM_TIMING__SVAL REG_SVAL_SHADOW
16015 #define R_SDRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW
16016 #define R_SDRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD
16017 #define R_SDRAM_TIMING__TYPE (REG_UDWORD)
16018 #define R_SDRAM_TIMING__GET REG_GET_WO
16019 #define R_SDRAM_TIMING__IGET REG_IGET_WO
16020 #define R_SDRAM_TIMING__SET REG_SET_WO
16021 #define R_SDRAM_TIMING__ISET REG_ISET_WO
16022 #define R_SDRAM_TIMING__SET_VAL REG_SET_VAL_WO
16023 #define R_SDRAM_TIMING__EQL REG_EQL_WO
16024 #define R_SDRAM_TIMING__IEQL REG_IEQL_WO
16025 #define R_SDRAM_TIMING__RD REG_RD_WO
16026 #define R_SDRAM_TIMING__IRD REG_IRD_WO
16027 #define R_SDRAM_TIMING__WR REG_WR_WO
16028 #define R_SDRAM_TIMING__IWR REG_IWR_WO
16029
16030 #define R_SDRAM_TIMING__WRITE(addr,value) \
16031 (*(addr) = (value))
16032
16033 #define R_SDRAM_TIMING__sdram__sdram__MASK 0x80000000U
16034 #define R_SDRAM_TIMING__mrs_data__mrs_data__MASK 0x7fff0000U
16035 #define R_SDRAM_TIMING__ref__ref__MASK 0x0000c000U
16036 #define R_SDRAM_TIMING__ddr__ddr__MASK 0x00002000U
16037 #define R_SDRAM_TIMING__clk100__clk100__MASK 0x00001000U
16038 #define R_SDRAM_TIMING__ps__ps__MASK 0x00000800U
16039 #define R_SDRAM_TIMING__cmd__cmd__MASK 0x00000600U
16040 #define R_SDRAM_TIMING__pde__pde__MASK 0x00000100U
16041 #define R_SDRAM_TIMING__rc__rc__MASK 0x000000c0U
16042 #define R_SDRAM_TIMING__rp__rp__MASK 0x00000030U
16043 #define R_SDRAM_TIMING__rcd__rcd__MASK 0x0000000cU
16044 #define R_SDRAM_TIMING__cl__cl__MASK 0x00000003U
16045
16046 #define R_SDRAM_TIMING__sdram__MAX 0x1
16047 #define R_SDRAM_TIMING__mrs_data__MAX 0x7fff
16048 #define R_SDRAM_TIMING__ref__MAX 0x3
16049 #define R_SDRAM_TIMING__ddr__MAX 0x1
16050 #define R_SDRAM_TIMING__clk100__MAX 0x1
16051 #define R_SDRAM_TIMING__ps__MAX 0x1
16052 #define R_SDRAM_TIMING__cmd__MAX 0x3
16053 #define R_SDRAM_TIMING__pde__MAX 1
16054 #define R_SDRAM_TIMING__rc__MAX 3
16055 #define R_SDRAM_TIMING__rp__MAX 3
16056 #define R_SDRAM_TIMING__rcd__MAX 3
16057 #define R_SDRAM_TIMING__cl__MAX 2
16058
16059 #define R_SDRAM_TIMING__sdram__MIN 0
16060 #define R_SDRAM_TIMING__mrs_data__MIN 0
16061 #define R_SDRAM_TIMING__ref__MIN 0
16062 #define R_SDRAM_TIMING__ddr__MIN 0
16063 #define R_SDRAM_TIMING__clk100__MIN 0
16064 #define R_SDRAM_TIMING__ps__MIN 0
16065 #define R_SDRAM_TIMING__cmd__MIN 0
16066 #define R_SDRAM_TIMING__pde__MIN 0
16067 #define R_SDRAM_TIMING__rc__MIN 0
16068 #define R_SDRAM_TIMING__rp__MIN 0
16069 #define R_SDRAM_TIMING__rcd__MIN 0
16070 #define R_SDRAM_TIMING__cl__MIN 0
16071
16072 #define R_SDRAM_TIMING__sdram__BITNR 31
16073 #define R_SDRAM_TIMING__mrs_data__BITNR 16
16074 #define R_SDRAM_TIMING__ref__BITNR 14
16075 #define R_SDRAM_TIMING__ddr__BITNR 13
16076 #define R_SDRAM_TIMING__clk100__BITNR 12
16077 #define R_SDRAM_TIMING__ps__BITNR 11
16078 #define R_SDRAM_TIMING__cmd__BITNR 9
16079 #define R_SDRAM_TIMING__pde__BITNR 8
16080 #define R_SDRAM_TIMING__rc__BITNR 6
16081 #define R_SDRAM_TIMING__rp__BITNR 4
16082 #define R_SDRAM_TIMING__rcd__BITNR 2
16083 #define R_SDRAM_TIMING__cl__BITNR 0
16084
16085 #define R_SDRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM
16086 #define R_SDRAM_TIMING__mrs_data__mrs_data__VAL REG_VAL_VAL
16087 #define R_SDRAM_TIMING__ref__ref__VAL REG_VAL_ENUM
16088 #define R_SDRAM_TIMING__ddr__ddr__VAL REG_VAL_ENUM
16089 #define R_SDRAM_TIMING__clk100__clk100__VAL REG_VAL_ENUM
16090 #define R_SDRAM_TIMING__ps__ps__VAL REG_VAL_ENUM
16091 #define R_SDRAM_TIMING__cmd__cmd__VAL REG_VAL_ENUM
16092 #define R_SDRAM_TIMING__pde__pde__VAL REG_VAL_VAL
16093 #define R_SDRAM_TIMING__rc__rc__VAL REG_VAL_VAL
16094 #define R_SDRAM_TIMING__rp__rp__VAL REG_VAL_VAL
16095 #define R_SDRAM_TIMING__rcd__rcd__VAL REG_VAL_VAL
16096 #define R_SDRAM_TIMING__cl__cl__VAL REG_VAL_VAL
16097
16098 #define R_SDRAM_TIMING__sdram__sdram__disable 0
16099 #define R_SDRAM_TIMING__sdram__sdram__enable 1
16100 #define R_SDRAM_TIMING__ref__ref__disable 3
16101 #define R_SDRAM_TIMING__ref__ref__e13us 1
16102 #define R_SDRAM_TIMING__ref__ref__e52us 0
16103 #define R_SDRAM_TIMING__ref__ref__e6500ns 2
16104 #define R_SDRAM_TIMING__ddr__ddr__off 0
16105 #define R_SDRAM_TIMING__ddr__ddr__on 1
16106 #define R_SDRAM_TIMING__clk100__clk100__off 0
16107 #define R_SDRAM_TIMING__clk100__clk100__on 1
16108 #define R_SDRAM_TIMING__ps__ps__off 0
16109 #define R_SDRAM_TIMING__ps__ps__on 1
16110 #define R_SDRAM_TIMING__cmd__cmd__mrs 1
16111 #define R_SDRAM_TIMING__cmd__cmd__nop 0
16112 #define R_SDRAM_TIMING__cmd__cmd__pre 3
16113 #define R_SDRAM_TIMING__cmd__cmd__ref 2
16114
16115 #endif
16116
16117 /*
16118 * R_SERIAL0_BAUD
16119 * - type: WO
16120 * - addr: 0xb0000063
16121 * - group: Serial port registers
16122 */
16123
16124 #if USE_GROUP__Serial_port_registers
16125
16126 #define R_SERIAL0_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000063)
16127
16128 #ifndef REG_NO_SHADOW
16129 #define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 3))
16130 #define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 3))
16131 #else /* REG_NO_SHADOW */
16132 #define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
16133 #define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
16134 #endif /* REG_NO_SHADOW */
16135
16136 #define R_SERIAL0_BAUD__STYPECAST REG_STYPECAST_BYTE
16137 #define R_SERIAL0_BAUD__SVAL REG_SVAL_SHADOW
16138 #define R_SERIAL0_BAUD__SVAL_I REG_SVAL_I_SHADOW
16139 #define R_SERIAL0_BAUD__TYPECAST REG_TYPECAST_BYTE
16140 #define R_SERIAL0_BAUD__TYPE (REG_BYTE)
16141 #define R_SERIAL0_BAUD__GET REG_GET_WO
16142 #define R_SERIAL0_BAUD__IGET REG_IGET_WO
16143 #define R_SERIAL0_BAUD__SET REG_SET_WO
16144 #define R_SERIAL0_BAUD__ISET REG_ISET_WO
16145 #define R_SERIAL0_BAUD__SET_VAL REG_SET_VAL_WO
16146 #define R_SERIAL0_BAUD__EQL REG_EQL_WO
16147 #define R_SERIAL0_BAUD__IEQL REG_IEQL_WO
16148 #define R_SERIAL0_BAUD__RD REG_RD_WO
16149 #define R_SERIAL0_BAUD__IRD REG_IRD_WO
16150 #define R_SERIAL0_BAUD__WR REG_WR_WO
16151 #define R_SERIAL0_BAUD__IWR REG_IWR_WO
16152
16153 #define R_SERIAL0_BAUD__WRITE(addr,value) \
16154 (*(addr) = (value))
16155
16156 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16157 #define R_SERIAL0_BAUD__FIRST 0
16158 #define R_SERIAL0_BAUD__IOFFSET 8
16159 #define R_SERIAL0_BAUD__LAST 3
16160 #define R_SERIAL0_BAUD__OFFSET 8
16161 #define R_SERIAL0_BAUD__SOFFSET 8
16162 /* end */
16163
16164 #define R_SERIAL0_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
16165 #define R_SERIAL0_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
16166
16167 #define R_SERIAL0_BAUD__tr_baud__MAX 0xf
16168 #define R_SERIAL0_BAUD__rec_baud__MAX 0xf
16169
16170 #define R_SERIAL0_BAUD__tr_baud__MIN 0
16171 #define R_SERIAL0_BAUD__rec_baud__MIN 0
16172
16173 #define R_SERIAL0_BAUD__tr_baud__BITNR 4
16174 #define R_SERIAL0_BAUD__rec_baud__BITNR 0
16175
16176 #define R_SERIAL0_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
16177 #define R_SERIAL0_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
16178
16179 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c115k2Hz 9
16180 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c1200Hz 2
16181 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c1843k2Hz 13
16182 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c19k2Hz 6
16183 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c230k4Hz 10
16184 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c2400Hz 3
16185 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c300Hz 0
16186 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c38k4Hz 7
16187 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c460k8Hz 11
16188 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c4800Hz 4
16189 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c57k6Hz 8
16190 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c600Hz 1
16191 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c6250kHz 14
16192 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c921k6Hz 12
16193 #define R_SERIAL0_BAUD__tr_baud__tr_baud__c9600Hz 5
16194 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c115k2Hz 9
16195 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c1200Hz 2
16196 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c1843k2Hz 13
16197 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c19k2Hz 6
16198 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c230k4Hz 10
16199 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c2400Hz 3
16200 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c300Hz 0
16201 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c38k4Hz 7
16202 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c460k8Hz 11
16203 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c4800Hz 4
16204 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c57k6Hz 8
16205 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c600Hz 1
16206 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c6250kHz 14
16207 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c921k6Hz 12
16208 #define R_SERIAL0_BAUD__rec_baud__rec_baud__c9600Hz 5
16209
16210 #endif
16211
16212 /*
16213 * R_SERIAL0_CTRL
16214 * - type: WO
16215 * - addr: 0xb0000060
16216 * - group: Serial port registers
16217 */
16218
16219 #if USE_GROUP__Serial_port_registers
16220
16221 #define R_SERIAL0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000060)
16222
16223 #ifndef REG_NO_SHADOW
16224 #define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_CTRL + 0))
16225 #define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_CTRL + 0))
16226 #else /* REG_NO_SHADOW */
16227 #define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
16228 #define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
16229 #endif /* REG_NO_SHADOW */
16230
16231 #define R_SERIAL0_CTRL__STYPECAST REG_STYPECAST_UDWORD
16232 #define R_SERIAL0_CTRL__SVAL REG_SVAL_SHADOW
16233 #define R_SERIAL0_CTRL__SVAL_I REG_SVAL_I_SHADOW
16234 #define R_SERIAL0_CTRL__TYPECAST REG_TYPECAST_UDWORD
16235 #define R_SERIAL0_CTRL__TYPE (REG_UDWORD)
16236 #define R_SERIAL0_CTRL__GET REG_GET_WO
16237 #define R_SERIAL0_CTRL__IGET REG_IGET_WO
16238 #define R_SERIAL0_CTRL__SET REG_SET_WO
16239 #define R_SERIAL0_CTRL__ISET REG_ISET_WO
16240 #define R_SERIAL0_CTRL__SET_VAL REG_SET_VAL_WO
16241 #define R_SERIAL0_CTRL__EQL REG_EQL_WO
16242 #define R_SERIAL0_CTRL__IEQL REG_IEQL_WO
16243 #define R_SERIAL0_CTRL__RD REG_RD_WO
16244 #define R_SERIAL0_CTRL__IRD REG_IRD_WO
16245 #define R_SERIAL0_CTRL__WR REG_WR_WO
16246 #define R_SERIAL0_CTRL__IWR REG_IWR_WO
16247
16248 #define R_SERIAL0_CTRL__WRITE(addr,value) \
16249 (*(addr) = (value))
16250
16251 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16252 #define R_SERIAL0_CTRL__FIRST 0
16253 #define R_SERIAL0_CTRL__IOFFSET 8
16254 #define R_SERIAL0_CTRL__LAST 3
16255 #define R_SERIAL0_CTRL__OFFSET 8
16256 #define R_SERIAL0_CTRL__SOFFSET 8
16257 /* end */
16258
16259 #define R_SERIAL0_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
16260 #define R_SERIAL0_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
16261 #define R_SERIAL0_CTRL__dma_err__dma_err__MASK 0x00800000U
16262 #define R_SERIAL0_CTRL__rec_enable__rec_enable__MASK 0x00400000U
16263 #define R_SERIAL0_CTRL__rts___rts___MASK 0x00200000U
16264 #define R_SERIAL0_CTRL__sampling__sampling__MASK 0x00100000U
16265 #define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
16266 #define R_SERIAL0_CTRL__rec_par__rec_par__MASK 0x00040000U
16267 #define R_SERIAL0_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
16268 #define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
16269 #define R_SERIAL0_CTRL__txd__txd__MASK 0x00008000U
16270 #define R_SERIAL0_CTRL__tr_enable__tr_enable__MASK 0x00004000U
16271 #define R_SERIAL0_CTRL__auto_cts__auto_cts__MASK 0x00002000U
16272 #define R_SERIAL0_CTRL__stop_bits__stop_bits__MASK 0x00001000U
16273 #define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
16274 #define R_SERIAL0_CTRL__tr_par__tr_par__MASK 0x00000400U
16275 #define R_SERIAL0_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
16276 #define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
16277 #define R_SERIAL0_CTRL__data_out__data_out__MASK 0x000000ffU
16278
16279 #define R_SERIAL0_CTRL__tr_baud__MAX 0xf
16280 #define R_SERIAL0_CTRL__rec_baud__MAX 0xf
16281 #define R_SERIAL0_CTRL__dma_err__MAX 0x1
16282 #define R_SERIAL0_CTRL__rec_enable__MAX 0x1
16283 #define R_SERIAL0_CTRL__rts___MAX 0x1
16284 #define R_SERIAL0_CTRL__sampling__MAX 0x1
16285 #define R_SERIAL0_CTRL__rec_stick_par__MAX 0x1
16286 #define R_SERIAL0_CTRL__rec_par__MAX 0x1
16287 #define R_SERIAL0_CTRL__rec_par_en__MAX 0x1
16288 #define R_SERIAL0_CTRL__rec_bitnr__MAX 0x1
16289 #define R_SERIAL0_CTRL__txd__MAX 0x1
16290 #define R_SERIAL0_CTRL__tr_enable__MAX 0x1
16291 #define R_SERIAL0_CTRL__auto_cts__MAX 0x1
16292 #define R_SERIAL0_CTRL__stop_bits__MAX 0x1
16293 #define R_SERIAL0_CTRL__tr_stick_par__MAX 0x1
16294 #define R_SERIAL0_CTRL__tr_par__MAX 0x1
16295 #define R_SERIAL0_CTRL__tr_par_en__MAX 0x1
16296 #define R_SERIAL0_CTRL__tr_bitnr__MAX 0x1
16297 #define R_SERIAL0_CTRL__data_out__MAX 0xff
16298
16299 #define R_SERIAL0_CTRL__tr_baud__MIN 0
16300 #define R_SERIAL0_CTRL__rec_baud__MIN 0
16301 #define R_SERIAL0_CTRL__dma_err__MIN 0
16302 #define R_SERIAL0_CTRL__rec_enable__MIN 0
16303 #define R_SERIAL0_CTRL__rts___MIN 0
16304 #define R_SERIAL0_CTRL__sampling__MIN 0
16305 #define R_SERIAL0_CTRL__rec_stick_par__MIN 0
16306 #define R_SERIAL0_CTRL__rec_par__MIN 0
16307 #define R_SERIAL0_CTRL__rec_par_en__MIN 0
16308 #define R_SERIAL0_CTRL__rec_bitnr__MIN 0
16309 #define R_SERIAL0_CTRL__txd__MIN 0
16310 #define R_SERIAL0_CTRL__tr_enable__MIN 0
16311 #define R_SERIAL0_CTRL__auto_cts__MIN 0
16312 #define R_SERIAL0_CTRL__stop_bits__MIN 0
16313 #define R_SERIAL0_CTRL__tr_stick_par__MIN 0
16314 #define R_SERIAL0_CTRL__tr_par__MIN 0
16315 #define R_SERIAL0_CTRL__tr_par_en__MIN 0
16316 #define R_SERIAL0_CTRL__tr_bitnr__MIN 0
16317 #define R_SERIAL0_CTRL__data_out__MIN 0
16318
16319 #define R_SERIAL0_CTRL__tr_baud__BITNR 28
16320 #define R_SERIAL0_CTRL__rec_baud__BITNR 24
16321 #define R_SERIAL0_CTRL__dma_err__BITNR 23
16322 #define R_SERIAL0_CTRL__rec_enable__BITNR 22
16323 #define R_SERIAL0_CTRL__rts___BITNR 21
16324 #define R_SERIAL0_CTRL__sampling__BITNR 20
16325 #define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
16326 #define R_SERIAL0_CTRL__rec_par__BITNR 18
16327 #define R_SERIAL0_CTRL__rec_par_en__BITNR 17
16328 #define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
16329 #define R_SERIAL0_CTRL__txd__BITNR 15
16330 #define R_SERIAL0_CTRL__tr_enable__BITNR 14
16331 #define R_SERIAL0_CTRL__auto_cts__BITNR 13
16332 #define R_SERIAL0_CTRL__stop_bits__BITNR 12
16333 #define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
16334 #define R_SERIAL0_CTRL__tr_par__BITNR 10
16335 #define R_SERIAL0_CTRL__tr_par_en__BITNR 9
16336 #define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
16337 #define R_SERIAL0_CTRL__data_out__BITNR 0
16338
16339 #define R_SERIAL0_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
16340 #define R_SERIAL0_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
16341 #define R_SERIAL0_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
16342 #define R_SERIAL0_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
16343 #define R_SERIAL0_CTRL__rts___rts___VAL REG_VAL_ENUM
16344 #define R_SERIAL0_CTRL__sampling__sampling__VAL REG_VAL_ENUM
16345 #define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
16346 #define R_SERIAL0_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
16347 #define R_SERIAL0_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
16348 #define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
16349 #define R_SERIAL0_CTRL__txd__txd__VAL REG_VAL_VAL
16350 #define R_SERIAL0_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
16351 #define R_SERIAL0_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
16352 #define R_SERIAL0_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
16353 #define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
16354 #define R_SERIAL0_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
16355 #define R_SERIAL0_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
16356 #define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
16357 #define R_SERIAL0_CTRL__data_out__data_out__VAL REG_VAL_VAL
16358
16359 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c115k2Hz 9
16360 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c1200Hz 2
16361 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c1843k2Hz 13
16362 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c19k2Hz 6
16363 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c230k4Hz 10
16364 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c2400Hz 3
16365 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c300Hz 0
16366 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c38k4Hz 7
16367 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c460k8Hz 11
16368 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c4800Hz 4
16369 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c57k6Hz 8
16370 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c600Hz 1
16371 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c6250kHz 14
16372 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c921k6Hz 12
16373 #define R_SERIAL0_CTRL__tr_baud__tr_baud__c9600Hz 5
16374 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c115k2Hz 9
16375 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c1200Hz 2
16376 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c1843k2Hz 13
16377 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c19k2Hz 6
16378 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c230k4Hz 10
16379 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c2400Hz 3
16380 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c300Hz 0
16381 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c38k4Hz 7
16382 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c460k8Hz 11
16383 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c4800Hz 4
16384 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c57k6Hz 8
16385 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c600Hz 1
16386 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c6250kHz 14
16387 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c921k6Hz 12
16388 #define R_SERIAL0_CTRL__rec_baud__rec_baud__c9600Hz 5
16389 #define R_SERIAL0_CTRL__dma_err__dma_err__ignore 1
16390 #define R_SERIAL0_CTRL__dma_err__dma_err__stop 0
16391 #define R_SERIAL0_CTRL__rec_enable__rec_enable__disable 0
16392 #define R_SERIAL0_CTRL__rec_enable__rec_enable__enable 1
16393 #define R_SERIAL0_CTRL__rts___rts___active 0
16394 #define R_SERIAL0_CTRL__rts___rts___inactive 1
16395 #define R_SERIAL0_CTRL__sampling__sampling__majority 1
16396 #define R_SERIAL0_CTRL__sampling__sampling__middle 0
16397 #define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__normal 0
16398 #define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__stick 1
16399 #define R_SERIAL0_CTRL__rec_par__rec_par__even 0
16400 #define R_SERIAL0_CTRL__rec_par__rec_par__odd 1
16401 #define R_SERIAL0_CTRL__rec_par_en__rec_par_en__disable 0
16402 #define R_SERIAL0_CTRL__rec_par_en__rec_par_en__enable 1
16403 #define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
16404 #define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
16405 #define R_SERIAL0_CTRL__tr_enable__tr_enable__disable 0
16406 #define R_SERIAL0_CTRL__tr_enable__tr_enable__enable 1
16407 #define R_SERIAL0_CTRL__auto_cts__auto_cts__active 1
16408 #define R_SERIAL0_CTRL__auto_cts__auto_cts__disabled 0
16409 #define R_SERIAL0_CTRL__stop_bits__stop_bits__one_bit 0
16410 #define R_SERIAL0_CTRL__stop_bits__stop_bits__two_bits 1
16411 #define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__normal 0
16412 #define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__stick 1
16413 #define R_SERIAL0_CTRL__tr_par__tr_par__even 0
16414 #define R_SERIAL0_CTRL__tr_par__tr_par__odd 1
16415 #define R_SERIAL0_CTRL__tr_par_en__tr_par_en__disable 0
16416 #define R_SERIAL0_CTRL__tr_par_en__tr_par_en__enable 1
16417 #define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
16418 #define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
16419
16420 #endif
16421
16422 /*
16423 * R_SERIAL0_READ
16424 * - type: RO
16425 * - addr: 0xb0000060
16426 * - group: Serial port registers
16427 */
16428
16429 #if USE_GROUP__Serial_port_registers
16430
16431 #define R_SERIAL0_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000060)
16432 #define R_SERIAL0_READ__SVAL REG_SVAL_SHADOW
16433 #define R_SERIAL0_READ__SVAL_I REG_SVAL_I_SHADOW
16434 #define R_SERIAL0_READ__TYPECAST REG_TYPECAST_UDWORD
16435 #define R_SERIAL0_READ__TYPE (REG_UDWORD)
16436 #define R_SERIAL0_READ__GET REG_GET_RO
16437 #define R_SERIAL0_READ__IGET REG_IGET_RO
16438 #define R_SERIAL0_READ__SET REG_SET_RO
16439 #define R_SERIAL0_READ__ISET REG_ISET_RO
16440 #define R_SERIAL0_READ__SET_VAL REG_SET_VAL_RO
16441 #define R_SERIAL0_READ__EQL REG_EQL_RO
16442 #define R_SERIAL0_READ__IEQL REG_IEQL_RO
16443 #define R_SERIAL0_READ__RD REG_RD_RO
16444 #define R_SERIAL0_READ__IRD REG_IRD_RO
16445 #define R_SERIAL0_READ__WR REG_WR_RO
16446 #define R_SERIAL0_READ__IWR REG_IWR_RO
16447
16448 #define R_SERIAL0_READ__READ(addr) \
16449 (*(addr))
16450
16451 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16452 #define R_SERIAL0_READ__FIRST 0
16453 #define R_SERIAL0_READ__LAST 3
16454 #define R_SERIAL0_READ__OFFSET 8
16455 /* end */
16456
16457 #define R_SERIAL0_READ__xoff_detect__xoff_detect__MASK 0x00008000U
16458 #define R_SERIAL0_READ__cts___cts___MASK 0x00004000U
16459 #define R_SERIAL0_READ__tr_ready__tr_ready__MASK 0x00002000U
16460 #define R_SERIAL0_READ__rxd__rxd__MASK 0x00001000U
16461 #define R_SERIAL0_READ__overrun__overrun__MASK 0x00000800U
16462 #define R_SERIAL0_READ__par_err__par_err__MASK 0x00000400U
16463 #define R_SERIAL0_READ__framing_err__framing_err__MASK 0x00000200U
16464 #define R_SERIAL0_READ__data_avail__data_avail__MASK 0x00000100U
16465 #define R_SERIAL0_READ__data_in__data_in__MASK 0x000000ffU
16466
16467 #define R_SERIAL0_READ__xoff_detect__MAX 0x1
16468 #define R_SERIAL0_READ__cts___MAX 0x1
16469 #define R_SERIAL0_READ__tr_ready__MAX 0x1
16470 #define R_SERIAL0_READ__rxd__MAX 0x1
16471 #define R_SERIAL0_READ__overrun__MAX 0x1
16472 #define R_SERIAL0_READ__par_err__MAX 0x1
16473 #define R_SERIAL0_READ__framing_err__MAX 0x1
16474 #define R_SERIAL0_READ__data_avail__MAX 0x1
16475 #define R_SERIAL0_READ__data_in__MAX 0xff
16476
16477 #define R_SERIAL0_READ__xoff_detect__MIN 0
16478 #define R_SERIAL0_READ__cts___MIN 0
16479 #define R_SERIAL0_READ__tr_ready__MIN 0
16480 #define R_SERIAL0_READ__rxd__MIN 0
16481 #define R_SERIAL0_READ__overrun__MIN 0
16482 #define R_SERIAL0_READ__par_err__MIN 0
16483 #define R_SERIAL0_READ__framing_err__MIN 0
16484 #define R_SERIAL0_READ__data_avail__MIN 0
16485 #define R_SERIAL0_READ__data_in__MIN 0
16486
16487 #define R_SERIAL0_READ__xoff_detect__BITNR 15
16488 #define R_SERIAL0_READ__cts___BITNR 14
16489 #define R_SERIAL0_READ__tr_ready__BITNR 13
16490 #define R_SERIAL0_READ__rxd__BITNR 12
16491 #define R_SERIAL0_READ__overrun__BITNR 11
16492 #define R_SERIAL0_READ__par_err__BITNR 10
16493 #define R_SERIAL0_READ__framing_err__BITNR 9
16494 #define R_SERIAL0_READ__data_avail__BITNR 8
16495 #define R_SERIAL0_READ__data_in__BITNR 0
16496
16497 #define R_SERIAL0_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
16498 #define R_SERIAL0_READ__cts___cts___VAL REG_VAL_ENUM
16499 #define R_SERIAL0_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
16500 #define R_SERIAL0_READ__rxd__rxd__VAL REG_VAL_VAL
16501 #define R_SERIAL0_READ__overrun__overrun__VAL REG_VAL_ENUM
16502 #define R_SERIAL0_READ__par_err__par_err__VAL REG_VAL_ENUM
16503 #define R_SERIAL0_READ__framing_err__framing_err__VAL REG_VAL_ENUM
16504 #define R_SERIAL0_READ__data_avail__data_avail__VAL REG_VAL_ENUM
16505 #define R_SERIAL0_READ__data_in__data_in__VAL REG_VAL_VAL
16506
16507 #define R_SERIAL0_READ__xoff_detect__xoff_detect__no_xoff 0
16508 #define R_SERIAL0_READ__xoff_detect__xoff_detect__xoff 1
16509 #define R_SERIAL0_READ__cts___cts___active 0
16510 #define R_SERIAL0_READ__cts___cts___inactive 1
16511 #define R_SERIAL0_READ__tr_ready__tr_ready__full 0
16512 #define R_SERIAL0_READ__tr_ready__tr_ready__ready 1
16513 #define R_SERIAL0_READ__overrun__overrun__no 0
16514 #define R_SERIAL0_READ__overrun__overrun__yes 1
16515 #define R_SERIAL0_READ__par_err__par_err__no 0
16516 #define R_SERIAL0_READ__par_err__par_err__yes 1
16517 #define R_SERIAL0_READ__framing_err__framing_err__no 0
16518 #define R_SERIAL0_READ__framing_err__framing_err__yes 1
16519 #define R_SERIAL0_READ__data_avail__data_avail__no 0
16520 #define R_SERIAL0_READ__data_avail__data_avail__yes 1
16521
16522 #endif
16523
16524 /*
16525 * R_SERIAL0_REC_CTRL
16526 * - type: WO
16527 * - addr: 0xb0000062
16528 * - group: Serial port registers
16529 */
16530
16531 #if USE_GROUP__Serial_port_registers
16532
16533 #define R_SERIAL0_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000062)
16534
16535 #ifndef REG_NO_SHADOW
16536 #define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 2))
16537 #define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 2))
16538 #else /* REG_NO_SHADOW */
16539 #define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
16540 #define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
16541 #endif /* REG_NO_SHADOW */
16542
16543 #define R_SERIAL0_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
16544 #define R_SERIAL0_REC_CTRL__SVAL REG_SVAL_SHADOW
16545 #define R_SERIAL0_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
16546 #define R_SERIAL0_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
16547 #define R_SERIAL0_REC_CTRL__TYPE (REG_BYTE)
16548 #define R_SERIAL0_REC_CTRL__GET REG_GET_WO
16549 #define R_SERIAL0_REC_CTRL__IGET REG_IGET_WO
16550 #define R_SERIAL0_REC_CTRL__SET REG_SET_WO
16551 #define R_SERIAL0_REC_CTRL__ISET REG_ISET_WO
16552 #define R_SERIAL0_REC_CTRL__SET_VAL REG_SET_VAL_WO
16553 #define R_SERIAL0_REC_CTRL__EQL REG_EQL_WO
16554 #define R_SERIAL0_REC_CTRL__IEQL REG_IEQL_WO
16555 #define R_SERIAL0_REC_CTRL__RD REG_RD_WO
16556 #define R_SERIAL0_REC_CTRL__IRD REG_IRD_WO
16557 #define R_SERIAL0_REC_CTRL__WR REG_WR_WO
16558 #define R_SERIAL0_REC_CTRL__IWR REG_IWR_WO
16559
16560 #define R_SERIAL0_REC_CTRL__WRITE(addr,value) \
16561 (*(addr) = (value))
16562
16563 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16564 #define R_SERIAL0_REC_CTRL__FIRST 0
16565 #define R_SERIAL0_REC_CTRL__IOFFSET 8
16566 #define R_SERIAL0_REC_CTRL__LAST 3
16567 #define R_SERIAL0_REC_CTRL__OFFSET 8
16568 #define R_SERIAL0_REC_CTRL__SOFFSET 8
16569 /* end */
16570
16571 #define R_SERIAL0_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
16572 #define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
16573 #define R_SERIAL0_REC_CTRL__rts___rts___MASK 0x00000020U
16574 #define R_SERIAL0_REC_CTRL__sampling__sampling__MASK 0x00000010U
16575 #define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
16576 #define R_SERIAL0_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
16577 #define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
16578 #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
16579
16580 #define R_SERIAL0_REC_CTRL__dma_err__MAX 0x1
16581 #define R_SERIAL0_REC_CTRL__rec_enable__MAX 0x1
16582 #define R_SERIAL0_REC_CTRL__rts___MAX 0x1
16583 #define R_SERIAL0_REC_CTRL__sampling__MAX 0x1
16584 #define R_SERIAL0_REC_CTRL__rec_stick_par__MAX 0x1
16585 #define R_SERIAL0_REC_CTRL__rec_par__MAX 0x1
16586 #define R_SERIAL0_REC_CTRL__rec_par_en__MAX 0x1
16587 #define R_SERIAL0_REC_CTRL__rec_bitnr__MAX 0x1
16588
16589 #define R_SERIAL0_REC_CTRL__dma_err__MIN 0
16590 #define R_SERIAL0_REC_CTRL__rec_enable__MIN 0
16591 #define R_SERIAL0_REC_CTRL__rts___MIN 0
16592 #define R_SERIAL0_REC_CTRL__sampling__MIN 0
16593 #define R_SERIAL0_REC_CTRL__rec_stick_par__MIN 0
16594 #define R_SERIAL0_REC_CTRL__rec_par__MIN 0
16595 #define R_SERIAL0_REC_CTRL__rec_par_en__MIN 0
16596 #define R_SERIAL0_REC_CTRL__rec_bitnr__MIN 0
16597
16598 #define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
16599 #define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
16600 #define R_SERIAL0_REC_CTRL__rts___BITNR 5
16601 #define R_SERIAL0_REC_CTRL__sampling__BITNR 4
16602 #define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
16603 #define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
16604 #define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
16605 #define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
16606
16607 #define R_SERIAL0_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
16608 #define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
16609 #define R_SERIAL0_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
16610 #define R_SERIAL0_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
16611 #define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
16612 #define R_SERIAL0_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
16613 #define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
16614 #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
16615
16616 #define R_SERIAL0_REC_CTRL__dma_err__dma_err__ignore 1
16617 #define R_SERIAL0_REC_CTRL__dma_err__dma_err__stop 0
16618 #define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__disable 0
16619 #define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__enable 1
16620 #define R_SERIAL0_REC_CTRL__rts___rts___active 0
16621 #define R_SERIAL0_REC_CTRL__rts___rts___inactive 1
16622 #define R_SERIAL0_REC_CTRL__sampling__sampling__majority 1
16623 #define R_SERIAL0_REC_CTRL__sampling__sampling__middle 0
16624 #define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
16625 #define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
16626 #define R_SERIAL0_REC_CTRL__rec_par__rec_par__even 0
16627 #define R_SERIAL0_REC_CTRL__rec_par__rec_par__odd 1
16628 #define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__disable 0
16629 #define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__enable 1
16630 #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
16631 #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
16632
16633 #endif
16634
16635 /*
16636 * R_SERIAL0_REC_DATA
16637 * - type: RO
16638 * - addr: 0xb0000060
16639 * - group: Serial port registers
16640 */
16641
16642 #if USE_GROUP__Serial_port_registers
16643
16644 #define R_SERIAL0_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060)
16645 #define R_SERIAL0_REC_DATA__SVAL REG_SVAL_SHADOW
16646 #define R_SERIAL0_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
16647 #define R_SERIAL0_REC_DATA__TYPECAST REG_TYPECAST_BYTE
16648 #define R_SERIAL0_REC_DATA__TYPE (REG_BYTE)
16649 #define R_SERIAL0_REC_DATA__GET REG_GET_RO
16650 #define R_SERIAL0_REC_DATA__IGET REG_IGET_RO
16651 #define R_SERIAL0_REC_DATA__SET REG_SET_RO
16652 #define R_SERIAL0_REC_DATA__ISET REG_ISET_RO
16653 #define R_SERIAL0_REC_DATA__SET_VAL REG_SET_VAL_RO
16654 #define R_SERIAL0_REC_DATA__EQL REG_EQL_RO
16655 #define R_SERIAL0_REC_DATA__IEQL REG_IEQL_RO
16656 #define R_SERIAL0_REC_DATA__RD REG_RD_RO
16657 #define R_SERIAL0_REC_DATA__IRD REG_IRD_RO
16658 #define R_SERIAL0_REC_DATA__WR REG_WR_RO
16659 #define R_SERIAL0_REC_DATA__IWR REG_IWR_RO
16660
16661 #define R_SERIAL0_REC_DATA__READ(addr) \
16662 (*(addr))
16663
16664 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16665 #define R_SERIAL0_REC_DATA__FIRST 0
16666 #define R_SERIAL0_REC_DATA__LAST 3
16667 #define R_SERIAL0_REC_DATA__OFFSET 8
16668 /* end */
16669
16670 #define R_SERIAL0_REC_DATA__data_in__data_in__MASK 0x000000ffU
16671
16672 #define R_SERIAL0_REC_DATA__data_in__MAX 0xff
16673
16674 #define R_SERIAL0_REC_DATA__data_in__MIN 0
16675
16676 #define R_SERIAL0_REC_DATA__data_in__BITNR 0
16677
16678 #define R_SERIAL0_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
16679
16680
16681 #endif
16682
16683 /*
16684 * R_SERIAL0_STATUS
16685 * - type: RO
16686 * - addr: 0xb0000061
16687 * - group: Serial port registers
16688 */
16689
16690 #if USE_GROUP__Serial_port_registers
16691
16692 #define R_SERIAL0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000061)
16693 #define R_SERIAL0_STATUS__SVAL REG_SVAL_SHADOW
16694 #define R_SERIAL0_STATUS__SVAL_I REG_SVAL_I_SHADOW
16695 #define R_SERIAL0_STATUS__TYPECAST REG_TYPECAST_BYTE
16696 #define R_SERIAL0_STATUS__TYPE (REG_BYTE)
16697 #define R_SERIAL0_STATUS__GET REG_GET_RO
16698 #define R_SERIAL0_STATUS__IGET REG_IGET_RO
16699 #define R_SERIAL0_STATUS__SET REG_SET_RO
16700 #define R_SERIAL0_STATUS__ISET REG_ISET_RO
16701 #define R_SERIAL0_STATUS__SET_VAL REG_SET_VAL_RO
16702 #define R_SERIAL0_STATUS__EQL REG_EQL_RO
16703 #define R_SERIAL0_STATUS__IEQL REG_IEQL_RO
16704 #define R_SERIAL0_STATUS__RD REG_RD_RO
16705 #define R_SERIAL0_STATUS__IRD REG_IRD_RO
16706 #define R_SERIAL0_STATUS__WR REG_WR_RO
16707 #define R_SERIAL0_STATUS__IWR REG_IWR_RO
16708
16709 #define R_SERIAL0_STATUS__READ(addr) \
16710 (*(addr))
16711
16712 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16713 #define R_SERIAL0_STATUS__FIRST 0
16714 #define R_SERIAL0_STATUS__LAST 3
16715 #define R_SERIAL0_STATUS__OFFSET 8
16716 /* end */
16717
16718 #define R_SERIAL0_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
16719 #define R_SERIAL0_STATUS__cts___cts___MASK 0x00000040U
16720 #define R_SERIAL0_STATUS__tr_ready__tr_ready__MASK 0x00000020U
16721 #define R_SERIAL0_STATUS__rxd__rxd__MASK 0x00000010U
16722 #define R_SERIAL0_STATUS__overrun__overrun__MASK 0x00000008U
16723 #define R_SERIAL0_STATUS__par_err__par_err__MASK 0x00000004U
16724 #define R_SERIAL0_STATUS__framing_err__framing_err__MASK 0x00000002U
16725 #define R_SERIAL0_STATUS__data_avail__data_avail__MASK 0x00000001U
16726
16727 #define R_SERIAL0_STATUS__xoff_detect__MAX 0x1
16728 #define R_SERIAL0_STATUS__cts___MAX 0x1
16729 #define R_SERIAL0_STATUS__tr_ready__MAX 0x1
16730 #define R_SERIAL0_STATUS__rxd__MAX 0x1
16731 #define R_SERIAL0_STATUS__overrun__MAX 0x1
16732 #define R_SERIAL0_STATUS__par_err__MAX 0x1
16733 #define R_SERIAL0_STATUS__framing_err__MAX 0x1
16734 #define R_SERIAL0_STATUS__data_avail__MAX 0x1
16735
16736 #define R_SERIAL0_STATUS__xoff_detect__MIN 0
16737 #define R_SERIAL0_STATUS__cts___MIN 0
16738 #define R_SERIAL0_STATUS__tr_ready__MIN 0
16739 #define R_SERIAL0_STATUS__rxd__MIN 0
16740 #define R_SERIAL0_STATUS__overrun__MIN 0
16741 #define R_SERIAL0_STATUS__par_err__MIN 0
16742 #define R_SERIAL0_STATUS__framing_err__MIN 0
16743 #define R_SERIAL0_STATUS__data_avail__MIN 0
16744
16745 #define R_SERIAL0_STATUS__xoff_detect__BITNR 7
16746 #define R_SERIAL0_STATUS__cts___BITNR 6
16747 #define R_SERIAL0_STATUS__tr_ready__BITNR 5
16748 #define R_SERIAL0_STATUS__rxd__BITNR 4
16749 #define R_SERIAL0_STATUS__overrun__BITNR 3
16750 #define R_SERIAL0_STATUS__par_err__BITNR 2
16751 #define R_SERIAL0_STATUS__framing_err__BITNR 1
16752 #define R_SERIAL0_STATUS__data_avail__BITNR 0
16753
16754 #define R_SERIAL0_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
16755 #define R_SERIAL0_STATUS__cts___cts___VAL REG_VAL_ENUM
16756 #define R_SERIAL0_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
16757 #define R_SERIAL0_STATUS__rxd__rxd__VAL REG_VAL_VAL
16758 #define R_SERIAL0_STATUS__overrun__overrun__VAL REG_VAL_ENUM
16759 #define R_SERIAL0_STATUS__par_err__par_err__VAL REG_VAL_ENUM
16760 #define R_SERIAL0_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
16761 #define R_SERIAL0_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
16762
16763 #define R_SERIAL0_STATUS__xoff_detect__xoff_detect__no_xoff 0
16764 #define R_SERIAL0_STATUS__xoff_detect__xoff_detect__xoff 1
16765 #define R_SERIAL0_STATUS__cts___cts___active 0
16766 #define R_SERIAL0_STATUS__cts___cts___inactive 1
16767 #define R_SERIAL0_STATUS__tr_ready__tr_ready__full 0
16768 #define R_SERIAL0_STATUS__tr_ready__tr_ready__ready 1
16769 #define R_SERIAL0_STATUS__overrun__overrun__no 0
16770 #define R_SERIAL0_STATUS__overrun__overrun__yes 1
16771 #define R_SERIAL0_STATUS__par_err__par_err__no 0
16772 #define R_SERIAL0_STATUS__par_err__par_err__yes 1
16773 #define R_SERIAL0_STATUS__framing_err__framing_err__no 0
16774 #define R_SERIAL0_STATUS__framing_err__framing_err__yes 1
16775 #define R_SERIAL0_STATUS__data_avail__data_avail__no 0
16776 #define R_SERIAL0_STATUS__data_avail__data_avail__yes 1
16777
16778 #endif
16779
16780 /*
16781 * R_SERIAL0_TR_CTRL
16782 * - type: WO
16783 * - addr: 0xb0000061
16784 * - group: Serial port registers
16785 */
16786
16787 #if USE_GROUP__Serial_port_registers
16788
16789 #define R_SERIAL0_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000061)
16790
16791 #ifndef REG_NO_SHADOW
16792 #define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 1))
16793 #define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 1))
16794 #else /* REG_NO_SHADOW */
16795 #define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
16796 #define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
16797 #endif /* REG_NO_SHADOW */
16798
16799 #define R_SERIAL0_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
16800 #define R_SERIAL0_TR_CTRL__SVAL REG_SVAL_SHADOW
16801 #define R_SERIAL0_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
16802 #define R_SERIAL0_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
16803 #define R_SERIAL0_TR_CTRL__TYPE (REG_BYTE)
16804 #define R_SERIAL0_TR_CTRL__GET REG_GET_WO
16805 #define R_SERIAL0_TR_CTRL__IGET REG_IGET_WO
16806 #define R_SERIAL0_TR_CTRL__SET REG_SET_WO
16807 #define R_SERIAL0_TR_CTRL__ISET REG_ISET_WO
16808 #define R_SERIAL0_TR_CTRL__SET_VAL REG_SET_VAL_WO
16809 #define R_SERIAL0_TR_CTRL__EQL REG_EQL_WO
16810 #define R_SERIAL0_TR_CTRL__IEQL REG_IEQL_WO
16811 #define R_SERIAL0_TR_CTRL__RD REG_RD_WO
16812 #define R_SERIAL0_TR_CTRL__IRD REG_IRD_WO
16813 #define R_SERIAL0_TR_CTRL__WR REG_WR_WO
16814 #define R_SERIAL0_TR_CTRL__IWR REG_IWR_WO
16815
16816 #define R_SERIAL0_TR_CTRL__WRITE(addr,value) \
16817 (*(addr) = (value))
16818
16819 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16820 #define R_SERIAL0_TR_CTRL__FIRST 0
16821 #define R_SERIAL0_TR_CTRL__IOFFSET 8
16822 #define R_SERIAL0_TR_CTRL__LAST 3
16823 #define R_SERIAL0_TR_CTRL__OFFSET 8
16824 #define R_SERIAL0_TR_CTRL__SOFFSET 8
16825 /* end */
16826
16827 #define R_SERIAL0_TR_CTRL__txd__txd__MASK 0x00000080U
16828 #define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
16829 #define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
16830 #define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
16831 #define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
16832 #define R_SERIAL0_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
16833 #define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
16834 #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
16835
16836 #define R_SERIAL0_TR_CTRL__txd__MAX 0x1
16837 #define R_SERIAL0_TR_CTRL__tr_enable__MAX 0x1
16838 #define R_SERIAL0_TR_CTRL__auto_cts__MAX 0x1
16839 #define R_SERIAL0_TR_CTRL__stop_bits__MAX 0x1
16840 #define R_SERIAL0_TR_CTRL__tr_stick_par__MAX 0x1
16841 #define R_SERIAL0_TR_CTRL__tr_par__MAX 0x1
16842 #define R_SERIAL0_TR_CTRL__tr_par_en__MAX 0x1
16843 #define R_SERIAL0_TR_CTRL__tr_bitnr__MAX 0x1
16844
16845 #define R_SERIAL0_TR_CTRL__txd__MIN 0
16846 #define R_SERIAL0_TR_CTRL__tr_enable__MIN 0
16847 #define R_SERIAL0_TR_CTRL__auto_cts__MIN 0
16848 #define R_SERIAL0_TR_CTRL__stop_bits__MIN 0
16849 #define R_SERIAL0_TR_CTRL__tr_stick_par__MIN 0
16850 #define R_SERIAL0_TR_CTRL__tr_par__MIN 0
16851 #define R_SERIAL0_TR_CTRL__tr_par_en__MIN 0
16852 #define R_SERIAL0_TR_CTRL__tr_bitnr__MIN 0
16853
16854 #define R_SERIAL0_TR_CTRL__txd__BITNR 7
16855 #define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
16856 #define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
16857 #define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
16858 #define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
16859 #define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
16860 #define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
16861 #define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
16862
16863 #define R_SERIAL0_TR_CTRL__txd__txd__VAL REG_VAL_VAL
16864 #define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
16865 #define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
16866 #define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
16867 #define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
16868 #define R_SERIAL0_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
16869 #define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
16870 #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
16871
16872 #define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__disable 0
16873 #define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__enable 1
16874 #define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__active 1
16875 #define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__disabled 0
16876 #define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__one_bit 0
16877 #define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__two_bits 1
16878 #define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
16879 #define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
16880 #define R_SERIAL0_TR_CTRL__tr_par__tr_par__even 0
16881 #define R_SERIAL0_TR_CTRL__tr_par__tr_par__odd 1
16882 #define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__disable 0
16883 #define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__enable 1
16884 #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
16885 #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
16886
16887 #endif
16888
16889 /*
16890 * R_SERIAL0_TR_DATA
16891 * - type: WO
16892 * - addr: 0xb0000060
16893 * - group: Serial port registers
16894 */
16895
16896 #if USE_GROUP__Serial_port_registers
16897
16898 #define R_SERIAL0_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060)
16899
16900 #ifndef REG_NO_SHADOW
16901 #define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 0))
16902 #define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 0))
16903 #else /* REG_NO_SHADOW */
16904 #define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
16905 #define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
16906 #endif /* REG_NO_SHADOW */
16907
16908 #define R_SERIAL0_TR_DATA__STYPECAST REG_STYPECAST_BYTE
16909 #define R_SERIAL0_TR_DATA__SVAL REG_SVAL_SHADOW
16910 #define R_SERIAL0_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
16911 #define R_SERIAL0_TR_DATA__TYPECAST REG_TYPECAST_BYTE
16912 #define R_SERIAL0_TR_DATA__TYPE (REG_BYTE)
16913 #define R_SERIAL0_TR_DATA__GET REG_GET_WO
16914 #define R_SERIAL0_TR_DATA__IGET REG_IGET_WO
16915 #define R_SERIAL0_TR_DATA__SET REG_SET_WO
16916 #define R_SERIAL0_TR_DATA__ISET REG_ISET_WO
16917 #define R_SERIAL0_TR_DATA__SET_VAL REG_SET_VAL_WO
16918 #define R_SERIAL0_TR_DATA__EQL REG_EQL_WO
16919 #define R_SERIAL0_TR_DATA__IEQL REG_IEQL_WO
16920 #define R_SERIAL0_TR_DATA__RD REG_RD_WO
16921 #define R_SERIAL0_TR_DATA__IRD REG_IRD_WO
16922 #define R_SERIAL0_TR_DATA__WR REG_WR_WO
16923 #define R_SERIAL0_TR_DATA__IWR REG_IWR_WO
16924
16925 #define R_SERIAL0_TR_DATA__WRITE(addr,value) \
16926 (*(addr) = (value))
16927
16928 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16929 #define R_SERIAL0_TR_DATA__FIRST 0
16930 #define R_SERIAL0_TR_DATA__IOFFSET 8
16931 #define R_SERIAL0_TR_DATA__LAST 3
16932 #define R_SERIAL0_TR_DATA__OFFSET 8
16933 #define R_SERIAL0_TR_DATA__SOFFSET 8
16934 /* end */
16935
16936 #define R_SERIAL0_TR_DATA__data_out__data_out__MASK 0x000000ffU
16937
16938 #define R_SERIAL0_TR_DATA__data_out__MAX 0xff
16939
16940 #define R_SERIAL0_TR_DATA__data_out__MIN 0
16941
16942 #define R_SERIAL0_TR_DATA__data_out__BITNR 0
16943
16944 #define R_SERIAL0_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
16945
16946
16947 #endif
16948
16949 /*
16950 * R_SERIAL0_XOFF
16951 * - type: WO
16952 * - addr: 0xb0000064
16953 * - group: Serial port registers
16954 */
16955
16956 #if USE_GROUP__Serial_port_registers
16957
16958 #define R_SERIAL0_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000064)
16959
16960 #ifndef REG_NO_SHADOW
16961 #define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_XOFF + 0))
16962 #define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_XOFF + 0))
16963 #else /* REG_NO_SHADOW */
16964 #define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
16965 #define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
16966 #endif /* REG_NO_SHADOW */
16967
16968 #define R_SERIAL0_XOFF__STYPECAST REG_STYPECAST_UDWORD
16969 #define R_SERIAL0_XOFF__SVAL REG_SVAL_SHADOW
16970 #define R_SERIAL0_XOFF__SVAL_I REG_SVAL_I_SHADOW
16971 #define R_SERIAL0_XOFF__TYPECAST REG_TYPECAST_UDWORD
16972 #define R_SERIAL0_XOFF__TYPE (REG_UDWORD)
16973 #define R_SERIAL0_XOFF__GET REG_GET_WO
16974 #define R_SERIAL0_XOFF__IGET REG_IGET_WO
16975 #define R_SERIAL0_XOFF__SET REG_SET_WO
16976 #define R_SERIAL0_XOFF__ISET REG_ISET_WO
16977 #define R_SERIAL0_XOFF__SET_VAL REG_SET_VAL_WO
16978 #define R_SERIAL0_XOFF__EQL REG_EQL_WO
16979 #define R_SERIAL0_XOFF__IEQL REG_IEQL_WO
16980 #define R_SERIAL0_XOFF__RD REG_RD_WO
16981 #define R_SERIAL0_XOFF__IRD REG_IRD_WO
16982 #define R_SERIAL0_XOFF__WR REG_WR_WO
16983 #define R_SERIAL0_XOFF__IWR REG_IWR_WO
16984
16985 #define R_SERIAL0_XOFF__WRITE(addr,value) \
16986 (*(addr) = (value))
16987
16988 /* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
16989 #define R_SERIAL0_XOFF__FIRST 0
16990 #define R_SERIAL0_XOFF__IOFFSET 8
16991 #define R_SERIAL0_XOFF__LAST 3
16992 #define R_SERIAL0_XOFF__OFFSET 8
16993 #define R_SERIAL0_XOFF__SOFFSET 8
16994 /* end */
16995
16996 #define R_SERIAL0_XOFF__tx_stop__tx_stop__MASK 0x00000200U
16997 #define R_SERIAL0_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
16998 #define R_SERIAL0_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
16999
17000 #define R_SERIAL0_XOFF__tx_stop__MAX 0x1
17001 #define R_SERIAL0_XOFF__auto_xoff__MAX 0x1
17002 #define R_SERIAL0_XOFF__xoff_char__MAX 0xff
17003
17004 #define R_SERIAL0_XOFF__tx_stop__MIN 0
17005 #define R_SERIAL0_XOFF__auto_xoff__MIN 0
17006 #define R_SERIAL0_XOFF__xoff_char__MIN 0
17007
17008 #define R_SERIAL0_XOFF__tx_stop__BITNR 9
17009 #define R_SERIAL0_XOFF__auto_xoff__BITNR 8
17010 #define R_SERIAL0_XOFF__xoff_char__BITNR 0
17011
17012 #define R_SERIAL0_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
17013 #define R_SERIAL0_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
17014 #define R_SERIAL0_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
17015
17016 #define R_SERIAL0_XOFF__tx_stop__tx_stop__enable 0
17017 #define R_SERIAL0_XOFF__tx_stop__tx_stop__stop 1
17018 #define R_SERIAL0_XOFF__auto_xoff__auto_xoff__disable 0
17019 #define R_SERIAL0_XOFF__auto_xoff__auto_xoff__enable 1
17020
17021 #endif
17022
17023 /*
17024 * R_SERIAL1_BAUD
17025 * - type: WO
17026 * - addr: 0xb000006b
17027 * - group: Serial port registers
17028 */
17029
17030 #if USE_GROUP__Serial_port_registers
17031
17032 #define R_SERIAL1_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000006b)
17033
17034 #ifndef REG_NO_SHADOW
17035 #define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 3))
17036 #define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 3))
17037 #else /* REG_NO_SHADOW */
17038 #define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
17039 #define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
17040 #endif /* REG_NO_SHADOW */
17041
17042 #define R_SERIAL1_BAUD__STYPECAST REG_STYPECAST_BYTE
17043 #define R_SERIAL1_BAUD__SVAL REG_SVAL_SHADOW
17044 #define R_SERIAL1_BAUD__SVAL_I REG_SVAL_I_SHADOW
17045 #define R_SERIAL1_BAUD__TYPECAST REG_TYPECAST_BYTE
17046 #define R_SERIAL1_BAUD__TYPE (REG_BYTE)
17047 #define R_SERIAL1_BAUD__GET REG_GET_WO
17048 #define R_SERIAL1_BAUD__IGET REG_IGET_WO
17049 #define R_SERIAL1_BAUD__SET REG_SET_WO
17050 #define R_SERIAL1_BAUD__ISET REG_ISET_WO
17051 #define R_SERIAL1_BAUD__SET_VAL REG_SET_VAL_WO
17052 #define R_SERIAL1_BAUD__EQL REG_EQL_WO
17053 #define R_SERIAL1_BAUD__IEQL REG_IEQL_WO
17054 #define R_SERIAL1_BAUD__RD REG_RD_WO
17055 #define R_SERIAL1_BAUD__IRD REG_IRD_WO
17056 #define R_SERIAL1_BAUD__WR REG_WR_WO
17057 #define R_SERIAL1_BAUD__IWR REG_IWR_WO
17058
17059 #define R_SERIAL1_BAUD__WRITE(addr,value) \
17060 (*(addr) = (value))
17061
17062 #define R_SERIAL1_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
17063 #define R_SERIAL1_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
17064
17065 #define R_SERIAL1_BAUD__tr_baud__MAX 0xf
17066 #define R_SERIAL1_BAUD__rec_baud__MAX 0xf
17067
17068 #define R_SERIAL1_BAUD__tr_baud__MIN 0
17069 #define R_SERIAL1_BAUD__rec_baud__MIN 0
17070
17071 #define R_SERIAL1_BAUD__tr_baud__BITNR 4
17072 #define R_SERIAL1_BAUD__rec_baud__BITNR 0
17073
17074 #define R_SERIAL1_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
17075 #define R_SERIAL1_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
17076
17077 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c115k2Hz 9
17078 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c1200Hz 2
17079 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c1843k2Hz 13
17080 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c19k2Hz 6
17081 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c230k4Hz 10
17082 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c2400Hz 3
17083 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c300Hz 0
17084 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c38k4Hz 7
17085 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c460k8Hz 11
17086 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c4800Hz 4
17087 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c57k6Hz 8
17088 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c600Hz 1
17089 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c6250kHz 14
17090 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c921k6Hz 12
17091 #define R_SERIAL1_BAUD__tr_baud__tr_baud__c9600Hz 5
17092 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c115k2Hz 9
17093 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c1200Hz 2
17094 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c1843k2Hz 13
17095 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c19k2Hz 6
17096 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c230k4Hz 10
17097 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c2400Hz 3
17098 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c300Hz 0
17099 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c38k4Hz 7
17100 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c460k8Hz 11
17101 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c4800Hz 4
17102 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c57k6Hz 8
17103 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c600Hz 1
17104 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c6250kHz 14
17105 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c921k6Hz 12
17106 #define R_SERIAL1_BAUD__rec_baud__rec_baud__c9600Hz 5
17107
17108 #endif
17109
17110 /*
17111 * R_SERIAL1_CTRL
17112 * - type: WO
17113 * - addr: 0xb0000068
17114 * - group: Serial port registers
17115 */
17116
17117 #if USE_GROUP__Serial_port_registers
17118
17119 #define R_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
17120
17121 #ifndef REG_NO_SHADOW
17122 #define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
17123 #define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
17124 #else /* REG_NO_SHADOW */
17125 #define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
17126 #define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
17127 #endif /* REG_NO_SHADOW */
17128
17129 #define R_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD
17130 #define R_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW
17131 #define R_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW
17132 #define R_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD
17133 #define R_SERIAL1_CTRL__TYPE (REG_UDWORD)
17134 #define R_SERIAL1_CTRL__GET REG_GET_WO
17135 #define R_SERIAL1_CTRL__IGET REG_IGET_WO
17136 #define R_SERIAL1_CTRL__SET REG_SET_WO
17137 #define R_SERIAL1_CTRL__ISET REG_ISET_WO
17138 #define R_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO
17139 #define R_SERIAL1_CTRL__EQL REG_EQL_WO
17140 #define R_SERIAL1_CTRL__IEQL REG_IEQL_WO
17141 #define R_SERIAL1_CTRL__RD REG_RD_WO
17142 #define R_SERIAL1_CTRL__IRD REG_IRD_WO
17143 #define R_SERIAL1_CTRL__WR REG_WR_WO
17144 #define R_SERIAL1_CTRL__IWR REG_IWR_WO
17145
17146 #define R_SERIAL1_CTRL__WRITE(addr,value) \
17147 (*(addr) = (value))
17148
17149 #define R_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
17150 #define R_SERIAL1_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
17151 #define R_SERIAL1_CTRL__dma_err__dma_err__MASK 0x00800000U
17152 #define R_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U
17153 #define R_SERIAL1_CTRL__rts___rts___MASK 0x00200000U
17154 #define R_SERIAL1_CTRL__sampling__sampling__MASK 0x00100000U
17155 #define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
17156 #define R_SERIAL1_CTRL__rec_par__rec_par__MASK 0x00040000U
17157 #define R_SERIAL1_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
17158 #define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
17159 #define R_SERIAL1_CTRL__txd__txd__MASK 0x00008000U
17160 #define R_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U
17161 #define R_SERIAL1_CTRL__auto_cts__auto_cts__MASK 0x00002000U
17162 #define R_SERIAL1_CTRL__stop_bits__stop_bits__MASK 0x00001000U
17163 #define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
17164 #define R_SERIAL1_CTRL__tr_par__tr_par__MASK 0x00000400U
17165 #define R_SERIAL1_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
17166 #define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
17167 #define R_SERIAL1_CTRL__data_out__data_out__MASK 0x000000ffU
17168
17169 #define R_SERIAL1_CTRL__tr_baud__MAX 0xf
17170 #define R_SERIAL1_CTRL__rec_baud__MAX 0xf
17171 #define R_SERIAL1_CTRL__dma_err__MAX 0x1
17172 #define R_SERIAL1_CTRL__rec_enable__MAX 0x1
17173 #define R_SERIAL1_CTRL__rts___MAX 0x1
17174 #define R_SERIAL1_CTRL__sampling__MAX 0x1
17175 #define R_SERIAL1_CTRL__rec_stick_par__MAX 0x1
17176 #define R_SERIAL1_CTRL__rec_par__MAX 0x1
17177 #define R_SERIAL1_CTRL__rec_par_en__MAX 0x1
17178 #define R_SERIAL1_CTRL__rec_bitnr__MAX 0x1
17179 #define R_SERIAL1_CTRL__txd__MAX 0x1
17180 #define R_SERIAL1_CTRL__tr_enable__MAX 0x1
17181 #define R_SERIAL1_CTRL__auto_cts__MAX 0x1
17182 #define R_SERIAL1_CTRL__stop_bits__MAX 0x1
17183 #define R_SERIAL1_CTRL__tr_stick_par__MAX 0x1
17184 #define R_SERIAL1_CTRL__tr_par__MAX 0x1
17185 #define R_SERIAL1_CTRL__tr_par_en__MAX 0x1
17186 #define R_SERIAL1_CTRL__tr_bitnr__MAX 0x1
17187 #define R_SERIAL1_CTRL__data_out__MAX 0xff
17188
17189 #define R_SERIAL1_CTRL__tr_baud__MIN 0
17190 #define R_SERIAL1_CTRL__rec_baud__MIN 0
17191 #define R_SERIAL1_CTRL__dma_err__MIN 0
17192 #define R_SERIAL1_CTRL__rec_enable__MIN 0
17193 #define R_SERIAL1_CTRL__rts___MIN 0
17194 #define R_SERIAL1_CTRL__sampling__MIN 0
17195 #define R_SERIAL1_CTRL__rec_stick_par__MIN 0
17196 #define R_SERIAL1_CTRL__rec_par__MIN 0
17197 #define R_SERIAL1_CTRL__rec_par_en__MIN 0
17198 #define R_SERIAL1_CTRL__rec_bitnr__MIN 0
17199 #define R_SERIAL1_CTRL__txd__MIN 0
17200 #define R_SERIAL1_CTRL__tr_enable__MIN 0
17201 #define R_SERIAL1_CTRL__auto_cts__MIN 0
17202 #define R_SERIAL1_CTRL__stop_bits__MIN 0
17203 #define R_SERIAL1_CTRL__tr_stick_par__MIN 0
17204 #define R_SERIAL1_CTRL__tr_par__MIN 0
17205 #define R_SERIAL1_CTRL__tr_par_en__MIN 0
17206 #define R_SERIAL1_CTRL__tr_bitnr__MIN 0
17207 #define R_SERIAL1_CTRL__data_out__MIN 0
17208
17209 #define R_SERIAL1_CTRL__tr_baud__BITNR 28
17210 #define R_SERIAL1_CTRL__rec_baud__BITNR 24
17211 #define R_SERIAL1_CTRL__dma_err__BITNR 23
17212 #define R_SERIAL1_CTRL__rec_enable__BITNR 22
17213 #define R_SERIAL1_CTRL__rts___BITNR 21
17214 #define R_SERIAL1_CTRL__sampling__BITNR 20
17215 #define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
17216 #define R_SERIAL1_CTRL__rec_par__BITNR 18
17217 #define R_SERIAL1_CTRL__rec_par_en__BITNR 17
17218 #define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
17219 #define R_SERIAL1_CTRL__txd__BITNR 15
17220 #define R_SERIAL1_CTRL__tr_enable__BITNR 14
17221 #define R_SERIAL1_CTRL__auto_cts__BITNR 13
17222 #define R_SERIAL1_CTRL__stop_bits__BITNR 12
17223 #define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
17224 #define R_SERIAL1_CTRL__tr_par__BITNR 10
17225 #define R_SERIAL1_CTRL__tr_par_en__BITNR 9
17226 #define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
17227 #define R_SERIAL1_CTRL__data_out__BITNR 0
17228
17229 #define R_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
17230 #define R_SERIAL1_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
17231 #define R_SERIAL1_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
17232 #define R_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
17233 #define R_SERIAL1_CTRL__rts___rts___VAL REG_VAL_ENUM
17234 #define R_SERIAL1_CTRL__sampling__sampling__VAL REG_VAL_ENUM
17235 #define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
17236 #define R_SERIAL1_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
17237 #define R_SERIAL1_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
17238 #define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
17239 #define R_SERIAL1_CTRL__txd__txd__VAL REG_VAL_VAL
17240 #define R_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
17241 #define R_SERIAL1_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
17242 #define R_SERIAL1_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
17243 #define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
17244 #define R_SERIAL1_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
17245 #define R_SERIAL1_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
17246 #define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
17247 #define R_SERIAL1_CTRL__data_out__data_out__VAL REG_VAL_VAL
17248
17249 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 9
17250 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 2
17251 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c1843k2Hz 13
17252 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 6
17253 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 10
17254 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 3
17255 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 0
17256 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c38k4Hz 7
17257 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 11
17258 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 4
17259 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 8
17260 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 1
17261 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c6250kHz 14
17262 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 12
17263 #define R_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 5
17264 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c115k2Hz 9
17265 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c1200Hz 2
17266 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c1843k2Hz 13
17267 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c19k2Hz 6
17268 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c230k4Hz 10
17269 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c2400Hz 3
17270 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c300Hz 0
17271 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c38k4Hz 7
17272 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c460k8Hz 11
17273 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c4800Hz 4
17274 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c57k6Hz 8
17275 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c600Hz 1
17276 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c6250kHz 14
17277 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c921k6Hz 12
17278 #define R_SERIAL1_CTRL__rec_baud__rec_baud__c9600Hz 5
17279 #define R_SERIAL1_CTRL__dma_err__dma_err__ignore 1
17280 #define R_SERIAL1_CTRL__dma_err__dma_err__stop 0
17281 #define R_SERIAL1_CTRL__rec_enable__rec_enable__disable 0
17282 #define R_SERIAL1_CTRL__rec_enable__rec_enable__enable 1
17283 #define R_SERIAL1_CTRL__rts___rts___active 0
17284 #define R_SERIAL1_CTRL__rts___rts___inactive 1
17285 #define R_SERIAL1_CTRL__sampling__sampling__majority 1
17286 #define R_SERIAL1_CTRL__sampling__sampling__middle 0
17287 #define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__normal 0
17288 #define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__stick 1
17289 #define R_SERIAL1_CTRL__rec_par__rec_par__even 0
17290 #define R_SERIAL1_CTRL__rec_par__rec_par__odd 1
17291 #define R_SERIAL1_CTRL__rec_par_en__rec_par_en__disable 0
17292 #define R_SERIAL1_CTRL__rec_par_en__rec_par_en__enable 1
17293 #define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
17294 #define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
17295 #define R_SERIAL1_CTRL__tr_enable__tr_enable__disable 0
17296 #define R_SERIAL1_CTRL__tr_enable__tr_enable__enable 1
17297 #define R_SERIAL1_CTRL__auto_cts__auto_cts__active 1
17298 #define R_SERIAL1_CTRL__auto_cts__auto_cts__disabled 0
17299 #define R_SERIAL1_CTRL__stop_bits__stop_bits__one_bit 0
17300 #define R_SERIAL1_CTRL__stop_bits__stop_bits__two_bits 1
17301 #define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__normal 0
17302 #define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__stick 1
17303 #define R_SERIAL1_CTRL__tr_par__tr_par__even 0
17304 #define R_SERIAL1_CTRL__tr_par__tr_par__odd 1
17305 #define R_SERIAL1_CTRL__tr_par_en__tr_par_en__disable 0
17306 #define R_SERIAL1_CTRL__tr_par_en__tr_par_en__enable 1
17307 #define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
17308 #define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
17309
17310 #endif
17311
17312 /*
17313 * R_SERIAL1_READ
17314 * - type: RO
17315 * - addr: 0xb0000068
17316 * - group: Serial port registers
17317 */
17318
17319 #if USE_GROUP__Serial_port_registers
17320
17321 #define R_SERIAL1_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
17322 #define R_SERIAL1_READ__SVAL REG_SVAL_SHADOW
17323 #define R_SERIAL1_READ__SVAL_I REG_SVAL_I_SHADOW
17324 #define R_SERIAL1_READ__TYPECAST REG_TYPECAST_UDWORD
17325 #define R_SERIAL1_READ__TYPE (REG_UDWORD)
17326 #define R_SERIAL1_READ__GET REG_GET_RO
17327 #define R_SERIAL1_READ__IGET REG_IGET_RO
17328 #define R_SERIAL1_READ__SET REG_SET_RO
17329 #define R_SERIAL1_READ__ISET REG_ISET_RO
17330 #define R_SERIAL1_READ__SET_VAL REG_SET_VAL_RO
17331 #define R_SERIAL1_READ__EQL REG_EQL_RO
17332 #define R_SERIAL1_READ__IEQL REG_IEQL_RO
17333 #define R_SERIAL1_READ__RD REG_RD_RO
17334 #define R_SERIAL1_READ__IRD REG_IRD_RO
17335 #define R_SERIAL1_READ__WR REG_WR_RO
17336 #define R_SERIAL1_READ__IWR REG_IWR_RO
17337
17338 #define R_SERIAL1_READ__READ(addr) \
17339 (*(addr))
17340
17341 #define R_SERIAL1_READ__xoff_detect__xoff_detect__MASK 0x00008000U
17342 #define R_SERIAL1_READ__cts___cts___MASK 0x00004000U
17343 #define R_SERIAL1_READ__tr_ready__tr_ready__MASK 0x00002000U
17344 #define R_SERIAL1_READ__rxd__rxd__MASK 0x00001000U
17345 #define R_SERIAL1_READ__overrun__overrun__MASK 0x00000800U
17346 #define R_SERIAL1_READ__par_err__par_err__MASK 0x00000400U
17347 #define R_SERIAL1_READ__framing_err__framing_err__MASK 0x00000200U
17348 #define R_SERIAL1_READ__data_avail__data_avail__MASK 0x00000100U
17349 #define R_SERIAL1_READ__data_in__data_in__MASK 0x000000ffU
17350
17351 #define R_SERIAL1_READ__xoff_detect__MAX 0x1
17352 #define R_SERIAL1_READ__cts___MAX 0x1
17353 #define R_SERIAL1_READ__tr_ready__MAX 0x1
17354 #define R_SERIAL1_READ__rxd__MAX 0x1
17355 #define R_SERIAL1_READ__overrun__MAX 0x1
17356 #define R_SERIAL1_READ__par_err__MAX 0x1
17357 #define R_SERIAL1_READ__framing_err__MAX 0x1
17358 #define R_SERIAL1_READ__data_avail__MAX 0x1
17359 #define R_SERIAL1_READ__data_in__MAX 0xff
17360
17361 #define R_SERIAL1_READ__xoff_detect__MIN 0
17362 #define R_SERIAL1_READ__cts___MIN 0
17363 #define R_SERIAL1_READ__tr_ready__MIN 0
17364 #define R_SERIAL1_READ__rxd__MIN 0
17365 #define R_SERIAL1_READ__overrun__MIN 0
17366 #define R_SERIAL1_READ__par_err__MIN 0
17367 #define R_SERIAL1_READ__framing_err__MIN 0
17368 #define R_SERIAL1_READ__data_avail__MIN 0
17369 #define R_SERIAL1_READ__data_in__MIN 0
17370
17371 #define R_SERIAL1_READ__xoff_detect__BITNR 15
17372 #define R_SERIAL1_READ__cts___BITNR 14
17373 #define R_SERIAL1_READ__tr_ready__BITNR 13
17374 #define R_SERIAL1_READ__rxd__BITNR 12
17375 #define R_SERIAL1_READ__overrun__BITNR 11
17376 #define R_SERIAL1_READ__par_err__BITNR 10
17377 #define R_SERIAL1_READ__framing_err__BITNR 9
17378 #define R_SERIAL1_READ__data_avail__BITNR 8
17379 #define R_SERIAL1_READ__data_in__BITNR 0
17380
17381 #define R_SERIAL1_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
17382 #define R_SERIAL1_READ__cts___cts___VAL REG_VAL_ENUM
17383 #define R_SERIAL1_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
17384 #define R_SERIAL1_READ__rxd__rxd__VAL REG_VAL_VAL
17385 #define R_SERIAL1_READ__overrun__overrun__VAL REG_VAL_ENUM
17386 #define R_SERIAL1_READ__par_err__par_err__VAL REG_VAL_ENUM
17387 #define R_SERIAL1_READ__framing_err__framing_err__VAL REG_VAL_ENUM
17388 #define R_SERIAL1_READ__data_avail__data_avail__VAL REG_VAL_ENUM
17389 #define R_SERIAL1_READ__data_in__data_in__VAL REG_VAL_VAL
17390
17391 #define R_SERIAL1_READ__xoff_detect__xoff_detect__no_xoff 0
17392 #define R_SERIAL1_READ__xoff_detect__xoff_detect__xoff 1
17393 #define R_SERIAL1_READ__cts___cts___active 0
17394 #define R_SERIAL1_READ__cts___cts___inactive 1
17395 #define R_SERIAL1_READ__tr_ready__tr_ready__full 0
17396 #define R_SERIAL1_READ__tr_ready__tr_ready__ready 1
17397 #define R_SERIAL1_READ__overrun__overrun__no 0
17398 #define R_SERIAL1_READ__overrun__overrun__yes 1
17399 #define R_SERIAL1_READ__par_err__par_err__no 0
17400 #define R_SERIAL1_READ__par_err__par_err__yes 1
17401 #define R_SERIAL1_READ__framing_err__framing_err__no 0
17402 #define R_SERIAL1_READ__framing_err__framing_err__yes 1
17403 #define R_SERIAL1_READ__data_avail__data_avail__no 0
17404 #define R_SERIAL1_READ__data_avail__data_avail__yes 1
17405
17406 #endif
17407
17408 /*
17409 * R_SERIAL1_REC_CTRL
17410 * - type: WO
17411 * - addr: 0xb000006a
17412 * - group: Serial port registers
17413 */
17414
17415 #if USE_GROUP__Serial_port_registers
17416
17417 #define R_SERIAL1_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000006a)
17418
17419 #ifndef REG_NO_SHADOW
17420 #define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2))
17421 #define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2))
17422 #else /* REG_NO_SHADOW */
17423 #define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
17424 #define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
17425 #endif /* REG_NO_SHADOW */
17426
17427 #define R_SERIAL1_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
17428 #define R_SERIAL1_REC_CTRL__SVAL REG_SVAL_SHADOW
17429 #define R_SERIAL1_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
17430 #define R_SERIAL1_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
17431 #define R_SERIAL1_REC_CTRL__TYPE (REG_BYTE)
17432 #define R_SERIAL1_REC_CTRL__GET REG_GET_WO
17433 #define R_SERIAL1_REC_CTRL__IGET REG_IGET_WO
17434 #define R_SERIAL1_REC_CTRL__SET REG_SET_WO
17435 #define R_SERIAL1_REC_CTRL__ISET REG_ISET_WO
17436 #define R_SERIAL1_REC_CTRL__SET_VAL REG_SET_VAL_WO
17437 #define R_SERIAL1_REC_CTRL__EQL REG_EQL_WO
17438 #define R_SERIAL1_REC_CTRL__IEQL REG_IEQL_WO
17439 #define R_SERIAL1_REC_CTRL__RD REG_RD_WO
17440 #define R_SERIAL1_REC_CTRL__IRD REG_IRD_WO
17441 #define R_SERIAL1_REC_CTRL__WR REG_WR_WO
17442 #define R_SERIAL1_REC_CTRL__IWR REG_IWR_WO
17443
17444 #define R_SERIAL1_REC_CTRL__WRITE(addr,value) \
17445 (*(addr) = (value))
17446
17447 #define R_SERIAL1_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
17448 #define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
17449 #define R_SERIAL1_REC_CTRL__rts___rts___MASK 0x00000020U
17450 #define R_SERIAL1_REC_CTRL__sampling__sampling__MASK 0x00000010U
17451 #define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
17452 #define R_SERIAL1_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
17453 #define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
17454 #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
17455
17456 #define R_SERIAL1_REC_CTRL__dma_err__MAX 0x1
17457 #define R_SERIAL1_REC_CTRL__rec_enable__MAX 0x1
17458 #define R_SERIAL1_REC_CTRL__rts___MAX 0x1
17459 #define R_SERIAL1_REC_CTRL__sampling__MAX 0x1
17460 #define R_SERIAL1_REC_CTRL__rec_stick_par__MAX 0x1
17461 #define R_SERIAL1_REC_CTRL__rec_par__MAX 0x1
17462 #define R_SERIAL1_REC_CTRL__rec_par_en__MAX 0x1
17463 #define R_SERIAL1_REC_CTRL__rec_bitnr__MAX 0x1
17464
17465 #define R_SERIAL1_REC_CTRL__dma_err__MIN 0
17466 #define R_SERIAL1_REC_CTRL__rec_enable__MIN 0
17467 #define R_SERIAL1_REC_CTRL__rts___MIN 0
17468 #define R_SERIAL1_REC_CTRL__sampling__MIN 0
17469 #define R_SERIAL1_REC_CTRL__rec_stick_par__MIN 0
17470 #define R_SERIAL1_REC_CTRL__rec_par__MIN 0
17471 #define R_SERIAL1_REC_CTRL__rec_par_en__MIN 0
17472 #define R_SERIAL1_REC_CTRL__rec_bitnr__MIN 0
17473
17474 #define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
17475 #define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
17476 #define R_SERIAL1_REC_CTRL__rts___BITNR 5
17477 #define R_SERIAL1_REC_CTRL__sampling__BITNR 4
17478 #define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
17479 #define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
17480 #define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
17481 #define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
17482
17483 #define R_SERIAL1_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
17484 #define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
17485 #define R_SERIAL1_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
17486 #define R_SERIAL1_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
17487 #define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
17488 #define R_SERIAL1_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
17489 #define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
17490 #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
17491
17492 #define R_SERIAL1_REC_CTRL__dma_err__dma_err__ignore 1
17493 #define R_SERIAL1_REC_CTRL__dma_err__dma_err__stop 0
17494 #define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__disable 0
17495 #define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__enable 1
17496 #define R_SERIAL1_REC_CTRL__rts___rts___active 0
17497 #define R_SERIAL1_REC_CTRL__rts___rts___inactive 1
17498 #define R_SERIAL1_REC_CTRL__sampling__sampling__majority 1
17499 #define R_SERIAL1_REC_CTRL__sampling__sampling__middle 0
17500 #define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
17501 #define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
17502 #define R_SERIAL1_REC_CTRL__rec_par__rec_par__even 0
17503 #define R_SERIAL1_REC_CTRL__rec_par__rec_par__odd 1
17504 #define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__disable 0
17505 #define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__enable 1
17506 #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
17507 #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
17508
17509 #endif
17510
17511 /*
17512 * R_SERIAL1_REC_DATA
17513 * - type: RO
17514 * - addr: 0xb0000068
17515 * - group: Serial port registers
17516 */
17517
17518 #if USE_GROUP__Serial_port_registers
17519
17520 #define R_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068)
17521 #define R_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW
17522 #define R_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
17523 #define R_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_BYTE
17524 #define R_SERIAL1_REC_DATA__TYPE (REG_BYTE)
17525 #define R_SERIAL1_REC_DATA__GET REG_GET_RO
17526 #define R_SERIAL1_REC_DATA__IGET REG_IGET_RO
17527 #define R_SERIAL1_REC_DATA__SET REG_SET_RO
17528 #define R_SERIAL1_REC_DATA__ISET REG_ISET_RO
17529 #define R_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO
17530 #define R_SERIAL1_REC_DATA__EQL REG_EQL_RO
17531 #define R_SERIAL1_REC_DATA__IEQL REG_IEQL_RO
17532 #define R_SERIAL1_REC_DATA__RD REG_RD_RO
17533 #define R_SERIAL1_REC_DATA__IRD REG_IRD_RO
17534 #define R_SERIAL1_REC_DATA__WR REG_WR_RO
17535 #define R_SERIAL1_REC_DATA__IWR REG_IWR_RO
17536
17537 #define R_SERIAL1_REC_DATA__READ(addr) \
17538 (*(addr))
17539
17540 #define R_SERIAL1_REC_DATA__data_in__data_in__MASK 0x000000ffU
17541
17542 #define R_SERIAL1_REC_DATA__data_in__MAX 0xff
17543
17544 #define R_SERIAL1_REC_DATA__data_in__MIN 0
17545
17546 #define R_SERIAL1_REC_DATA__data_in__BITNR 0
17547
17548 #define R_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
17549
17550
17551 #endif
17552
17553 /*
17554 * R_SERIAL1_STATUS
17555 * - type: RO
17556 * - addr: 0xb0000069
17557 * - group: Serial port registers
17558 */
17559
17560 #if USE_GROUP__Serial_port_registers
17561
17562 #define R_SERIAL1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000069)
17563 #define R_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW
17564 #define R_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW
17565 #define R_SERIAL1_STATUS__TYPECAST REG_TYPECAST_BYTE
17566 #define R_SERIAL1_STATUS__TYPE (REG_BYTE)
17567 #define R_SERIAL1_STATUS__GET REG_GET_RO
17568 #define R_SERIAL1_STATUS__IGET REG_IGET_RO
17569 #define R_SERIAL1_STATUS__SET REG_SET_RO
17570 #define R_SERIAL1_STATUS__ISET REG_ISET_RO
17571 #define R_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO
17572 #define R_SERIAL1_STATUS__EQL REG_EQL_RO
17573 #define R_SERIAL1_STATUS__IEQL REG_IEQL_RO
17574 #define R_SERIAL1_STATUS__RD REG_RD_RO
17575 #define R_SERIAL1_STATUS__IRD REG_IRD_RO
17576 #define R_SERIAL1_STATUS__WR REG_WR_RO
17577 #define R_SERIAL1_STATUS__IWR REG_IWR_RO
17578
17579 #define R_SERIAL1_STATUS__READ(addr) \
17580 (*(addr))
17581
17582 #define R_SERIAL1_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
17583 #define R_SERIAL1_STATUS__cts___cts___MASK 0x00000040U
17584 #define R_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00000020U
17585 #define R_SERIAL1_STATUS__rxd__rxd__MASK 0x00000010U
17586 #define R_SERIAL1_STATUS__overrun__overrun__MASK 0x00000008U
17587 #define R_SERIAL1_STATUS__par_err__par_err__MASK 0x00000004U
17588 #define R_SERIAL1_STATUS__framing_err__framing_err__MASK 0x00000002U
17589 #define R_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000001U
17590
17591 #define R_SERIAL1_STATUS__xoff_detect__MAX 0x1
17592 #define R_SERIAL1_STATUS__cts___MAX 0x1
17593 #define R_SERIAL1_STATUS__tr_ready__MAX 0x1
17594 #define R_SERIAL1_STATUS__rxd__MAX 0x1
17595 #define R_SERIAL1_STATUS__overrun__MAX 0x1
17596 #define R_SERIAL1_STATUS__par_err__MAX 0x1
17597 #define R_SERIAL1_STATUS__framing_err__MAX 0x1
17598 #define R_SERIAL1_STATUS__data_avail__MAX 0x1
17599
17600 #define R_SERIAL1_STATUS__xoff_detect__MIN 0
17601 #define R_SERIAL1_STATUS__cts___MIN 0
17602 #define R_SERIAL1_STATUS__tr_ready__MIN 0
17603 #define R_SERIAL1_STATUS__rxd__MIN 0
17604 #define R_SERIAL1_STATUS__overrun__MIN 0
17605 #define R_SERIAL1_STATUS__par_err__MIN 0
17606 #define R_SERIAL1_STATUS__framing_err__MIN 0
17607 #define R_SERIAL1_STATUS__data_avail__MIN 0
17608
17609 #define R_SERIAL1_STATUS__xoff_detect__BITNR 7
17610 #define R_SERIAL1_STATUS__cts___BITNR 6
17611 #define R_SERIAL1_STATUS__tr_ready__BITNR 5
17612 #define R_SERIAL1_STATUS__rxd__BITNR 4
17613 #define R_SERIAL1_STATUS__overrun__BITNR 3
17614 #define R_SERIAL1_STATUS__par_err__BITNR 2
17615 #define R_SERIAL1_STATUS__framing_err__BITNR 1
17616 #define R_SERIAL1_STATUS__data_avail__BITNR 0
17617
17618 #define R_SERIAL1_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
17619 #define R_SERIAL1_STATUS__cts___cts___VAL REG_VAL_ENUM
17620 #define R_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
17621 #define R_SERIAL1_STATUS__rxd__rxd__VAL REG_VAL_VAL
17622 #define R_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM
17623 #define R_SERIAL1_STATUS__par_err__par_err__VAL REG_VAL_ENUM
17624 #define R_SERIAL1_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
17625 #define R_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
17626
17627 #define R_SERIAL1_STATUS__xoff_detect__xoff_detect__no_xoff 0
17628 #define R_SERIAL1_STATUS__xoff_detect__xoff_detect__xoff 1
17629 #define R_SERIAL1_STATUS__cts___cts___active 0
17630 #define R_SERIAL1_STATUS__cts___cts___inactive 1
17631 #define R_SERIAL1_STATUS__tr_ready__tr_ready__full 0
17632 #define R_SERIAL1_STATUS__tr_ready__tr_ready__ready 1
17633 #define R_SERIAL1_STATUS__overrun__overrun__no 0
17634 #define R_SERIAL1_STATUS__overrun__overrun__yes 1
17635 #define R_SERIAL1_STATUS__par_err__par_err__no 0
17636 #define R_SERIAL1_STATUS__par_err__par_err__yes 1
17637 #define R_SERIAL1_STATUS__framing_err__framing_err__no 0
17638 #define R_SERIAL1_STATUS__framing_err__framing_err__yes 1
17639 #define R_SERIAL1_STATUS__data_avail__data_avail__no 0
17640 #define R_SERIAL1_STATUS__data_avail__data_avail__yes 1
17641
17642 #endif
17643
17644 /*
17645 * R_SERIAL1_TR_CTRL
17646 * - type: WO
17647 * - addr: 0xb0000069
17648 * - group: Serial port registers
17649 */
17650
17651 #if USE_GROUP__Serial_port_registers
17652
17653 #define R_SERIAL1_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000069)
17654
17655 #ifndef REG_NO_SHADOW
17656 #define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 1))
17657 #define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 1))
17658 #else /* REG_NO_SHADOW */
17659 #define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
17660 #define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
17661 #endif /* REG_NO_SHADOW */
17662
17663 #define R_SERIAL1_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
17664 #define R_SERIAL1_TR_CTRL__SVAL REG_SVAL_SHADOW
17665 #define R_SERIAL1_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
17666 #define R_SERIAL1_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
17667 #define R_SERIAL1_TR_CTRL__TYPE (REG_BYTE)
17668 #define R_SERIAL1_TR_CTRL__GET REG_GET_WO
17669 #define R_SERIAL1_TR_CTRL__IGET REG_IGET_WO
17670 #define R_SERIAL1_TR_CTRL__SET REG_SET_WO
17671 #define R_SERIAL1_TR_CTRL__ISET REG_ISET_WO
17672 #define R_SERIAL1_TR_CTRL__SET_VAL REG_SET_VAL_WO
17673 #define R_SERIAL1_TR_CTRL__EQL REG_EQL_WO
17674 #define R_SERIAL1_TR_CTRL__IEQL REG_IEQL_WO
17675 #define R_SERIAL1_TR_CTRL__RD REG_RD_WO
17676 #define R_SERIAL1_TR_CTRL__IRD REG_IRD_WO
17677 #define R_SERIAL1_TR_CTRL__WR REG_WR_WO
17678 #define R_SERIAL1_TR_CTRL__IWR REG_IWR_WO
17679
17680 #define R_SERIAL1_TR_CTRL__WRITE(addr,value) \
17681 (*(addr) = (value))
17682
17683 #define R_SERIAL1_TR_CTRL__txd__txd__MASK 0x00000080U
17684 #define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
17685 #define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
17686 #define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
17687 #define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
17688 #define R_SERIAL1_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
17689 #define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
17690 #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
17691
17692 #define R_SERIAL1_TR_CTRL__txd__MAX 0x1
17693 #define R_SERIAL1_TR_CTRL__tr_enable__MAX 0x1
17694 #define R_SERIAL1_TR_CTRL__auto_cts__MAX 0x1
17695 #define R_SERIAL1_TR_CTRL__stop_bits__MAX 0x1
17696 #define R_SERIAL1_TR_CTRL__tr_stick_par__MAX 0x1
17697 #define R_SERIAL1_TR_CTRL__tr_par__MAX 0x1
17698 #define R_SERIAL1_TR_CTRL__tr_par_en__MAX 0x1
17699 #define R_SERIAL1_TR_CTRL__tr_bitnr__MAX 0x1
17700
17701 #define R_SERIAL1_TR_CTRL__txd__MIN 0
17702 #define R_SERIAL1_TR_CTRL__tr_enable__MIN 0
17703 #define R_SERIAL1_TR_CTRL__auto_cts__MIN 0
17704 #define R_SERIAL1_TR_CTRL__stop_bits__MIN 0
17705 #define R_SERIAL1_TR_CTRL__tr_stick_par__MIN 0
17706 #define R_SERIAL1_TR_CTRL__tr_par__MIN 0
17707 #define R_SERIAL1_TR_CTRL__tr_par_en__MIN 0
17708 #define R_SERIAL1_TR_CTRL__tr_bitnr__MIN 0
17709
17710 #define R_SERIAL1_TR_CTRL__txd__BITNR 7
17711 #define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
17712 #define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
17713 #define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
17714 #define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
17715 #define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
17716 #define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
17717 #define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
17718
17719 #define R_SERIAL1_TR_CTRL__txd__txd__VAL REG_VAL_VAL
17720 #define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
17721 #define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
17722 #define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
17723 #define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
17724 #define R_SERIAL1_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
17725 #define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
17726 #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
17727
17728 #define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__disable 0
17729 #define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__enable 1
17730 #define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__active 1
17731 #define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__disabled 0
17732 #define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__one_bit 0
17733 #define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__two_bits 1
17734 #define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
17735 #define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
17736 #define R_SERIAL1_TR_CTRL__tr_par__tr_par__even 0
17737 #define R_SERIAL1_TR_CTRL__tr_par__tr_par__odd 1
17738 #define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__disable 0
17739 #define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__enable 1
17740 #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
17741 #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
17742
17743 #endif
17744
17745 /*
17746 * R_SERIAL1_TR_DATA
17747 * - type: WO
17748 * - addr: 0xb0000068
17749 * - group: Serial port registers
17750 */
17751
17752 #if USE_GROUP__Serial_port_registers
17753
17754 #define R_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068)
17755
17756 #ifndef REG_NO_SHADOW
17757 #define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
17758 #define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
17759 #else /* REG_NO_SHADOW */
17760 #define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
17761 #define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
17762 #endif /* REG_NO_SHADOW */
17763
17764 #define R_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_BYTE
17765 #define R_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW
17766 #define R_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
17767 #define R_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_BYTE
17768 #define R_SERIAL1_TR_DATA__TYPE (REG_BYTE)
17769 #define R_SERIAL1_TR_DATA__GET REG_GET_WO
17770 #define R_SERIAL1_TR_DATA__IGET REG_IGET_WO
17771 #define R_SERIAL1_TR_DATA__SET REG_SET_WO
17772 #define R_SERIAL1_TR_DATA__ISET REG_ISET_WO
17773 #define R_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO
17774 #define R_SERIAL1_TR_DATA__EQL REG_EQL_WO
17775 #define R_SERIAL1_TR_DATA__IEQL REG_IEQL_WO
17776 #define R_SERIAL1_TR_DATA__RD REG_RD_WO
17777 #define R_SERIAL1_TR_DATA__IRD REG_IRD_WO
17778 #define R_SERIAL1_TR_DATA__WR REG_WR_WO
17779 #define R_SERIAL1_TR_DATA__IWR REG_IWR_WO
17780
17781 #define R_SERIAL1_TR_DATA__WRITE(addr,value) \
17782 (*(addr) = (value))
17783
17784 #define R_SERIAL1_TR_DATA__data_out__data_out__MASK 0x000000ffU
17785
17786 #define R_SERIAL1_TR_DATA__data_out__MAX 0xff
17787
17788 #define R_SERIAL1_TR_DATA__data_out__MIN 0
17789
17790 #define R_SERIAL1_TR_DATA__data_out__BITNR 0
17791
17792 #define R_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
17793
17794
17795 #endif
17796
17797 /*
17798 * R_SERIAL1_XOFF
17799 * - type: WO
17800 * - addr: 0xb000006c
17801 * - group: Serial port registers
17802 */
17803
17804 #if USE_GROUP__Serial_port_registers
17805
17806 #define R_SERIAL1_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
17807
17808 #ifndef REG_NO_SHADOW
17809 #define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
17810 #define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
17811 #else /* REG_NO_SHADOW */
17812 #define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
17813 #define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
17814 #endif /* REG_NO_SHADOW */
17815
17816 #define R_SERIAL1_XOFF__STYPECAST REG_STYPECAST_UDWORD
17817 #define R_SERIAL1_XOFF__SVAL REG_SVAL_SHADOW
17818 #define R_SERIAL1_XOFF__SVAL_I REG_SVAL_I_SHADOW
17819 #define R_SERIAL1_XOFF__TYPECAST REG_TYPECAST_UDWORD
17820 #define R_SERIAL1_XOFF__TYPE (REG_UDWORD)
17821 #define R_SERIAL1_XOFF__GET REG_GET_WO
17822 #define R_SERIAL1_XOFF__IGET REG_IGET_WO
17823 #define R_SERIAL1_XOFF__SET REG_SET_WO
17824 #define R_SERIAL1_XOFF__ISET REG_ISET_WO
17825 #define R_SERIAL1_XOFF__SET_VAL REG_SET_VAL_WO
17826 #define R_SERIAL1_XOFF__EQL REG_EQL_WO
17827 #define R_SERIAL1_XOFF__IEQL REG_IEQL_WO
17828 #define R_SERIAL1_XOFF__RD REG_RD_WO
17829 #define R_SERIAL1_XOFF__IRD REG_IRD_WO
17830 #define R_SERIAL1_XOFF__WR REG_WR_WO
17831 #define R_SERIAL1_XOFF__IWR REG_IWR_WO
17832
17833 #define R_SERIAL1_XOFF__WRITE(addr,value) \
17834 (*(addr) = (value))
17835
17836 #define R_SERIAL1_XOFF__tx_stop__tx_stop__MASK 0x00000200U
17837 #define R_SERIAL1_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
17838 #define R_SERIAL1_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
17839
17840 #define R_SERIAL1_XOFF__tx_stop__MAX 0x1
17841 #define R_SERIAL1_XOFF__auto_xoff__MAX 0x1
17842 #define R_SERIAL1_XOFF__xoff_char__MAX 0xff
17843
17844 #define R_SERIAL1_XOFF__tx_stop__MIN 0
17845 #define R_SERIAL1_XOFF__auto_xoff__MIN 0
17846 #define R_SERIAL1_XOFF__xoff_char__MIN 0
17847
17848 #define R_SERIAL1_XOFF__tx_stop__BITNR 9
17849 #define R_SERIAL1_XOFF__auto_xoff__BITNR 8
17850 #define R_SERIAL1_XOFF__xoff_char__BITNR 0
17851
17852 #define R_SERIAL1_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
17853 #define R_SERIAL1_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
17854 #define R_SERIAL1_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
17855
17856 #define R_SERIAL1_XOFF__tx_stop__tx_stop__enable 0
17857 #define R_SERIAL1_XOFF__tx_stop__tx_stop__stop 1
17858 #define R_SERIAL1_XOFF__auto_xoff__auto_xoff__disable 0
17859 #define R_SERIAL1_XOFF__auto_xoff__auto_xoff__enable 1
17860
17861 #endif
17862
17863 /*
17864 * R_SERIAL2_BAUD
17865 * - type: WO
17866 * - addr: 0xb0000073
17867 * - group: Serial port registers
17868 */
17869
17870 #if USE_GROUP__Serial_port_registers
17871
17872 #define R_SERIAL2_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000073)
17873
17874 #ifndef REG_NO_SHADOW
17875 #define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 3))
17876 #define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 3))
17877 #else /* REG_NO_SHADOW */
17878 #define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
17879 #define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
17880 #endif /* REG_NO_SHADOW */
17881
17882 #define R_SERIAL2_BAUD__STYPECAST REG_STYPECAST_BYTE
17883 #define R_SERIAL2_BAUD__SVAL REG_SVAL_SHADOW
17884 #define R_SERIAL2_BAUD__SVAL_I REG_SVAL_I_SHADOW
17885 #define R_SERIAL2_BAUD__TYPECAST REG_TYPECAST_BYTE
17886 #define R_SERIAL2_BAUD__TYPE (REG_BYTE)
17887 #define R_SERIAL2_BAUD__GET REG_GET_WO
17888 #define R_SERIAL2_BAUD__IGET REG_IGET_WO
17889 #define R_SERIAL2_BAUD__SET REG_SET_WO
17890 #define R_SERIAL2_BAUD__ISET REG_ISET_WO
17891 #define R_SERIAL2_BAUD__SET_VAL REG_SET_VAL_WO
17892 #define R_SERIAL2_BAUD__EQL REG_EQL_WO
17893 #define R_SERIAL2_BAUD__IEQL REG_IEQL_WO
17894 #define R_SERIAL2_BAUD__RD REG_RD_WO
17895 #define R_SERIAL2_BAUD__IRD REG_IRD_WO
17896 #define R_SERIAL2_BAUD__WR REG_WR_WO
17897 #define R_SERIAL2_BAUD__IWR REG_IWR_WO
17898
17899 #define R_SERIAL2_BAUD__WRITE(addr,value) \
17900 (*(addr) = (value))
17901
17902 #define R_SERIAL2_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
17903 #define R_SERIAL2_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
17904
17905 #define R_SERIAL2_BAUD__tr_baud__MAX 0xf
17906 #define R_SERIAL2_BAUD__rec_baud__MAX 0xf
17907
17908 #define R_SERIAL2_BAUD__tr_baud__MIN 0
17909 #define R_SERIAL2_BAUD__rec_baud__MIN 0
17910
17911 #define R_SERIAL2_BAUD__tr_baud__BITNR 4
17912 #define R_SERIAL2_BAUD__rec_baud__BITNR 0
17913
17914 #define R_SERIAL2_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
17915 #define R_SERIAL2_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
17916
17917 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c115k2Hz 9
17918 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c1200Hz 2
17919 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c1843k2Hz 13
17920 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c19k2Hz 6
17921 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c230k4Hz 10
17922 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c2400Hz 3
17923 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c300Hz 0
17924 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c38k4Hz 7
17925 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c460k8Hz 11
17926 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c4800Hz 4
17927 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c57k6Hz 8
17928 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c600Hz 1
17929 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c6250kHz 14
17930 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c921k6Hz 12
17931 #define R_SERIAL2_BAUD__tr_baud__tr_baud__c9600Hz 5
17932 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c115k2Hz 9
17933 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c1200Hz 2
17934 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c1843k2Hz 13
17935 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c19k2Hz 6
17936 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c230k4Hz 10
17937 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c2400Hz 3
17938 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c300Hz 0
17939 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c38k4Hz 7
17940 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c460k8Hz 11
17941 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c4800Hz 4
17942 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c57k6Hz 8
17943 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c600Hz 1
17944 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c6250kHz 14
17945 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c921k6Hz 12
17946 #define R_SERIAL2_BAUD__rec_baud__rec_baud__c9600Hz 5
17947
17948 #endif
17949
17950 /*
17951 * R_SERIAL2_CTRL
17952 * - type: WO
17953 * - addr: 0xb0000070
17954 * - group: Serial port registers
17955 */
17956
17957 #if USE_GROUP__Serial_port_registers
17958
17959 #define R_SERIAL2_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000070)
17960
17961 #ifndef REG_NO_SHADOW
17962 #define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_CTRL + 0))
17963 #define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_CTRL + 0))
17964 #else /* REG_NO_SHADOW */
17965 #define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
17966 #define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
17967 #endif /* REG_NO_SHADOW */
17968
17969 #define R_SERIAL2_CTRL__STYPECAST REG_STYPECAST_UDWORD
17970 #define R_SERIAL2_CTRL__SVAL REG_SVAL_SHADOW
17971 #define R_SERIAL2_CTRL__SVAL_I REG_SVAL_I_SHADOW
17972 #define R_SERIAL2_CTRL__TYPECAST REG_TYPECAST_UDWORD
17973 #define R_SERIAL2_CTRL__TYPE (REG_UDWORD)
17974 #define R_SERIAL2_CTRL__GET REG_GET_WO
17975 #define R_SERIAL2_CTRL__IGET REG_IGET_WO
17976 #define R_SERIAL2_CTRL__SET REG_SET_WO
17977 #define R_SERIAL2_CTRL__ISET REG_ISET_WO
17978 #define R_SERIAL2_CTRL__SET_VAL REG_SET_VAL_WO
17979 #define R_SERIAL2_CTRL__EQL REG_EQL_WO
17980 #define R_SERIAL2_CTRL__IEQL REG_IEQL_WO
17981 #define R_SERIAL2_CTRL__RD REG_RD_WO
17982 #define R_SERIAL2_CTRL__IRD REG_IRD_WO
17983 #define R_SERIAL2_CTRL__WR REG_WR_WO
17984 #define R_SERIAL2_CTRL__IWR REG_IWR_WO
17985
17986 #define R_SERIAL2_CTRL__WRITE(addr,value) \
17987 (*(addr) = (value))
17988
17989 #define R_SERIAL2_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
17990 #define R_SERIAL2_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
17991 #define R_SERIAL2_CTRL__dma_err__dma_err__MASK 0x00800000U
17992 #define R_SERIAL2_CTRL__rec_enable__rec_enable__MASK 0x00400000U
17993 #define R_SERIAL2_CTRL__rts___rts___MASK 0x00200000U
17994 #define R_SERIAL2_CTRL__sampling__sampling__MASK 0x00100000U
17995 #define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
17996 #define R_SERIAL2_CTRL__rec_par__rec_par__MASK 0x00040000U
17997 #define R_SERIAL2_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
17998 #define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
17999 #define R_SERIAL2_CTRL__txd__txd__MASK 0x00008000U
18000 #define R_SERIAL2_CTRL__tr_enable__tr_enable__MASK 0x00004000U
18001 #define R_SERIAL2_CTRL__auto_cts__auto_cts__MASK 0x00002000U
18002 #define R_SERIAL2_CTRL__stop_bits__stop_bits__MASK 0x00001000U
18003 #define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
18004 #define R_SERIAL2_CTRL__tr_par__tr_par__MASK 0x00000400U
18005 #define R_SERIAL2_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
18006 #define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
18007 #define R_SERIAL2_CTRL__data_out__data_out__MASK 0x000000ffU
18008
18009 #define R_SERIAL2_CTRL__tr_baud__MAX 0xf
18010 #define R_SERIAL2_CTRL__rec_baud__MAX 0xf
18011 #define R_SERIAL2_CTRL__dma_err__MAX 0x1
18012 #define R_SERIAL2_CTRL__rec_enable__MAX 0x1
18013 #define R_SERIAL2_CTRL__rts___MAX 0x1
18014 #define R_SERIAL2_CTRL__sampling__MAX 0x1
18015 #define R_SERIAL2_CTRL__rec_stick_par__MAX 0x1
18016 #define R_SERIAL2_CTRL__rec_par__MAX 0x1
18017 #define R_SERIAL2_CTRL__rec_par_en__MAX 0x1
18018 #define R_SERIAL2_CTRL__rec_bitnr__MAX 0x1
18019 #define R_SERIAL2_CTRL__txd__MAX 0x1
18020 #define R_SERIAL2_CTRL__tr_enable__MAX 0x1
18021 #define R_SERIAL2_CTRL__auto_cts__MAX 0x1
18022 #define R_SERIAL2_CTRL__stop_bits__MAX 0x1
18023 #define R_SERIAL2_CTRL__tr_stick_par__MAX 0x1
18024 #define R_SERIAL2_CTRL__tr_par__MAX 0x1
18025 #define R_SERIAL2_CTRL__tr_par_en__MAX 0x1
18026 #define R_SERIAL2_CTRL__tr_bitnr__MAX 0x1
18027 #define R_SERIAL2_CTRL__data_out__MAX 0xff
18028
18029 #define R_SERIAL2_CTRL__tr_baud__MIN 0
18030 #define R_SERIAL2_CTRL__rec_baud__MIN 0
18031 #define R_SERIAL2_CTRL__dma_err__MIN 0
18032 #define R_SERIAL2_CTRL__rec_enable__MIN 0
18033 #define R_SERIAL2_CTRL__rts___MIN 0
18034 #define R_SERIAL2_CTRL__sampling__MIN 0
18035 #define R_SERIAL2_CTRL__rec_stick_par__MIN 0
18036 #define R_SERIAL2_CTRL__rec_par__MIN 0
18037 #define R_SERIAL2_CTRL__rec_par_en__MIN 0
18038 #define R_SERIAL2_CTRL__rec_bitnr__MIN 0
18039 #define R_SERIAL2_CTRL__txd__MIN 0
18040 #define R_SERIAL2_CTRL__tr_enable__MIN 0
18041 #define R_SERIAL2_CTRL__auto_cts__MIN 0
18042 #define R_SERIAL2_CTRL__stop_bits__MIN 0
18043 #define R_SERIAL2_CTRL__tr_stick_par__MIN 0
18044 #define R_SERIAL2_CTRL__tr_par__MIN 0
18045 #define R_SERIAL2_CTRL__tr_par_en__MIN 0
18046 #define R_SERIAL2_CTRL__tr_bitnr__MIN 0
18047 #define R_SERIAL2_CTRL__data_out__MIN 0
18048
18049 #define R_SERIAL2_CTRL__tr_baud__BITNR 28
18050 #define R_SERIAL2_CTRL__rec_baud__BITNR 24
18051 #define R_SERIAL2_CTRL__dma_err__BITNR 23
18052 #define R_SERIAL2_CTRL__rec_enable__BITNR 22
18053 #define R_SERIAL2_CTRL__rts___BITNR 21
18054 #define R_SERIAL2_CTRL__sampling__BITNR 20
18055 #define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
18056 #define R_SERIAL2_CTRL__rec_par__BITNR 18
18057 #define R_SERIAL2_CTRL__rec_par_en__BITNR 17
18058 #define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
18059 #define R_SERIAL2_CTRL__txd__BITNR 15
18060 #define R_SERIAL2_CTRL__tr_enable__BITNR 14
18061 #define R_SERIAL2_CTRL__auto_cts__BITNR 13
18062 #define R_SERIAL2_CTRL__stop_bits__BITNR 12
18063 #define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
18064 #define R_SERIAL2_CTRL__tr_par__BITNR 10
18065 #define R_SERIAL2_CTRL__tr_par_en__BITNR 9
18066 #define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
18067 #define R_SERIAL2_CTRL__data_out__BITNR 0
18068
18069 #define R_SERIAL2_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
18070 #define R_SERIAL2_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
18071 #define R_SERIAL2_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
18072 #define R_SERIAL2_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
18073 #define R_SERIAL2_CTRL__rts___rts___VAL REG_VAL_ENUM
18074 #define R_SERIAL2_CTRL__sampling__sampling__VAL REG_VAL_ENUM
18075 #define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
18076 #define R_SERIAL2_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
18077 #define R_SERIAL2_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
18078 #define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
18079 #define R_SERIAL2_CTRL__txd__txd__VAL REG_VAL_VAL
18080 #define R_SERIAL2_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
18081 #define R_SERIAL2_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
18082 #define R_SERIAL2_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
18083 #define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
18084 #define R_SERIAL2_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
18085 #define R_SERIAL2_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
18086 #define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
18087 #define R_SERIAL2_CTRL__data_out__data_out__VAL REG_VAL_VAL
18088
18089 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c115k2Hz 9
18090 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c1200Hz 2
18091 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c1843k2Hz 13
18092 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c19k2Hz 6
18093 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c230k4Hz 10
18094 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c2400Hz 3
18095 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c300Hz 0
18096 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c38k4Hz 7
18097 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c460k8Hz 11
18098 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c4800Hz 4
18099 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c57k6Hz 8
18100 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c600Hz 1
18101 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c6250kHz 14
18102 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c921k6Hz 12
18103 #define R_SERIAL2_CTRL__tr_baud__tr_baud__c9600Hz 5
18104 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c115k2Hz 9
18105 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c1200Hz 2
18106 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c1843k2Hz 13
18107 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c19k2Hz 6
18108 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c230k4Hz 10
18109 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c2400Hz 3
18110 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c300Hz 0
18111 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c38k4Hz 7
18112 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c460k8Hz 11
18113 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c4800Hz 4
18114 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c57k6Hz 8
18115 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c600Hz 1
18116 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c6250kHz 14
18117 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c921k6Hz 12
18118 #define R_SERIAL2_CTRL__rec_baud__rec_baud__c9600Hz 5
18119 #define R_SERIAL2_CTRL__dma_err__dma_err__ignore 1
18120 #define R_SERIAL2_CTRL__dma_err__dma_err__stop 0
18121 #define R_SERIAL2_CTRL__rec_enable__rec_enable__disable 0
18122 #define R_SERIAL2_CTRL__rec_enable__rec_enable__enable 1
18123 #define R_SERIAL2_CTRL__rts___rts___active 0
18124 #define R_SERIAL2_CTRL__rts___rts___inactive 1
18125 #define R_SERIAL2_CTRL__sampling__sampling__majority 1
18126 #define R_SERIAL2_CTRL__sampling__sampling__middle 0
18127 #define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__normal 0
18128 #define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__stick 1
18129 #define R_SERIAL2_CTRL__rec_par__rec_par__even 0
18130 #define R_SERIAL2_CTRL__rec_par__rec_par__odd 1
18131 #define R_SERIAL2_CTRL__rec_par_en__rec_par_en__disable 0
18132 #define R_SERIAL2_CTRL__rec_par_en__rec_par_en__enable 1
18133 #define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
18134 #define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
18135 #define R_SERIAL2_CTRL__tr_enable__tr_enable__disable 0
18136 #define R_SERIAL2_CTRL__tr_enable__tr_enable__enable 1
18137 #define R_SERIAL2_CTRL__auto_cts__auto_cts__active 1
18138 #define R_SERIAL2_CTRL__auto_cts__auto_cts__disabled 0
18139 #define R_SERIAL2_CTRL__stop_bits__stop_bits__one_bit 0
18140 #define R_SERIAL2_CTRL__stop_bits__stop_bits__two_bits 1
18141 #define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__normal 0
18142 #define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__stick 1
18143 #define R_SERIAL2_CTRL__tr_par__tr_par__even 0
18144 #define R_SERIAL2_CTRL__tr_par__tr_par__odd 1
18145 #define R_SERIAL2_CTRL__tr_par_en__tr_par_en__disable 0
18146 #define R_SERIAL2_CTRL__tr_par_en__tr_par_en__enable 1
18147 #define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
18148 #define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
18149
18150 #endif
18151
18152 /*
18153 * R_SERIAL2_READ
18154 * - type: RO
18155 * - addr: 0xb0000070
18156 * - group: Serial port registers
18157 */
18158
18159 #if USE_GROUP__Serial_port_registers
18160
18161 #define R_SERIAL2_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000070)
18162 #define R_SERIAL2_READ__SVAL REG_SVAL_SHADOW
18163 #define R_SERIAL2_READ__SVAL_I REG_SVAL_I_SHADOW
18164 #define R_SERIAL2_READ__TYPECAST REG_TYPECAST_UDWORD
18165 #define R_SERIAL2_READ__TYPE (REG_UDWORD)
18166 #define R_SERIAL2_READ__GET REG_GET_RO
18167 #define R_SERIAL2_READ__IGET REG_IGET_RO
18168 #define R_SERIAL2_READ__SET REG_SET_RO
18169 #define R_SERIAL2_READ__ISET REG_ISET_RO
18170 #define R_SERIAL2_READ__SET_VAL REG_SET_VAL_RO
18171 #define R_SERIAL2_READ__EQL REG_EQL_RO
18172 #define R_SERIAL2_READ__IEQL REG_IEQL_RO
18173 #define R_SERIAL2_READ__RD REG_RD_RO
18174 #define R_SERIAL2_READ__IRD REG_IRD_RO
18175 #define R_SERIAL2_READ__WR REG_WR_RO
18176 #define R_SERIAL2_READ__IWR REG_IWR_RO
18177
18178 #define R_SERIAL2_READ__READ(addr) \
18179 (*(addr))
18180
18181 #define R_SERIAL2_READ__xoff_detect__xoff_detect__MASK 0x00008000U
18182 #define R_SERIAL2_READ__cts___cts___MASK 0x00004000U
18183 #define R_SERIAL2_READ__tr_ready__tr_ready__MASK 0x00002000U
18184 #define R_SERIAL2_READ__rxd__rxd__MASK 0x00001000U
18185 #define R_SERIAL2_READ__overrun__overrun__MASK 0x00000800U
18186 #define R_SERIAL2_READ__par_err__par_err__MASK 0x00000400U
18187 #define R_SERIAL2_READ__framing_err__framing_err__MASK 0x00000200U
18188 #define R_SERIAL2_READ__data_avail__data_avail__MASK 0x00000100U
18189 #define R_SERIAL2_READ__data_in__data_in__MASK 0x000000ffU
18190
18191 #define R_SERIAL2_READ__xoff_detect__MAX 0x1
18192 #define R_SERIAL2_READ__cts___MAX 0x1
18193 #define R_SERIAL2_READ__tr_ready__MAX 0x1
18194 #define R_SERIAL2_READ__rxd__MAX 0x1
18195 #define R_SERIAL2_READ__overrun__MAX 0x1
18196 #define R_SERIAL2_READ__par_err__MAX 0x1
18197 #define R_SERIAL2_READ__framing_err__MAX 0x1
18198 #define R_SERIAL2_READ__data_avail__MAX 0x1
18199 #define R_SERIAL2_READ__data_in__MAX 0xff
18200
18201 #define R_SERIAL2_READ__xoff_detect__MIN 0
18202 #define R_SERIAL2_READ__cts___MIN 0
18203 #define R_SERIAL2_READ__tr_ready__MIN 0
18204 #define R_SERIAL2_READ__rxd__MIN 0
18205 #define R_SERIAL2_READ__overrun__MIN 0
18206 #define R_SERIAL2_READ__par_err__MIN 0
18207 #define R_SERIAL2_READ__framing_err__MIN 0
18208 #define R_SERIAL2_READ__data_avail__MIN 0
18209 #define R_SERIAL2_READ__data_in__MIN 0
18210
18211 #define R_SERIAL2_READ__xoff_detect__BITNR 15
18212 #define R_SERIAL2_READ__cts___BITNR 14
18213 #define R_SERIAL2_READ__tr_ready__BITNR 13
18214 #define R_SERIAL2_READ__rxd__BITNR 12
18215 #define R_SERIAL2_READ__overrun__BITNR 11
18216 #define R_SERIAL2_READ__par_err__BITNR 10
18217 #define R_SERIAL2_READ__framing_err__BITNR 9
18218 #define R_SERIAL2_READ__data_avail__BITNR 8
18219 #define R_SERIAL2_READ__data_in__BITNR 0
18220
18221 #define R_SERIAL2_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
18222 #define R_SERIAL2_READ__cts___cts___VAL REG_VAL_ENUM
18223 #define R_SERIAL2_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
18224 #define R_SERIAL2_READ__rxd__rxd__VAL REG_VAL_VAL
18225 #define R_SERIAL2_READ__overrun__overrun__VAL REG_VAL_ENUM
18226 #define R_SERIAL2_READ__par_err__par_err__VAL REG_VAL_ENUM
18227 #define R_SERIAL2_READ__framing_err__framing_err__VAL REG_VAL_ENUM
18228 #define R_SERIAL2_READ__data_avail__data_avail__VAL REG_VAL_ENUM
18229 #define R_SERIAL2_READ__data_in__data_in__VAL REG_VAL_VAL
18230
18231 #define R_SERIAL2_READ__xoff_detect__xoff_detect__no_xoff 0
18232 #define R_SERIAL2_READ__xoff_detect__xoff_detect__xoff 1
18233 #define R_SERIAL2_READ__cts___cts___active 0
18234 #define R_SERIAL2_READ__cts___cts___inactive 1
18235 #define R_SERIAL2_READ__tr_ready__tr_ready__full 0
18236 #define R_SERIAL2_READ__tr_ready__tr_ready__ready 1
18237 #define R_SERIAL2_READ__overrun__overrun__no 0
18238 #define R_SERIAL2_READ__overrun__overrun__yes 1
18239 #define R_SERIAL2_READ__par_err__par_err__no 0
18240 #define R_SERIAL2_READ__par_err__par_err__yes 1
18241 #define R_SERIAL2_READ__framing_err__framing_err__no 0
18242 #define R_SERIAL2_READ__framing_err__framing_err__yes 1
18243 #define R_SERIAL2_READ__data_avail__data_avail__no 0
18244 #define R_SERIAL2_READ__data_avail__data_avail__yes 1
18245
18246 #endif
18247
18248 /*
18249 * R_SERIAL2_REC_CTRL
18250 * - type: WO
18251 * - addr: 0xb0000072
18252 * - group: Serial port registers
18253 */
18254
18255 #if USE_GROUP__Serial_port_registers
18256
18257 #define R_SERIAL2_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000072)
18258
18259 #ifndef REG_NO_SHADOW
18260 #define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 2))
18261 #define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 2))
18262 #else /* REG_NO_SHADOW */
18263 #define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
18264 #define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
18265 #endif /* REG_NO_SHADOW */
18266
18267 #define R_SERIAL2_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
18268 #define R_SERIAL2_REC_CTRL__SVAL REG_SVAL_SHADOW
18269 #define R_SERIAL2_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
18270 #define R_SERIAL2_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
18271 #define R_SERIAL2_REC_CTRL__TYPE (REG_BYTE)
18272 #define R_SERIAL2_REC_CTRL__GET REG_GET_WO
18273 #define R_SERIAL2_REC_CTRL__IGET REG_IGET_WO
18274 #define R_SERIAL2_REC_CTRL__SET REG_SET_WO
18275 #define R_SERIAL2_REC_CTRL__ISET REG_ISET_WO
18276 #define R_SERIAL2_REC_CTRL__SET_VAL REG_SET_VAL_WO
18277 #define R_SERIAL2_REC_CTRL__EQL REG_EQL_WO
18278 #define R_SERIAL2_REC_CTRL__IEQL REG_IEQL_WO
18279 #define R_SERIAL2_REC_CTRL__RD REG_RD_WO
18280 #define R_SERIAL2_REC_CTRL__IRD REG_IRD_WO
18281 #define R_SERIAL2_REC_CTRL__WR REG_WR_WO
18282 #define R_SERIAL2_REC_CTRL__IWR REG_IWR_WO
18283
18284 #define R_SERIAL2_REC_CTRL__WRITE(addr,value) \
18285 (*(addr) = (value))
18286
18287 #define R_SERIAL2_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
18288 #define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
18289 #define R_SERIAL2_REC_CTRL__rts___rts___MASK 0x00000020U
18290 #define R_SERIAL2_REC_CTRL__sampling__sampling__MASK 0x00000010U
18291 #define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
18292 #define R_SERIAL2_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
18293 #define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
18294 #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
18295
18296 #define R_SERIAL2_REC_CTRL__dma_err__MAX 0x1
18297 #define R_SERIAL2_REC_CTRL__rec_enable__MAX 0x1
18298 #define R_SERIAL2_REC_CTRL__rts___MAX 0x1
18299 #define R_SERIAL2_REC_CTRL__sampling__MAX 0x1
18300 #define R_SERIAL2_REC_CTRL__rec_stick_par__MAX 0x1
18301 #define R_SERIAL2_REC_CTRL__rec_par__MAX 0x1
18302 #define R_SERIAL2_REC_CTRL__rec_par_en__MAX 0x1
18303 #define R_SERIAL2_REC_CTRL__rec_bitnr__MAX 0x1
18304
18305 #define R_SERIAL2_REC_CTRL__dma_err__MIN 0
18306 #define R_SERIAL2_REC_CTRL__rec_enable__MIN 0
18307 #define R_SERIAL2_REC_CTRL__rts___MIN 0
18308 #define R_SERIAL2_REC_CTRL__sampling__MIN 0
18309 #define R_SERIAL2_REC_CTRL__rec_stick_par__MIN 0
18310 #define R_SERIAL2_REC_CTRL__rec_par__MIN 0
18311 #define R_SERIAL2_REC_CTRL__rec_par_en__MIN 0
18312 #define R_SERIAL2_REC_CTRL__rec_bitnr__MIN 0
18313
18314 #define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
18315 #define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
18316 #define R_SERIAL2_REC_CTRL__rts___BITNR 5
18317 #define R_SERIAL2_REC_CTRL__sampling__BITNR 4
18318 #define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
18319 #define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
18320 #define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
18321 #define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
18322
18323 #define R_SERIAL2_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
18324 #define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
18325 #define R_SERIAL2_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
18326 #define R_SERIAL2_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
18327 #define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
18328 #define R_SERIAL2_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
18329 #define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
18330 #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
18331
18332 #define R_SERIAL2_REC_CTRL__dma_err__dma_err__ignore 1
18333 #define R_SERIAL2_REC_CTRL__dma_err__dma_err__stop 0
18334 #define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__disable 0
18335 #define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__enable 1
18336 #define R_SERIAL2_REC_CTRL__rts___rts___active 0
18337 #define R_SERIAL2_REC_CTRL__rts___rts___inactive 1
18338 #define R_SERIAL2_REC_CTRL__sampling__sampling__majority 1
18339 #define R_SERIAL2_REC_CTRL__sampling__sampling__middle 0
18340 #define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
18341 #define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
18342 #define R_SERIAL2_REC_CTRL__rec_par__rec_par__even 0
18343 #define R_SERIAL2_REC_CTRL__rec_par__rec_par__odd 1
18344 #define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__disable 0
18345 #define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__enable 1
18346 #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
18347 #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
18348
18349 #endif
18350
18351 /*
18352 * R_SERIAL2_REC_DATA
18353 * - type: RO
18354 * - addr: 0xb0000070
18355 * - group: Serial port registers
18356 */
18357
18358 #if USE_GROUP__Serial_port_registers
18359
18360 #define R_SERIAL2_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070)
18361 #define R_SERIAL2_REC_DATA__SVAL REG_SVAL_SHADOW
18362 #define R_SERIAL2_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
18363 #define R_SERIAL2_REC_DATA__TYPECAST REG_TYPECAST_BYTE
18364 #define R_SERIAL2_REC_DATA__TYPE (REG_BYTE)
18365 #define R_SERIAL2_REC_DATA__GET REG_GET_RO
18366 #define R_SERIAL2_REC_DATA__IGET REG_IGET_RO
18367 #define R_SERIAL2_REC_DATA__SET REG_SET_RO
18368 #define R_SERIAL2_REC_DATA__ISET REG_ISET_RO
18369 #define R_SERIAL2_REC_DATA__SET_VAL REG_SET_VAL_RO
18370 #define R_SERIAL2_REC_DATA__EQL REG_EQL_RO
18371 #define R_SERIAL2_REC_DATA__IEQL REG_IEQL_RO
18372 #define R_SERIAL2_REC_DATA__RD REG_RD_RO
18373 #define R_SERIAL2_REC_DATA__IRD REG_IRD_RO
18374 #define R_SERIAL2_REC_DATA__WR REG_WR_RO
18375 #define R_SERIAL2_REC_DATA__IWR REG_IWR_RO
18376
18377 #define R_SERIAL2_REC_DATA__READ(addr) \
18378 (*(addr))
18379
18380 #define R_SERIAL2_REC_DATA__data_in__data_in__MASK 0x000000ffU
18381
18382 #define R_SERIAL2_REC_DATA__data_in__MAX 0xff
18383
18384 #define R_SERIAL2_REC_DATA__data_in__MIN 0
18385
18386 #define R_SERIAL2_REC_DATA__data_in__BITNR 0
18387
18388 #define R_SERIAL2_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
18389
18390
18391 #endif
18392
18393 /*
18394 * R_SERIAL2_STATUS
18395 * - type: RO
18396 * - addr: 0xb0000071
18397 * - group: Serial port registers
18398 */
18399
18400 #if USE_GROUP__Serial_port_registers
18401
18402 #define R_SERIAL2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000071)
18403 #define R_SERIAL2_STATUS__SVAL REG_SVAL_SHADOW
18404 #define R_SERIAL2_STATUS__SVAL_I REG_SVAL_I_SHADOW
18405 #define R_SERIAL2_STATUS__TYPECAST REG_TYPECAST_BYTE
18406 #define R_SERIAL2_STATUS__TYPE (REG_BYTE)
18407 #define R_SERIAL2_STATUS__GET REG_GET_RO
18408 #define R_SERIAL2_STATUS__IGET REG_IGET_RO
18409 #define R_SERIAL2_STATUS__SET REG_SET_RO
18410 #define R_SERIAL2_STATUS__ISET REG_ISET_RO
18411 #define R_SERIAL2_STATUS__SET_VAL REG_SET_VAL_RO
18412 #define R_SERIAL2_STATUS__EQL REG_EQL_RO
18413 #define R_SERIAL2_STATUS__IEQL REG_IEQL_RO
18414 #define R_SERIAL2_STATUS__RD REG_RD_RO
18415 #define R_SERIAL2_STATUS__IRD REG_IRD_RO
18416 #define R_SERIAL2_STATUS__WR REG_WR_RO
18417 #define R_SERIAL2_STATUS__IWR REG_IWR_RO
18418
18419 #define R_SERIAL2_STATUS__READ(addr) \
18420 (*(addr))
18421
18422 #define R_SERIAL2_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
18423 #define R_SERIAL2_STATUS__cts___cts___MASK 0x00000040U
18424 #define R_SERIAL2_STATUS__tr_ready__tr_ready__MASK 0x00000020U
18425 #define R_SERIAL2_STATUS__rxd__rxd__MASK 0x00000010U
18426 #define R_SERIAL2_STATUS__overrun__overrun__MASK 0x00000008U
18427 #define R_SERIAL2_STATUS__par_err__par_err__MASK 0x00000004U
18428 #define R_SERIAL2_STATUS__framing_err__framing_err__MASK 0x00000002U
18429 #define R_SERIAL2_STATUS__data_avail__data_avail__MASK 0x00000001U
18430
18431 #define R_SERIAL2_STATUS__xoff_detect__MAX 0x1
18432 #define R_SERIAL2_STATUS__cts___MAX 0x1
18433 #define R_SERIAL2_STATUS__tr_ready__MAX 0x1
18434 #define R_SERIAL2_STATUS__rxd__MAX 0x1
18435 #define R_SERIAL2_STATUS__overrun__MAX 0x1
18436 #define R_SERIAL2_STATUS__par_err__MAX 0x1
18437 #define R_SERIAL2_STATUS__framing_err__MAX 0x1
18438 #define R_SERIAL2_STATUS__data_avail__MAX 0x1
18439
18440 #define R_SERIAL2_STATUS__xoff_detect__MIN 0
18441 #define R_SERIAL2_STATUS__cts___MIN 0
18442 #define R_SERIAL2_STATUS__tr_ready__MIN 0
18443 #define R_SERIAL2_STATUS__rxd__MIN 0
18444 #define R_SERIAL2_STATUS__overrun__MIN 0
18445 #define R_SERIAL2_STATUS__par_err__MIN 0
18446 #define R_SERIAL2_STATUS__framing_err__MIN 0
18447 #define R_SERIAL2_STATUS__data_avail__MIN 0
18448
18449 #define R_SERIAL2_STATUS__xoff_detect__BITNR 7
18450 #define R_SERIAL2_STATUS__cts___BITNR 6
18451 #define R_SERIAL2_STATUS__tr_ready__BITNR 5
18452 #define R_SERIAL2_STATUS__rxd__BITNR 4
18453 #define R_SERIAL2_STATUS__overrun__BITNR 3
18454 #define R_SERIAL2_STATUS__par_err__BITNR 2
18455 #define R_SERIAL2_STATUS__framing_err__BITNR 1
18456 #define R_SERIAL2_STATUS__data_avail__BITNR 0
18457
18458 #define R_SERIAL2_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
18459 #define R_SERIAL2_STATUS__cts___cts___VAL REG_VAL_ENUM
18460 #define R_SERIAL2_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
18461 #define R_SERIAL2_STATUS__rxd__rxd__VAL REG_VAL_VAL
18462 #define R_SERIAL2_STATUS__overrun__overrun__VAL REG_VAL_ENUM
18463 #define R_SERIAL2_STATUS__par_err__par_err__VAL REG_VAL_ENUM
18464 #define R_SERIAL2_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
18465 #define R_SERIAL2_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
18466
18467 #define R_SERIAL2_STATUS__xoff_detect__xoff_detect__no_xoff 0
18468 #define R_SERIAL2_STATUS__xoff_detect__xoff_detect__xoff 1
18469 #define R_SERIAL2_STATUS__cts___cts___active 0
18470 #define R_SERIAL2_STATUS__cts___cts___inactive 1
18471 #define R_SERIAL2_STATUS__tr_ready__tr_ready__full 0
18472 #define R_SERIAL2_STATUS__tr_ready__tr_ready__ready 1
18473 #define R_SERIAL2_STATUS__overrun__overrun__no 0
18474 #define R_SERIAL2_STATUS__overrun__overrun__yes 1
18475 #define R_SERIAL2_STATUS__par_err__par_err__no 0
18476 #define R_SERIAL2_STATUS__par_err__par_err__yes 1
18477 #define R_SERIAL2_STATUS__framing_err__framing_err__no 0
18478 #define R_SERIAL2_STATUS__framing_err__framing_err__yes 1
18479 #define R_SERIAL2_STATUS__data_avail__data_avail__no 0
18480 #define R_SERIAL2_STATUS__data_avail__data_avail__yes 1
18481
18482 #endif
18483
18484 /*
18485 * R_SERIAL2_TR_CTRL
18486 * - type: WO
18487 * - addr: 0xb0000071
18488 * - group: Serial port registers
18489 */
18490
18491 #if USE_GROUP__Serial_port_registers
18492
18493 #define R_SERIAL2_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000071)
18494
18495 #ifndef REG_NO_SHADOW
18496 #define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 1))
18497 #define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 1))
18498 #else /* REG_NO_SHADOW */
18499 #define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
18500 #define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
18501 #endif /* REG_NO_SHADOW */
18502
18503 #define R_SERIAL2_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
18504 #define R_SERIAL2_TR_CTRL__SVAL REG_SVAL_SHADOW
18505 #define R_SERIAL2_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
18506 #define R_SERIAL2_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
18507 #define R_SERIAL2_TR_CTRL__TYPE (REG_BYTE)
18508 #define R_SERIAL2_TR_CTRL__GET REG_GET_WO
18509 #define R_SERIAL2_TR_CTRL__IGET REG_IGET_WO
18510 #define R_SERIAL2_TR_CTRL__SET REG_SET_WO
18511 #define R_SERIAL2_TR_CTRL__ISET REG_ISET_WO
18512 #define R_SERIAL2_TR_CTRL__SET_VAL REG_SET_VAL_WO
18513 #define R_SERIAL2_TR_CTRL__EQL REG_EQL_WO
18514 #define R_SERIAL2_TR_CTRL__IEQL REG_IEQL_WO
18515 #define R_SERIAL2_TR_CTRL__RD REG_RD_WO
18516 #define R_SERIAL2_TR_CTRL__IRD REG_IRD_WO
18517 #define R_SERIAL2_TR_CTRL__WR REG_WR_WO
18518 #define R_SERIAL2_TR_CTRL__IWR REG_IWR_WO
18519
18520 #define R_SERIAL2_TR_CTRL__WRITE(addr,value) \
18521 (*(addr) = (value))
18522
18523 #define R_SERIAL2_TR_CTRL__txd__txd__MASK 0x00000080U
18524 #define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
18525 #define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
18526 #define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
18527 #define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
18528 #define R_SERIAL2_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
18529 #define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
18530 #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
18531
18532 #define R_SERIAL2_TR_CTRL__txd__MAX 0x1
18533 #define R_SERIAL2_TR_CTRL__tr_enable__MAX 0x1
18534 #define R_SERIAL2_TR_CTRL__auto_cts__MAX 0x1
18535 #define R_SERIAL2_TR_CTRL__stop_bits__MAX 0x1
18536 #define R_SERIAL2_TR_CTRL__tr_stick_par__MAX 0x1
18537 #define R_SERIAL2_TR_CTRL__tr_par__MAX 0x1
18538 #define R_SERIAL2_TR_CTRL__tr_par_en__MAX 0x1
18539 #define R_SERIAL2_TR_CTRL__tr_bitnr__MAX 0x1
18540
18541 #define R_SERIAL2_TR_CTRL__txd__MIN 0
18542 #define R_SERIAL2_TR_CTRL__tr_enable__MIN 0
18543 #define R_SERIAL2_TR_CTRL__auto_cts__MIN 0
18544 #define R_SERIAL2_TR_CTRL__stop_bits__MIN 0
18545 #define R_SERIAL2_TR_CTRL__tr_stick_par__MIN 0
18546 #define R_SERIAL2_TR_CTRL__tr_par__MIN 0
18547 #define R_SERIAL2_TR_CTRL__tr_par_en__MIN 0
18548 #define R_SERIAL2_TR_CTRL__tr_bitnr__MIN 0
18549
18550 #define R_SERIAL2_TR_CTRL__txd__BITNR 7
18551 #define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
18552 #define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
18553 #define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
18554 #define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
18555 #define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
18556 #define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
18557 #define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
18558
18559 #define R_SERIAL2_TR_CTRL__txd__txd__VAL REG_VAL_VAL
18560 #define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
18561 #define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
18562 #define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
18563 #define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
18564 #define R_SERIAL2_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
18565 #define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
18566 #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
18567
18568 #define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__disable 0
18569 #define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__enable 1
18570 #define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__active 1
18571 #define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__disabled 0
18572 #define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__one_bit 0
18573 #define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__two_bits 1
18574 #define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
18575 #define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
18576 #define R_SERIAL2_TR_CTRL__tr_par__tr_par__even 0
18577 #define R_SERIAL2_TR_CTRL__tr_par__tr_par__odd 1
18578 #define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__disable 0
18579 #define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__enable 1
18580 #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
18581 #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
18582
18583 #endif
18584
18585 /*
18586 * R_SERIAL2_TR_DATA
18587 * - type: WO
18588 * - addr: 0xb0000070
18589 * - group: Serial port registers
18590 */
18591
18592 #if USE_GROUP__Serial_port_registers
18593
18594 #define R_SERIAL2_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070)
18595
18596 #ifndef REG_NO_SHADOW
18597 #define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 0))
18598 #define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 0))
18599 #else /* REG_NO_SHADOW */
18600 #define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
18601 #define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
18602 #endif /* REG_NO_SHADOW */
18603
18604 #define R_SERIAL2_TR_DATA__STYPECAST REG_STYPECAST_BYTE
18605 #define R_SERIAL2_TR_DATA__SVAL REG_SVAL_SHADOW
18606 #define R_SERIAL2_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
18607 #define R_SERIAL2_TR_DATA__TYPECAST REG_TYPECAST_BYTE
18608 #define R_SERIAL2_TR_DATA__TYPE (REG_BYTE)
18609 #define R_SERIAL2_TR_DATA__GET REG_GET_WO
18610 #define R_SERIAL2_TR_DATA__IGET REG_IGET_WO
18611 #define R_SERIAL2_TR_DATA__SET REG_SET_WO
18612 #define R_SERIAL2_TR_DATA__ISET REG_ISET_WO
18613 #define R_SERIAL2_TR_DATA__SET_VAL REG_SET_VAL_WO
18614 #define R_SERIAL2_TR_DATA__EQL REG_EQL_WO
18615 #define R_SERIAL2_TR_DATA__IEQL REG_IEQL_WO
18616 #define R_SERIAL2_TR_DATA__RD REG_RD_WO
18617 #define R_SERIAL2_TR_DATA__IRD REG_IRD_WO
18618 #define R_SERIAL2_TR_DATA__WR REG_WR_WO
18619 #define R_SERIAL2_TR_DATA__IWR REG_IWR_WO
18620
18621 #define R_SERIAL2_TR_DATA__WRITE(addr,value) \
18622 (*(addr) = (value))
18623
18624 #define R_SERIAL2_TR_DATA__data_out__data_out__MASK 0x000000ffU
18625
18626 #define R_SERIAL2_TR_DATA__data_out__MAX 0xff
18627
18628 #define R_SERIAL2_TR_DATA__data_out__MIN 0
18629
18630 #define R_SERIAL2_TR_DATA__data_out__BITNR 0
18631
18632 #define R_SERIAL2_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
18633
18634
18635 #endif
18636
18637 /*
18638 * R_SERIAL2_XOFF
18639 * - type: WO
18640 * - addr: 0xb0000074
18641 * - group: Serial port registers
18642 */
18643
18644 #if USE_GROUP__Serial_port_registers
18645
18646 #define R_SERIAL2_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000074)
18647
18648 #ifndef REG_NO_SHADOW
18649 #define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_XOFF + 0))
18650 #define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_XOFF + 0))
18651 #else /* REG_NO_SHADOW */
18652 #define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
18653 #define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
18654 #endif /* REG_NO_SHADOW */
18655
18656 #define R_SERIAL2_XOFF__STYPECAST REG_STYPECAST_UDWORD
18657 #define R_SERIAL2_XOFF__SVAL REG_SVAL_SHADOW
18658 #define R_SERIAL2_XOFF__SVAL_I REG_SVAL_I_SHADOW
18659 #define R_SERIAL2_XOFF__TYPECAST REG_TYPECAST_UDWORD
18660 #define R_SERIAL2_XOFF__TYPE (REG_UDWORD)
18661 #define R_SERIAL2_XOFF__GET REG_GET_WO
18662 #define R_SERIAL2_XOFF__IGET REG_IGET_WO
18663 #define R_SERIAL2_XOFF__SET REG_SET_WO
18664 #define R_SERIAL2_XOFF__ISET REG_ISET_WO
18665 #define R_SERIAL2_XOFF__SET_VAL REG_SET_VAL_WO
18666 #define R_SERIAL2_XOFF__EQL REG_EQL_WO
18667 #define R_SERIAL2_XOFF__IEQL REG_IEQL_WO
18668 #define R_SERIAL2_XOFF__RD REG_RD_WO
18669 #define R_SERIAL2_XOFF__IRD REG_IRD_WO
18670 #define R_SERIAL2_XOFF__WR REG_WR_WO
18671 #define R_SERIAL2_XOFF__IWR REG_IWR_WO
18672
18673 #define R_SERIAL2_XOFF__WRITE(addr,value) \
18674 (*(addr) = (value))
18675
18676 #define R_SERIAL2_XOFF__tx_stop__tx_stop__MASK 0x00000200U
18677 #define R_SERIAL2_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
18678 #define R_SERIAL2_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
18679
18680 #define R_SERIAL2_XOFF__tx_stop__MAX 0x1
18681 #define R_SERIAL2_XOFF__auto_xoff__MAX 0x1
18682 #define R_SERIAL2_XOFF__xoff_char__MAX 0xff
18683
18684 #define R_SERIAL2_XOFF__tx_stop__MIN 0
18685 #define R_SERIAL2_XOFF__auto_xoff__MIN 0
18686 #define R_SERIAL2_XOFF__xoff_char__MIN 0
18687
18688 #define R_SERIAL2_XOFF__tx_stop__BITNR 9
18689 #define R_SERIAL2_XOFF__auto_xoff__BITNR 8
18690 #define R_SERIAL2_XOFF__xoff_char__BITNR 0
18691
18692 #define R_SERIAL2_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
18693 #define R_SERIAL2_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
18694 #define R_SERIAL2_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
18695
18696 #define R_SERIAL2_XOFF__tx_stop__tx_stop__enable 0
18697 #define R_SERIAL2_XOFF__tx_stop__tx_stop__stop 1
18698 #define R_SERIAL2_XOFF__auto_xoff__auto_xoff__disable 0
18699 #define R_SERIAL2_XOFF__auto_xoff__auto_xoff__enable 1
18700
18701 #endif
18702
18703 /*
18704 * R_SERIAL3_BAUD
18705 * - type: WO
18706 * - addr: 0xb000007b
18707 * - group: Serial port registers
18708 */
18709
18710 #if USE_GROUP__Serial_port_registers
18711
18712 #define R_SERIAL3_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000007b)
18713
18714 #ifndef REG_NO_SHADOW
18715 #define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 3))
18716 #define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 3))
18717 #else /* REG_NO_SHADOW */
18718 #define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
18719 #define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
18720 #endif /* REG_NO_SHADOW */
18721
18722 #define R_SERIAL3_BAUD__STYPECAST REG_STYPECAST_BYTE
18723 #define R_SERIAL3_BAUD__SVAL REG_SVAL_SHADOW
18724 #define R_SERIAL3_BAUD__SVAL_I REG_SVAL_I_SHADOW
18725 #define R_SERIAL3_BAUD__TYPECAST REG_TYPECAST_BYTE
18726 #define R_SERIAL3_BAUD__TYPE (REG_BYTE)
18727 #define R_SERIAL3_BAUD__GET REG_GET_WO
18728 #define R_SERIAL3_BAUD__IGET REG_IGET_WO
18729 #define R_SERIAL3_BAUD__SET REG_SET_WO
18730 #define R_SERIAL3_BAUD__ISET REG_ISET_WO
18731 #define R_SERIAL3_BAUD__SET_VAL REG_SET_VAL_WO
18732 #define R_SERIAL3_BAUD__EQL REG_EQL_WO
18733 #define R_SERIAL3_BAUD__IEQL REG_IEQL_WO
18734 #define R_SERIAL3_BAUD__RD REG_RD_WO
18735 #define R_SERIAL3_BAUD__IRD REG_IRD_WO
18736 #define R_SERIAL3_BAUD__WR REG_WR_WO
18737 #define R_SERIAL3_BAUD__IWR REG_IWR_WO
18738
18739 #define R_SERIAL3_BAUD__WRITE(addr,value) \
18740 (*(addr) = (value))
18741
18742 #define R_SERIAL3_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
18743 #define R_SERIAL3_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
18744
18745 #define R_SERIAL3_BAUD__tr_baud__MAX 0xf
18746 #define R_SERIAL3_BAUD__rec_baud__MAX 0xf
18747
18748 #define R_SERIAL3_BAUD__tr_baud__MIN 0
18749 #define R_SERIAL3_BAUD__rec_baud__MIN 0
18750
18751 #define R_SERIAL3_BAUD__tr_baud__BITNR 4
18752 #define R_SERIAL3_BAUD__rec_baud__BITNR 0
18753
18754 #define R_SERIAL3_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
18755 #define R_SERIAL3_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
18756
18757 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c115k2Hz 9
18758 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c1200Hz 2
18759 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c1843k2Hz 13
18760 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c19k2Hz 6
18761 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c230k4Hz 10
18762 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c2400Hz 3
18763 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c300Hz 0
18764 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c38k4Hz 7
18765 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c460k8Hz 11
18766 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c4800Hz 4
18767 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c57k6Hz 8
18768 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c600Hz 1
18769 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c6250kHz 14
18770 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c921k6Hz 12
18771 #define R_SERIAL3_BAUD__tr_baud__tr_baud__c9600Hz 5
18772 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c115k2Hz 9
18773 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c1200Hz 2
18774 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c1843k2Hz 13
18775 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c19k2Hz 6
18776 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c230k4Hz 10
18777 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c2400Hz 3
18778 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c300Hz 0
18779 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c38k4Hz 7
18780 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c460k8Hz 11
18781 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c4800Hz 4
18782 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c57k6Hz 8
18783 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c600Hz 1
18784 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c6250kHz 14
18785 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c921k6Hz 12
18786 #define R_SERIAL3_BAUD__rec_baud__rec_baud__c9600Hz 5
18787
18788 #endif
18789
18790 /*
18791 * R_SERIAL3_CTRL
18792 * - type: WO
18793 * - addr: 0xb0000078
18794 * - group: Serial port registers
18795 */
18796
18797 #if USE_GROUP__Serial_port_registers
18798
18799 #define R_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
18800
18801 #ifndef REG_NO_SHADOW
18802 #define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
18803 #define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
18804 #else /* REG_NO_SHADOW */
18805 #define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
18806 #define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
18807 #endif /* REG_NO_SHADOW */
18808
18809 #define R_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD
18810 #define R_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW
18811 #define R_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW
18812 #define R_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD
18813 #define R_SERIAL3_CTRL__TYPE (REG_UDWORD)
18814 #define R_SERIAL3_CTRL__GET REG_GET_WO
18815 #define R_SERIAL3_CTRL__IGET REG_IGET_WO
18816 #define R_SERIAL3_CTRL__SET REG_SET_WO
18817 #define R_SERIAL3_CTRL__ISET REG_ISET_WO
18818 #define R_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO
18819 #define R_SERIAL3_CTRL__EQL REG_EQL_WO
18820 #define R_SERIAL3_CTRL__IEQL REG_IEQL_WO
18821 #define R_SERIAL3_CTRL__RD REG_RD_WO
18822 #define R_SERIAL3_CTRL__IRD REG_IRD_WO
18823 #define R_SERIAL3_CTRL__WR REG_WR_WO
18824 #define R_SERIAL3_CTRL__IWR REG_IWR_WO
18825
18826 #define R_SERIAL3_CTRL__WRITE(addr,value) \
18827 (*(addr) = (value))
18828
18829 #define R_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
18830 #define R_SERIAL3_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
18831 #define R_SERIAL3_CTRL__dma_err__dma_err__MASK 0x00800000U
18832 #define R_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U
18833 #define R_SERIAL3_CTRL__rts___rts___MASK 0x00200000U
18834 #define R_SERIAL3_CTRL__sampling__sampling__MASK 0x00100000U
18835 #define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
18836 #define R_SERIAL3_CTRL__rec_par__rec_par__MASK 0x00040000U
18837 #define R_SERIAL3_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
18838 #define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
18839 #define R_SERIAL3_CTRL__txd__txd__MASK 0x00008000U
18840 #define R_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U
18841 #define R_SERIAL3_CTRL__auto_cts__auto_cts__MASK 0x00002000U
18842 #define R_SERIAL3_CTRL__stop_bits__stop_bits__MASK 0x00001000U
18843 #define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
18844 #define R_SERIAL3_CTRL__tr_par__tr_par__MASK 0x00000400U
18845 #define R_SERIAL3_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
18846 #define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
18847 #define R_SERIAL3_CTRL__data_out__data_out__MASK 0x000000ffU
18848
18849 #define R_SERIAL3_CTRL__tr_baud__MAX 0xf
18850 #define R_SERIAL3_CTRL__rec_baud__MAX 0xf
18851 #define R_SERIAL3_CTRL__dma_err__MAX 0x1
18852 #define R_SERIAL3_CTRL__rec_enable__MAX 0x1
18853 #define R_SERIAL3_CTRL__rts___MAX 0x1
18854 #define R_SERIAL3_CTRL__sampling__MAX 0x1
18855 #define R_SERIAL3_CTRL__rec_stick_par__MAX 0x1
18856 #define R_SERIAL3_CTRL__rec_par__MAX 0x1
18857 #define R_SERIAL3_CTRL__rec_par_en__MAX 0x1
18858 #define R_SERIAL3_CTRL__rec_bitnr__MAX 0x1
18859 #define R_SERIAL3_CTRL__txd__MAX 0x1
18860 #define R_SERIAL3_CTRL__tr_enable__MAX 0x1
18861 #define R_SERIAL3_CTRL__auto_cts__MAX 0x1
18862 #define R_SERIAL3_CTRL__stop_bits__MAX 0x1
18863 #define R_SERIAL3_CTRL__tr_stick_par__MAX 0x1
18864 #define R_SERIAL3_CTRL__tr_par__MAX 0x1
18865 #define R_SERIAL3_CTRL__tr_par_en__MAX 0x1
18866 #define R_SERIAL3_CTRL__tr_bitnr__MAX 0x1
18867 #define R_SERIAL3_CTRL__data_out__MAX 0xff
18868
18869 #define R_SERIAL3_CTRL__tr_baud__MIN 0
18870 #define R_SERIAL3_CTRL__rec_baud__MIN 0
18871 #define R_SERIAL3_CTRL__dma_err__MIN 0
18872 #define R_SERIAL3_CTRL__rec_enable__MIN 0
18873 #define R_SERIAL3_CTRL__rts___MIN 0
18874 #define R_SERIAL3_CTRL__sampling__MIN 0
18875 #define R_SERIAL3_CTRL__rec_stick_par__MIN 0
18876 #define R_SERIAL3_CTRL__rec_par__MIN 0
18877 #define R_SERIAL3_CTRL__rec_par_en__MIN 0
18878 #define R_SERIAL3_CTRL__rec_bitnr__MIN 0
18879 #define R_SERIAL3_CTRL__txd__MIN 0
18880 #define R_SERIAL3_CTRL__tr_enable__MIN 0
18881 #define R_SERIAL3_CTRL__auto_cts__MIN 0
18882 #define R_SERIAL3_CTRL__stop_bits__MIN 0
18883 #define R_SERIAL3_CTRL__tr_stick_par__MIN 0
18884 #define R_SERIAL3_CTRL__tr_par__MIN 0
18885 #define R_SERIAL3_CTRL__tr_par_en__MIN 0
18886 #define R_SERIAL3_CTRL__tr_bitnr__MIN 0
18887 #define R_SERIAL3_CTRL__data_out__MIN 0
18888
18889 #define R_SERIAL3_CTRL__tr_baud__BITNR 28
18890 #define R_SERIAL3_CTRL__rec_baud__BITNR 24
18891 #define R_SERIAL3_CTRL__dma_err__BITNR 23
18892 #define R_SERIAL3_CTRL__rec_enable__BITNR 22
18893 #define R_SERIAL3_CTRL__rts___BITNR 21
18894 #define R_SERIAL3_CTRL__sampling__BITNR 20
18895 #define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
18896 #define R_SERIAL3_CTRL__rec_par__BITNR 18
18897 #define R_SERIAL3_CTRL__rec_par_en__BITNR 17
18898 #define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
18899 #define R_SERIAL3_CTRL__txd__BITNR 15
18900 #define R_SERIAL3_CTRL__tr_enable__BITNR 14
18901 #define R_SERIAL3_CTRL__auto_cts__BITNR 13
18902 #define R_SERIAL3_CTRL__stop_bits__BITNR 12
18903 #define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
18904 #define R_SERIAL3_CTRL__tr_par__BITNR 10
18905 #define R_SERIAL3_CTRL__tr_par_en__BITNR 9
18906 #define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
18907 #define R_SERIAL3_CTRL__data_out__BITNR 0
18908
18909 #define R_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
18910 #define R_SERIAL3_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
18911 #define R_SERIAL3_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
18912 #define R_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
18913 #define R_SERIAL3_CTRL__rts___rts___VAL REG_VAL_ENUM
18914 #define R_SERIAL3_CTRL__sampling__sampling__VAL REG_VAL_ENUM
18915 #define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
18916 #define R_SERIAL3_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
18917 #define R_SERIAL3_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
18918 #define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
18919 #define R_SERIAL3_CTRL__txd__txd__VAL REG_VAL_VAL
18920 #define R_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
18921 #define R_SERIAL3_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
18922 #define R_SERIAL3_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
18923 #define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
18924 #define R_SERIAL3_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
18925 #define R_SERIAL3_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
18926 #define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
18927 #define R_SERIAL3_CTRL__data_out__data_out__VAL REG_VAL_VAL
18928
18929 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 9
18930 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 2
18931 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c1843k2Hz 13
18932 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 6
18933 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 10
18934 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 3
18935 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 0
18936 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c38k4Hz 7
18937 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 11
18938 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 4
18939 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 8
18940 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 1
18941 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c6250kHz 14
18942 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 12
18943 #define R_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 5
18944 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c115k2Hz 9
18945 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c1200Hz 2
18946 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c1843k2Hz 13
18947 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c19k2Hz 6
18948 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c230k4Hz 10
18949 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c2400Hz 3
18950 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c300Hz 0
18951 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c38k4Hz 7
18952 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c460k8Hz 11
18953 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c4800Hz 4
18954 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c57k6Hz 8
18955 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c600Hz 1
18956 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c6250kHz 14
18957 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c921k6Hz 12
18958 #define R_SERIAL3_CTRL__rec_baud__rec_baud__c9600Hz 5
18959 #define R_SERIAL3_CTRL__dma_err__dma_err__ignore 1
18960 #define R_SERIAL3_CTRL__dma_err__dma_err__stop 0
18961 #define R_SERIAL3_CTRL__rec_enable__rec_enable__disable 0
18962 #define R_SERIAL3_CTRL__rec_enable__rec_enable__enable 1
18963 #define R_SERIAL3_CTRL__rts___rts___active 0
18964 #define R_SERIAL3_CTRL__rts___rts___inactive 1
18965 #define R_SERIAL3_CTRL__sampling__sampling__majority 1
18966 #define R_SERIAL3_CTRL__sampling__sampling__middle 0
18967 #define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__normal 0
18968 #define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__stick 1
18969 #define R_SERIAL3_CTRL__rec_par__rec_par__even 0
18970 #define R_SERIAL3_CTRL__rec_par__rec_par__odd 1
18971 #define R_SERIAL3_CTRL__rec_par_en__rec_par_en__disable 0
18972 #define R_SERIAL3_CTRL__rec_par_en__rec_par_en__enable 1
18973 #define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
18974 #define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
18975 #define R_SERIAL3_CTRL__tr_enable__tr_enable__disable 0
18976 #define R_SERIAL3_CTRL__tr_enable__tr_enable__enable 1
18977 #define R_SERIAL3_CTRL__auto_cts__auto_cts__active 1
18978 #define R_SERIAL3_CTRL__auto_cts__auto_cts__disabled 0
18979 #define R_SERIAL3_CTRL__stop_bits__stop_bits__one_bit 0
18980 #define R_SERIAL3_CTRL__stop_bits__stop_bits__two_bits 1
18981 #define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__normal 0
18982 #define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__stick 1
18983 #define R_SERIAL3_CTRL__tr_par__tr_par__even 0
18984 #define R_SERIAL3_CTRL__tr_par__tr_par__odd 1
18985 #define R_SERIAL3_CTRL__tr_par_en__tr_par_en__disable 0
18986 #define R_SERIAL3_CTRL__tr_par_en__tr_par_en__enable 1
18987 #define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
18988 #define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
18989
18990 #endif
18991
18992 /*
18993 * R_SERIAL3_READ
18994 * - type: RO
18995 * - addr: 0xb0000078
18996 * - group: Serial port registers
18997 */
18998
18999 #if USE_GROUP__Serial_port_registers
19000
19001 #define R_SERIAL3_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
19002 #define R_SERIAL3_READ__SVAL REG_SVAL_SHADOW
19003 #define R_SERIAL3_READ__SVAL_I REG_SVAL_I_SHADOW
19004 #define R_SERIAL3_READ__TYPECAST REG_TYPECAST_UDWORD
19005 #define R_SERIAL3_READ__TYPE (REG_UDWORD)
19006 #define R_SERIAL3_READ__GET REG_GET_RO
19007 #define R_SERIAL3_READ__IGET REG_IGET_RO
19008 #define R_SERIAL3_READ__SET REG_SET_RO
19009 #define R_SERIAL3_READ__ISET REG_ISET_RO
19010 #define R_SERIAL3_READ__SET_VAL REG_SET_VAL_RO
19011 #define R_SERIAL3_READ__EQL REG_EQL_RO
19012 #define R_SERIAL3_READ__IEQL REG_IEQL_RO
19013 #define R_SERIAL3_READ__RD REG_RD_RO
19014 #define R_SERIAL3_READ__IRD REG_IRD_RO
19015 #define R_SERIAL3_READ__WR REG_WR_RO
19016 #define R_SERIAL3_READ__IWR REG_IWR_RO
19017
19018 #define R_SERIAL3_READ__READ(addr) \
19019 (*(addr))
19020
19021 #define R_SERIAL3_READ__xoff_detect__xoff_detect__MASK 0x00008000U
19022 #define R_SERIAL3_READ__cts___cts___MASK 0x00004000U
19023 #define R_SERIAL3_READ__tr_ready__tr_ready__MASK 0x00002000U
19024 #define R_SERIAL3_READ__rxd__rxd__MASK 0x00001000U
19025 #define R_SERIAL3_READ__overrun__overrun__MASK 0x00000800U
19026 #define R_SERIAL3_READ__par_err__par_err__MASK 0x00000400U
19027 #define R_SERIAL3_READ__framing_err__framing_err__MASK 0x00000200U
19028 #define R_SERIAL3_READ__data_avail__data_avail__MASK 0x00000100U
19029 #define R_SERIAL3_READ__data_in__data_in__MASK 0x000000ffU
19030
19031 #define R_SERIAL3_READ__xoff_detect__MAX 0x1
19032 #define R_SERIAL3_READ__cts___MAX 0x1
19033 #define R_SERIAL3_READ__tr_ready__MAX 0x1
19034 #define R_SERIAL3_READ__rxd__MAX 0x1
19035 #define R_SERIAL3_READ__overrun__MAX 0x1
19036 #define R_SERIAL3_READ__par_err__MAX 0x1
19037 #define R_SERIAL3_READ__framing_err__MAX 0x1
19038 #define R_SERIAL3_READ__data_avail__MAX 0x1
19039 #define R_SERIAL3_READ__data_in__MAX 0xff
19040
19041 #define R_SERIAL3_READ__xoff_detect__MIN 0
19042 #define R_SERIAL3_READ__cts___MIN 0
19043 #define R_SERIAL3_READ__tr_ready__MIN 0
19044 #define R_SERIAL3_READ__rxd__MIN 0
19045 #define R_SERIAL3_READ__overrun__MIN 0
19046 #define R_SERIAL3_READ__par_err__MIN 0
19047 #define R_SERIAL3_READ__framing_err__MIN 0
19048 #define R_SERIAL3_READ__data_avail__MIN 0
19049 #define R_SERIAL3_READ__data_in__MIN 0
19050
19051 #define R_SERIAL3_READ__xoff_detect__BITNR 15
19052 #define R_SERIAL3_READ__cts___BITNR 14
19053 #define R_SERIAL3_READ__tr_ready__BITNR 13
19054 #define R_SERIAL3_READ__rxd__BITNR 12
19055 #define R_SERIAL3_READ__overrun__BITNR 11
19056 #define R_SERIAL3_READ__par_err__BITNR 10
19057 #define R_SERIAL3_READ__framing_err__BITNR 9
19058 #define R_SERIAL3_READ__data_avail__BITNR 8
19059 #define R_SERIAL3_READ__data_in__BITNR 0
19060
19061 #define R_SERIAL3_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
19062 #define R_SERIAL3_READ__cts___cts___VAL REG_VAL_ENUM
19063 #define R_SERIAL3_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
19064 #define R_SERIAL3_READ__rxd__rxd__VAL REG_VAL_VAL
19065 #define R_SERIAL3_READ__overrun__overrun__VAL REG_VAL_ENUM
19066 #define R_SERIAL3_READ__par_err__par_err__VAL REG_VAL_ENUM
19067 #define R_SERIAL3_READ__framing_err__framing_err__VAL REG_VAL_ENUM
19068 #define R_SERIAL3_READ__data_avail__data_avail__VAL REG_VAL_ENUM
19069 #define R_SERIAL3_READ__data_in__data_in__VAL REG_VAL_VAL
19070
19071 #define R_SERIAL3_READ__xoff_detect__xoff_detect__no_xoff 0
19072 #define R_SERIAL3_READ__xoff_detect__xoff_detect__xoff 1
19073 #define R_SERIAL3_READ__cts___cts___active 0
19074 #define R_SERIAL3_READ__cts___cts___inactive 1
19075 #define R_SERIAL3_READ__tr_ready__tr_ready__full 0
19076 #define R_SERIAL3_READ__tr_ready__tr_ready__ready 1
19077 #define R_SERIAL3_READ__overrun__overrun__no 0
19078 #define R_SERIAL3_READ__overrun__overrun__yes 1
19079 #define R_SERIAL3_READ__par_err__par_err__no 0
19080 #define R_SERIAL3_READ__par_err__par_err__yes 1
19081 #define R_SERIAL3_READ__framing_err__framing_err__no 0
19082 #define R_SERIAL3_READ__framing_err__framing_err__yes 1
19083 #define R_SERIAL3_READ__data_avail__data_avail__no 0
19084 #define R_SERIAL3_READ__data_avail__data_avail__yes 1
19085
19086 #endif
19087
19088 /*
19089 * R_SERIAL3_REC_CTRL
19090 * - type: WO
19091 * - addr: 0xb000007a
19092 * - group: Serial port registers
19093 */
19094
19095 #if USE_GROUP__Serial_port_registers
19096
19097 #define R_SERIAL3_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000007a)
19098
19099 #ifndef REG_NO_SHADOW
19100 #define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 2))
19101 #define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 2))
19102 #else /* REG_NO_SHADOW */
19103 #define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
19104 #define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
19105 #endif /* REG_NO_SHADOW */
19106
19107 #define R_SERIAL3_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
19108 #define R_SERIAL3_REC_CTRL__SVAL REG_SVAL_SHADOW
19109 #define R_SERIAL3_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
19110 #define R_SERIAL3_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
19111 #define R_SERIAL3_REC_CTRL__TYPE (REG_BYTE)
19112 #define R_SERIAL3_REC_CTRL__GET REG_GET_WO
19113 #define R_SERIAL3_REC_CTRL__IGET REG_IGET_WO
19114 #define R_SERIAL3_REC_CTRL__SET REG_SET_WO
19115 #define R_SERIAL3_REC_CTRL__ISET REG_ISET_WO
19116 #define R_SERIAL3_REC_CTRL__SET_VAL REG_SET_VAL_WO
19117 #define R_SERIAL3_REC_CTRL__EQL REG_EQL_WO
19118 #define R_SERIAL3_REC_CTRL__IEQL REG_IEQL_WO
19119 #define R_SERIAL3_REC_CTRL__RD REG_RD_WO
19120 #define R_SERIAL3_REC_CTRL__IRD REG_IRD_WO
19121 #define R_SERIAL3_REC_CTRL__WR REG_WR_WO
19122 #define R_SERIAL3_REC_CTRL__IWR REG_IWR_WO
19123
19124 #define R_SERIAL3_REC_CTRL__WRITE(addr,value) \
19125 (*(addr) = (value))
19126
19127 #define R_SERIAL3_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
19128 #define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
19129 #define R_SERIAL3_REC_CTRL__rts___rts___MASK 0x00000020U
19130 #define R_SERIAL3_REC_CTRL__sampling__sampling__MASK 0x00000010U
19131 #define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
19132 #define R_SERIAL3_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
19133 #define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
19134 #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
19135
19136 #define R_SERIAL3_REC_CTRL__dma_err__MAX 0x1
19137 #define R_SERIAL3_REC_CTRL__rec_enable__MAX 0x1
19138 #define R_SERIAL3_REC_CTRL__rts___MAX 0x1
19139 #define R_SERIAL3_REC_CTRL__sampling__MAX 0x1
19140 #define R_SERIAL3_REC_CTRL__rec_stick_par__MAX 0x1
19141 #define R_SERIAL3_REC_CTRL__rec_par__MAX 0x1
19142 #define R_SERIAL3_REC_CTRL__rec_par_en__MAX 0x1
19143 #define R_SERIAL3_REC_CTRL__rec_bitnr__MAX 0x1
19144
19145 #define R_SERIAL3_REC_CTRL__dma_err__MIN 0
19146 #define R_SERIAL3_REC_CTRL__rec_enable__MIN 0
19147 #define R_SERIAL3_REC_CTRL__rts___MIN 0
19148 #define R_SERIAL3_REC_CTRL__sampling__MIN 0
19149 #define R_SERIAL3_REC_CTRL__rec_stick_par__MIN 0
19150 #define R_SERIAL3_REC_CTRL__rec_par__MIN 0
19151 #define R_SERIAL3_REC_CTRL__rec_par_en__MIN 0
19152 #define R_SERIAL3_REC_CTRL__rec_bitnr__MIN 0
19153
19154 #define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
19155 #define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
19156 #define R_SERIAL3_REC_CTRL__rts___BITNR 5
19157 #define R_SERIAL3_REC_CTRL__sampling__BITNR 4
19158 #define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
19159 #define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
19160 #define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
19161 #define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
19162
19163 #define R_SERIAL3_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
19164 #define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
19165 #define R_SERIAL3_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
19166 #define R_SERIAL3_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
19167 #define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
19168 #define R_SERIAL3_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
19169 #define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
19170 #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
19171
19172 #define R_SERIAL3_REC_CTRL__dma_err__dma_err__ignore 1
19173 #define R_SERIAL3_REC_CTRL__dma_err__dma_err__stop 0
19174 #define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__disable 0
19175 #define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__enable 1
19176 #define R_SERIAL3_REC_CTRL__rts___rts___active 0
19177 #define R_SERIAL3_REC_CTRL__rts___rts___inactive 1
19178 #define R_SERIAL3_REC_CTRL__sampling__sampling__majority 1
19179 #define R_SERIAL3_REC_CTRL__sampling__sampling__middle 0
19180 #define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
19181 #define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
19182 #define R_SERIAL3_REC_CTRL__rec_par__rec_par__even 0
19183 #define R_SERIAL3_REC_CTRL__rec_par__rec_par__odd 1
19184 #define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__disable 0
19185 #define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__enable 1
19186 #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
19187 #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
19188
19189 #endif
19190
19191 /*
19192 * R_SERIAL3_REC_DATA
19193 * - type: RO
19194 * - addr: 0xb0000078
19195 * - group: Serial port registers
19196 */
19197
19198 #if USE_GROUP__Serial_port_registers
19199
19200 #define R_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078)
19201 #define R_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW
19202 #define R_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
19203 #define R_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_BYTE
19204 #define R_SERIAL3_REC_DATA__TYPE (REG_BYTE)
19205 #define R_SERIAL3_REC_DATA__GET REG_GET_RO
19206 #define R_SERIAL3_REC_DATA__IGET REG_IGET_RO
19207 #define R_SERIAL3_REC_DATA__SET REG_SET_RO
19208 #define R_SERIAL3_REC_DATA__ISET REG_ISET_RO
19209 #define R_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO
19210 #define R_SERIAL3_REC_DATA__EQL REG_EQL_RO
19211 #define R_SERIAL3_REC_DATA__IEQL REG_IEQL_RO
19212 #define R_SERIAL3_REC_DATA__RD REG_RD_RO
19213 #define R_SERIAL3_REC_DATA__IRD REG_IRD_RO
19214 #define R_SERIAL3_REC_DATA__WR REG_WR_RO
19215 #define R_SERIAL3_REC_DATA__IWR REG_IWR_RO
19216
19217 #define R_SERIAL3_REC_DATA__READ(addr) \
19218 (*(addr))
19219
19220 #define R_SERIAL3_REC_DATA__data_in__data_in__MASK 0x000000ffU
19221
19222 #define R_SERIAL3_REC_DATA__data_in__MAX 0xff
19223
19224 #define R_SERIAL3_REC_DATA__data_in__MIN 0
19225
19226 #define R_SERIAL3_REC_DATA__data_in__BITNR 0
19227
19228 #define R_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
19229
19230
19231 #endif
19232
19233 /*
19234 * R_SERIAL3_STATUS
19235 * - type: RO
19236 * - addr: 0xb0000079
19237 * - group: Serial port registers
19238 */
19239
19240 #if USE_GROUP__Serial_port_registers
19241
19242 #define R_SERIAL3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000079)
19243 #define R_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW
19244 #define R_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW
19245 #define R_SERIAL3_STATUS__TYPECAST REG_TYPECAST_BYTE
19246 #define R_SERIAL3_STATUS__TYPE (REG_BYTE)
19247 #define R_SERIAL3_STATUS__GET REG_GET_RO
19248 #define R_SERIAL3_STATUS__IGET REG_IGET_RO
19249 #define R_SERIAL3_STATUS__SET REG_SET_RO
19250 #define R_SERIAL3_STATUS__ISET REG_ISET_RO
19251 #define R_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO
19252 #define R_SERIAL3_STATUS__EQL REG_EQL_RO
19253 #define R_SERIAL3_STATUS__IEQL REG_IEQL_RO
19254 #define R_SERIAL3_STATUS__RD REG_RD_RO
19255 #define R_SERIAL3_STATUS__IRD REG_IRD_RO
19256 #define R_SERIAL3_STATUS__WR REG_WR_RO
19257 #define R_SERIAL3_STATUS__IWR REG_IWR_RO
19258
19259 #define R_SERIAL3_STATUS__READ(addr) \
19260 (*(addr))
19261
19262 #define R_SERIAL3_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
19263 #define R_SERIAL3_STATUS__cts___cts___MASK 0x00000040U
19264 #define R_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00000020U
19265 #define R_SERIAL3_STATUS__rxd__rxd__MASK 0x00000010U
19266 #define R_SERIAL3_STATUS__overrun__overrun__MASK 0x00000008U
19267 #define R_SERIAL3_STATUS__par_err__par_err__MASK 0x00000004U
19268 #define R_SERIAL3_STATUS__framing_err__framing_err__MASK 0x00000002U
19269 #define R_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000001U
19270
19271 #define R_SERIAL3_STATUS__xoff_detect__MAX 0x1
19272 #define R_SERIAL3_STATUS__cts___MAX 0x1
19273 #define R_SERIAL3_STATUS__tr_ready__MAX 0x1
19274 #define R_SERIAL3_STATUS__rxd__MAX 0x1
19275 #define R_SERIAL3_STATUS__overrun__MAX 0x1
19276 #define R_SERIAL3_STATUS__par_err__MAX 0x1
19277 #define R_SERIAL3_STATUS__framing_err__MAX 0x1
19278 #define R_SERIAL3_STATUS__data_avail__MAX 0x1
19279
19280 #define R_SERIAL3_STATUS__xoff_detect__MIN 0
19281 #define R_SERIAL3_STATUS__cts___MIN 0
19282 #define R_SERIAL3_STATUS__tr_ready__MIN 0
19283 #define R_SERIAL3_STATUS__rxd__MIN 0
19284 #define R_SERIAL3_STATUS__overrun__MIN 0
19285 #define R_SERIAL3_STATUS__par_err__MIN 0
19286 #define R_SERIAL3_STATUS__framing_err__MIN 0
19287 #define R_SERIAL3_STATUS__data_avail__MIN 0
19288
19289 #define R_SERIAL3_STATUS__xoff_detect__BITNR 7
19290 #define R_SERIAL3_STATUS__cts___BITNR 6
19291 #define R_SERIAL3_STATUS__tr_ready__BITNR 5
19292 #define R_SERIAL3_STATUS__rxd__BITNR 4
19293 #define R_SERIAL3_STATUS__overrun__BITNR 3
19294 #define R_SERIAL3_STATUS__par_err__BITNR 2
19295 #define R_SERIAL3_STATUS__framing_err__BITNR 1
19296 #define R_SERIAL3_STATUS__data_avail__BITNR 0
19297
19298 #define R_SERIAL3_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
19299 #define R_SERIAL3_STATUS__cts___cts___VAL REG_VAL_ENUM
19300 #define R_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
19301 #define R_SERIAL3_STATUS__rxd__rxd__VAL REG_VAL_VAL
19302 #define R_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM
19303 #define R_SERIAL3_STATUS__par_err__par_err__VAL REG_VAL_ENUM
19304 #define R_SERIAL3_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
19305 #define R_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
19306
19307 #define R_SERIAL3_STATUS__xoff_detect__xoff_detect__no_xoff 0
19308 #define R_SERIAL3_STATUS__xoff_detect__xoff_detect__xoff 1
19309 #define R_SERIAL3_STATUS__cts___cts___active 0
19310 #define R_SERIAL3_STATUS__cts___cts___inactive 1
19311 #define R_SERIAL3_STATUS__tr_ready__tr_ready__full 0
19312 #define R_SERIAL3_STATUS__tr_ready__tr_ready__ready 1
19313 #define R_SERIAL3_STATUS__overrun__overrun__no 0
19314 #define R_SERIAL3_STATUS__overrun__overrun__yes 1
19315 #define R_SERIAL3_STATUS__par_err__par_err__no 0
19316 #define R_SERIAL3_STATUS__par_err__par_err__yes 1
19317 #define R_SERIAL3_STATUS__framing_err__framing_err__no 0
19318 #define R_SERIAL3_STATUS__framing_err__framing_err__yes 1
19319 #define R_SERIAL3_STATUS__data_avail__data_avail__no 0
19320 #define R_SERIAL3_STATUS__data_avail__data_avail__yes 1
19321
19322 #endif
19323
19324 /*
19325 * R_SERIAL3_TR_CTRL
19326 * - type: WO
19327 * - addr: 0xb0000079
19328 * - group: Serial port registers
19329 */
19330
19331 #if USE_GROUP__Serial_port_registers
19332
19333 #define R_SERIAL3_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000079)
19334
19335 #ifndef REG_NO_SHADOW
19336 #define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 1))
19337 #define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 1))
19338 #else /* REG_NO_SHADOW */
19339 #define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
19340 #define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
19341 #endif /* REG_NO_SHADOW */
19342
19343 #define R_SERIAL3_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
19344 #define R_SERIAL3_TR_CTRL__SVAL REG_SVAL_SHADOW
19345 #define R_SERIAL3_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
19346 #define R_SERIAL3_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
19347 #define R_SERIAL3_TR_CTRL__TYPE (REG_BYTE)
19348 #define R_SERIAL3_TR_CTRL__GET REG_GET_WO
19349 #define R_SERIAL3_TR_CTRL__IGET REG_IGET_WO
19350 #define R_SERIAL3_TR_CTRL__SET REG_SET_WO
19351 #define R_SERIAL3_TR_CTRL__ISET REG_ISET_WO
19352 #define R_SERIAL3_TR_CTRL__SET_VAL REG_SET_VAL_WO
19353 #define R_SERIAL3_TR_CTRL__EQL REG_EQL_WO
19354 #define R_SERIAL3_TR_CTRL__IEQL REG_IEQL_WO
19355 #define R_SERIAL3_TR_CTRL__RD REG_RD_WO
19356 #define R_SERIAL3_TR_CTRL__IRD REG_IRD_WO
19357 #define R_SERIAL3_TR_CTRL__WR REG_WR_WO
19358 #define R_SERIAL3_TR_CTRL__IWR REG_IWR_WO
19359
19360 #define R_SERIAL3_TR_CTRL__WRITE(addr,value) \
19361 (*(addr) = (value))
19362
19363 #define R_SERIAL3_TR_CTRL__txd__txd__MASK 0x00000080U
19364 #define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
19365 #define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
19366 #define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
19367 #define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
19368 #define R_SERIAL3_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
19369 #define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
19370 #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
19371
19372 #define R_SERIAL3_TR_CTRL__txd__MAX 0x1
19373 #define R_SERIAL3_TR_CTRL__tr_enable__MAX 0x1
19374 #define R_SERIAL3_TR_CTRL__auto_cts__MAX 0x1
19375 #define R_SERIAL3_TR_CTRL__stop_bits__MAX 0x1
19376 #define R_SERIAL3_TR_CTRL__tr_stick_par__MAX 0x1
19377 #define R_SERIAL3_TR_CTRL__tr_par__MAX 0x1
19378 #define R_SERIAL3_TR_CTRL__tr_par_en__MAX 0x1
19379 #define R_SERIAL3_TR_CTRL__tr_bitnr__MAX 0x1
19380
19381 #define R_SERIAL3_TR_CTRL__txd__MIN 0
19382 #define R_SERIAL3_TR_CTRL__tr_enable__MIN 0
19383 #define R_SERIAL3_TR_CTRL__auto_cts__MIN 0
19384 #define R_SERIAL3_TR_CTRL__stop_bits__MIN 0
19385 #define R_SERIAL3_TR_CTRL__tr_stick_par__MIN 0
19386 #define R_SERIAL3_TR_CTRL__tr_par__MIN 0
19387 #define R_SERIAL3_TR_CTRL__tr_par_en__MIN 0
19388 #define R_SERIAL3_TR_CTRL__tr_bitnr__MIN 0
19389
19390 #define R_SERIAL3_TR_CTRL__txd__BITNR 7
19391 #define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
19392 #define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
19393 #define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
19394 #define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
19395 #define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
19396 #define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
19397 #define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
19398
19399 #define R_SERIAL3_TR_CTRL__txd__txd__VAL REG_VAL_VAL
19400 #define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
19401 #define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
19402 #define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
19403 #define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
19404 #define R_SERIAL3_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
19405 #define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
19406 #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
19407
19408 #define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__disable 0
19409 #define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__enable 1
19410 #define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__active 1
19411 #define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__disabled 0
19412 #define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__one_bit 0
19413 #define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__two_bits 1
19414 #define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
19415 #define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
19416 #define R_SERIAL3_TR_CTRL__tr_par__tr_par__even 0
19417 #define R_SERIAL3_TR_CTRL__tr_par__tr_par__odd 1
19418 #define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__disable 0
19419 #define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__enable 1
19420 #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
19421 #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
19422
19423 #endif
19424
19425 /*
19426 * R_SERIAL3_TR_DATA
19427 * - type: WO
19428 * - addr: 0xb0000078
19429 * - group: Serial port registers
19430 */
19431
19432 #if USE_GROUP__Serial_port_registers
19433
19434 #define R_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078)
19435
19436 #ifndef REG_NO_SHADOW
19437 #define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
19438 #define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
19439 #else /* REG_NO_SHADOW */
19440 #define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
19441 #define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
19442 #endif /* REG_NO_SHADOW */
19443
19444 #define R_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_BYTE
19445 #define R_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW
19446 #define R_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
19447 #define R_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_BYTE
19448 #define R_SERIAL3_TR_DATA__TYPE (REG_BYTE)
19449 #define R_SERIAL3_TR_DATA__GET REG_GET_WO
19450 #define R_SERIAL3_TR_DATA__IGET REG_IGET_WO
19451 #define R_SERIAL3_TR_DATA__SET REG_SET_WO
19452 #define R_SERIAL3_TR_DATA__ISET REG_ISET_WO
19453 #define R_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO
19454 #define R_SERIAL3_TR_DATA__EQL REG_EQL_WO
19455 #define R_SERIAL3_TR_DATA__IEQL REG_IEQL_WO
19456 #define R_SERIAL3_TR_DATA__RD REG_RD_WO
19457 #define R_SERIAL3_TR_DATA__IRD REG_IRD_WO
19458 #define R_SERIAL3_TR_DATA__WR REG_WR_WO
19459 #define R_SERIAL3_TR_DATA__IWR REG_IWR_WO
19460
19461 #define R_SERIAL3_TR_DATA__WRITE(addr,value) \
19462 (*(addr) = (value))
19463
19464 #define R_SERIAL3_TR_DATA__data_out__data_out__MASK 0x000000ffU
19465
19466 #define R_SERIAL3_TR_DATA__data_out__MAX 0xff
19467
19468 #define R_SERIAL3_TR_DATA__data_out__MIN 0
19469
19470 #define R_SERIAL3_TR_DATA__data_out__BITNR 0
19471
19472 #define R_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
19473
19474
19475 #endif
19476
19477 /*
19478 * R_SERIAL3_XOFF
19479 * - type: WO
19480 * - addr: 0xb000007c
19481 * - group: Serial port registers
19482 */
19483
19484 #if USE_GROUP__Serial_port_registers
19485
19486 #define R_SERIAL3_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
19487
19488 #ifndef REG_NO_SHADOW
19489 #define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
19490 #define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
19491 #else /* REG_NO_SHADOW */
19492 #define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
19493 #define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
19494 #endif /* REG_NO_SHADOW */
19495
19496 #define R_SERIAL3_XOFF__STYPECAST REG_STYPECAST_UDWORD
19497 #define R_SERIAL3_XOFF__SVAL REG_SVAL_SHADOW
19498 #define R_SERIAL3_XOFF__SVAL_I REG_SVAL_I_SHADOW
19499 #define R_SERIAL3_XOFF__TYPECAST REG_TYPECAST_UDWORD
19500 #define R_SERIAL3_XOFF__TYPE (REG_UDWORD)
19501 #define R_SERIAL3_XOFF__GET REG_GET_WO
19502 #define R_SERIAL3_XOFF__IGET REG_IGET_WO
19503 #define R_SERIAL3_XOFF__SET REG_SET_WO
19504 #define R_SERIAL3_XOFF__ISET REG_ISET_WO
19505 #define R_SERIAL3_XOFF__SET_VAL REG_SET_VAL_WO
19506 #define R_SERIAL3_XOFF__EQL REG_EQL_WO
19507 #define R_SERIAL3_XOFF__IEQL REG_IEQL_WO
19508 #define R_SERIAL3_XOFF__RD REG_RD_WO
19509 #define R_SERIAL3_XOFF__IRD REG_IRD_WO
19510 #define R_SERIAL3_XOFF__WR REG_WR_WO
19511 #define R_SERIAL3_XOFF__IWR REG_IWR_WO
19512
19513 #define R_SERIAL3_XOFF__WRITE(addr,value) \
19514 (*(addr) = (value))
19515
19516 #define R_SERIAL3_XOFF__tx_stop__tx_stop__MASK 0x00000200U
19517 #define R_SERIAL3_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
19518 #define R_SERIAL3_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
19519
19520 #define R_SERIAL3_XOFF__tx_stop__MAX 0x1
19521 #define R_SERIAL3_XOFF__auto_xoff__MAX 0x1
19522 #define R_SERIAL3_XOFF__xoff_char__MAX 0xff
19523
19524 #define R_SERIAL3_XOFF__tx_stop__MIN 0
19525 #define R_SERIAL3_XOFF__auto_xoff__MIN 0
19526 #define R_SERIAL3_XOFF__xoff_char__MIN 0
19527
19528 #define R_SERIAL3_XOFF__tx_stop__BITNR 9
19529 #define R_SERIAL3_XOFF__auto_xoff__BITNR 8
19530 #define R_SERIAL3_XOFF__xoff_char__BITNR 0
19531
19532 #define R_SERIAL3_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
19533 #define R_SERIAL3_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
19534 #define R_SERIAL3_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
19535
19536 #define R_SERIAL3_XOFF__tx_stop__tx_stop__enable 0
19537 #define R_SERIAL3_XOFF__tx_stop__tx_stop__stop 1
19538 #define R_SERIAL3_XOFF__auto_xoff__auto_xoff__disable 0
19539 #define R_SERIAL3_XOFF__auto_xoff__auto_xoff__enable 1
19540
19541 #endif
19542
19543 /*
19544 * R_SERIAL_PRESCALE
19545 * - type: WO
19546 * - addr: 0xb00000f2
19547 * - group: Timer registers
19548 */
19549
19550 #if USE_GROUP__Timer_registers
19551
19552 #define R_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f2)
19553
19554 #ifndef REG_NO_SHADOW
19555 #define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 2))
19556 #define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 2))
19557 #else /* REG_NO_SHADOW */
19558 #define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
19559 #define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
19560 #endif /* REG_NO_SHADOW */
19561
19562 #define R_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UWORD
19563 #define R_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW
19564 #define R_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
19565 #define R_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UWORD
19566 #define R_SERIAL_PRESCALE__TYPE (REG_UWORD)
19567 #define R_SERIAL_PRESCALE__GET REG_GET_WO
19568 #define R_SERIAL_PRESCALE__IGET REG_IGET_WO
19569 #define R_SERIAL_PRESCALE__SET REG_SET_WO
19570 #define R_SERIAL_PRESCALE__ISET REG_ISET_WO
19571 #define R_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO
19572 #define R_SERIAL_PRESCALE__EQL REG_EQL_WO
19573 #define R_SERIAL_PRESCALE__IEQL REG_IEQL_WO
19574 #define R_SERIAL_PRESCALE__RD REG_RD_WO
19575 #define R_SERIAL_PRESCALE__IRD REG_IRD_WO
19576 #define R_SERIAL_PRESCALE__WR REG_WR_WO
19577 #define R_SERIAL_PRESCALE__IWR REG_IWR_WO
19578
19579 #define R_SERIAL_PRESCALE__WRITE(addr,value) \
19580 (*(addr) = (value))
19581
19582 #define R_SERIAL_PRESCALE__ser_presc__ser_presc__MASK 0x0000ffffU
19583
19584 #define R_SERIAL_PRESCALE__ser_presc__MAX 0xffff
19585
19586 #define R_SERIAL_PRESCALE__ser_presc__MIN 0
19587
19588 #define R_SERIAL_PRESCALE__ser_presc__BITNR 0
19589
19590 #define R_SERIAL_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL
19591
19592
19593 #endif
19594
19595 /*
19596 * R_SER_PRESC_STATUS
19597 * - type: RO
19598 * - addr: 0xb00000f2
19599 * - group: Timer registers
19600 */
19601
19602 #if USE_GROUP__Timer_registers
19603
19604 #define R_SER_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f2)
19605 #define R_SER_PRESC_STATUS__SVAL REG_SVAL_SHADOW
19606 #define R_SER_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW
19607 #define R_SER_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD
19608 #define R_SER_PRESC_STATUS__TYPE (REG_UWORD)
19609 #define R_SER_PRESC_STATUS__GET REG_GET_RO
19610 #define R_SER_PRESC_STATUS__IGET REG_IGET_RO
19611 #define R_SER_PRESC_STATUS__SET REG_SET_RO
19612 #define R_SER_PRESC_STATUS__ISET REG_ISET_RO
19613 #define R_SER_PRESC_STATUS__SET_VAL REG_SET_VAL_RO
19614 #define R_SER_PRESC_STATUS__EQL REG_EQL_RO
19615 #define R_SER_PRESC_STATUS__IEQL REG_IEQL_RO
19616 #define R_SER_PRESC_STATUS__RD REG_RD_RO
19617 #define R_SER_PRESC_STATUS__IRD REG_IRD_RO
19618 #define R_SER_PRESC_STATUS__WR REG_WR_RO
19619 #define R_SER_PRESC_STATUS__IWR REG_IWR_RO
19620
19621 #define R_SER_PRESC_STATUS__READ(addr) \
19622 (*(addr))
19623
19624 #define R_SER_PRESC_STATUS__ser_status__ser_status__MASK 0x0000ffffU
19625
19626 #define R_SER_PRESC_STATUS__ser_status__MAX 0xffff
19627
19628 #define R_SER_PRESC_STATUS__ser_status__MIN 0
19629
19630 #define R_SER_PRESC_STATUS__ser_status__BITNR 0
19631
19632 #define R_SER_PRESC_STATUS__ser_status__ser_status__VAL REG_VAL_VAL
19633
19634
19635 #endif
19636
19637 /*
19638 * R_SET_EOP
19639 * - type: WO
19640 * - addr: 0xb000003c
19641 * - group: DMA registers
19642 */
19643
19644 #if USE_GROUP__DMA_registers
19645
19646 #define R_SET_EOP__ADDR (REG_TYPECAST_UDWORD 0xb000003c)
19647
19648 #ifndef REG_NO_SHADOW
19649 #define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SET_EOP + 0))
19650 #define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SET_EOP + 0))
19651 #else /* REG_NO_SHADOW */
19652 #define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
19653 #define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
19654 #endif /* REG_NO_SHADOW */
19655
19656 #define R_SET_EOP__STYPECAST REG_STYPECAST_UDWORD
19657 #define R_SET_EOP__SVAL REG_SVAL_ZERO
19658 #define R_SET_EOP__SVAL_I REG_SVAL_I_ZERO
19659 #define R_SET_EOP__TYPECAST REG_TYPECAST_UDWORD
19660 #define R_SET_EOP__TYPE (REG_UDWORD)
19661 #define R_SET_EOP__GET REG_GET_WO
19662 #define R_SET_EOP__IGET REG_IGET_WO
19663 #define R_SET_EOP__SET REG_SET_WO
19664 #define R_SET_EOP__ISET REG_ISET_WO
19665 #define R_SET_EOP__SET_VAL REG_SET_VAL_WO
19666 #define R_SET_EOP__EQL REG_EQL_WO
19667 #define R_SET_EOP__IEQL REG_IEQL_WO
19668 #define R_SET_EOP__RD REG_RD_WO
19669 #define R_SET_EOP__IRD REG_IRD_WO
19670 #define R_SET_EOP__WR REG_WR_WO
19671 #define R_SET_EOP__IWR REG_IWR_WO
19672
19673 #define R_SET_EOP__WRITE(addr,value) \
19674 (*(addr) = (value))
19675
19676 #define R_SET_EOP__ch9_eop__ch9_eop__MASK 0x00000008U
19677 #define R_SET_EOP__ch7_eop__ch7_eop__MASK 0x00000004U
19678 #define R_SET_EOP__ch5_eop__ch5_eop__MASK 0x00000002U
19679 #define R_SET_EOP__ch3_eop__ch3_eop__MASK 0x00000001U
19680
19681 #define R_SET_EOP__ch9_eop__MAX 0x1
19682 #define R_SET_EOP__ch7_eop__MAX 0x1
19683 #define R_SET_EOP__ch5_eop__MAX 0x1
19684 #define R_SET_EOP__ch3_eop__MAX 0x1
19685
19686 #define R_SET_EOP__ch9_eop__MIN 0
19687 #define R_SET_EOP__ch7_eop__MIN 0
19688 #define R_SET_EOP__ch5_eop__MIN 0
19689 #define R_SET_EOP__ch3_eop__MIN 0
19690
19691 #define R_SET_EOP__ch9_eop__BITNR 3
19692 #define R_SET_EOP__ch7_eop__BITNR 2
19693 #define R_SET_EOP__ch5_eop__BITNR 1
19694 #define R_SET_EOP__ch3_eop__BITNR 0
19695
19696 #define R_SET_EOP__ch9_eop__ch9_eop__VAL REG_VAL_ENUM
19697 #define R_SET_EOP__ch7_eop__ch7_eop__VAL REG_VAL_ENUM
19698 #define R_SET_EOP__ch5_eop__ch5_eop__VAL REG_VAL_ENUM
19699 #define R_SET_EOP__ch3_eop__ch3_eop__VAL REG_VAL_ENUM
19700
19701 #define R_SET_EOP__ch9_eop__ch9_eop__nop 0
19702 #define R_SET_EOP__ch9_eop__ch9_eop__set 1
19703 #define R_SET_EOP__ch7_eop__ch7_eop__nop 0
19704 #define R_SET_EOP__ch7_eop__ch7_eop__set 1
19705 #define R_SET_EOP__ch5_eop__ch5_eop__nop 0
19706 #define R_SET_EOP__ch5_eop__ch5_eop__set 1
19707 #define R_SET_EOP__ch3_eop__ch3_eop__nop 0
19708 #define R_SET_EOP__ch3_eop__ch3_eop__set 1
19709
19710 #endif
19711
19712 /*
19713 * R_SHARED_RAM_ADDR
19714 * - type: WO
19715 * - addr: 0xb0000044
19716 * - group: Shared RAM interface registers
19717 */
19718
19719 #if USE_GROUP__Shared_RAM_interface_registers
19720
19721 #define R_SHARED_RAM_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
19722
19723 #ifndef REG_NO_SHADOW
19724 #define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
19725 #define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
19726 #else /* REG_NO_SHADOW */
19727 #define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
19728 #define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
19729 #endif /* REG_NO_SHADOW */
19730
19731 #define R_SHARED_RAM_ADDR__STYPECAST REG_STYPECAST_UDWORD
19732 #define R_SHARED_RAM_ADDR__SVAL REG_SVAL_SHADOW
19733 #define R_SHARED_RAM_ADDR__SVAL_I REG_SVAL_I_SHADOW
19734 #define R_SHARED_RAM_ADDR__TYPECAST REG_TYPECAST_UDWORD
19735 #define R_SHARED_RAM_ADDR__TYPE (REG_UDWORD)
19736 #define R_SHARED_RAM_ADDR__GET REG_GET_WO
19737 #define R_SHARED_RAM_ADDR__IGET REG_IGET_WO
19738 #define R_SHARED_RAM_ADDR__SET REG_SET_WO
19739 #define R_SHARED_RAM_ADDR__ISET REG_ISET_WO
19740 #define R_SHARED_RAM_ADDR__SET_VAL REG_SET_VAL_WO
19741 #define R_SHARED_RAM_ADDR__EQL REG_EQL_WO
19742 #define R_SHARED_RAM_ADDR__IEQL REG_IEQL_WO
19743 #define R_SHARED_RAM_ADDR__RD REG_RD_WO
19744 #define R_SHARED_RAM_ADDR__IRD REG_IRD_WO
19745 #define R_SHARED_RAM_ADDR__WR REG_WR_WO
19746 #define R_SHARED_RAM_ADDR__IWR REG_IWR_WO
19747
19748 #define R_SHARED_RAM_ADDR__WRITE(addr,value) \
19749 (*(addr) = (value))
19750
19751 #define R_SHARED_RAM_ADDR__base_addr__base_addr__MASK 0x3fffff00U
19752
19753 #define R_SHARED_RAM_ADDR__base_addr__MAX 0x3fffff
19754
19755 #define R_SHARED_RAM_ADDR__base_addr__MIN 0
19756
19757 #define R_SHARED_RAM_ADDR__base_addr__BITNR 8
19758
19759 #define R_SHARED_RAM_ADDR__base_addr__base_addr__VAL REG_VAL_VAL
19760
19761
19762 #endif
19763
19764 /*
19765 * R_SHARED_RAM_CONFIG
19766 * - type: WO
19767 * - addr: 0xb0000040
19768 * - group: Shared RAM interface registers
19769 */
19770
19771 #if USE_GROUP__Shared_RAM_interface_registers
19772
19773 #define R_SHARED_RAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
19774
19775 #ifndef REG_NO_SHADOW
19776 #define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
19777 #define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
19778 #else /* REG_NO_SHADOW */
19779 #define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
19780 #define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
19781 #endif /* REG_NO_SHADOW */
19782
19783 #define R_SHARED_RAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
19784 #define R_SHARED_RAM_CONFIG__SVAL REG_SVAL_SHADOW
19785 #define R_SHARED_RAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
19786 #define R_SHARED_RAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
19787 #define R_SHARED_RAM_CONFIG__TYPE (REG_UDWORD)
19788 #define R_SHARED_RAM_CONFIG__GET REG_GET_WO
19789 #define R_SHARED_RAM_CONFIG__IGET REG_IGET_WO
19790 #define R_SHARED_RAM_CONFIG__SET REG_SET_WO
19791 #define R_SHARED_RAM_CONFIG__ISET REG_ISET_WO
19792 #define R_SHARED_RAM_CONFIG__SET_VAL REG_SET_VAL_WO
19793 #define R_SHARED_RAM_CONFIG__EQL REG_EQL_WO
19794 #define R_SHARED_RAM_CONFIG__IEQL REG_IEQL_WO
19795 #define R_SHARED_RAM_CONFIG__RD REG_RD_WO
19796 #define R_SHARED_RAM_CONFIG__IRD REG_IRD_WO
19797 #define R_SHARED_RAM_CONFIG__WR REG_WR_WO
19798 #define R_SHARED_RAM_CONFIG__IWR REG_IWR_WO
19799
19800 #define R_SHARED_RAM_CONFIG__WRITE(addr,value) \
19801 (*(addr) = (value))
19802
19803 #define R_SHARED_RAM_CONFIG__width__width__MASK 0x00000008U
19804 #define R_SHARED_RAM_CONFIG__enable__enable__MASK 0x00000004U
19805 #define R_SHARED_RAM_CONFIG__pint__pint__MASK 0x00000002U
19806 #define R_SHARED_RAM_CONFIG__clri__clri__MASK 0x00000001U
19807
19808 #define R_SHARED_RAM_CONFIG__width__MAX 0x1
19809 #define R_SHARED_RAM_CONFIG__enable__MAX 0x1
19810 #define R_SHARED_RAM_CONFIG__pint__MAX 0x1
19811 #define R_SHARED_RAM_CONFIG__clri__MAX 0x1
19812
19813 #define R_SHARED_RAM_CONFIG__width__MIN 0
19814 #define R_SHARED_RAM_CONFIG__enable__MIN 0
19815 #define R_SHARED_RAM_CONFIG__pint__MIN 0
19816 #define R_SHARED_RAM_CONFIG__clri__MIN 0
19817
19818 #define R_SHARED_RAM_CONFIG__width__BITNR 3
19819 #define R_SHARED_RAM_CONFIG__enable__BITNR 2
19820 #define R_SHARED_RAM_CONFIG__pint__BITNR 1
19821 #define R_SHARED_RAM_CONFIG__clri__BITNR 0
19822
19823 #define R_SHARED_RAM_CONFIG__width__width__VAL REG_VAL_ENUM
19824 #define R_SHARED_RAM_CONFIG__enable__enable__VAL REG_VAL_ENUM
19825 #define R_SHARED_RAM_CONFIG__pint__pint__VAL REG_VAL_ENUM
19826 #define R_SHARED_RAM_CONFIG__clri__clri__VAL REG_VAL_ENUM
19827
19828 #define R_SHARED_RAM_CONFIG__width__width__byte 0
19829 #define R_SHARED_RAM_CONFIG__width__width__word 1
19830 #define R_SHARED_RAM_CONFIG__enable__enable__no 0
19831 #define R_SHARED_RAM_CONFIG__enable__enable__yes 1
19832 #define R_SHARED_RAM_CONFIG__pint__pint__int 1
19833 #define R_SHARED_RAM_CONFIG__pint__pint__nop 0
19834 #define R_SHARED_RAM_CONFIG__clri__clri__clr 1
19835 #define R_SHARED_RAM_CONFIG__clri__clri__nop 0
19836
19837 #endif
19838
19839 /*
19840 * R_SINGLE_STEP
19841 * - type: WO
19842 * - addr: 0xb00000fe
19843 * - group: Test mode registers
19844 */
19845
19846 #if USE_GROUP__Test_mode_registers
19847
19848 #define R_SINGLE_STEP__ADDR (REG_TYPECAST_BYTE 0xb00000fe)
19849
19850 #ifndef REG_NO_SHADOW
19851 #define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_TEST_MODE + 2))
19852 #define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_TEST_MODE + 2))
19853 #else /* REG_NO_SHADOW */
19854 #define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
19855 #define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
19856 #endif /* REG_NO_SHADOW */
19857
19858 #define R_SINGLE_STEP__STYPECAST REG_STYPECAST_BYTE
19859 #define R_SINGLE_STEP__SVAL REG_SVAL_SHADOW
19860 #define R_SINGLE_STEP__SVAL_I REG_SVAL_I_SHADOW
19861 #define R_SINGLE_STEP__TYPECAST REG_TYPECAST_BYTE
19862 #define R_SINGLE_STEP__TYPE (REG_BYTE)
19863 #define R_SINGLE_STEP__GET REG_GET_WO
19864 #define R_SINGLE_STEP__IGET REG_IGET_WO
19865 #define R_SINGLE_STEP__SET REG_SET_WO
19866 #define R_SINGLE_STEP__ISET REG_ISET_WO
19867 #define R_SINGLE_STEP__SET_VAL REG_SET_VAL_WO
19868 #define R_SINGLE_STEP__EQL REG_EQL_WO
19869 #define R_SINGLE_STEP__IEQL REG_IEQL_WO
19870 #define R_SINGLE_STEP__RD REG_RD_WO
19871 #define R_SINGLE_STEP__IRD REG_IRD_WO
19872 #define R_SINGLE_STEP__WR REG_WR_WO
19873 #define R_SINGLE_STEP__IWR REG_IWR_WO
19874
19875 #define R_SINGLE_STEP__WRITE(addr,value) \
19876 (*(addr) = (value))
19877
19878 #define R_SINGLE_STEP__single_step__single_step__MASK 0x00000008U
19879 #define R_SINGLE_STEP__step_wr__step_wr__MASK 0x00000004U
19880 #define R_SINGLE_STEP__step_rd__step_rd__MASK 0x00000002U
19881 #define R_SINGLE_STEP__step_fetch__step_fetch__MASK 0x00000001U
19882
19883 #define R_SINGLE_STEP__single_step__MAX 0x1
19884 #define R_SINGLE_STEP__step_wr__MAX 0x1
19885 #define R_SINGLE_STEP__step_rd__MAX 0x1
19886 #define R_SINGLE_STEP__step_fetch__MAX 0x1
19887
19888 #define R_SINGLE_STEP__single_step__MIN 0
19889 #define R_SINGLE_STEP__step_wr__MIN 0
19890 #define R_SINGLE_STEP__step_rd__MIN 0
19891 #define R_SINGLE_STEP__step_fetch__MIN 0
19892
19893 #define R_SINGLE_STEP__single_step__BITNR 3
19894 #define R_SINGLE_STEP__step_wr__BITNR 2
19895 #define R_SINGLE_STEP__step_rd__BITNR 1
19896 #define R_SINGLE_STEP__step_fetch__BITNR 0
19897
19898 #define R_SINGLE_STEP__single_step__single_step__VAL REG_VAL_ENUM
19899 #define R_SINGLE_STEP__step_wr__step_wr__VAL REG_VAL_ENUM
19900 #define R_SINGLE_STEP__step_rd__step_rd__VAL REG_VAL_ENUM
19901 #define R_SINGLE_STEP__step_fetch__step_fetch__VAL REG_VAL_ENUM
19902
19903 #define R_SINGLE_STEP__single_step__single_step__off 0
19904 #define R_SINGLE_STEP__single_step__single_step__on 1
19905 #define R_SINGLE_STEP__step_wr__step_wr__off 0
19906 #define R_SINGLE_STEP__step_wr__step_wr__on 1
19907 #define R_SINGLE_STEP__step_rd__step_rd__off 0
19908 #define R_SINGLE_STEP__step_rd__step_rd__on 1
19909 #define R_SINGLE_STEP__step_fetch__step_fetch__off 0
19910 #define R_SINGLE_STEP__step_fetch__step_fetch__on 1
19911
19912 #endif
19913
19914 /*
19915 * R_SYNC_SERIAL1_CTRL
19916 * - type: WO
19917 * - addr: 0xb0000068
19918 * - group: Syncrounous serial port registers
19919 */
19920
19921 #if USE_GROUP__Syncrounous_serial_port_registers
19922
19923 #define R_SYNC_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
19924
19925 #ifndef REG_NO_SHADOW
19926 #define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
19927 #define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
19928 #else /* REG_NO_SHADOW */
19929 #define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
19930 #define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
19931 #endif /* REG_NO_SHADOW */
19932
19933 #define R_SYNC_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD
19934 #define R_SYNC_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW
19935 #define R_SYNC_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW
19936 #define R_SYNC_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD
19937 #define R_SYNC_SERIAL1_CTRL__TYPE (REG_UDWORD)
19938 #define R_SYNC_SERIAL1_CTRL__GET REG_GET_WO
19939 #define R_SYNC_SERIAL1_CTRL__IGET REG_IGET_WO
19940 #define R_SYNC_SERIAL1_CTRL__SET REG_SET_WO
19941 #define R_SYNC_SERIAL1_CTRL__ISET REG_ISET_WO
19942 #define R_SYNC_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO
19943 #define R_SYNC_SERIAL1_CTRL__EQL REG_EQL_WO
19944 #define R_SYNC_SERIAL1_CTRL__IEQL REG_IEQL_WO
19945 #define R_SYNC_SERIAL1_CTRL__RD REG_RD_WO
19946 #define R_SYNC_SERIAL1_CTRL__IRD REG_IRD_WO
19947 #define R_SYNC_SERIAL1_CTRL__WR REG_WR_WO
19948 #define R_SYNC_SERIAL1_CTRL__IWR REG_IWR_WO
19949
19950 #define R_SYNC_SERIAL1_CTRL__WRITE(addr,value) \
19951 (*(addr) = (value))
19952
19953 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
19954 #define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__MASK 0x08000000U
19955 #define R_SYNC_SERIAL1_CTRL__mode__mode__MASK 0x07000000U
19956 #define R_SYNC_SERIAL1_CTRL__error__error__MASK 0x00800000U
19957 #define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U
19958 #define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__MASK 0x00200000U
19959 #define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U
19960 #define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__MASK 0x00040000U
19961 #define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__MASK 0x00020000U
19962 #define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__MASK 0x00010000U
19963 #define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__MASK 0x00008000U
19964 #define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U
19965 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__MASK 0x00003800U
19966 #define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__MASK 0x00000400U
19967 #define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__MASK 0x00000200U
19968 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U
19969 #define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U
19970 #define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U
19971 #define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__MASK 0x00000010U
19972 #define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__MASK 0x00000008U
19973 #define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__MASK 0x00000004U
19974 #define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__MASK 0x00000002U
19975 #define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__MASK 0x00000001U
19976
19977 #define R_SYNC_SERIAL1_CTRL__tr_baud__MAX 0xf
19978 #define R_SYNC_SERIAL1_CTRL__dma_enable__MAX 0x1
19979 #define R_SYNC_SERIAL1_CTRL__mode__MAX 0x7
19980 #define R_SYNC_SERIAL1_CTRL__error__MAX 0x1
19981 #define R_SYNC_SERIAL1_CTRL__rec_enable__MAX 0x1
19982 #define R_SYNC_SERIAL1_CTRL__f_synctype__MAX 0x1
19983 #define R_SYNC_SERIAL1_CTRL__f_syncsize__MAX 0x3
19984 #define R_SYNC_SERIAL1_CTRL__f_sync__MAX 0x1
19985 #define R_SYNC_SERIAL1_CTRL__clk_mode__MAX 0x1
19986 #define R_SYNC_SERIAL1_CTRL__clk_halt__MAX 0x1
19987 #define R_SYNC_SERIAL1_CTRL__bitorder__MAX 0x1
19988 #define R_SYNC_SERIAL1_CTRL__tr_enable__MAX 0x1
19989 #define R_SYNC_SERIAL1_CTRL__wordsize__MAX 0x7
19990 #define R_SYNC_SERIAL1_CTRL__buf_empty__MAX 0x1
19991 #define R_SYNC_SERIAL1_CTRL__buf_full__MAX 0x1
19992 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__MAX 0x1
19993 #define R_SYNC_SERIAL1_CTRL__clk_polarity__MAX 0x1
19994 #define R_SYNC_SERIAL1_CTRL__frame_polarity__MAX 0x1
19995 #define R_SYNC_SERIAL1_CTRL__status_polarity__MAX 0x1
19996 #define R_SYNC_SERIAL1_CTRL__clk_driver__MAX 0x1
19997 #define R_SYNC_SERIAL1_CTRL__frame_driver__MAX 0x1
19998 #define R_SYNC_SERIAL1_CTRL__status_driver__MAX 0x1
19999 #define R_SYNC_SERIAL1_CTRL__def_out0__MAX 0x1
20000
20001 #define R_SYNC_SERIAL1_CTRL__tr_baud__MIN 0
20002 #define R_SYNC_SERIAL1_CTRL__dma_enable__MIN 0
20003 #define R_SYNC_SERIAL1_CTRL__mode__MIN 0
20004 #define R_SYNC_SERIAL1_CTRL__error__MIN 0
20005 #define R_SYNC_SERIAL1_CTRL__rec_enable__MIN 0
20006 #define R_SYNC_SERIAL1_CTRL__f_synctype__MIN 0
20007 #define R_SYNC_SERIAL1_CTRL__f_syncsize__MIN 0
20008 #define R_SYNC_SERIAL1_CTRL__f_sync__MIN 0
20009 #define R_SYNC_SERIAL1_CTRL__clk_mode__MIN 0
20010 #define R_SYNC_SERIAL1_CTRL__clk_halt__MIN 0
20011 #define R_SYNC_SERIAL1_CTRL__bitorder__MIN 0
20012 #define R_SYNC_SERIAL1_CTRL__tr_enable__MIN 0
20013 #define R_SYNC_SERIAL1_CTRL__wordsize__MIN 0
20014 #define R_SYNC_SERIAL1_CTRL__buf_empty__MIN 0
20015 #define R_SYNC_SERIAL1_CTRL__buf_full__MIN 0
20016 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__MIN 0
20017 #define R_SYNC_SERIAL1_CTRL__clk_polarity__MIN 0
20018 #define R_SYNC_SERIAL1_CTRL__frame_polarity__MIN 0
20019 #define R_SYNC_SERIAL1_CTRL__status_polarity__MIN 0
20020 #define R_SYNC_SERIAL1_CTRL__clk_driver__MIN 0
20021 #define R_SYNC_SERIAL1_CTRL__frame_driver__MIN 0
20022 #define R_SYNC_SERIAL1_CTRL__status_driver__MIN 0
20023 #define R_SYNC_SERIAL1_CTRL__def_out0__MIN 0
20024
20025 #define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
20026 #define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
20027 #define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
20028 #define R_SYNC_SERIAL1_CTRL__error__BITNR 23
20029 #define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
20030 #define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
20031 #define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
20032 #define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
20033 #define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
20034 #define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
20035 #define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
20036 #define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
20037 #define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
20038 #define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
20039 #define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
20040 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
20041 #define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
20042 #define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
20043 #define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
20044 #define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
20045 #define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
20046 #define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
20047 #define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
20048
20049 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
20050 #define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM
20051 #define R_SYNC_SERIAL1_CTRL__mode__mode__VAL REG_VAL_ENUM
20052 #define R_SYNC_SERIAL1_CTRL__error__error__VAL REG_VAL_ENUM
20053 #define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
20054 #define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM
20055 #define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM
20056 #define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM
20057 #define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM
20058 #define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM
20059 #define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM
20060 #define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
20061 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM
20062 #define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM
20063 #define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM
20064 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM
20065 #define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM
20066 #define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM
20067 #define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM
20068 #define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM
20069 #define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM
20070 #define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM
20071 #define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM
20072
20073 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 10
20074 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 3
20075 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c150Hz 0
20076 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 7
20077 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 11
20078 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 4
20079 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c28k8Hz 8
20080 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 1
20081 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c3125kHz 14
20082 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 12
20083 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 5
20084 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 9
20085 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 2
20086 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 13
20087 #define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 6
20088 #define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__off 0
20089 #define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__on 1
20090 #define R_SYNC_SERIAL1_CTRL__mode__mode__master_bidir 4
20091 #define R_SYNC_SERIAL1_CTRL__mode__mode__master_input 2
20092 #define R_SYNC_SERIAL1_CTRL__mode__mode__master_output 0
20093 #define R_SYNC_SERIAL1_CTRL__mode__mode__slave_bidir 5
20094 #define R_SYNC_SERIAL1_CTRL__mode__mode__slave_input 3
20095 #define R_SYNC_SERIAL1_CTRL__mode__mode__slave_output 1
20096 #define R_SYNC_SERIAL1_CTRL__error__error__ignore 1
20097 #define R_SYNC_SERIAL1_CTRL__error__error__normal 0
20098 #define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__disable 0
20099 #define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__enable 1
20100 #define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__early 1
20101 #define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__normal 0
20102 #define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__bit 0
20103 #define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__extended 2
20104 #define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__word 1
20105 #define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__off 1
20106 #define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__on 0
20107 #define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__gated 1
20108 #define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__normal 0
20109 #define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__running 0
20110 #define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__stopped 1
20111 #define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__lsb 0
20112 #define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__msb 1
20113 #define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__disable 0
20114 #define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__enable 1
20115 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size12bit 1
20116 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size16bit 2
20117 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size24bit 3
20118 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size32bit 4
20119 #define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size8bit 0
20120 #define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_0 1
20121 #define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_8 0
20122 #define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_32 0
20123 #define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_8 1
20124 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__disabled 0
20125 #define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__enabled 1
20126 #define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__neg 1
20127 #define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__pos 0
20128 #define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__inverted 1
20129 #define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__normal 0
20130 #define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__inverted 1
20131 #define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__normal 0
20132 #define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__inverted 1
20133 #define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__normal 0
20134 #define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__inverted 1
20135 #define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__normal 0
20136 #define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__inverted 1
20137 #define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__normal 0
20138 #define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__high 1
20139 #define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__low 0
20140
20141 #endif
20142
20143 /*
20144 * R_SYNC_SERIAL1_REC_BYTE
20145 * - type: RO
20146 * - addr: 0xb000006c
20147 * - group: Syncrounous serial port registers
20148 */
20149
20150 #if USE_GROUP__Syncrounous_serial_port_registers
20151
20152 #define R_SYNC_SERIAL1_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c)
20153 #define R_SYNC_SERIAL1_REC_BYTE__SVAL REG_SVAL_SHADOW
20154 #define R_SYNC_SERIAL1_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW
20155 #define R_SYNC_SERIAL1_REC_BYTE__TYPECAST REG_TYPECAST_BYTE
20156 #define R_SYNC_SERIAL1_REC_BYTE__TYPE (REG_BYTE)
20157 #define R_SYNC_SERIAL1_REC_BYTE__GET REG_GET_RO
20158 #define R_SYNC_SERIAL1_REC_BYTE__IGET REG_IGET_RO
20159 #define R_SYNC_SERIAL1_REC_BYTE__SET REG_SET_RO
20160 #define R_SYNC_SERIAL1_REC_BYTE__ISET REG_ISET_RO
20161 #define R_SYNC_SERIAL1_REC_BYTE__SET_VAL REG_SET_VAL_RO
20162 #define R_SYNC_SERIAL1_REC_BYTE__EQL REG_EQL_RO
20163 #define R_SYNC_SERIAL1_REC_BYTE__IEQL REG_IEQL_RO
20164 #define R_SYNC_SERIAL1_REC_BYTE__RD REG_RD_RO
20165 #define R_SYNC_SERIAL1_REC_BYTE__IRD REG_IRD_RO
20166 #define R_SYNC_SERIAL1_REC_BYTE__WR REG_WR_RO
20167 #define R_SYNC_SERIAL1_REC_BYTE__IWR REG_IWR_RO
20168
20169 #define R_SYNC_SERIAL1_REC_BYTE__READ(addr) \
20170 (*(addr))
20171
20172 #define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__MASK 0x000000ffU
20173
20174 #define R_SYNC_SERIAL1_REC_BYTE__data_in__MAX 0xff
20175
20176 #define R_SYNC_SERIAL1_REC_BYTE__data_in__MIN 0
20177
20178 #define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
20179
20180 #define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL
20181
20182
20183 #endif
20184
20185 /*
20186 * R_SYNC_SERIAL1_REC_DATA
20187 * - type: RO
20188 * - addr: 0xb000006c
20189 * - group: Syncrounous serial port registers
20190 */
20191
20192 #if USE_GROUP__Syncrounous_serial_port_registers
20193
20194 #define R_SYNC_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
20195 #define R_SYNC_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW
20196 #define R_SYNC_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
20197 #define R_SYNC_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_UDWORD
20198 #define R_SYNC_SERIAL1_REC_DATA__TYPE (REG_UDWORD)
20199 #define R_SYNC_SERIAL1_REC_DATA__GET REG_GET_RO
20200 #define R_SYNC_SERIAL1_REC_DATA__IGET REG_IGET_RO
20201 #define R_SYNC_SERIAL1_REC_DATA__SET REG_SET_RO
20202 #define R_SYNC_SERIAL1_REC_DATA__ISET REG_ISET_RO
20203 #define R_SYNC_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO
20204 #define R_SYNC_SERIAL1_REC_DATA__EQL REG_EQL_RO
20205 #define R_SYNC_SERIAL1_REC_DATA__IEQL REG_IEQL_RO
20206 #define R_SYNC_SERIAL1_REC_DATA__RD REG_RD_RO
20207 #define R_SYNC_SERIAL1_REC_DATA__IRD REG_IRD_RO
20208 #define R_SYNC_SERIAL1_REC_DATA__WR REG_WR_RO
20209 #define R_SYNC_SERIAL1_REC_DATA__IWR REG_IWR_RO
20210
20211 #define R_SYNC_SERIAL1_REC_DATA__READ(addr) \
20212 (*(addr))
20213
20214 #define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__MASK 0xffffffffU
20215
20216 #define R_SYNC_SERIAL1_REC_DATA__data_in__MAX 0xffffffff
20217
20218 #define R_SYNC_SERIAL1_REC_DATA__data_in__MIN 0
20219
20220 #define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
20221
20222 #define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
20223
20224
20225 #endif
20226
20227 /*
20228 * R_SYNC_SERIAL1_REC_WORD
20229 * - type: RO
20230 * - addr: 0xb000006c
20231 * - group: Syncrounous serial port registers
20232 */
20233
20234 #if USE_GROUP__Syncrounous_serial_port_registers
20235
20236 #define R_SYNC_SERIAL1_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c)
20237 #define R_SYNC_SERIAL1_REC_WORD__SVAL REG_SVAL_SHADOW
20238 #define R_SYNC_SERIAL1_REC_WORD__SVAL_I REG_SVAL_I_SHADOW
20239 #define R_SYNC_SERIAL1_REC_WORD__TYPECAST REG_TYPECAST_UWORD
20240 #define R_SYNC_SERIAL1_REC_WORD__TYPE (REG_UWORD)
20241 #define R_SYNC_SERIAL1_REC_WORD__GET REG_GET_RO
20242 #define R_SYNC_SERIAL1_REC_WORD__IGET REG_IGET_RO
20243 #define R_SYNC_SERIAL1_REC_WORD__SET REG_SET_RO
20244 #define R_SYNC_SERIAL1_REC_WORD__ISET REG_ISET_RO
20245 #define R_SYNC_SERIAL1_REC_WORD__SET_VAL REG_SET_VAL_RO
20246 #define R_SYNC_SERIAL1_REC_WORD__EQL REG_EQL_RO
20247 #define R_SYNC_SERIAL1_REC_WORD__IEQL REG_IEQL_RO
20248 #define R_SYNC_SERIAL1_REC_WORD__RD REG_RD_RO
20249 #define R_SYNC_SERIAL1_REC_WORD__IRD REG_IRD_RO
20250 #define R_SYNC_SERIAL1_REC_WORD__WR REG_WR_RO
20251 #define R_SYNC_SERIAL1_REC_WORD__IWR REG_IWR_RO
20252
20253 #define R_SYNC_SERIAL1_REC_WORD__READ(addr) \
20254 (*(addr))
20255
20256 #define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__MASK 0x0000ffffU
20257
20258 #define R_SYNC_SERIAL1_REC_WORD__data_in__MAX 0xffff
20259
20260 #define R_SYNC_SERIAL1_REC_WORD__data_in__MIN 0
20261
20262 #define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
20263
20264 #define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__VAL REG_VAL_VAL
20265
20266
20267 #endif
20268
20269 /*
20270 * R_SYNC_SERIAL1_STATUS
20271 * - type: RO
20272 * - addr: 0xb0000068
20273 * - group: Syncrounous serial port registers
20274 */
20275
20276 #if USE_GROUP__Syncrounous_serial_port_registers
20277
20278 #define R_SYNC_SERIAL1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
20279 #define R_SYNC_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW
20280 #define R_SYNC_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW
20281 #define R_SYNC_SERIAL1_STATUS__TYPECAST REG_TYPECAST_UDWORD
20282 #define R_SYNC_SERIAL1_STATUS__TYPE (REG_UDWORD)
20283 #define R_SYNC_SERIAL1_STATUS__GET REG_GET_RO
20284 #define R_SYNC_SERIAL1_STATUS__IGET REG_IGET_RO
20285 #define R_SYNC_SERIAL1_STATUS__SET REG_SET_RO
20286 #define R_SYNC_SERIAL1_STATUS__ISET REG_ISET_RO
20287 #define R_SYNC_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO
20288 #define R_SYNC_SERIAL1_STATUS__EQL REG_EQL_RO
20289 #define R_SYNC_SERIAL1_STATUS__IEQL REG_IEQL_RO
20290 #define R_SYNC_SERIAL1_STATUS__RD REG_RD_RO
20291 #define R_SYNC_SERIAL1_STATUS__IRD REG_IRD_RO
20292 #define R_SYNC_SERIAL1_STATUS__WR REG_WR_RO
20293 #define R_SYNC_SERIAL1_STATUS__IWR REG_IWR_RO
20294
20295 #define R_SYNC_SERIAL1_STATUS__READ(addr) \
20296 (*(addr))
20297
20298 #define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__MASK 0x00008000U
20299 #define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__MASK 0x00004000U
20300 #define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00002000U
20301 #define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__MASK 0x00001000U
20302 #define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__MASK 0x00000800U
20303 #define R_SYNC_SERIAL1_STATUS__underflow__underflow__MASK 0x00000400U
20304 #define R_SYNC_SERIAL1_STATUS__overrun__overrun__MASK 0x00000200U
20305 #define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000100U
20306 #define R_SYNC_SERIAL1_STATUS__data__data__MASK 0x000000ffU
20307
20308 #define R_SYNC_SERIAL1_STATUS__rec_status__MAX 0x1
20309 #define R_SYNC_SERIAL1_STATUS__tr_empty__MAX 0x1
20310 #define R_SYNC_SERIAL1_STATUS__tr_ready__MAX 0x1
20311 #define R_SYNC_SERIAL1_STATUS__pin_1__MAX 0x1
20312 #define R_SYNC_SERIAL1_STATUS__pin_0__MAX 0x1
20313 #define R_SYNC_SERIAL1_STATUS__underflow__MAX 0x1
20314 #define R_SYNC_SERIAL1_STATUS__overrun__MAX 0x1
20315 #define R_SYNC_SERIAL1_STATUS__data_avail__MAX 0x1
20316 #define R_SYNC_SERIAL1_STATUS__data__MAX 0xff
20317
20318 #define R_SYNC_SERIAL1_STATUS__rec_status__MIN 0
20319 #define R_SYNC_SERIAL1_STATUS__tr_empty__MIN 0
20320 #define R_SYNC_SERIAL1_STATUS__tr_ready__MIN 0
20321 #define R_SYNC_SERIAL1_STATUS__pin_1__MIN 0
20322 #define R_SYNC_SERIAL1_STATUS__pin_0__MIN 0
20323 #define R_SYNC_SERIAL1_STATUS__underflow__MIN 0
20324 #define R_SYNC_SERIAL1_STATUS__overrun__MIN 0
20325 #define R_SYNC_SERIAL1_STATUS__data_avail__MIN 0
20326 #define R_SYNC_SERIAL1_STATUS__data__MIN 0
20327
20328 #define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
20329 #define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
20330 #define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
20331 #define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
20332 #define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
20333 #define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
20334 #define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
20335 #define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
20336 #define R_SYNC_SERIAL1_STATUS__data__BITNR 0
20337
20338 #define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM
20339 #define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM
20340 #define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
20341 #define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM
20342 #define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM
20343 #define R_SYNC_SERIAL1_STATUS__underflow__underflow__VAL REG_VAL_ENUM
20344 #define R_SYNC_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM
20345 #define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
20346 #define R_SYNC_SERIAL1_STATUS__data__data__VAL REG_VAL_VAL
20347
20348 #define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__idle 1
20349 #define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__running 0
20350 #define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__empty 1
20351 #define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__not_empty 0
20352 #define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__full 0
20353 #define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__ready 1
20354 #define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__high 1
20355 #define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__low 0
20356 #define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__high 1
20357 #define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__low 0
20358 #define R_SYNC_SERIAL1_STATUS__underflow__underflow__no 0
20359 #define R_SYNC_SERIAL1_STATUS__underflow__underflow__yes 1
20360 #define R_SYNC_SERIAL1_STATUS__overrun__overrun__no 0
20361 #define R_SYNC_SERIAL1_STATUS__overrun__overrun__yes 1
20362 #define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__no 0
20363 #define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__yes 1
20364
20365 #endif
20366
20367 /*
20368 * R_SYNC_SERIAL1_TR_BYTE
20369 * - type: WO
20370 * - addr: 0xb000006c
20371 * - group: Syncrounous serial port registers
20372 */
20373
20374 #if USE_GROUP__Syncrounous_serial_port_registers
20375
20376 #define R_SYNC_SERIAL1_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c)
20377
20378 #ifndef REG_NO_SHADOW
20379 #define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
20380 #define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
20381 #else /* REG_NO_SHADOW */
20382 #define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
20383 #define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
20384 #endif /* REG_NO_SHADOW */
20385
20386 #define R_SYNC_SERIAL1_TR_BYTE__STYPECAST REG_STYPECAST_BYTE
20387 #define R_SYNC_SERIAL1_TR_BYTE__SVAL REG_SVAL_SHADOW
20388 #define R_SYNC_SERIAL1_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW
20389 #define R_SYNC_SERIAL1_TR_BYTE__TYPECAST REG_TYPECAST_BYTE
20390 #define R_SYNC_SERIAL1_TR_BYTE__TYPE (REG_BYTE)
20391 #define R_SYNC_SERIAL1_TR_BYTE__GET REG_GET_WO
20392 #define R_SYNC_SERIAL1_TR_BYTE__IGET REG_IGET_WO
20393 #define R_SYNC_SERIAL1_TR_BYTE__SET REG_SET_WO
20394 #define R_SYNC_SERIAL1_TR_BYTE__ISET REG_ISET_WO
20395 #define R_SYNC_SERIAL1_TR_BYTE__SET_VAL REG_SET_VAL_WO
20396 #define R_SYNC_SERIAL1_TR_BYTE__EQL REG_EQL_WO
20397 #define R_SYNC_SERIAL1_TR_BYTE__IEQL REG_IEQL_WO
20398 #define R_SYNC_SERIAL1_TR_BYTE__RD REG_RD_WO
20399 #define R_SYNC_SERIAL1_TR_BYTE__IRD REG_IRD_WO
20400 #define R_SYNC_SERIAL1_TR_BYTE__WR REG_WR_WO
20401 #define R_SYNC_SERIAL1_TR_BYTE__IWR REG_IWR_WO
20402
20403 #define R_SYNC_SERIAL1_TR_BYTE__WRITE(addr,value) \
20404 (*(addr) = (value))
20405
20406 #define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__MASK 0x000000ffU
20407
20408 #define R_SYNC_SERIAL1_TR_BYTE__data_out__MAX 0xff
20409
20410 #define R_SYNC_SERIAL1_TR_BYTE__data_out__MIN 0
20411
20412 #define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
20413
20414 #define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL
20415
20416
20417 #endif
20418
20419 /*
20420 * R_SYNC_SERIAL1_TR_DATA
20421 * - type: WO
20422 * - addr: 0xb000006c
20423 * - group: Syncrounous serial port registers
20424 */
20425
20426 #if USE_GROUP__Syncrounous_serial_port_registers
20427
20428 #define R_SYNC_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
20429
20430 #ifndef REG_NO_SHADOW
20431 #define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
20432 #define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
20433 #else /* REG_NO_SHADOW */
20434 #define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
20435 #define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
20436 #endif /* REG_NO_SHADOW */
20437
20438 #define R_SYNC_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_UDWORD
20439 #define R_SYNC_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW
20440 #define R_SYNC_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
20441 #define R_SYNC_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_UDWORD
20442 #define R_SYNC_SERIAL1_TR_DATA__TYPE (REG_UDWORD)
20443 #define R_SYNC_SERIAL1_TR_DATA__GET REG_GET_WO
20444 #define R_SYNC_SERIAL1_TR_DATA__IGET REG_IGET_WO
20445 #define R_SYNC_SERIAL1_TR_DATA__SET REG_SET_WO
20446 #define R_SYNC_SERIAL1_TR_DATA__ISET REG_ISET_WO
20447 #define R_SYNC_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO
20448 #define R_SYNC_SERIAL1_TR_DATA__EQL REG_EQL_WO
20449 #define R_SYNC_SERIAL1_TR_DATA__IEQL REG_IEQL_WO
20450 #define R_SYNC_SERIAL1_TR_DATA__RD REG_RD_WO
20451 #define R_SYNC_SERIAL1_TR_DATA__IRD REG_IRD_WO
20452 #define R_SYNC_SERIAL1_TR_DATA__WR REG_WR_WO
20453 #define R_SYNC_SERIAL1_TR_DATA__IWR REG_IWR_WO
20454
20455 #define R_SYNC_SERIAL1_TR_DATA__WRITE(addr,value) \
20456 (*(addr) = (value))
20457
20458 #define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__MASK 0xffffffffU
20459
20460 #define R_SYNC_SERIAL1_TR_DATA__data_out__MAX 0xffffffff
20461
20462 #define R_SYNC_SERIAL1_TR_DATA__data_out__MIN 0
20463
20464 #define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
20465
20466 #define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
20467
20468
20469 #endif
20470
20471 /*
20472 * R_SYNC_SERIAL1_TR_WORD
20473 * - type: WO
20474 * - addr: 0xb000006c
20475 * - group: Syncrounous serial port registers
20476 */
20477
20478 #if USE_GROUP__Syncrounous_serial_port_registers
20479
20480 #define R_SYNC_SERIAL1_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c)
20481
20482 #ifndef REG_NO_SHADOW
20483 #define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
20484 #define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
20485 #else /* REG_NO_SHADOW */
20486 #define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
20487 #define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
20488 #endif /* REG_NO_SHADOW */
20489
20490 #define R_SYNC_SERIAL1_TR_WORD__STYPECAST REG_STYPECAST_UWORD
20491 #define R_SYNC_SERIAL1_TR_WORD__SVAL REG_SVAL_SHADOW
20492 #define R_SYNC_SERIAL1_TR_WORD__SVAL_I REG_SVAL_I_SHADOW
20493 #define R_SYNC_SERIAL1_TR_WORD__TYPECAST REG_TYPECAST_UWORD
20494 #define R_SYNC_SERIAL1_TR_WORD__TYPE (REG_UWORD)
20495 #define R_SYNC_SERIAL1_TR_WORD__GET REG_GET_WO
20496 #define R_SYNC_SERIAL1_TR_WORD__IGET REG_IGET_WO
20497 #define R_SYNC_SERIAL1_TR_WORD__SET REG_SET_WO
20498 #define R_SYNC_SERIAL1_TR_WORD__ISET REG_ISET_WO
20499 #define R_SYNC_SERIAL1_TR_WORD__SET_VAL REG_SET_VAL_WO
20500 #define R_SYNC_SERIAL1_TR_WORD__EQL REG_EQL_WO
20501 #define R_SYNC_SERIAL1_TR_WORD__IEQL REG_IEQL_WO
20502 #define R_SYNC_SERIAL1_TR_WORD__RD REG_RD_WO
20503 #define R_SYNC_SERIAL1_TR_WORD__IRD REG_IRD_WO
20504 #define R_SYNC_SERIAL1_TR_WORD__WR REG_WR_WO
20505 #define R_SYNC_SERIAL1_TR_WORD__IWR REG_IWR_WO
20506
20507 #define R_SYNC_SERIAL1_TR_WORD__WRITE(addr,value) \
20508 (*(addr) = (value))
20509
20510 #define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__MASK 0x0000ffffU
20511
20512 #define R_SYNC_SERIAL1_TR_WORD__data_out__MAX 0xffff
20513
20514 #define R_SYNC_SERIAL1_TR_WORD__data_out__MIN 0
20515
20516 #define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
20517
20518 #define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__VAL REG_VAL_VAL
20519
20520
20521 #endif
20522
20523 /*
20524 * R_SYNC_SERIAL3_CTRL
20525 * - type: WO
20526 * - addr: 0xb0000078
20527 * - group: Syncrounous serial port registers
20528 */
20529
20530 #if USE_GROUP__Syncrounous_serial_port_registers
20531
20532 #define R_SYNC_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
20533
20534 #ifndef REG_NO_SHADOW
20535 #define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
20536 #define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
20537 #else /* REG_NO_SHADOW */
20538 #define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
20539 #define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
20540 #endif /* REG_NO_SHADOW */
20541
20542 #define R_SYNC_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD
20543 #define R_SYNC_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW
20544 #define R_SYNC_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW
20545 #define R_SYNC_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD
20546 #define R_SYNC_SERIAL3_CTRL__TYPE (REG_UDWORD)
20547 #define R_SYNC_SERIAL3_CTRL__GET REG_GET_WO
20548 #define R_SYNC_SERIAL3_CTRL__IGET REG_IGET_WO
20549 #define R_SYNC_SERIAL3_CTRL__SET REG_SET_WO
20550 #define R_SYNC_SERIAL3_CTRL__ISET REG_ISET_WO
20551 #define R_SYNC_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO
20552 #define R_SYNC_SERIAL3_CTRL__EQL REG_EQL_WO
20553 #define R_SYNC_SERIAL3_CTRL__IEQL REG_IEQL_WO
20554 #define R_SYNC_SERIAL3_CTRL__RD REG_RD_WO
20555 #define R_SYNC_SERIAL3_CTRL__IRD REG_IRD_WO
20556 #define R_SYNC_SERIAL3_CTRL__WR REG_WR_WO
20557 #define R_SYNC_SERIAL3_CTRL__IWR REG_IWR_WO
20558
20559 #define R_SYNC_SERIAL3_CTRL__WRITE(addr,value) \
20560 (*(addr) = (value))
20561
20562 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
20563 #define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__MASK 0x08000000U
20564 #define R_SYNC_SERIAL3_CTRL__mode__mode__MASK 0x07000000U
20565 #define R_SYNC_SERIAL3_CTRL__error__error__MASK 0x00800000U
20566 #define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U
20567 #define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__MASK 0x00200000U
20568 #define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U
20569 #define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__MASK 0x00040000U
20570 #define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__MASK 0x00020000U
20571 #define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__MASK 0x00010000U
20572 #define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__MASK 0x00008000U
20573 #define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U
20574 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__MASK 0x00003800U
20575 #define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__MASK 0x00000400U
20576 #define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__MASK 0x00000200U
20577 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U
20578 #define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U
20579 #define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U
20580 #define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__MASK 0x00000010U
20581 #define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__MASK 0x00000008U
20582 #define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__MASK 0x00000004U
20583 #define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__MASK 0x00000002U
20584 #define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__MASK 0x00000001U
20585
20586 #define R_SYNC_SERIAL3_CTRL__tr_baud__MAX 0xf
20587 #define R_SYNC_SERIAL3_CTRL__dma_enable__MAX 0x1
20588 #define R_SYNC_SERIAL3_CTRL__mode__MAX 0x7
20589 #define R_SYNC_SERIAL3_CTRL__error__MAX 0x1
20590 #define R_SYNC_SERIAL3_CTRL__rec_enable__MAX 0x1
20591 #define R_SYNC_SERIAL3_CTRL__f_synctype__MAX 0x1
20592 #define R_SYNC_SERIAL3_CTRL__f_syncsize__MAX 0x3
20593 #define R_SYNC_SERIAL3_CTRL__f_sync__MAX 0x1
20594 #define R_SYNC_SERIAL3_CTRL__clk_mode__MAX 0x1
20595 #define R_SYNC_SERIAL3_CTRL__clk_halt__MAX 0x1
20596 #define R_SYNC_SERIAL3_CTRL__bitorder__MAX 0x1
20597 #define R_SYNC_SERIAL3_CTRL__tr_enable__MAX 0x1
20598 #define R_SYNC_SERIAL3_CTRL__wordsize__MAX 0x7
20599 #define R_SYNC_SERIAL3_CTRL__buf_empty__MAX 0x1
20600 #define R_SYNC_SERIAL3_CTRL__buf_full__MAX 0x1
20601 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__MAX 0x1
20602 #define R_SYNC_SERIAL3_CTRL__clk_polarity__MAX 0x1
20603 #define R_SYNC_SERIAL3_CTRL__frame_polarity__MAX 0x1
20604 #define R_SYNC_SERIAL3_CTRL__status_polarity__MAX 0x1
20605 #define R_SYNC_SERIAL3_CTRL__clk_driver__MAX 0x1
20606 #define R_SYNC_SERIAL3_CTRL__frame_driver__MAX 0x1
20607 #define R_SYNC_SERIAL3_CTRL__status_driver__MAX 0x1
20608 #define R_SYNC_SERIAL3_CTRL__def_out0__MAX 0x1
20609
20610 #define R_SYNC_SERIAL3_CTRL__tr_baud__MIN 0
20611 #define R_SYNC_SERIAL3_CTRL__dma_enable__MIN 0
20612 #define R_SYNC_SERIAL3_CTRL__mode__MIN 0
20613 #define R_SYNC_SERIAL3_CTRL__error__MIN 0
20614 #define R_SYNC_SERIAL3_CTRL__rec_enable__MIN 0
20615 #define R_SYNC_SERIAL3_CTRL__f_synctype__MIN 0
20616 #define R_SYNC_SERIAL3_CTRL__f_syncsize__MIN 0
20617 #define R_SYNC_SERIAL3_CTRL__f_sync__MIN 0
20618 #define R_SYNC_SERIAL3_CTRL__clk_mode__MIN 0
20619 #define R_SYNC_SERIAL3_CTRL__clk_halt__MIN 0
20620 #define R_SYNC_SERIAL3_CTRL__bitorder__MIN 0
20621 #define R_SYNC_SERIAL3_CTRL__tr_enable__MIN 0
20622 #define R_SYNC_SERIAL3_CTRL__wordsize__MIN 0
20623 #define R_SYNC_SERIAL3_CTRL__buf_empty__MIN 0
20624 #define R_SYNC_SERIAL3_CTRL__buf_full__MIN 0
20625 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__MIN 0
20626 #define R_SYNC_SERIAL3_CTRL__clk_polarity__MIN 0
20627 #define R_SYNC_SERIAL3_CTRL__frame_polarity__MIN 0
20628 #define R_SYNC_SERIAL3_CTRL__status_polarity__MIN 0
20629 #define R_SYNC_SERIAL3_CTRL__clk_driver__MIN 0
20630 #define R_SYNC_SERIAL3_CTRL__frame_driver__MIN 0
20631 #define R_SYNC_SERIAL3_CTRL__status_driver__MIN 0
20632 #define R_SYNC_SERIAL3_CTRL__def_out0__MIN 0
20633
20634 #define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
20635 #define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
20636 #define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
20637 #define R_SYNC_SERIAL3_CTRL__error__BITNR 23
20638 #define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
20639 #define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
20640 #define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
20641 #define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
20642 #define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
20643 #define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
20644 #define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
20645 #define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
20646 #define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
20647 #define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
20648 #define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
20649 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
20650 #define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
20651 #define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
20652 #define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
20653 #define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
20654 #define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
20655 #define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
20656 #define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
20657
20658 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
20659 #define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM
20660 #define R_SYNC_SERIAL3_CTRL__mode__mode__VAL REG_VAL_ENUM
20661 #define R_SYNC_SERIAL3_CTRL__error__error__VAL REG_VAL_ENUM
20662 #define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
20663 #define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM
20664 #define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM
20665 #define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM
20666 #define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM
20667 #define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM
20668 #define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM
20669 #define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
20670 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM
20671 #define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM
20672 #define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM
20673 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM
20674 #define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM
20675 #define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM
20676 #define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM
20677 #define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM
20678 #define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM
20679 #define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM
20680 #define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM
20681
20682 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 10
20683 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 3
20684 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c150Hz 0
20685 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 7
20686 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 11
20687 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 4
20688 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c28k8Hz 8
20689 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 1
20690 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c3125kHz 14
20691 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 12
20692 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 5
20693 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 9
20694 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 2
20695 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 13
20696 #define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 6
20697 #define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__off 0
20698 #define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__on 1
20699 #define R_SYNC_SERIAL3_CTRL__mode__mode__master_bidir 4
20700 #define R_SYNC_SERIAL3_CTRL__mode__mode__master_input 2
20701 #define R_SYNC_SERIAL3_CTRL__mode__mode__master_output 0
20702 #define R_SYNC_SERIAL3_CTRL__mode__mode__slave_bidir 5
20703 #define R_SYNC_SERIAL3_CTRL__mode__mode__slave_input 3
20704 #define R_SYNC_SERIAL3_CTRL__mode__mode__slave_output 1
20705 #define R_SYNC_SERIAL3_CTRL__error__error__ignore 1
20706 #define R_SYNC_SERIAL3_CTRL__error__error__normal 0
20707 #define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__disable 0
20708 #define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__enable 1
20709 #define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__early 1
20710 #define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__normal 0
20711 #define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__bit 0
20712 #define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__extended 2
20713 #define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__word 1
20714 #define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__off 1
20715 #define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__on 0
20716 #define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__gated 1
20717 #define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__normal 0
20718 #define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__running 0
20719 #define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__stopped 1
20720 #define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__lsb 0
20721 #define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__msb 1
20722 #define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__disable 0
20723 #define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__enable 1
20724 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size12bit 1
20725 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size16bit 2
20726 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size24bit 3
20727 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size32bit 4
20728 #define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size8bit 0
20729 #define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_0 1
20730 #define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_8 0
20731 #define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_32 0
20732 #define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_8 1
20733 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__disabled 0
20734 #define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__enabled 1
20735 #define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__neg 1
20736 #define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__pos 0
20737 #define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__inverted 1
20738 #define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__normal 0
20739 #define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__inverted 1
20740 #define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__normal 0
20741 #define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__inverted 1
20742 #define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__normal 0
20743 #define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__inverted 1
20744 #define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__normal 0
20745 #define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__inverted 1
20746 #define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__normal 0
20747 #define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__high 1
20748 #define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__low 0
20749
20750 #endif
20751
20752 /*
20753 * R_SYNC_SERIAL3_REC_BYTE
20754 * - type: RO
20755 * - addr: 0xb000007c
20756 * - group: Syncrounous serial port registers
20757 */
20758
20759 #if USE_GROUP__Syncrounous_serial_port_registers
20760
20761 #define R_SYNC_SERIAL3_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c)
20762 #define R_SYNC_SERIAL3_REC_BYTE__SVAL REG_SVAL_SHADOW
20763 #define R_SYNC_SERIAL3_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW
20764 #define R_SYNC_SERIAL3_REC_BYTE__TYPECAST REG_TYPECAST_BYTE
20765 #define R_SYNC_SERIAL3_REC_BYTE__TYPE (REG_BYTE)
20766 #define R_SYNC_SERIAL3_REC_BYTE__GET REG_GET_RO
20767 #define R_SYNC_SERIAL3_REC_BYTE__IGET REG_IGET_RO
20768 #define R_SYNC_SERIAL3_REC_BYTE__SET REG_SET_RO
20769 #define R_SYNC_SERIAL3_REC_BYTE__ISET REG_ISET_RO
20770 #define R_SYNC_SERIAL3_REC_BYTE__SET_VAL REG_SET_VAL_RO
20771 #define R_SYNC_SERIAL3_REC_BYTE__EQL REG_EQL_RO
20772 #define R_SYNC_SERIAL3_REC_BYTE__IEQL REG_IEQL_RO
20773 #define R_SYNC_SERIAL3_REC_BYTE__RD REG_RD_RO
20774 #define R_SYNC_SERIAL3_REC_BYTE__IRD REG_IRD_RO
20775 #define R_SYNC_SERIAL3_REC_BYTE__WR REG_WR_RO
20776 #define R_SYNC_SERIAL3_REC_BYTE__IWR REG_IWR_RO
20777
20778 #define R_SYNC_SERIAL3_REC_BYTE__READ(addr) \
20779 (*(addr))
20780
20781 #define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__MASK 0x000000ffU
20782
20783 #define R_SYNC_SERIAL3_REC_BYTE__data_in__MAX 0xff
20784
20785 #define R_SYNC_SERIAL3_REC_BYTE__data_in__MIN 0
20786
20787 #define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
20788
20789 #define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL
20790
20791
20792 #endif
20793
20794 /*
20795 * R_SYNC_SERIAL3_REC_DATA
20796 * - type: RO
20797 * - addr: 0xb000007c
20798 * - group: Syncrounous serial port registers
20799 */
20800
20801 #if USE_GROUP__Syncrounous_serial_port_registers
20802
20803 #define R_SYNC_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
20804 #define R_SYNC_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW
20805 #define R_SYNC_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
20806 #define R_SYNC_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_UDWORD
20807 #define R_SYNC_SERIAL3_REC_DATA__TYPE (REG_UDWORD)
20808 #define R_SYNC_SERIAL3_REC_DATA__GET REG_GET_RO
20809 #define R_SYNC_SERIAL3_REC_DATA__IGET REG_IGET_RO
20810 #define R_SYNC_SERIAL3_REC_DATA__SET REG_SET_RO
20811 #define R_SYNC_SERIAL3_REC_DATA__ISET REG_ISET_RO
20812 #define R_SYNC_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO
20813 #define R_SYNC_SERIAL3_REC_DATA__EQL REG_EQL_RO
20814 #define R_SYNC_SERIAL3_REC_DATA__IEQL REG_IEQL_RO
20815 #define R_SYNC_SERIAL3_REC_DATA__RD REG_RD_RO
20816 #define R_SYNC_SERIAL3_REC_DATA__IRD REG_IRD_RO
20817 #define R_SYNC_SERIAL3_REC_DATA__WR REG_WR_RO
20818 #define R_SYNC_SERIAL3_REC_DATA__IWR REG_IWR_RO
20819
20820 #define R_SYNC_SERIAL3_REC_DATA__READ(addr) \
20821 (*(addr))
20822
20823 #define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__MASK 0xffffffffU
20824
20825 #define R_SYNC_SERIAL3_REC_DATA__data_in__MAX 0xffffffff
20826
20827 #define R_SYNC_SERIAL3_REC_DATA__data_in__MIN 0
20828
20829 #define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
20830
20831 #define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
20832
20833
20834 #endif
20835
20836 /*
20837 * R_SYNC_SERIAL3_REC_WORD
20838 * - type: RO
20839 * - addr: 0xb000007c
20840 * - group: Syncrounous serial port registers
20841 */
20842
20843 #if USE_GROUP__Syncrounous_serial_port_registers
20844
20845 #define R_SYNC_SERIAL3_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c)
20846 #define R_SYNC_SERIAL3_REC_WORD__SVAL REG_SVAL_SHADOW
20847 #define R_SYNC_SERIAL3_REC_WORD__SVAL_I REG_SVAL_I_SHADOW
20848 #define R_SYNC_SERIAL3_REC_WORD__TYPECAST REG_TYPECAST_UWORD
20849 #define R_SYNC_SERIAL3_REC_WORD__TYPE (REG_UWORD)
20850 #define R_SYNC_SERIAL3_REC_WORD__GET REG_GET_RO
20851 #define R_SYNC_SERIAL3_REC_WORD__IGET REG_IGET_RO
20852 #define R_SYNC_SERIAL3_REC_WORD__SET REG_SET_RO
20853 #define R_SYNC_SERIAL3_REC_WORD__ISET REG_ISET_RO
20854 #define R_SYNC_SERIAL3_REC_WORD__SET_VAL REG_SET_VAL_RO
20855 #define R_SYNC_SERIAL3_REC_WORD__EQL REG_EQL_RO
20856 #define R_SYNC_SERIAL3_REC_WORD__IEQL REG_IEQL_RO
20857 #define R_SYNC_SERIAL3_REC_WORD__RD REG_RD_RO
20858 #define R_SYNC_SERIAL3_REC_WORD__IRD REG_IRD_RO
20859 #define R_SYNC_SERIAL3_REC_WORD__WR REG_WR_RO
20860 #define R_SYNC_SERIAL3_REC_WORD__IWR REG_IWR_RO
20861
20862 #define R_SYNC_SERIAL3_REC_WORD__READ(addr) \
20863 (*(addr))
20864
20865 #define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__MASK 0x0000ffffU
20866
20867 #define R_SYNC_SERIAL3_REC_WORD__data_in__MAX 0xffff
20868
20869 #define R_SYNC_SERIAL3_REC_WORD__data_in__MIN 0
20870
20871 #define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
20872
20873 #define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__VAL REG_VAL_VAL
20874
20875
20876 #endif
20877
20878 /*
20879 * R_SYNC_SERIAL3_STATUS
20880 * - type: RO
20881 * - addr: 0xb0000078
20882 * - group: Syncrounous serial port registers
20883 */
20884
20885 #if USE_GROUP__Syncrounous_serial_port_registers
20886
20887 #define R_SYNC_SERIAL3_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
20888 #define R_SYNC_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW
20889 #define R_SYNC_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW
20890 #define R_SYNC_SERIAL3_STATUS__TYPECAST REG_TYPECAST_UDWORD
20891 #define R_SYNC_SERIAL3_STATUS__TYPE (REG_UDWORD)
20892 #define R_SYNC_SERIAL3_STATUS__GET REG_GET_RO
20893 #define R_SYNC_SERIAL3_STATUS__IGET REG_IGET_RO
20894 #define R_SYNC_SERIAL3_STATUS__SET REG_SET_RO
20895 #define R_SYNC_SERIAL3_STATUS__ISET REG_ISET_RO
20896 #define R_SYNC_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO
20897 #define R_SYNC_SERIAL3_STATUS__EQL REG_EQL_RO
20898 #define R_SYNC_SERIAL3_STATUS__IEQL REG_IEQL_RO
20899 #define R_SYNC_SERIAL3_STATUS__RD REG_RD_RO
20900 #define R_SYNC_SERIAL3_STATUS__IRD REG_IRD_RO
20901 #define R_SYNC_SERIAL3_STATUS__WR REG_WR_RO
20902 #define R_SYNC_SERIAL3_STATUS__IWR REG_IWR_RO
20903
20904 #define R_SYNC_SERIAL3_STATUS__READ(addr) \
20905 (*(addr))
20906
20907 #define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__MASK 0x00008000U
20908 #define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__MASK 0x00004000U
20909 #define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00002000U
20910 #define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__MASK 0x00001000U
20911 #define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__MASK 0x00000800U
20912 #define R_SYNC_SERIAL3_STATUS__underflow__underflow__MASK 0x00000400U
20913 #define R_SYNC_SERIAL3_STATUS__overrun__overrun__MASK 0x00000200U
20914 #define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000100U
20915 #define R_SYNC_SERIAL3_STATUS__data__data__MASK 0x000000ffU
20916
20917 #define R_SYNC_SERIAL3_STATUS__rec_status__MAX 0x1
20918 #define R_SYNC_SERIAL3_STATUS__tr_empty__MAX 0x1
20919 #define R_SYNC_SERIAL3_STATUS__tr_ready__MAX 0x1
20920 #define R_SYNC_SERIAL3_STATUS__pin_1__MAX 0x1
20921 #define R_SYNC_SERIAL3_STATUS__pin_0__MAX 0x1
20922 #define R_SYNC_SERIAL3_STATUS__underflow__MAX 0x1
20923 #define R_SYNC_SERIAL3_STATUS__overrun__MAX 0x1
20924 #define R_SYNC_SERIAL3_STATUS__data_avail__MAX 0x1
20925 #define R_SYNC_SERIAL3_STATUS__data__MAX 0xff
20926
20927 #define R_SYNC_SERIAL3_STATUS__rec_status__MIN 0
20928 #define R_SYNC_SERIAL3_STATUS__tr_empty__MIN 0
20929 #define R_SYNC_SERIAL3_STATUS__tr_ready__MIN 0
20930 #define R_SYNC_SERIAL3_STATUS__pin_1__MIN 0
20931 #define R_SYNC_SERIAL3_STATUS__pin_0__MIN 0
20932 #define R_SYNC_SERIAL3_STATUS__underflow__MIN 0
20933 #define R_SYNC_SERIAL3_STATUS__overrun__MIN 0
20934 #define R_SYNC_SERIAL3_STATUS__data_avail__MIN 0
20935 #define R_SYNC_SERIAL3_STATUS__data__MIN 0
20936
20937 #define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
20938 #define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
20939 #define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
20940 #define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
20941 #define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
20942 #define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
20943 #define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
20944 #define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
20945 #define R_SYNC_SERIAL3_STATUS__data__BITNR 0
20946
20947 #define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM
20948 #define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM
20949 #define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
20950 #define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM
20951 #define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM
20952 #define R_SYNC_SERIAL3_STATUS__underflow__underflow__VAL REG_VAL_ENUM
20953 #define R_SYNC_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM
20954 #define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
20955 #define R_SYNC_SERIAL3_STATUS__data__data__VAL REG_VAL_VAL
20956
20957 #define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__idle 1
20958 #define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__running 0
20959 #define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__empty 1
20960 #define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__not_empty 0
20961 #define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__full 0
20962 #define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__ready 1
20963 #define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__high 1
20964 #define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__low 0
20965 #define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__high 1
20966 #define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__low 0
20967 #define R_SYNC_SERIAL3_STATUS__underflow__underflow__no 0
20968 #define R_SYNC_SERIAL3_STATUS__underflow__underflow__yes 1
20969 #define R_SYNC_SERIAL3_STATUS__overrun__overrun__no 0
20970 #define R_SYNC_SERIAL3_STATUS__overrun__overrun__yes 1
20971 #define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__no 0
20972 #define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__yes 1
20973
20974 #endif
20975
20976 /*
20977 * R_SYNC_SERIAL3_TR_BYTE
20978 * - type: WO
20979 * - addr: 0xb000007c
20980 * - group: Syncrounous serial port registers
20981 */
20982
20983 #if USE_GROUP__Syncrounous_serial_port_registers
20984
20985 #define R_SYNC_SERIAL3_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c)
20986
20987 #ifndef REG_NO_SHADOW
20988 #define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
20989 #define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
20990 #else /* REG_NO_SHADOW */
20991 #define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
20992 #define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
20993 #endif /* REG_NO_SHADOW */
20994
20995 #define R_SYNC_SERIAL3_TR_BYTE__STYPECAST REG_STYPECAST_BYTE
20996 #define R_SYNC_SERIAL3_TR_BYTE__SVAL REG_SVAL_SHADOW
20997 #define R_SYNC_SERIAL3_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW
20998 #define R_SYNC_SERIAL3_TR_BYTE__TYPECAST REG_TYPECAST_BYTE
20999 #define R_SYNC_SERIAL3_TR_BYTE__TYPE (REG_BYTE)
21000 #define R_SYNC_SERIAL3_TR_BYTE__GET REG_GET_WO
21001 #define R_SYNC_SERIAL3_TR_BYTE__IGET REG_IGET_WO
21002 #define R_SYNC_SERIAL3_TR_BYTE__SET REG_SET_WO
21003 #define R_SYNC_SERIAL3_TR_BYTE__ISET REG_ISET_WO
21004 #define R_SYNC_SERIAL3_TR_BYTE__SET_VAL REG_SET_VAL_WO
21005 #define R_SYNC_SERIAL3_TR_BYTE__EQL REG_EQL_WO
21006 #define R_SYNC_SERIAL3_TR_BYTE__IEQL REG_IEQL_WO
21007 #define R_SYNC_SERIAL3_TR_BYTE__RD REG_RD_WO
21008 #define R_SYNC_SERIAL3_TR_BYTE__IRD REG_IRD_WO
21009 #define R_SYNC_SERIAL3_TR_BYTE__WR REG_WR_WO
21010 #define R_SYNC_SERIAL3_TR_BYTE__IWR REG_IWR_WO
21011
21012 #define R_SYNC_SERIAL3_TR_BYTE__WRITE(addr,value) \
21013 (*(addr) = (value))
21014
21015 #define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__MASK 0x000000ffU
21016
21017 #define R_SYNC_SERIAL3_TR_BYTE__data_out__MAX 0xff
21018
21019 #define R_SYNC_SERIAL3_TR_BYTE__data_out__MIN 0
21020
21021 #define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
21022
21023 #define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL
21024
21025
21026 #endif
21027
21028 /*
21029 * R_SYNC_SERIAL3_TR_DATA
21030 * - type: WO
21031 * - addr: 0xb000007c
21032 * - group: Syncrounous serial port registers
21033 */
21034
21035 #if USE_GROUP__Syncrounous_serial_port_registers
21036
21037 #define R_SYNC_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
21038
21039 #ifndef REG_NO_SHADOW
21040 #define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
21041 #define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
21042 #else /* REG_NO_SHADOW */
21043 #define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
21044 #define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
21045 #endif /* REG_NO_SHADOW */
21046
21047 #define R_SYNC_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_UDWORD
21048 #define R_SYNC_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW
21049 #define R_SYNC_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
21050 #define R_SYNC_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_UDWORD
21051 #define R_SYNC_SERIAL3_TR_DATA__TYPE (REG_UDWORD)
21052 #define R_SYNC_SERIAL3_TR_DATA__GET REG_GET_WO
21053 #define R_SYNC_SERIAL3_TR_DATA__IGET REG_IGET_WO
21054 #define R_SYNC_SERIAL3_TR_DATA__SET REG_SET_WO
21055 #define R_SYNC_SERIAL3_TR_DATA__ISET REG_ISET_WO
21056 #define R_SYNC_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO
21057 #define R_SYNC_SERIAL3_TR_DATA__EQL REG_EQL_WO
21058 #define R_SYNC_SERIAL3_TR_DATA__IEQL REG_IEQL_WO
21059 #define R_SYNC_SERIAL3_TR_DATA__RD REG_RD_WO
21060 #define R_SYNC_SERIAL3_TR_DATA__IRD REG_IRD_WO
21061 #define R_SYNC_SERIAL3_TR_DATA__WR REG_WR_WO
21062 #define R_SYNC_SERIAL3_TR_DATA__IWR REG_IWR_WO
21063
21064 #define R_SYNC_SERIAL3_TR_DATA__WRITE(addr,value) \
21065 (*(addr) = (value))
21066
21067 #define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__MASK 0xffffffffU
21068
21069 #define R_SYNC_SERIAL3_TR_DATA__data_out__MAX 0xffffffff
21070
21071 #define R_SYNC_SERIAL3_TR_DATA__data_out__MIN 0
21072
21073 #define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
21074
21075 #define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
21076
21077
21078 #endif
21079
21080 /*
21081 * R_SYNC_SERIAL3_TR_WORD
21082 * - type: WO
21083 * - addr: 0xb000007c
21084 * - group: Syncrounous serial port registers
21085 */
21086
21087 #if USE_GROUP__Syncrounous_serial_port_registers
21088
21089 #define R_SYNC_SERIAL3_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c)
21090
21091 #ifndef REG_NO_SHADOW
21092 #define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
21093 #define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
21094 #else /* REG_NO_SHADOW */
21095 #define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
21096 #define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
21097 #endif /* REG_NO_SHADOW */
21098
21099 #define R_SYNC_SERIAL3_TR_WORD__STYPECAST REG_STYPECAST_UWORD
21100 #define R_SYNC_SERIAL3_TR_WORD__SVAL REG_SVAL_SHADOW
21101 #define R_SYNC_SERIAL3_TR_WORD__SVAL_I REG_SVAL_I_SHADOW
21102 #define R_SYNC_SERIAL3_TR_WORD__TYPECAST REG_TYPECAST_UWORD
21103 #define R_SYNC_SERIAL3_TR_WORD__TYPE (REG_UWORD)
21104 #define R_SYNC_SERIAL3_TR_WORD__GET REG_GET_WO
21105 #define R_SYNC_SERIAL3_TR_WORD__IGET REG_IGET_WO
21106 #define R_SYNC_SERIAL3_TR_WORD__SET REG_SET_WO
21107 #define R_SYNC_SERIAL3_TR_WORD__ISET REG_ISET_WO
21108 #define R_SYNC_SERIAL3_TR_WORD__SET_VAL REG_SET_VAL_WO
21109 #define R_SYNC_SERIAL3_TR_WORD__EQL REG_EQL_WO
21110 #define R_SYNC_SERIAL3_TR_WORD__IEQL REG_IEQL_WO
21111 #define R_SYNC_SERIAL3_TR_WORD__RD REG_RD_WO
21112 #define R_SYNC_SERIAL3_TR_WORD__IRD REG_IRD_WO
21113 #define R_SYNC_SERIAL3_TR_WORD__WR REG_WR_WO
21114 #define R_SYNC_SERIAL3_TR_WORD__IWR REG_IWR_WO
21115
21116 #define R_SYNC_SERIAL3_TR_WORD__WRITE(addr,value) \
21117 (*(addr) = (value))
21118
21119 #define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__MASK 0x0000ffffU
21120
21121 #define R_SYNC_SERIAL3_TR_WORD__data_out__MAX 0xffff
21122
21123 #define R_SYNC_SERIAL3_TR_WORD__data_out__MIN 0
21124
21125 #define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
21126
21127 #define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__VAL REG_VAL_VAL
21128
21129
21130 #endif
21131
21132 /*
21133 * R_SYNC_SERIAL_PRESCALE
21134 * - type: WO
21135 * - addr: 0xb00000f4
21136 * - group: Timer registers
21137 */
21138
21139 #if USE_GROUP__Timer_registers
21140
21141 #define R_SYNC_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f4)
21142
21143 #ifndef REG_NO_SHADOW
21144 #define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SYNC_SERIAL_PRESCALE + 0))
21145 #define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SYNC_SERIAL_PRESCALE + 0))
21146 #else /* REG_NO_SHADOW */
21147 #define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
21148 #define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
21149 #endif /* REG_NO_SHADOW */
21150
21151 #define R_SYNC_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UDWORD
21152 #define R_SYNC_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW
21153 #define R_SYNC_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
21154 #define R_SYNC_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UDWORD
21155 #define R_SYNC_SERIAL_PRESCALE__TYPE (REG_UDWORD)
21156 #define R_SYNC_SERIAL_PRESCALE__GET REG_GET_WO
21157 #define R_SYNC_SERIAL_PRESCALE__IGET REG_IGET_WO
21158 #define R_SYNC_SERIAL_PRESCALE__SET REG_SET_WO
21159 #define R_SYNC_SERIAL_PRESCALE__ISET REG_ISET_WO
21160 #define R_SYNC_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO
21161 #define R_SYNC_SERIAL_PRESCALE__EQL REG_EQL_WO
21162 #define R_SYNC_SERIAL_PRESCALE__IEQL REG_IEQL_WO
21163 #define R_SYNC_SERIAL_PRESCALE__RD REG_RD_WO
21164 #define R_SYNC_SERIAL_PRESCALE__IRD REG_IRD_WO
21165 #define R_SYNC_SERIAL_PRESCALE__WR REG_WR_WO
21166 #define R_SYNC_SERIAL_PRESCALE__IWR REG_IWR_WO
21167
21168 #define R_SYNC_SERIAL_PRESCALE__WRITE(addr,value) \
21169 (*(addr) = (value))
21170
21171 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__MASK 0x00800000U
21172 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__MASK 0x00400000U
21173 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__MASK 0x00200000U
21174 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__MASK 0x00100000U
21175 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__MASK 0x00070000U
21176 #define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__MASK 0x00008000U
21177 #define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__MASK 0x00007800U
21178 #define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__MASK 0x000003ffU
21179
21180 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MAX 0x1
21181 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MAX 0x1
21182 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MAX 0x1
21183 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MAX 0x1
21184 #define R_SYNC_SERIAL_PRESCALE__prescaler__MAX 0x7
21185 #define R_SYNC_SERIAL_PRESCALE__warp_mode__MAX 0x1
21186 #define R_SYNC_SERIAL_PRESCALE__frame_rate__MAX 0xf
21187 #define R_SYNC_SERIAL_PRESCALE__word_rate__MAX 0x3ff
21188
21189 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MIN 0
21190 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MIN 0
21191 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MIN 0
21192 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MIN 0
21193 #define R_SYNC_SERIAL_PRESCALE__prescaler__MIN 0
21194 #define R_SYNC_SERIAL_PRESCALE__warp_mode__MIN 0
21195 #define R_SYNC_SERIAL_PRESCALE__frame_rate__MIN 0
21196 #define R_SYNC_SERIAL_PRESCALE__word_rate__MIN 0
21197
21198 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
21199 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
21200 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
21201 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
21202 #define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
21203 #define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
21204 #define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
21205 #define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
21206
21207 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__VAL REG_VAL_ENUM
21208 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__VAL REG_VAL_ENUM
21209 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__VAL REG_VAL_ENUM
21210 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__VAL REG_VAL_ENUM
21211 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__VAL REG_VAL_ENUM
21212 #define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__VAL REG_VAL_ENUM
21213 #define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__VAL REG_VAL_VAL
21214 #define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__VAL REG_VAL_VAL
21215
21216 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__baudrate 1
21217 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__codec 0
21218 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__external 0
21219 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__internal 1
21220 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__baudrate 1
21221 #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__codec 0
21222 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__external 0
21223 #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__internal 1
21224 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div1 0
21225 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div128 7
21226 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div16 4
21227 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div2 1
21228 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div32 5
21229 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div4 2
21230 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div64 6
21231 #define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div8 3
21232 #define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__enabled 1
21233 #define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__normal 0
21234
21235 #endif
21236
21237 /*
21238 * R_TEST_MODE
21239 * - type: WO
21240 * - addr: 0xb00000fc
21241 * - group: Test mode registers
21242 */
21243
21244 #if USE_GROUP__Test_mode_registers
21245
21246 #define R_TEST_MODE__ADDR (REG_TYPECAST_UDWORD 0xb00000fc)
21247
21248 #ifndef REG_NO_SHADOW
21249 #define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TEST_MODE + 0))
21250 #define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TEST_MODE + 0))
21251 #else /* REG_NO_SHADOW */
21252 #define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
21253 #define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
21254 #endif /* REG_NO_SHADOW */
21255
21256 #define R_TEST_MODE__STYPECAST REG_STYPECAST_UDWORD
21257 #define R_TEST_MODE__SVAL REG_SVAL_SHADOW
21258 #define R_TEST_MODE__SVAL_I REG_SVAL_I_SHADOW
21259 #define R_TEST_MODE__TYPECAST REG_TYPECAST_UDWORD
21260 #define R_TEST_MODE__TYPE (REG_UDWORD)
21261 #define R_TEST_MODE__GET REG_GET_WO
21262 #define R_TEST_MODE__IGET REG_IGET_WO
21263 #define R_TEST_MODE__SET REG_SET_WO
21264 #define R_TEST_MODE__ISET REG_ISET_WO
21265 #define R_TEST_MODE__SET_VAL REG_SET_VAL_WO
21266 #define R_TEST_MODE__EQL REG_EQL_WO
21267 #define R_TEST_MODE__IEQL REG_IEQL_WO
21268 #define R_TEST_MODE__RD REG_RD_WO
21269 #define R_TEST_MODE__IRD REG_IRD_WO
21270 #define R_TEST_MODE__WR REG_WR_WO
21271 #define R_TEST_MODE__IWR REG_IWR_WO
21272
21273 #define R_TEST_MODE__WRITE(addr,value) \
21274 (*(addr) = (value))
21275
21276 #define R_TEST_MODE__single_step__single_step__MASK 0x00080000U
21277 #define R_TEST_MODE__step_wr__step_wr__MASK 0x00040000U
21278 #define R_TEST_MODE__step_rd__step_rd__MASK 0x00020000U
21279 #define R_TEST_MODE__step_fetch__step_fetch__MASK 0x00010000U
21280 #define R_TEST_MODE__mmu_test__mmu_test__MASK 0x00001000U
21281 #define R_TEST_MODE__usb_test__usb_test__MASK 0x00000800U
21282 #define R_TEST_MODE__scsi_timer_test__scsi_timer_test__MASK 0x00000400U
21283 #define R_TEST_MODE__backoff__backoff__MASK 0x00000200U
21284 #define R_TEST_MODE__snmp_test__snmp_test__MASK 0x00000100U
21285 #define R_TEST_MODE__snmp_inc__snmp_inc__MASK 0x00000080U
21286 #define R_TEST_MODE__ser_loop__ser_loop__MASK 0x00000040U
21287 #define R_TEST_MODE__baudrate__baudrate__MASK 0x00000020U
21288 #define R_TEST_MODE__timer__timer__MASK 0x00000018U
21289 #define R_TEST_MODE__cache_test__cache_test__MASK 0x00000004U
21290 #define R_TEST_MODE__tag_test__tag_test__MASK 0x00000002U
21291 #define R_TEST_MODE__cache_enable__cache_enable__MASK 0x00000001U
21292
21293 #define R_TEST_MODE__single_step__MAX 0x1
21294 #define R_TEST_MODE__step_wr__MAX 0x1
21295 #define R_TEST_MODE__step_rd__MAX 0x1
21296 #define R_TEST_MODE__step_fetch__MAX 0x1
21297 #define R_TEST_MODE__mmu_test__MAX 0x1
21298 #define R_TEST_MODE__usb_test__MAX 0x1
21299 #define R_TEST_MODE__scsi_timer_test__MAX 0x1
21300 #define R_TEST_MODE__backoff__MAX 0x1
21301 #define R_TEST_MODE__snmp_test__MAX 0x1
21302 #define R_TEST_MODE__snmp_inc__MAX 0x1
21303 #define R_TEST_MODE__ser_loop__MAX 0x1
21304 #define R_TEST_MODE__baudrate__MAX 0x1
21305 #define R_TEST_MODE__timer__MAX 0x3
21306 #define R_TEST_MODE__cache_test__MAX 0x1
21307 #define R_TEST_MODE__tag_test__MAX 0x1
21308 #define R_TEST_MODE__cache_enable__MAX 0x1
21309
21310 #define R_TEST_MODE__single_step__MIN 0
21311 #define R_TEST_MODE__step_wr__MIN 0
21312 #define R_TEST_MODE__step_rd__MIN 0
21313 #define R_TEST_MODE__step_fetch__MIN 0
21314 #define R_TEST_MODE__mmu_test__MIN 0
21315 #define R_TEST_MODE__usb_test__MIN 0
21316 #define R_TEST_MODE__scsi_timer_test__MIN 0
21317 #define R_TEST_MODE__backoff__MIN 0
21318 #define R_TEST_MODE__snmp_test__MIN 0
21319 #define R_TEST_MODE__snmp_inc__MIN 0
21320 #define R_TEST_MODE__ser_loop__MIN 0
21321 #define R_TEST_MODE__baudrate__MIN 0
21322 #define R_TEST_MODE__timer__MIN 0
21323 #define R_TEST_MODE__cache_test__MIN 0
21324 #define R_TEST_MODE__tag_test__MIN 0
21325 #define R_TEST_MODE__cache_enable__MIN 0
21326
21327 #define R_TEST_MODE__single_step__BITNR 19
21328 #define R_TEST_MODE__step_wr__BITNR 18
21329 #define R_TEST_MODE__step_rd__BITNR 17
21330 #define R_TEST_MODE__step_fetch__BITNR 16
21331 #define R_TEST_MODE__mmu_test__BITNR 12
21332 #define R_TEST_MODE__usb_test__BITNR 11
21333 #define R_TEST_MODE__scsi_timer_test__BITNR 10
21334 #define R_TEST_MODE__backoff__BITNR 9
21335 #define R_TEST_MODE__snmp_test__BITNR 8
21336 #define R_TEST_MODE__snmp_inc__BITNR 7
21337 #define R_TEST_MODE__ser_loop__BITNR 6
21338 #define R_TEST_MODE__baudrate__BITNR 5
21339 #define R_TEST_MODE__timer__BITNR 3
21340 #define R_TEST_MODE__cache_test__BITNR 2
21341 #define R_TEST_MODE__tag_test__BITNR 1
21342 #define R_TEST_MODE__cache_enable__BITNR 0
21343
21344 #define R_TEST_MODE__single_step__single_step__VAL REG_VAL_ENUM
21345 #define R_TEST_MODE__step_wr__step_wr__VAL REG_VAL_ENUM
21346 #define R_TEST_MODE__step_rd__step_rd__VAL REG_VAL_ENUM
21347 #define R_TEST_MODE__step_fetch__step_fetch__VAL REG_VAL_ENUM
21348 #define R_TEST_MODE__mmu_test__mmu_test__VAL REG_VAL_ENUM
21349 #define R_TEST_MODE__usb_test__usb_test__VAL REG_VAL_ENUM
21350 #define R_TEST_MODE__scsi_timer_test__scsi_timer_test__VAL REG_VAL_ENUM
21351 #define R_TEST_MODE__backoff__backoff__VAL REG_VAL_ENUM
21352 #define R_TEST_MODE__snmp_test__snmp_test__VAL REG_VAL_ENUM
21353 #define R_TEST_MODE__snmp_inc__snmp_inc__VAL REG_VAL_ENUM
21354 #define R_TEST_MODE__ser_loop__ser_loop__VAL REG_VAL_ENUM
21355 #define R_TEST_MODE__baudrate__baudrate__VAL REG_VAL_ENUM
21356 #define R_TEST_MODE__timer__timer__VAL REG_VAL_ENUM
21357 #define R_TEST_MODE__cache_test__cache_test__VAL REG_VAL_ENUM
21358 #define R_TEST_MODE__tag_test__tag_test__VAL REG_VAL_ENUM
21359 #define R_TEST_MODE__cache_enable__cache_enable__VAL REG_VAL_ENUM
21360
21361 #define R_TEST_MODE__single_step__single_step__off 0
21362 #define R_TEST_MODE__single_step__single_step__on 1
21363 #define R_TEST_MODE__step_wr__step_wr__off 0
21364 #define R_TEST_MODE__step_wr__step_wr__on 1
21365 #define R_TEST_MODE__step_rd__step_rd__off 0
21366 #define R_TEST_MODE__step_rd__step_rd__on 1
21367 #define R_TEST_MODE__step_fetch__step_fetch__off 0
21368 #define R_TEST_MODE__step_fetch__step_fetch__on 1
21369 #define R_TEST_MODE__mmu_test__mmu_test__off 0
21370 #define R_TEST_MODE__mmu_test__mmu_test__on 1
21371 #define R_TEST_MODE__usb_test__usb_test__off 0
21372 #define R_TEST_MODE__usb_test__usb_test__on 1
21373 #define R_TEST_MODE__scsi_timer_test__scsi_timer_test__off 0
21374 #define R_TEST_MODE__scsi_timer_test__scsi_timer_test__on 1
21375 #define R_TEST_MODE__backoff__backoff__off 0
21376 #define R_TEST_MODE__backoff__backoff__on 1
21377 #define R_TEST_MODE__snmp_test__snmp_test__off 0
21378 #define R_TEST_MODE__snmp_test__snmp_test__on 1
21379 #define R_TEST_MODE__snmp_inc__snmp_inc__do 1
21380 #define R_TEST_MODE__snmp_inc__snmp_inc__dont 0
21381 #define R_TEST_MODE__ser_loop__ser_loop__off 0
21382 #define R_TEST_MODE__ser_loop__ser_loop__on 1
21383 #define R_TEST_MODE__baudrate__baudrate__off 0
21384 #define R_TEST_MODE__baudrate__baudrate__on 1
21385 #define R_TEST_MODE__timer__timer__all 3
21386 #define R_TEST_MODE__timer__timer__even 1
21387 #define R_TEST_MODE__timer__timer__odd 2
21388 #define R_TEST_MODE__timer__timer__off 0
21389 #define R_TEST_MODE__cache_test__cache_test__normal 0
21390 #define R_TEST_MODE__cache_test__cache_test__test 1
21391 #define R_TEST_MODE__tag_test__tag_test__normal 0
21392 #define R_TEST_MODE__tag_test__tag_test__test 1
21393 #define R_TEST_MODE__cache_enable__cache_enable__disable 0
21394 #define R_TEST_MODE__cache_enable__cache_enable__enable 1
21395
21396 #endif
21397
21398 /*
21399 * R_TIMER01_DATA
21400 * - type: RO
21401 * - addr: 0xb0000022
21402 * - group: Timer registers
21403 */
21404
21405 #if USE_GROUP__Timer_registers
21406
21407 #define R_TIMER01_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000022)
21408 #define R_TIMER01_DATA__SVAL REG_SVAL_SHADOW
21409 #define R_TIMER01_DATA__SVAL_I REG_SVAL_I_SHADOW
21410 #define R_TIMER01_DATA__TYPECAST REG_TYPECAST_UWORD
21411 #define R_TIMER01_DATA__TYPE (REG_UWORD)
21412 #define R_TIMER01_DATA__GET REG_GET_RO
21413 #define R_TIMER01_DATA__IGET REG_IGET_RO
21414 #define R_TIMER01_DATA__SET REG_SET_RO
21415 #define R_TIMER01_DATA__ISET REG_ISET_RO
21416 #define R_TIMER01_DATA__SET_VAL REG_SET_VAL_RO
21417 #define R_TIMER01_DATA__EQL REG_EQL_RO
21418 #define R_TIMER01_DATA__IEQL REG_IEQL_RO
21419 #define R_TIMER01_DATA__RD REG_RD_RO
21420 #define R_TIMER01_DATA__IRD REG_IRD_RO
21421 #define R_TIMER01_DATA__WR REG_WR_RO
21422 #define R_TIMER01_DATA__IWR REG_IWR_RO
21423
21424 #define R_TIMER01_DATA__READ(addr) \
21425 (*(addr))
21426
21427 #define R_TIMER01_DATA__count__count__MASK 0x0000ffffU
21428
21429 #define R_TIMER01_DATA__count__MAX 0xffff
21430
21431 #define R_TIMER01_DATA__count__MIN 0
21432
21433 #define R_TIMER01_DATA__count__BITNR 0
21434
21435 #define R_TIMER01_DATA__count__count__VAL REG_VAL_VAL
21436
21437
21438 #endif
21439
21440 /*
21441 * R_TIMER0_DATA
21442 * - type: RO
21443 * - addr: 0xb0000022
21444 * - group: Timer registers
21445 */
21446
21447 #if USE_GROUP__Timer_registers
21448
21449 #define R_TIMER0_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000022)
21450 #define R_TIMER0_DATA__SVAL REG_SVAL_SHADOW
21451 #define R_TIMER0_DATA__SVAL_I REG_SVAL_I_SHADOW
21452 #define R_TIMER0_DATA__TYPECAST REG_TYPECAST_BYTE
21453 #define R_TIMER0_DATA__TYPE (REG_BYTE)
21454 #define R_TIMER0_DATA__GET REG_GET_RO
21455 #define R_TIMER0_DATA__IGET REG_IGET_RO
21456 #define R_TIMER0_DATA__SET REG_SET_RO
21457 #define R_TIMER0_DATA__ISET REG_ISET_RO
21458 #define R_TIMER0_DATA__SET_VAL REG_SET_VAL_RO
21459 #define R_TIMER0_DATA__EQL REG_EQL_RO
21460 #define R_TIMER0_DATA__IEQL REG_IEQL_RO
21461 #define R_TIMER0_DATA__RD REG_RD_RO
21462 #define R_TIMER0_DATA__IRD REG_IRD_RO
21463 #define R_TIMER0_DATA__WR REG_WR_RO
21464 #define R_TIMER0_DATA__IWR REG_IWR_RO
21465
21466 #define R_TIMER0_DATA__READ(addr) \
21467 (*(addr))
21468
21469 #define R_TIMER0_DATA__count__count__MASK 0x000000ffU
21470
21471 #define R_TIMER0_DATA__count__MAX 0xff
21472
21473 #define R_TIMER0_DATA__count__MIN 0
21474
21475 #define R_TIMER0_DATA__count__BITNR 0
21476
21477 #define R_TIMER0_DATA__count__count__VAL REG_VAL_VAL
21478
21479
21480 #endif
21481
21482 /*
21483 * R_TIMER1_DATA
21484 * - type: RO
21485 * - addr: 0xb0000023
21486 * - group: Timer registers
21487 */
21488
21489 #if USE_GROUP__Timer_registers
21490
21491 #define R_TIMER1_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000023)
21492 #define R_TIMER1_DATA__SVAL REG_SVAL_SHADOW
21493 #define R_TIMER1_DATA__SVAL_I REG_SVAL_I_SHADOW
21494 #define R_TIMER1_DATA__TYPECAST REG_TYPECAST_BYTE
21495 #define R_TIMER1_DATA__TYPE (REG_BYTE)
21496 #define R_TIMER1_DATA__GET REG_GET_RO
21497 #define R_TIMER1_DATA__IGET REG_IGET_RO
21498 #define R_TIMER1_DATA__SET REG_SET_RO
21499 #define R_TIMER1_DATA__ISET REG_ISET_RO
21500 #define R_TIMER1_DATA__SET_VAL REG_SET_VAL_RO
21501 #define R_TIMER1_DATA__EQL REG_EQL_RO
21502 #define R_TIMER1_DATA__IEQL REG_IEQL_RO
21503 #define R_TIMER1_DATA__RD REG_RD_RO
21504 #define R_TIMER1_DATA__IRD REG_IRD_RO
21505 #define R_TIMER1_DATA__WR REG_WR_RO
21506 #define R_TIMER1_DATA__IWR REG_IWR_RO
21507
21508 #define R_TIMER1_DATA__READ(addr) \
21509 (*(addr))
21510
21511 #define R_TIMER1_DATA__count__count__MASK 0x000000ffU
21512
21513 #define R_TIMER1_DATA__count__MAX 0xff
21514
21515 #define R_TIMER1_DATA__count__MIN 0
21516
21517 #define R_TIMER1_DATA__count__BITNR 0
21518
21519 #define R_TIMER1_DATA__count__count__VAL REG_VAL_VAL
21520
21521
21522 #endif
21523
21524 /*
21525 * R_TIMER_CTRL
21526 * - type: WO
21527 * - addr: 0xb0000020
21528 * - group: Timer registers
21529 */
21530
21531 #if USE_GROUP__Timer_registers
21532
21533 #define R_TIMER_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000020)
21534
21535 #ifndef REG_NO_SHADOW
21536 #define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TIMER_CTRL + 0))
21537 #define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TIMER_CTRL + 0))
21538 #else /* REG_NO_SHADOW */
21539 #define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
21540 #define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
21541 #endif /* REG_NO_SHADOW */
21542
21543 #define R_TIMER_CTRL__STYPECAST REG_STYPECAST_UDWORD
21544 #define R_TIMER_CTRL__SVAL REG_SVAL_SHADOW
21545 #define R_TIMER_CTRL__SVAL_I REG_SVAL_I_SHADOW
21546 #define R_TIMER_CTRL__TYPECAST REG_TYPECAST_UDWORD
21547 #define R_TIMER_CTRL__TYPE (REG_UDWORD)
21548 #define R_TIMER_CTRL__GET REG_GET_WO
21549 #define R_TIMER_CTRL__IGET REG_IGET_WO
21550 #define R_TIMER_CTRL__SET REG_SET_WO
21551 #define R_TIMER_CTRL__ISET REG_ISET_WO
21552 #define R_TIMER_CTRL__SET_VAL REG_SET_VAL_WO
21553 #define R_TIMER_CTRL__EQL REG_EQL_WO
21554 #define R_TIMER_CTRL__IEQL REG_IEQL_WO
21555 #define R_TIMER_CTRL__RD REG_RD_WO
21556 #define R_TIMER_CTRL__IRD REG_IRD_WO
21557 #define R_TIMER_CTRL__WR REG_WR_WO
21558 #define R_TIMER_CTRL__IWR REG_IWR_WO
21559
21560 #define R_TIMER_CTRL__WRITE(addr,value) \
21561 (*(addr) = (value))
21562
21563 #define R_TIMER_CTRL__timerdiv1__timerdiv1__MASK 0xff000000U
21564 #define R_TIMER_CTRL__timerdiv0__timerdiv0__MASK 0x00ff0000U
21565 #define R_TIMER_CTRL__presc_timer1__presc_timer1__MASK 0x00008000U
21566 #define R_TIMER_CTRL__i1__i1__MASK 0x00004000U
21567 #define R_TIMER_CTRL__tm1__tm1__MASK 0x00003000U
21568 #define R_TIMER_CTRL__clksel1__clksel1__MASK 0x00000f00U
21569 #define R_TIMER_CTRL__presc_ext__presc_ext__MASK 0x00000080U
21570 #define R_TIMER_CTRL__i0__i0__MASK 0x00000040U
21571 #define R_TIMER_CTRL__tm0__tm0__MASK 0x00000030U
21572 #define R_TIMER_CTRL__clksel0__clksel0__MASK 0x0000000fU
21573
21574 #define R_TIMER_CTRL__timerdiv1__MAX 0xff
21575 #define R_TIMER_CTRL__timerdiv0__MAX 0xff
21576 #define R_TIMER_CTRL__presc_timer1__MAX 0x1
21577 #define R_TIMER_CTRL__i1__MAX 0x1
21578 #define R_TIMER_CTRL__tm1__MAX 0x3
21579 #define R_TIMER_CTRL__clksel1__MAX 0xf
21580 #define R_TIMER_CTRL__presc_ext__MAX 0x1
21581 #define R_TIMER_CTRL__i0__MAX 0x1
21582 #define R_TIMER_CTRL__tm0__MAX 0x3
21583 #define R_TIMER_CTRL__clksel0__MAX 0xf
21584
21585 #define R_TIMER_CTRL__timerdiv1__MIN 0
21586 #define R_TIMER_CTRL__timerdiv0__MIN 0
21587 #define R_TIMER_CTRL__presc_timer1__MIN 0
21588 #define R_TIMER_CTRL__i1__MIN 0
21589 #define R_TIMER_CTRL__tm1__MIN 0
21590 #define R_TIMER_CTRL__clksel1__MIN 0
21591 #define R_TIMER_CTRL__presc_ext__MIN 0
21592 #define R_TIMER_CTRL__i0__MIN 0
21593 #define R_TIMER_CTRL__tm0__MIN 0
21594 #define R_TIMER_CTRL__clksel0__MIN 0
21595
21596 #define R_TIMER_CTRL__timerdiv1__BITNR 24
21597 #define R_TIMER_CTRL__timerdiv0__BITNR 16
21598 #define R_TIMER_CTRL__presc_timer1__BITNR 15
21599 #define R_TIMER_CTRL__i1__BITNR 14
21600 #define R_TIMER_CTRL__tm1__BITNR 12
21601 #define R_TIMER_CTRL__clksel1__BITNR 8
21602 #define R_TIMER_CTRL__presc_ext__BITNR 7
21603 #define R_TIMER_CTRL__i0__BITNR 6
21604 #define R_TIMER_CTRL__tm0__BITNR 4
21605 #define R_TIMER_CTRL__clksel0__BITNR 0
21606
21607 #define R_TIMER_CTRL__timerdiv1__timerdiv1__VAL REG_VAL_VAL
21608 #define R_TIMER_CTRL__timerdiv0__timerdiv0__VAL REG_VAL_VAL
21609 #define R_TIMER_CTRL__presc_timer1__presc_timer1__VAL REG_VAL_ENUM
21610 #define R_TIMER_CTRL__i1__i1__VAL REG_VAL_ENUM
21611 #define R_TIMER_CTRL__tm1__tm1__VAL REG_VAL_ENUM
21612 #define R_TIMER_CTRL__clksel1__clksel1__VAL REG_VAL_ENUM
21613 #define R_TIMER_CTRL__presc_ext__presc_ext__VAL REG_VAL_ENUM
21614 #define R_TIMER_CTRL__i0__i0__VAL REG_VAL_ENUM
21615 #define R_TIMER_CTRL__tm0__tm0__VAL REG_VAL_ENUM
21616 #define R_TIMER_CTRL__clksel0__clksel0__VAL REG_VAL_ENUM
21617
21618 #define R_TIMER_CTRL__presc_timer1__presc_timer1__normal 0
21619 #define R_TIMER_CTRL__presc_timer1__presc_timer1__prescale 1
21620 #define R_TIMER_CTRL__i1__i1__clr 1
21621 #define R_TIMER_CTRL__i1__i1__nop 0
21622 #define R_TIMER_CTRL__tm1__tm1__freeze 1
21623 #define R_TIMER_CTRL__tm1__tm1__run 2
21624 #define R_TIMER_CTRL__tm1__tm1__stop_ld 0
21625 #define R_TIMER_CTRL__clksel1__clksel1__c115k2Hz 9
21626 #define R_TIMER_CTRL__clksel1__clksel1__c1200Hz 2
21627 #define R_TIMER_CTRL__clksel1__clksel1__c1843k2Hz 13
21628 #define R_TIMER_CTRL__clksel1__clksel1__c19k2Hz 6
21629 #define R_TIMER_CTRL__clksel1__clksel1__c230k4Hz 10
21630 #define R_TIMER_CTRL__clksel1__clksel1__c2400Hz 3
21631 #define R_TIMER_CTRL__clksel1__clksel1__c300Hz 0
21632 #define R_TIMER_CTRL__clksel1__clksel1__c38k4Hz 7
21633 #define R_TIMER_CTRL__clksel1__clksel1__c460k8Hz 11
21634 #define R_TIMER_CTRL__clksel1__clksel1__c4800Hz 4
21635 #define R_TIMER_CTRL__clksel1__clksel1__c57k6Hz 8
21636 #define R_TIMER_CTRL__clksel1__clksel1__c600Hz 1
21637 #define R_TIMER_CTRL__clksel1__clksel1__c6250kHz 14
21638 #define R_TIMER_CTRL__clksel1__clksel1__c921k6Hz 12
21639 #define R_TIMER_CTRL__clksel1__clksel1__c9600Hz 5
21640 #define R_TIMER_CTRL__clksel1__clksel1__cascade0 15
21641 #define R_TIMER_CTRL__presc_ext__presc_ext__external 1
21642 #define R_TIMER_CTRL__presc_ext__presc_ext__prescale 0
21643 #define R_TIMER_CTRL__i0__i0__clr 1
21644 #define R_TIMER_CTRL__i0__i0__nop 0
21645 #define R_TIMER_CTRL__tm0__tm0__freeze 1
21646 #define R_TIMER_CTRL__tm0__tm0__run 2
21647 #define R_TIMER_CTRL__tm0__tm0__stop_ld 0
21648 #define R_TIMER_CTRL__clksel0__clksel0__c115k2Hz 9
21649 #define R_TIMER_CTRL__clksel0__clksel0__c1200Hz 2
21650 #define R_TIMER_CTRL__clksel0__clksel0__c1843k2Hz 13
21651 #define R_TIMER_CTRL__clksel0__clksel0__c19k2Hz 6
21652 #define R_TIMER_CTRL__clksel0__clksel0__c230k4Hz 10
21653 #define R_TIMER_CTRL__clksel0__clksel0__c2400Hz 3
21654 #define R_TIMER_CTRL__clksel0__clksel0__c300Hz 0
21655 #define R_TIMER_CTRL__clksel0__clksel0__c38k4Hz 7
21656 #define R_TIMER_CTRL__clksel0__clksel0__c460k8Hz 11
21657 #define R_TIMER_CTRL__clksel0__clksel0__c4800Hz 4
21658 #define R_TIMER_CTRL__clksel0__clksel0__c57k6Hz 8
21659 #define R_TIMER_CTRL__clksel0__clksel0__c600Hz 1
21660 #define R_TIMER_CTRL__clksel0__clksel0__c6250kHz 14
21661 #define R_TIMER_CTRL__clksel0__clksel0__c921k6Hz 12
21662 #define R_TIMER_CTRL__clksel0__clksel0__c9600Hz 5
21663 #define R_TIMER_CTRL__clksel0__clksel0__flexible 15
21664
21665 #endif
21666
21667 /*
21668 * R_TIMER_DATA
21669 * - type: RO
21670 * - addr: 0xb0000020
21671 * - group: Timer registers
21672 */
21673
21674 #if USE_GROUP__Timer_registers
21675
21676 #define R_TIMER_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000020)
21677 #define R_TIMER_DATA__SVAL REG_SVAL_SHADOW
21678 #define R_TIMER_DATA__SVAL_I REG_SVAL_I_SHADOW
21679 #define R_TIMER_DATA__TYPECAST REG_TYPECAST_UDWORD
21680 #define R_TIMER_DATA__TYPE (REG_UDWORD)
21681 #define R_TIMER_DATA__GET REG_GET_RO
21682 #define R_TIMER_DATA__IGET REG_IGET_RO
21683 #define R_TIMER_DATA__SET REG_SET_RO
21684 #define R_TIMER_DATA__ISET REG_ISET_RO
21685 #define R_TIMER_DATA__SET_VAL REG_SET_VAL_RO
21686 #define R_TIMER_DATA__EQL REG_EQL_RO
21687 #define R_TIMER_DATA__IEQL REG_IEQL_RO
21688 #define R_TIMER_DATA__RD REG_RD_RO
21689 #define R_TIMER_DATA__IRD REG_IRD_RO
21690 #define R_TIMER_DATA__WR REG_WR_RO
21691 #define R_TIMER_DATA__IWR REG_IWR_RO
21692
21693 #define R_TIMER_DATA__READ(addr) \
21694 (*(addr))
21695
21696 #define R_TIMER_DATA__timer1__timer1__MASK 0xff000000U
21697 #define R_TIMER_DATA__timer0__timer0__MASK 0x00ff0000U
21698 #define R_TIMER_DATA__clkdiv_high__clkdiv_high__MASK 0x0000ff00U
21699 #define R_TIMER_DATA__clkdiv_low__clkdiv_low__MASK 0x000000ffU
21700
21701 #define R_TIMER_DATA__timer1__MAX 0xff
21702 #define R_TIMER_DATA__timer0__MAX 0xff
21703 #define R_TIMER_DATA__clkdiv_high__MAX 0xff
21704 #define R_TIMER_DATA__clkdiv_low__MAX 0xff
21705
21706 #define R_TIMER_DATA__timer1__MIN 0
21707 #define R_TIMER_DATA__timer0__MIN 0
21708 #define R_TIMER_DATA__clkdiv_high__MIN 0
21709 #define R_TIMER_DATA__clkdiv_low__MIN 0
21710
21711 #define R_TIMER_DATA__timer1__BITNR 24
21712 #define R_TIMER_DATA__timer0__BITNR 16
21713 #define R_TIMER_DATA__clkdiv_high__BITNR 8
21714 #define R_TIMER_DATA__clkdiv_low__BITNR 0
21715
21716 #define R_TIMER_DATA__timer1__timer1__VAL REG_VAL_VAL
21717 #define R_TIMER_DATA__timer0__timer0__VAL REG_VAL_VAL
21718 #define R_TIMER_DATA__clkdiv_high__clkdiv_high__VAL REG_VAL_VAL
21719 #define R_TIMER_DATA__clkdiv_low__clkdiv_low__VAL REG_VAL_VAL
21720
21721
21722 #endif
21723
21724 /*
21725 * R_TIMER_PRESCALE
21726 * - type: WO
21727 * - addr: 0xb00000f0
21728 * - group: Timer registers
21729 */
21730
21731 #if USE_GROUP__Timer_registers
21732
21733 #define R_TIMER_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f0)
21734
21735 #ifndef REG_NO_SHADOW
21736 #define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0))
21737 #define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0))
21738 #else /* REG_NO_SHADOW */
21739 #define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
21740 #define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
21741 #endif /* REG_NO_SHADOW */
21742
21743 #define R_TIMER_PRESCALE__STYPECAST REG_STYPECAST_UWORD
21744 #define R_TIMER_PRESCALE__SVAL REG_SVAL_SHADOW
21745 #define R_TIMER_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
21746 #define R_TIMER_PRESCALE__TYPECAST REG_TYPECAST_UWORD
21747 #define R_TIMER_PRESCALE__TYPE (REG_UWORD)
21748 #define R_TIMER_PRESCALE__GET REG_GET_WO
21749 #define R_TIMER_PRESCALE__IGET REG_IGET_WO
21750 #define R_TIMER_PRESCALE__SET REG_SET_WO
21751 #define R_TIMER_PRESCALE__ISET REG_ISET_WO
21752 #define R_TIMER_PRESCALE__SET_VAL REG_SET_VAL_WO
21753 #define R_TIMER_PRESCALE__EQL REG_EQL_WO
21754 #define R_TIMER_PRESCALE__IEQL REG_IEQL_WO
21755 #define R_TIMER_PRESCALE__RD REG_RD_WO
21756 #define R_TIMER_PRESCALE__IRD REG_IRD_WO
21757 #define R_TIMER_PRESCALE__WR REG_WR_WO
21758 #define R_TIMER_PRESCALE__IWR REG_IWR_WO
21759
21760 #define R_TIMER_PRESCALE__WRITE(addr,value) \
21761 (*(addr) = (value))
21762
21763 #define R_TIMER_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU
21764
21765 #define R_TIMER_PRESCALE__tim_presc__MAX 0xffff
21766
21767 #define R_TIMER_PRESCALE__tim_presc__MIN 0
21768
21769 #define R_TIMER_PRESCALE__tim_presc__BITNR 0
21770
21771 #define R_TIMER_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL
21772
21773
21774 #endif
21775
21776 /*
21777 * R_TIM_PRESC_STATUS
21778 * - type: RO
21779 * - addr: 0xb00000f0
21780 * - group: Timer registers
21781 */
21782
21783 #if USE_GROUP__Timer_registers
21784
21785 #define R_TIM_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f0)
21786 #define R_TIM_PRESC_STATUS__SVAL REG_SVAL_SHADOW
21787 #define R_TIM_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW
21788 #define R_TIM_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD
21789 #define R_TIM_PRESC_STATUS__TYPE (REG_UWORD)
21790 #define R_TIM_PRESC_STATUS__GET REG_GET_RO
21791 #define R_TIM_PRESC_STATUS__IGET REG_IGET_RO
21792 #define R_TIM_PRESC_STATUS__SET REG_SET_RO
21793 #define R_TIM_PRESC_STATUS__ISET REG_ISET_RO
21794 #define R_TIM_PRESC_STATUS__SET_VAL REG_SET_VAL_RO
21795 #define R_TIM_PRESC_STATUS__EQL REG_EQL_RO
21796 #define R_TIM_PRESC_STATUS__IEQL REG_IEQL_RO
21797 #define R_TIM_PRESC_STATUS__RD REG_RD_RO
21798 #define R_TIM_PRESC_STATUS__IRD REG_IRD_RO
21799 #define R_TIM_PRESC_STATUS__WR REG_WR_RO
21800 #define R_TIM_PRESC_STATUS__IWR REG_IWR_RO
21801
21802 #define R_TIM_PRESC_STATUS__READ(addr) \
21803 (*(addr))
21804
21805 #define R_TIM_PRESC_STATUS__tim_status__tim_status__MASK 0x0000ffffU
21806
21807 #define R_TIM_PRESC_STATUS__tim_status__MAX 0xffff
21808
21809 #define R_TIM_PRESC_STATUS__tim_status__MIN 0
21810
21811 #define R_TIM_PRESC_STATUS__tim_status__BITNR 0
21812
21813 #define R_TIM_PRESC_STATUS__tim_status__tim_status__VAL REG_VAL_VAL
21814
21815
21816 #endif
21817
21818 /*
21819 * R_TLB_HI
21820 * - type: RW
21821 * - addr: 0xb000025c
21822 * - group: MMU registers
21823 */
21824
21825 #if USE_GROUP__MMU_registers
21826
21827 #define R_TLB_HI__ADDR (REG_TYPECAST_UDWORD 0xb000025c)
21828 #define R_TLB_HI__SVAL REG_SVAL_SHADOW
21829 #define R_TLB_HI__SVAL_I REG_SVAL_I_SHADOW
21830 #define R_TLB_HI__TYPECAST REG_TYPECAST_UDWORD
21831 #define R_TLB_HI__TYPE (REG_UDWORD)
21832 #define R_TLB_HI__GET REG_GET_RW
21833 #define R_TLB_HI__IGET REG_IGET_RW
21834 #define R_TLB_HI__SET REG_SET_RW
21835 #define R_TLB_HI__ISET REG_ISET_RW
21836 #define R_TLB_HI__SET_VAL REG_SET_VAL_RW
21837 #define R_TLB_HI__EQL REG_EQL_RW
21838 #define R_TLB_HI__IEQL REG_IEQL_RW
21839 #define R_TLB_HI__RD REG_RD_RW
21840 #define R_TLB_HI__IRD REG_IRD_RW
21841 #define R_TLB_HI__WR REG_WR_RW
21842 #define R_TLB_HI__IWR REG_IWR_RW
21843
21844 #define R_TLB_HI__WRITE(addr,value) \
21845 (*(addr) = (value))
21846 #define R_TLB_HI__READ(addr) \
21847 (*(addr))
21848
21849 #define R_TLB_HI__vpn__vpn__MASK 0xffffe000U
21850 #define R_TLB_HI__page_id__page_id__MASK 0x0000003fU
21851
21852 #define R_TLB_HI__vpn__MAX 0x7ffff
21853 #define R_TLB_HI__page_id__MAX 63
21854
21855 #define R_TLB_HI__vpn__MIN 0
21856 #define R_TLB_HI__page_id__MIN 0
21857
21858 #define R_TLB_HI__vpn__BITNR 13
21859 #define R_TLB_HI__page_id__BITNR 0
21860
21861 #define R_TLB_HI__vpn__vpn__VAL REG_VAL_VAL
21862 #define R_TLB_HI__page_id__page_id__VAL REG_VAL_VAL
21863
21864
21865 #endif
21866
21867 /*
21868 * R_TLB_LO
21869 * - type: RW
21870 * - addr: 0xb0000258
21871 * - group: MMU registers
21872 */
21873
21874 #if USE_GROUP__MMU_registers
21875
21876 #define R_TLB_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000258)
21877 #define R_TLB_LO__SVAL REG_SVAL_SHADOW
21878 #define R_TLB_LO__SVAL_I REG_SVAL_I_SHADOW
21879 #define R_TLB_LO__TYPECAST REG_TYPECAST_UDWORD
21880 #define R_TLB_LO__TYPE (REG_UDWORD)
21881 #define R_TLB_LO__GET REG_GET_RW
21882 #define R_TLB_LO__IGET REG_IGET_RW
21883 #define R_TLB_LO__SET REG_SET_RW
21884 #define R_TLB_LO__ISET REG_ISET_RW
21885 #define R_TLB_LO__SET_VAL REG_SET_VAL_RW
21886 #define R_TLB_LO__EQL REG_EQL_RW
21887 #define R_TLB_LO__IEQL REG_IEQL_RW
21888 #define R_TLB_LO__RD REG_RD_RW
21889 #define R_TLB_LO__IRD REG_IRD_RW
21890 #define R_TLB_LO__WR REG_WR_RW
21891 #define R_TLB_LO__IWR REG_IWR_RW
21892
21893 #define R_TLB_LO__WRITE(addr,value) \
21894 (*(addr) = (value))
21895 #define R_TLB_LO__READ(addr) \
21896 (*(addr))
21897
21898 #define R_TLB_LO__pfn__pfn__MASK 0xffffe000U
21899 #define R_TLB_LO__global__global__MASK 0x00000008U
21900 #define R_TLB_LO__valid__valid__MASK 0x00000004U
21901 #define R_TLB_LO__kernel__kernel__MASK 0x00000002U
21902 #define R_TLB_LO__we__we__MASK 0x00000001U
21903
21904 #define R_TLB_LO__pfn__MAX 0x7ffff
21905 #define R_TLB_LO__global__MAX 0x1
21906 #define R_TLB_LO__valid__MAX 0x1
21907 #define R_TLB_LO__kernel__MAX 0x1
21908 #define R_TLB_LO__we__MAX 0x1
21909
21910 #define R_TLB_LO__pfn__MIN 0
21911 #define R_TLB_LO__global__MIN 0
21912 #define R_TLB_LO__valid__MIN 0
21913 #define R_TLB_LO__kernel__MIN 0
21914 #define R_TLB_LO__we__MIN 0
21915
21916 #define R_TLB_LO__pfn__BITNR 13
21917 #define R_TLB_LO__global__BITNR 3
21918 #define R_TLB_LO__valid__BITNR 2
21919 #define R_TLB_LO__kernel__BITNR 1
21920 #define R_TLB_LO__we__BITNR 0
21921
21922 #define R_TLB_LO__pfn__pfn__VAL REG_VAL_VAL
21923 #define R_TLB_LO__global__global__VAL REG_VAL_ENUM
21924 #define R_TLB_LO__valid__valid__VAL REG_VAL_ENUM
21925 #define R_TLB_LO__kernel__kernel__VAL REG_VAL_ENUM
21926 #define R_TLB_LO__we__we__VAL REG_VAL_ENUM
21927
21928 #define R_TLB_LO__global__global__no 0
21929 #define R_TLB_LO__global__global__yes 1
21930 #define R_TLB_LO__valid__valid__no 0
21931 #define R_TLB_LO__valid__valid__yes 1
21932 #define R_TLB_LO__kernel__kernel__no 0
21933 #define R_TLB_LO__kernel__kernel__yes 1
21934 #define R_TLB_LO__we__we__no 0
21935 #define R_TLB_LO__we__we__yes 1
21936
21937 #endif
21938
21939 /*
21940 * R_TLB_SELECT
21941 * - type: RW
21942 * - addr: 0xb0000254
21943 * - group: MMU registers
21944 */
21945
21946 #if USE_GROUP__MMU_registers
21947
21948 #define R_TLB_SELECT__ADDR (REG_TYPECAST_BYTE 0xb0000254)
21949 #define R_TLB_SELECT__SVAL REG_SVAL_SHADOW
21950 #define R_TLB_SELECT__SVAL_I REG_SVAL_I_SHADOW
21951 #define R_TLB_SELECT__TYPECAST REG_TYPECAST_BYTE
21952 #define R_TLB_SELECT__TYPE (REG_BYTE)
21953 #define R_TLB_SELECT__GET REG_GET_RW
21954 #define R_TLB_SELECT__IGET REG_IGET_RW
21955 #define R_TLB_SELECT__SET REG_SET_RW
21956 #define R_TLB_SELECT__ISET REG_ISET_RW
21957 #define R_TLB_SELECT__SET_VAL REG_SET_VAL_RW
21958 #define R_TLB_SELECT__EQL REG_EQL_RW
21959 #define R_TLB_SELECT__IEQL REG_IEQL_RW
21960 #define R_TLB_SELECT__RD REG_RD_RW
21961 #define R_TLB_SELECT__IRD REG_IRD_RW
21962 #define R_TLB_SELECT__WR REG_WR_RW
21963 #define R_TLB_SELECT__IWR REG_IWR_RW
21964
21965 #define R_TLB_SELECT__WRITE(addr,value) \
21966 (*(addr) = (value))
21967 #define R_TLB_SELECT__READ(addr) \
21968 (*(addr))
21969
21970 #define R_TLB_SELECT__index__index__MASK 0x0000003fU
21971
21972 #define R_TLB_SELECT__index__MAX 63
21973
21974 #define R_TLB_SELECT__index__MIN 0
21975
21976 #define R_TLB_SELECT__index__BITNR 0
21977
21978 #define R_TLB_SELECT__index__index__VAL REG_VAL_VAL
21979
21980
21981 #endif
21982
21983 /*
21984 * R_TR_COUNTERS
21985 * - type: RO
21986 * - addr: 0xb00000a8
21987 * - group: Network interface registers
21988 */
21989
21990 #if USE_GROUP__Network_interface_registers
21991
21992 #define R_TR_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a8)
21993 #define R_TR_COUNTERS__SVAL REG_SVAL_SHADOW
21994 #define R_TR_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
21995 #define R_TR_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
21996 #define R_TR_COUNTERS__TYPE (REG_UDWORD)
21997 #define R_TR_COUNTERS__GET REG_GET_RO
21998 #define R_TR_COUNTERS__IGET REG_IGET_RO
21999 #define R_TR_COUNTERS__SET REG_SET_RO
22000 #define R_TR_COUNTERS__ISET REG_ISET_RO
22001 #define R_TR_COUNTERS__SET_VAL REG_SET_VAL_RO
22002 #define R_TR_COUNTERS__EQL REG_EQL_RO
22003 #define R_TR_COUNTERS__IEQL REG_IEQL_RO
22004 #define R_TR_COUNTERS__RD REG_RD_RO
22005 #define R_TR_COUNTERS__IRD REG_IRD_RO
22006 #define R_TR_COUNTERS__WR REG_WR_RO
22007 #define R_TR_COUNTERS__IWR REG_IWR_RO
22008
22009 #define R_TR_COUNTERS__READ(addr) \
22010 (*(addr))
22011
22012 #define R_TR_COUNTERS__deferred__deferred__MASK 0xff000000U
22013 #define R_TR_COUNTERS__late_col__late_col__MASK 0x00ff0000U
22014 #define R_TR_COUNTERS__multiple_col__multiple_col__MASK 0x0000ff00U
22015 #define R_TR_COUNTERS__single_col__single_col__MASK 0x000000ffU
22016
22017 #define R_TR_COUNTERS__deferred__MAX 0xff
22018 #define R_TR_COUNTERS__late_col__MAX 0xff
22019 #define R_TR_COUNTERS__multiple_col__MAX 0xff
22020 #define R_TR_COUNTERS__single_col__MAX 0xff
22021
22022 #define R_TR_COUNTERS__deferred__MIN 0
22023 #define R_TR_COUNTERS__late_col__MIN 0
22024 #define R_TR_COUNTERS__multiple_col__MIN 0
22025 #define R_TR_COUNTERS__single_col__MIN 0
22026
22027 #define R_TR_COUNTERS__deferred__BITNR 24
22028 #define R_TR_COUNTERS__late_col__BITNR 16
22029 #define R_TR_COUNTERS__multiple_col__BITNR 8
22030 #define R_TR_COUNTERS__single_col__BITNR 0
22031
22032 #define R_TR_COUNTERS__deferred__deferred__VAL REG_VAL_VAL
22033 #define R_TR_COUNTERS__late_col__late_col__VAL REG_VAL_VAL
22034 #define R_TR_COUNTERS__multiple_col__multiple_col__VAL REG_VAL_VAL
22035 #define R_TR_COUNTERS__single_col__single_col__VAL REG_VAL_VAL
22036
22037
22038 #endif
22039
22040 /*
22041 * R_USB_COMMAND
22042 * - type: RW
22043 * - addr: 0xb0000201
22044 * - group: USB interface control registers
22045 */
22046
22047 #if USE_GROUP__USB_interface_control_registers
22048
22049 #define R_USB_COMMAND__ADDR (REG_TYPECAST_BYTE 0xb0000201)
22050 #define R_USB_COMMAND__SVAL REG_SVAL_SHADOW
22051 #define R_USB_COMMAND__SVAL_I REG_SVAL_I_SHADOW
22052 #define R_USB_COMMAND__TYPECAST REG_TYPECAST_BYTE
22053 #define R_USB_COMMAND__TYPE (REG_BYTE)
22054 #define R_USB_COMMAND__GET REG_GET_RW
22055 #define R_USB_COMMAND__IGET REG_IGET_RW
22056 #define R_USB_COMMAND__SET REG_SET_RW
22057 #define R_USB_COMMAND__ISET REG_ISET_RW
22058 #define R_USB_COMMAND__SET_VAL REG_SET_VAL_RW
22059 #define R_USB_COMMAND__EQL REG_EQL_RW
22060 #define R_USB_COMMAND__IEQL REG_IEQL_RW
22061 #define R_USB_COMMAND__RD REG_RD_RW
22062 #define R_USB_COMMAND__IRD REG_IRD_RW
22063 #define R_USB_COMMAND__WR REG_WR_RW
22064 #define R_USB_COMMAND__IWR REG_IWR_RW
22065
22066 #define R_USB_COMMAND__WRITE(addr,value) \
22067 (*(addr) = (value))
22068 #define R_USB_COMMAND__READ(addr) \
22069 (*(addr))
22070
22071 #define R_USB_COMMAND__port_sel__port_sel__MASK 0x000000c0U
22072 #define R_USB_COMMAND__port_cmd__port_cmd__MASK 0x00000030U
22073 #define R_USB_COMMAND__busy__busy__MASK 0x00000008U
22074 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__MASK 0x00000007U
22075
22076 #define R_USB_COMMAND__port_sel__MAX 0x3
22077 #define R_USB_COMMAND__port_cmd__MAX 0x3
22078 #define R_USB_COMMAND__busy__MAX 0x1
22079 #define R_USB_COMMAND__ctrl_cmd__MAX 0x7
22080
22081 #define R_USB_COMMAND__port_sel__MIN 0
22082 #define R_USB_COMMAND__port_cmd__MIN 0
22083 #define R_USB_COMMAND__busy__MIN 0
22084 #define R_USB_COMMAND__ctrl_cmd__MIN 0
22085
22086 #define R_USB_COMMAND__port_sel__BITNR 6
22087 #define R_USB_COMMAND__port_cmd__BITNR 4
22088 #define R_USB_COMMAND__busy__BITNR 3
22089 #define R_USB_COMMAND__ctrl_cmd__BITNR 0
22090
22091 #define R_USB_COMMAND__port_sel__port_sel__VAL REG_VAL_ENUM
22092 #define R_USB_COMMAND__port_cmd__port_cmd__VAL REG_VAL_ENUM
22093 #define R_USB_COMMAND__busy__busy__VAL REG_VAL_ENUM
22094 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM
22095
22096 #define R_USB_COMMAND__port_sel__port_sel__both 3
22097 #define R_USB_COMMAND__port_sel__port_sel__nop 0
22098 #define R_USB_COMMAND__port_sel__port_sel__port1 1
22099 #define R_USB_COMMAND__port_sel__port_sel__port2 2
22100 #define R_USB_COMMAND__port_cmd__port_cmd__disable 1
22101 #define R_USB_COMMAND__port_cmd__port_cmd__reset 0
22102 #define R_USB_COMMAND__port_cmd__port_cmd__resume 3
22103 #define R_USB_COMMAND__port_cmd__port_cmd__suspend 2
22104 #define R_USB_COMMAND__busy__busy__no 0
22105 #define R_USB_COMMAND__busy__busy__yes 1
22106 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__deconfig 2
22107 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__dev_config 4
22108 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_config 3
22109 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_nop 5
22110 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_run 6
22111 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_stop 7
22112 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__nop 0
22113 #define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__reset 1
22114
22115 #endif
22116
22117 /*
22118 * R_USB_COMMAND_DEV
22119 * - type: RW
22120 * - addr: 0xb0000201
22121 * - group: USB interface control registers
22122 */
22123
22124 #if USE_GROUP__USB_interface_control_registers
22125
22126 #define R_USB_COMMAND_DEV__ADDR (REG_TYPECAST_BYTE 0xb0000201)
22127 #define R_USB_COMMAND_DEV__SVAL REG_SVAL_SHADOW
22128 #define R_USB_COMMAND_DEV__SVAL_I REG_SVAL_I_SHADOW
22129 #define R_USB_COMMAND_DEV__TYPECAST REG_TYPECAST_BYTE
22130 #define R_USB_COMMAND_DEV__TYPE (REG_BYTE)
22131 #define R_USB_COMMAND_DEV__GET REG_GET_RW
22132 #define R_USB_COMMAND_DEV__IGET REG_IGET_RW
22133 #define R_USB_COMMAND_DEV__SET REG_SET_RW
22134 #define R_USB_COMMAND_DEV__ISET REG_ISET_RW
22135 #define R_USB_COMMAND_DEV__SET_VAL REG_SET_VAL_RW
22136 #define R_USB_COMMAND_DEV__EQL REG_EQL_RW
22137 #define R_USB_COMMAND_DEV__IEQL REG_IEQL_RW
22138 #define R_USB_COMMAND_DEV__RD REG_RD_RW
22139 #define R_USB_COMMAND_DEV__IRD REG_IRD_RW
22140 #define R_USB_COMMAND_DEV__WR REG_WR_RW
22141 #define R_USB_COMMAND_DEV__IWR REG_IWR_RW
22142
22143 #define R_USB_COMMAND_DEV__WRITE(addr,value) \
22144 (*(addr) = (value))
22145 #define R_USB_COMMAND_DEV__READ(addr) \
22146 (*(addr))
22147
22148 #define R_USB_COMMAND_DEV__port_sel__port_sel__MASK 0x000000c0U
22149 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__MASK 0x00000030U
22150 #define R_USB_COMMAND_DEV__busy__busy__MASK 0x00000008U
22151 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__MASK 0x00000007U
22152
22153 #define R_USB_COMMAND_DEV__port_sel__MAX 0x3
22154 #define R_USB_COMMAND_DEV__port_cmd__MAX 0x3
22155 #define R_USB_COMMAND_DEV__busy__MAX 0x1
22156 #define R_USB_COMMAND_DEV__ctrl_cmd__MAX 0x7
22157
22158 #define R_USB_COMMAND_DEV__port_sel__MIN 0
22159 #define R_USB_COMMAND_DEV__port_cmd__MIN 0
22160 #define R_USB_COMMAND_DEV__busy__MIN 0
22161 #define R_USB_COMMAND_DEV__ctrl_cmd__MIN 0
22162
22163 #define R_USB_COMMAND_DEV__port_sel__BITNR 6
22164 #define R_USB_COMMAND_DEV__port_cmd__BITNR 4
22165 #define R_USB_COMMAND_DEV__busy__BITNR 3
22166 #define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
22167
22168 #define R_USB_COMMAND_DEV__port_sel__port_sel__VAL REG_VAL_ENUM
22169 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__VAL REG_VAL_ENUM
22170 #define R_USB_COMMAND_DEV__busy__busy__VAL REG_VAL_ENUM
22171 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM
22172
22173 #define R_USB_COMMAND_DEV__port_sel__port_sel__any 3
22174 #define R_USB_COMMAND_DEV__port_sel__port_sel__dummy1 1
22175 #define R_USB_COMMAND_DEV__port_sel__port_sel__dummy2 2
22176 #define R_USB_COMMAND_DEV__port_sel__port_sel__nop 0
22177 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__active 0
22178 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__nop 2
22179 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__passive 1
22180 #define R_USB_COMMAND_DEV__port_cmd__port_cmd__wakeup 3
22181 #define R_USB_COMMAND_DEV__busy__busy__no 0
22182 #define R_USB_COMMAND_DEV__busy__busy__yes 1
22183 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__deconfig 2
22184 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_config 4
22185 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop 1
22186 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop2 5
22187 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop3 6
22188 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop4 7
22189 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__host_config 3
22190 #define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__nop 0
22191
22192 #endif
22193
22194 /*
22195 * R_USB_EPID_ATTN
22196 * - type: RO
22197 * - addr: 0xb0000224
22198 * - group: USB interface control registers
22199 */
22200
22201 #if USE_GROUP__USB_interface_control_registers
22202
22203 #define R_USB_EPID_ATTN__ADDR (REG_TYPECAST_UDWORD 0xb0000224)
22204 #define R_USB_EPID_ATTN__SVAL REG_SVAL_SHADOW
22205 #define R_USB_EPID_ATTN__SVAL_I REG_SVAL_I_SHADOW
22206 #define R_USB_EPID_ATTN__TYPECAST REG_TYPECAST_UDWORD
22207 #define R_USB_EPID_ATTN__TYPE (REG_UDWORD)
22208 #define R_USB_EPID_ATTN__GET REG_GET_RO
22209 #define R_USB_EPID_ATTN__IGET REG_IGET_RO
22210 #define R_USB_EPID_ATTN__SET REG_SET_RO
22211 #define R_USB_EPID_ATTN__ISET REG_ISET_RO
22212 #define R_USB_EPID_ATTN__SET_VAL REG_SET_VAL_RO
22213 #define R_USB_EPID_ATTN__EQL REG_EQL_RO
22214 #define R_USB_EPID_ATTN__IEQL REG_IEQL_RO
22215 #define R_USB_EPID_ATTN__RD REG_RD_RO
22216 #define R_USB_EPID_ATTN__IRD REG_IRD_RO
22217 #define R_USB_EPID_ATTN__WR REG_WR_RO
22218 #define R_USB_EPID_ATTN__IWR REG_IWR_RO
22219
22220 #define R_USB_EPID_ATTN__READ(addr) \
22221 (*(addr))
22222
22223 #define R_USB_EPID_ATTN__value__value__MASK 0xffffffffU
22224
22225 #define R_USB_EPID_ATTN__value__MAX 0xffffffff
22226
22227 #define R_USB_EPID_ATTN__value__MIN 0
22228
22229 #define R_USB_EPID_ATTN__value__BITNR 0
22230
22231 #define R_USB_EPID_ATTN__value__value__VAL REG_VAL_VAL
22232
22233
22234 #endif
22235
22236 /*
22237 * R_USB_EPT_DATA
22238 * - type: RW
22239 * - addr: 0xb000021c
22240 * - group: USB interface control registers
22241 */
22242
22243 #if USE_GROUP__USB_interface_control_registers
22244
22245 #define R_USB_EPT_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
22246 #define R_USB_EPT_DATA__SVAL REG_SVAL_SHADOW
22247 #define R_USB_EPT_DATA__SVAL_I REG_SVAL_I_SHADOW
22248 #define R_USB_EPT_DATA__TYPECAST REG_TYPECAST_UDWORD
22249 #define R_USB_EPT_DATA__TYPE (REG_UDWORD)
22250 #define R_USB_EPT_DATA__GET REG_GET_RW
22251 #define R_USB_EPT_DATA__IGET REG_IGET_RW
22252 #define R_USB_EPT_DATA__SET REG_SET_RW
22253 #define R_USB_EPT_DATA__ISET REG_ISET_RW
22254 #define R_USB_EPT_DATA__SET_VAL REG_SET_VAL_RW
22255 #define R_USB_EPT_DATA__EQL REG_EQL_RW
22256 #define R_USB_EPT_DATA__IEQL REG_IEQL_RW
22257 #define R_USB_EPT_DATA__RD REG_RD_RW
22258 #define R_USB_EPT_DATA__IRD REG_IRD_RW
22259 #define R_USB_EPT_DATA__WR REG_WR_RW
22260 #define R_USB_EPT_DATA__IWR REG_IWR_RW
22261
22262 #define R_USB_EPT_DATA__WRITE(addr,value) \
22263 (*(addr) = (value))
22264 #define R_USB_EPT_DATA__READ(addr) \
22265 (*(addr))
22266
22267 #define R_USB_EPT_DATA__valid__valid__MASK 0x80000000U
22268 #define R_USB_EPT_DATA__hold__hold__MASK 0x40000000U
22269 #define R_USB_EPT_DATA__error_count_in__error_count_in__MASK 0x30000000U
22270 #define R_USB_EPT_DATA__t_in__t_in__MASK 0x08000000U
22271 #define R_USB_EPT_DATA__low_speed__low_speed__MASK 0x04000000U
22272 #define R_USB_EPT_DATA__port__port__MASK 0x03000000U
22273 #define R_USB_EPT_DATA__error_code__error_code__MASK 0x00c00000U
22274 #define R_USB_EPT_DATA__t_out__t_out__MASK 0x00200000U
22275 #define R_USB_EPT_DATA__error_count_out__error_count_out__MASK 0x00180000U
22276 #define R_USB_EPT_DATA__max_len__max_len__MASK 0x0003f800U
22277 #define R_USB_EPT_DATA__ep__ep__MASK 0x00000780U
22278 #define R_USB_EPT_DATA__dev__dev__MASK 0x0000007fU
22279
22280 #define R_USB_EPT_DATA__valid__MAX 0x1
22281 #define R_USB_EPT_DATA__hold__MAX 0x1
22282 #define R_USB_EPT_DATA__error_count_in__MAX 3
22283 #define R_USB_EPT_DATA__t_in__MAX 1
22284 #define R_USB_EPT_DATA__low_speed__MAX 0x1
22285 #define R_USB_EPT_DATA__port__MAX 0x3
22286 #define R_USB_EPT_DATA__error_code__MAX 0x3
22287 #define R_USB_EPT_DATA__t_out__MAX 1
22288 #define R_USB_EPT_DATA__error_count_out__MAX 3
22289 #define R_USB_EPT_DATA__max_len__MAX 64
22290 #define R_USB_EPT_DATA__ep__MAX 0xf
22291 #define R_USB_EPT_DATA__dev__MAX 0x7f
22292
22293 #define R_USB_EPT_DATA__valid__MIN 0
22294 #define R_USB_EPT_DATA__hold__MIN 0
22295 #define R_USB_EPT_DATA__error_count_in__MIN 0
22296 #define R_USB_EPT_DATA__t_in__MIN 0
22297 #define R_USB_EPT_DATA__low_speed__MIN 0
22298 #define R_USB_EPT_DATA__port__MIN 0
22299 #define R_USB_EPT_DATA__error_code__MIN 0
22300 #define R_USB_EPT_DATA__t_out__MIN 0
22301 #define R_USB_EPT_DATA__error_count_out__MIN 0
22302 #define R_USB_EPT_DATA__max_len__MIN 1
22303 #define R_USB_EPT_DATA__ep__MIN 0
22304 #define R_USB_EPT_DATA__dev__MIN 0
22305
22306 #define R_USB_EPT_DATA__valid__BITNR 31
22307 #define R_USB_EPT_DATA__hold__BITNR 30
22308 #define R_USB_EPT_DATA__error_count_in__BITNR 28
22309 #define R_USB_EPT_DATA__t_in__BITNR 27
22310 #define R_USB_EPT_DATA__low_speed__BITNR 26
22311 #define R_USB_EPT_DATA__port__BITNR 24
22312 #define R_USB_EPT_DATA__error_code__BITNR 22
22313 #define R_USB_EPT_DATA__t_out__BITNR 21
22314 #define R_USB_EPT_DATA__error_count_out__BITNR 19
22315 #define R_USB_EPT_DATA__max_len__BITNR 11
22316 #define R_USB_EPT_DATA__ep__BITNR 7
22317 #define R_USB_EPT_DATA__dev__BITNR 0
22318
22319 #define R_USB_EPT_DATA__valid__valid__VAL REG_VAL_ENUM
22320 #define R_USB_EPT_DATA__hold__hold__VAL REG_VAL_ENUM
22321 #define R_USB_EPT_DATA__error_count_in__error_count_in__VAL REG_VAL_VAL
22322 #define R_USB_EPT_DATA__t_in__t_in__VAL REG_VAL_VAL
22323 #define R_USB_EPT_DATA__low_speed__low_speed__VAL REG_VAL_ENUM
22324 #define R_USB_EPT_DATA__port__port__VAL REG_VAL_ENUM
22325 #define R_USB_EPT_DATA__error_code__error_code__VAL REG_VAL_ENUM
22326 #define R_USB_EPT_DATA__t_out__t_out__VAL REG_VAL_VAL
22327 #define R_USB_EPT_DATA__error_count_out__error_count_out__VAL REG_VAL_VAL
22328 #define R_USB_EPT_DATA__max_len__max_len__VAL REG_VAL_VAL
22329 #define R_USB_EPT_DATA__ep__ep__VAL REG_VAL_VAL
22330 #define R_USB_EPT_DATA__dev__dev__VAL REG_VAL_VAL
22331
22332 #define R_USB_EPT_DATA__valid__valid__no 0
22333 #define R_USB_EPT_DATA__valid__valid__yes 1
22334 #define R_USB_EPT_DATA__hold__hold__no 0
22335 #define R_USB_EPT_DATA__hold__hold__yes 1
22336 #define R_USB_EPT_DATA__low_speed__low_speed__no 0
22337 #define R_USB_EPT_DATA__low_speed__low_speed__yes 1
22338 #define R_USB_EPT_DATA__port__port__any 0
22339 #define R_USB_EPT_DATA__port__port__p1 1
22340 #define R_USB_EPT_DATA__port__port__p2 2
22341 #define R_USB_EPT_DATA__port__port__undef 3
22342 #define R_USB_EPT_DATA__error_code__error_code__buffer_error 3
22343 #define R_USB_EPT_DATA__error_code__error_code__bus_error 2
22344 #define R_USB_EPT_DATA__error_code__error_code__no_error 0
22345 #define R_USB_EPT_DATA__error_code__error_code__stall 1
22346
22347 #endif
22348
22349 /*
22350 * R_USB_EPT_DATA_DEV
22351 * - type: RW
22352 * - addr: 0xb000021c
22353 * - group: USB interface control registers
22354 */
22355
22356 #if USE_GROUP__USB_interface_control_registers
22357
22358 #define R_USB_EPT_DATA_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
22359 #define R_USB_EPT_DATA_DEV__SVAL REG_SVAL_SHADOW
22360 #define R_USB_EPT_DATA_DEV__SVAL_I REG_SVAL_I_SHADOW
22361 #define R_USB_EPT_DATA_DEV__TYPECAST REG_TYPECAST_UDWORD
22362 #define R_USB_EPT_DATA_DEV__TYPE (REG_UDWORD)
22363 #define R_USB_EPT_DATA_DEV__GET REG_GET_RW
22364 #define R_USB_EPT_DATA_DEV__IGET REG_IGET_RW
22365 #define R_USB_EPT_DATA_DEV__SET REG_SET_RW
22366 #define R_USB_EPT_DATA_DEV__ISET REG_ISET_RW
22367 #define R_USB_EPT_DATA_DEV__SET_VAL REG_SET_VAL_RW
22368 #define R_USB_EPT_DATA_DEV__EQL REG_EQL_RW
22369 #define R_USB_EPT_DATA_DEV__IEQL REG_IEQL_RW
22370 #define R_USB_EPT_DATA_DEV__RD REG_RD_RW
22371 #define R_USB_EPT_DATA_DEV__IRD REG_IRD_RW
22372 #define R_USB_EPT_DATA_DEV__WR REG_WR_RW
22373 #define R_USB_EPT_DATA_DEV__IWR REG_IWR_RW
22374
22375 #define R_USB_EPT_DATA_DEV__WRITE(addr,value) \
22376 (*(addr) = (value))
22377 #define R_USB_EPT_DATA_DEV__READ(addr) \
22378 (*(addr))
22379
22380 #define R_USB_EPT_DATA_DEV__valid__valid__MASK 0x80000000U
22381 #define R_USB_EPT_DATA_DEV__hold__hold__MASK 0x40000000U
22382 #define R_USB_EPT_DATA_DEV__stall__stall__MASK 0x20000000U
22383 #define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__MASK 0x10000000U
22384 #define R_USB_EPT_DATA_DEV__ctrl__ctrl__MASK 0x08000000U
22385 #define R_USB_EPT_DATA_DEV__iso__iso__MASK 0x04000000U
22386 #define R_USB_EPT_DATA_DEV__port__port__MASK 0x03000000U
22387 #define R_USB_EPT_DATA_DEV__control_phase__control_phase__MASK 0x00400000U
22388 #define R_USB_EPT_DATA_DEV__t__t__MASK 0x00200000U
22389 #define R_USB_EPT_DATA_DEV__max_len__max_len__MASK 0x001ff800U
22390 #define R_USB_EPT_DATA_DEV__ep__ep__MASK 0x00000780U
22391 #define R_USB_EPT_DATA_DEV__dev__dev__MASK 0x0000007fU
22392
22393 #define R_USB_EPT_DATA_DEV__valid__MAX 0x1
22394 #define R_USB_EPT_DATA_DEV__hold__MAX 0x1
22395 #define R_USB_EPT_DATA_DEV__stall__MAX 0x1
22396 #define R_USB_EPT_DATA_DEV__iso_resp__MAX 0x1
22397 #define R_USB_EPT_DATA_DEV__ctrl__MAX 0x1
22398 #define R_USB_EPT_DATA_DEV__iso__MAX 0x1
22399 #define R_USB_EPT_DATA_DEV__port__MAX 0x3
22400 #define R_USB_EPT_DATA_DEV__control_phase__MAX 0x1
22401 #define R_USB_EPT_DATA_DEV__t__MAX 1
22402 #define R_USB_EPT_DATA_DEV__max_len__MAX 1023
22403 #define R_USB_EPT_DATA_DEV__ep__MAX 15
22404 #define R_USB_EPT_DATA_DEV__dev__MAX 127
22405
22406 #define R_USB_EPT_DATA_DEV__valid__MIN 0
22407 #define R_USB_EPT_DATA_DEV__hold__MIN 0
22408 #define R_USB_EPT_DATA_DEV__stall__MIN 0
22409 #define R_USB_EPT_DATA_DEV__iso_resp__MIN 0
22410 #define R_USB_EPT_DATA_DEV__ctrl__MIN 0
22411 #define R_USB_EPT_DATA_DEV__iso__MIN 0
22412 #define R_USB_EPT_DATA_DEV__port__MIN 0
22413 #define R_USB_EPT_DATA_DEV__control_phase__MIN 0
22414 #define R_USB_EPT_DATA_DEV__t__MIN 0
22415 #define R_USB_EPT_DATA_DEV__max_len__MIN 1
22416 #define R_USB_EPT_DATA_DEV__ep__MIN 0
22417 #define R_USB_EPT_DATA_DEV__dev__MIN 0
22418
22419 #define R_USB_EPT_DATA_DEV__valid__BITNR 31
22420 #define R_USB_EPT_DATA_DEV__hold__BITNR 30
22421 #define R_USB_EPT_DATA_DEV__stall__BITNR 29
22422 #define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
22423 #define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
22424 #define R_USB_EPT_DATA_DEV__iso__BITNR 26
22425 #define R_USB_EPT_DATA_DEV__port__BITNR 24
22426 #define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
22427 #define R_USB_EPT_DATA_DEV__t__BITNR 21
22428 #define R_USB_EPT_DATA_DEV__max_len__BITNR 11
22429 #define R_USB_EPT_DATA_DEV__ep__BITNR 7
22430 #define R_USB_EPT_DATA_DEV__dev__BITNR 0
22431
22432 #define R_USB_EPT_DATA_DEV__valid__valid__VAL REG_VAL_ENUM
22433 #define R_USB_EPT_DATA_DEV__hold__hold__VAL REG_VAL_ENUM
22434 #define R_USB_EPT_DATA_DEV__stall__stall__VAL REG_VAL_ENUM
22435 #define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__VAL REG_VAL_ENUM
22436 #define R_USB_EPT_DATA_DEV__ctrl__ctrl__VAL REG_VAL_ENUM
22437 #define R_USB_EPT_DATA_DEV__iso__iso__VAL REG_VAL_ENUM
22438 #define R_USB_EPT_DATA_DEV__port__port__VAL REG_VAL_VAL
22439 #define R_USB_EPT_DATA_DEV__control_phase__control_phase__VAL REG_VAL_VAL
22440 #define R_USB_EPT_DATA_DEV__t__t__VAL REG_VAL_VAL
22441 #define R_USB_EPT_DATA_DEV__max_len__max_len__VAL REG_VAL_VAL
22442 #define R_USB_EPT_DATA_DEV__ep__ep__VAL REG_VAL_VAL
22443 #define R_USB_EPT_DATA_DEV__dev__dev__VAL REG_VAL_VAL
22444
22445 #define R_USB_EPT_DATA_DEV__valid__valid__no 0
22446 #define R_USB_EPT_DATA_DEV__valid__valid__yes 1
22447 #define R_USB_EPT_DATA_DEV__hold__hold__no 0
22448 #define R_USB_EPT_DATA_DEV__hold__hold__yes 1
22449 #define R_USB_EPT_DATA_DEV__stall__stall__no 0
22450 #define R_USB_EPT_DATA_DEV__stall__stall__yes 1
22451 #define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__quiet 0
22452 #define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__yes 1
22453 #define R_USB_EPT_DATA_DEV__ctrl__ctrl__no 0
22454 #define R_USB_EPT_DATA_DEV__ctrl__ctrl__yes 1
22455 #define R_USB_EPT_DATA_DEV__iso__iso__no 0
22456 #define R_USB_EPT_DATA_DEV__iso__iso__yes 1
22457
22458 #endif
22459
22460 /*
22461 * R_USB_EPT_DATA_ISO
22462 * - type: RW
22463 * - addr: 0xb000021c
22464 * - group: USB interface control registers
22465 */
22466
22467 #if USE_GROUP__USB_interface_control_registers
22468
22469 #define R_USB_EPT_DATA_ISO__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
22470 #define R_USB_EPT_DATA_ISO__SVAL REG_SVAL_SHADOW
22471 #define R_USB_EPT_DATA_ISO__SVAL_I REG_SVAL_I_SHADOW
22472 #define R_USB_EPT_DATA_ISO__TYPECAST REG_TYPECAST_UDWORD
22473 #define R_USB_EPT_DATA_ISO__TYPE (REG_UDWORD)
22474 #define R_USB_EPT_DATA_ISO__GET REG_GET_RW
22475 #define R_USB_EPT_DATA_ISO__IGET REG_IGET_RW
22476 #define R_USB_EPT_DATA_ISO__SET REG_SET_RW
22477 #define R_USB_EPT_DATA_ISO__ISET REG_ISET_RW
22478 #define R_USB_EPT_DATA_ISO__SET_VAL REG_SET_VAL_RW
22479 #define R_USB_EPT_DATA_ISO__EQL REG_EQL_RW
22480 #define R_USB_EPT_DATA_ISO__IEQL REG_IEQL_RW
22481 #define R_USB_EPT_DATA_ISO__RD REG_RD_RW
22482 #define R_USB_EPT_DATA_ISO__IRD REG_IRD_RW
22483 #define R_USB_EPT_DATA_ISO__WR REG_WR_RW
22484 #define R_USB_EPT_DATA_ISO__IWR REG_IWR_RW
22485
22486 #define R_USB_EPT_DATA_ISO__WRITE(addr,value) \
22487 (*(addr) = (value))
22488 #define R_USB_EPT_DATA_ISO__READ(addr) \
22489 (*(addr))
22490
22491 #define R_USB_EPT_DATA_ISO__valid__valid__MASK 0x80000000U
22492 #define R_USB_EPT_DATA_ISO__port__port__MASK 0x03000000U
22493 #define R_USB_EPT_DATA_ISO__error_code__error_code__MASK 0x00c00000U
22494 #define R_USB_EPT_DATA_ISO__max_len__max_len__MASK 0x001ff800U
22495 #define R_USB_EPT_DATA_ISO__ep__ep__MASK 0x00000780U
22496 #define R_USB_EPT_DATA_ISO__dev__dev__MASK 0x0000007fU
22497
22498 #define R_USB_EPT_DATA_ISO__valid__MAX 0x1
22499 #define R_USB_EPT_DATA_ISO__port__MAX 0x3
22500 #define R_USB_EPT_DATA_ISO__error_code__MAX 0x3
22501 #define R_USB_EPT_DATA_ISO__max_len__MAX 1023
22502 #define R_USB_EPT_DATA_ISO__ep__MAX 0xf
22503 #define R_USB_EPT_DATA_ISO__dev__MAX 0x7f
22504
22505 #define R_USB_EPT_DATA_ISO__valid__MIN 0
22506 #define R_USB_EPT_DATA_ISO__port__MIN 0
22507 #define R_USB_EPT_DATA_ISO__error_code__MIN 0
22508 #define R_USB_EPT_DATA_ISO__max_len__MIN 1
22509 #define R_USB_EPT_DATA_ISO__ep__MIN 0
22510 #define R_USB_EPT_DATA_ISO__dev__MIN 0
22511
22512 #define R_USB_EPT_DATA_ISO__valid__BITNR 31
22513 #define R_USB_EPT_DATA_ISO__port__BITNR 24
22514 #define R_USB_EPT_DATA_ISO__error_code__BITNR 22
22515 #define R_USB_EPT_DATA_ISO__max_len__BITNR 11
22516 #define R_USB_EPT_DATA_ISO__ep__BITNR 7
22517 #define R_USB_EPT_DATA_ISO__dev__BITNR 0
22518
22519 #define R_USB_EPT_DATA_ISO__valid__valid__VAL REG_VAL_ENUM
22520 #define R_USB_EPT_DATA_ISO__port__port__VAL REG_VAL_ENUM
22521 #define R_USB_EPT_DATA_ISO__error_code__error_code__VAL REG_VAL_ENUM
22522 #define R_USB_EPT_DATA_ISO__max_len__max_len__VAL REG_VAL_VAL
22523 #define R_USB_EPT_DATA_ISO__ep__ep__VAL REG_VAL_VAL
22524 #define R_USB_EPT_DATA_ISO__dev__dev__VAL REG_VAL_VAL
22525
22526 #define R_USB_EPT_DATA_ISO__valid__valid__no 0
22527 #define R_USB_EPT_DATA_ISO__valid__valid__yes 1
22528 #define R_USB_EPT_DATA_ISO__port__port__any 0
22529 #define R_USB_EPT_DATA_ISO__port__port__p1 1
22530 #define R_USB_EPT_DATA_ISO__port__port__p2 2
22531 #define R_USB_EPT_DATA_ISO__port__port__undef 3
22532 #define R_USB_EPT_DATA_ISO__error_code__error_code__TBD3 3
22533 #define R_USB_EPT_DATA_ISO__error_code__error_code__bus_error 2
22534 #define R_USB_EPT_DATA_ISO__error_code__error_code__no_error 0
22535 #define R_USB_EPT_DATA_ISO__error_code__error_code__stall 1
22536
22537 #endif
22538
22539 /*
22540 * R_USB_EPT_INDEX
22541 * - type: RW
22542 * - addr: 0xb0000208
22543 * - group: USB interface control registers
22544 */
22545
22546 #if USE_GROUP__USB_interface_control_registers
22547
22548 #define R_USB_EPT_INDEX__ADDR (REG_TYPECAST_BYTE 0xb0000208)
22549 #define R_USB_EPT_INDEX__SVAL REG_SVAL_SHADOW
22550 #define R_USB_EPT_INDEX__SVAL_I REG_SVAL_I_SHADOW
22551 #define R_USB_EPT_INDEX__TYPECAST REG_TYPECAST_BYTE
22552 #define R_USB_EPT_INDEX__TYPE (REG_BYTE)
22553 #define R_USB_EPT_INDEX__GET REG_GET_RW
22554 #define R_USB_EPT_INDEX__IGET REG_IGET_RW
22555 #define R_USB_EPT_INDEX__SET REG_SET_RW
22556 #define R_USB_EPT_INDEX__ISET REG_ISET_RW
22557 #define R_USB_EPT_INDEX__SET_VAL REG_SET_VAL_RW
22558 #define R_USB_EPT_INDEX__EQL REG_EQL_RW
22559 #define R_USB_EPT_INDEX__IEQL REG_IEQL_RW
22560 #define R_USB_EPT_INDEX__RD REG_RD_RW
22561 #define R_USB_EPT_INDEX__IRD REG_IRD_RW
22562 #define R_USB_EPT_INDEX__WR REG_WR_RW
22563 #define R_USB_EPT_INDEX__IWR REG_IWR_RW
22564
22565 #define R_USB_EPT_INDEX__WRITE(addr,value) \
22566 (*(addr) = (value))
22567 #define R_USB_EPT_INDEX__READ(addr) \
22568 (*(addr))
22569
22570 #define R_USB_EPT_INDEX__value__value__MASK 0x0000001fU
22571
22572 #define R_USB_EPT_INDEX__value__MAX 31
22573
22574 #define R_USB_EPT_INDEX__value__MIN 0
22575
22576 #define R_USB_EPT_INDEX__value__BITNR 0
22577
22578 #define R_USB_EPT_INDEX__value__value__VAL REG_VAL_VAL
22579
22580
22581 #endif
22582
22583 /*
22584 * R_USB_FM_INTERVAL
22585 * - type: RW
22586 * - addr: 0xb0000210
22587 * - group: USB interface control registers
22588 */
22589
22590 #if USE_GROUP__USB_interface_control_registers
22591
22592 #define R_USB_FM_INTERVAL__ADDR (REG_TYPECAST_UWORD 0xb0000210)
22593 #define R_USB_FM_INTERVAL__SVAL REG_SVAL_SHADOW
22594 #define R_USB_FM_INTERVAL__SVAL_I REG_SVAL_I_SHADOW
22595 #define R_USB_FM_INTERVAL__TYPECAST REG_TYPECAST_UWORD
22596 #define R_USB_FM_INTERVAL__TYPE (REG_UWORD)
22597 #define R_USB_FM_INTERVAL__GET REG_GET_RW
22598 #define R_USB_FM_INTERVAL__IGET REG_IGET_RW
22599 #define R_USB_FM_INTERVAL__SET REG_SET_RW
22600 #define R_USB_FM_INTERVAL__ISET REG_ISET_RW
22601 #define R_USB_FM_INTERVAL__SET_VAL REG_SET_VAL_RW
22602 #define R_USB_FM_INTERVAL__EQL REG_EQL_RW
22603 #define R_USB_FM_INTERVAL__IEQL REG_IEQL_RW
22604 #define R_USB_FM_INTERVAL__RD REG_RD_RW
22605 #define R_USB_FM_INTERVAL__IRD REG_IRD_RW
22606 #define R_USB_FM_INTERVAL__WR REG_WR_RW
22607 #define R_USB_FM_INTERVAL__IWR REG_IWR_RW
22608
22609 #define R_USB_FM_INTERVAL__WRITE(addr,value) \
22610 (*(addr) = (value))
22611 #define R_USB_FM_INTERVAL__READ(addr) \
22612 (*(addr))
22613
22614 #define R_USB_FM_INTERVAL__fixed__fixed__MASK 0x00003fc0U
22615 #define R_USB_FM_INTERVAL__adj__adj__MASK 0x0000003fU
22616
22617 #define R_USB_FM_INTERVAL__fixed__MAX 0xff
22618 #define R_USB_FM_INTERVAL__adj__MAX 63
22619
22620 #define R_USB_FM_INTERVAL__fixed__MIN 0
22621 #define R_USB_FM_INTERVAL__adj__MIN 0
22622
22623 #define R_USB_FM_INTERVAL__fixed__BITNR 6
22624 #define R_USB_FM_INTERVAL__adj__BITNR 0
22625
22626 #define R_USB_FM_INTERVAL__fixed__fixed__VAL REG_VAL_VAL
22627 #define R_USB_FM_INTERVAL__adj__adj__VAL REG_VAL_VAL
22628
22629
22630 #endif
22631
22632 /*
22633 * R_USB_FM_NUMBER
22634 * - type: RW
22635 * - addr: 0xb000020c
22636 * - group: USB interface control registers
22637 */
22638
22639 #if USE_GROUP__USB_interface_control_registers
22640
22641 #define R_USB_FM_NUMBER__ADDR (REG_TYPECAST_UDWORD 0xb000020c)
22642 #define R_USB_FM_NUMBER__SVAL REG_SVAL_SHADOW
22643 #define R_USB_FM_NUMBER__SVAL_I REG_SVAL_I_SHADOW
22644 #define R_USB_FM_NUMBER__TYPECAST REG_TYPECAST_UDWORD
22645 #define R_USB_FM_NUMBER__TYPE (REG_UDWORD)
22646 #define R_USB_FM_NUMBER__GET REG_GET_RW
22647 #define R_USB_FM_NUMBER__IGET REG_IGET_RW
22648 #define R_USB_FM_NUMBER__SET REG_SET_RW
22649 #define R_USB_FM_NUMBER__ISET REG_ISET_RW
22650 #define R_USB_FM_NUMBER__SET_VAL REG_SET_VAL_RW
22651 #define R_USB_FM_NUMBER__EQL REG_EQL_RW
22652 #define R_USB_FM_NUMBER__IEQL REG_IEQL_RW
22653 #define R_USB_FM_NUMBER__RD REG_RD_RW
22654 #define R_USB_FM_NUMBER__IRD REG_IRD_RW
22655 #define R_USB_FM_NUMBER__WR REG_WR_RW
22656 #define R_USB_FM_NUMBER__IWR REG_IWR_RW
22657
22658 #define R_USB_FM_NUMBER__WRITE(addr,value) \
22659 (*(addr) = (value))
22660 #define R_USB_FM_NUMBER__READ(addr) \
22661 (*(addr))
22662
22663 #define R_USB_FM_NUMBER__value__value__MASK 0xffffffffU
22664
22665 #define R_USB_FM_NUMBER__value__MAX 0xffffffff
22666
22667 #define R_USB_FM_NUMBER__value__MIN 0
22668
22669 #define R_USB_FM_NUMBER__value__BITNR 0
22670
22671 #define R_USB_FM_NUMBER__value__value__VAL REG_VAL_VAL
22672
22673
22674 #endif
22675
22676 /*
22677 * R_USB_FM_NUMBER_DEV
22678 * - type: RW
22679 * - addr: 0xb000020c
22680 * - group: USB interface control registers
22681 */
22682
22683 #if USE_GROUP__USB_interface_control_registers
22684
22685 #define R_USB_FM_NUMBER_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000020c)
22686 #define R_USB_FM_NUMBER_DEV__SVAL REG_SVAL_SHADOW
22687 #define R_USB_FM_NUMBER_DEV__SVAL_I REG_SVAL_I_SHADOW
22688 #define R_USB_FM_NUMBER_DEV__TYPECAST REG_TYPECAST_UDWORD
22689 #define R_USB_FM_NUMBER_DEV__TYPE (REG_UDWORD)
22690 #define R_USB_FM_NUMBER_DEV__GET REG_GET_RW
22691 #define R_USB_FM_NUMBER_DEV__IGET REG_IGET_RW
22692 #define R_USB_FM_NUMBER_DEV__SET REG_SET_RW
22693 #define R_USB_FM_NUMBER_DEV__ISET REG_ISET_RW
22694 #define R_USB_FM_NUMBER_DEV__SET_VAL REG_SET_VAL_RW
22695 #define R_USB_FM_NUMBER_DEV__EQL REG_EQL_RW
22696 #define R_USB_FM_NUMBER_DEV__IEQL REG_IEQL_RW
22697 #define R_USB_FM_NUMBER_DEV__RD REG_RD_RW
22698 #define R_USB_FM_NUMBER_DEV__IRD REG_IRD_RW
22699 #define R_USB_FM_NUMBER_DEV__WR REG_WR_RW
22700 #define R_USB_FM_NUMBER_DEV__IWR REG_IWR_RW
22701
22702 #define R_USB_FM_NUMBER_DEV__WRITE(addr,value) \
22703 (*(addr) = (value))
22704 #define R_USB_FM_NUMBER_DEV__READ(addr) \
22705 (*(addr))
22706
22707 #define R_USB_FM_NUMBER_DEV__sign__sign__MASK 0x80000000U
22708 #define R_USB_FM_NUMBER_DEV__deviation__deviation__MASK 0x7f000000U
22709 #define R_USB_FM_NUMBER_DEV__fm_number__fm_number__MASK 0x000007ffU
22710
22711 #define R_USB_FM_NUMBER_DEV__sign__MAX 0x1
22712 #define R_USB_FM_NUMBER_DEV__deviation__MAX 127
22713 #define R_USB_FM_NUMBER_DEV__fm_number__MAX 0x7ff
22714
22715 #define R_USB_FM_NUMBER_DEV__sign__MIN 0
22716 #define R_USB_FM_NUMBER_DEV__deviation__MIN 0
22717 #define R_USB_FM_NUMBER_DEV__fm_number__MIN 0
22718
22719 #define R_USB_FM_NUMBER_DEV__sign__BITNR 31
22720 #define R_USB_FM_NUMBER_DEV__deviation__BITNR 24
22721 #define R_USB_FM_NUMBER_DEV__fm_number__BITNR 0
22722
22723 #define R_USB_FM_NUMBER_DEV__sign__sign__VAL REG_VAL_ENUM
22724 #define R_USB_FM_NUMBER_DEV__deviation__deviation__VAL REG_VAL_VAL
22725 #define R_USB_FM_NUMBER_DEV__fm_number__fm_number__VAL REG_VAL_VAL
22726
22727 #define R_USB_FM_NUMBER_DEV__sign__sign__early 0
22728 #define R_USB_FM_NUMBER_DEV__sign__sign__late 1
22729
22730 #endif
22731
22732 /*
22733 * R_USB_FM_PSTART
22734 * - type: RW
22735 * - addr: 0xb0000214
22736 * - group: USB interface control registers
22737 */
22738
22739 #if USE_GROUP__USB_interface_control_registers
22740
22741 #define R_USB_FM_PSTART__ADDR (REG_TYPECAST_UWORD 0xb0000214)
22742 #define R_USB_FM_PSTART__SVAL REG_SVAL_SHADOW
22743 #define R_USB_FM_PSTART__SVAL_I REG_SVAL_I_SHADOW
22744 #define R_USB_FM_PSTART__TYPECAST REG_TYPECAST_UWORD
22745 #define R_USB_FM_PSTART__TYPE (REG_UWORD)
22746 #define R_USB_FM_PSTART__GET REG_GET_RW
22747 #define R_USB_FM_PSTART__IGET REG_IGET_RW
22748 #define R_USB_FM_PSTART__SET REG_SET_RW
22749 #define R_USB_FM_PSTART__ISET REG_ISET_RW
22750 #define R_USB_FM_PSTART__SET_VAL REG_SET_VAL_RW
22751 #define R_USB_FM_PSTART__EQL REG_EQL_RW
22752 #define R_USB_FM_PSTART__IEQL REG_IEQL_RW
22753 #define R_USB_FM_PSTART__RD REG_RD_RW
22754 #define R_USB_FM_PSTART__IRD REG_IRD_RW
22755 #define R_USB_FM_PSTART__WR REG_WR_RW
22756 #define R_USB_FM_PSTART__IWR REG_IWR_RW
22757
22758 #define R_USB_FM_PSTART__WRITE(addr,value) \
22759 (*(addr) = (value))
22760 #define R_USB_FM_PSTART__READ(addr) \
22761 (*(addr))
22762
22763 #define R_USB_FM_PSTART__value__value__MASK 0x00003fffU
22764
22765 #define R_USB_FM_PSTART__value__MAX 0x3fff
22766
22767 #define R_USB_FM_PSTART__value__MIN 0
22768
22769 #define R_USB_FM_PSTART__value__BITNR 0
22770
22771 #define R_USB_FM_PSTART__value__value__VAL REG_VAL_VAL
22772
22773
22774 #endif
22775
22776 /*
22777 * R_USB_FM_REMAINING
22778 * - type: RO
22779 * - addr: 0xb0000212
22780 * - group: USB interface control registers
22781 */
22782
22783 #if USE_GROUP__USB_interface_control_registers
22784
22785 #define R_USB_FM_REMAINING__ADDR (REG_TYPECAST_UWORD 0xb0000212)
22786 #define R_USB_FM_REMAINING__SVAL REG_SVAL_SHADOW
22787 #define R_USB_FM_REMAINING__SVAL_I REG_SVAL_I_SHADOW
22788 #define R_USB_FM_REMAINING__TYPECAST REG_TYPECAST_UWORD
22789 #define R_USB_FM_REMAINING__TYPE (REG_UWORD)
22790 #define R_USB_FM_REMAINING__GET REG_GET_RO
22791 #define R_USB_FM_REMAINING__IGET REG_IGET_RO
22792 #define R_USB_FM_REMAINING__SET REG_SET_RO
22793 #define R_USB_FM_REMAINING__ISET REG_ISET_RO
22794 #define R_USB_FM_REMAINING__SET_VAL REG_SET_VAL_RO
22795 #define R_USB_FM_REMAINING__EQL REG_EQL_RO
22796 #define R_USB_FM_REMAINING__IEQL REG_IEQL_RO
22797 #define R_USB_FM_REMAINING__RD REG_RD_RO
22798 #define R_USB_FM_REMAINING__IRD REG_IRD_RO
22799 #define R_USB_FM_REMAINING__WR REG_WR_RO
22800 #define R_USB_FM_REMAINING__IWR REG_IWR_RO
22801
22802 #define R_USB_FM_REMAINING__READ(addr) \
22803 (*(addr))
22804
22805 #define R_USB_FM_REMAINING__value__value__MASK 0x00003fffU
22806
22807 #define R_USB_FM_REMAINING__value__MAX 0x3fff
22808
22809 #define R_USB_FM_REMAINING__value__MIN 0
22810
22811 #define R_USB_FM_REMAINING__value__BITNR 0
22812
22813 #define R_USB_FM_REMAINING__value__value__VAL REG_VAL_VAL
22814
22815
22816 #endif
22817
22818 /*
22819 * R_USB_IRQ_MASK_CLR
22820 * - type: WO
22821 * - addr: 0xb0000206
22822 * - group: USB interface control registers
22823 */
22824
22825 #if USE_GROUP__USB_interface_control_registers
22826
22827 #define R_USB_IRQ_MASK_CLR__ADDR (REG_TYPECAST_UWORD 0xb0000206)
22828
22829 #ifndef REG_NO_SHADOW
22830 #define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0))
22831 #define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0))
22832 #else /* REG_NO_SHADOW */
22833 #define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
22834 #define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
22835 #endif /* REG_NO_SHADOW */
22836
22837 #define R_USB_IRQ_MASK_CLR__STYPECAST REG_STYPECAST_UWORD
22838 #define R_USB_IRQ_MASK_CLR__SVAL REG_SVAL_ZERO
22839 #define R_USB_IRQ_MASK_CLR__SVAL_I REG_SVAL_I_ZERO
22840 #define R_USB_IRQ_MASK_CLR__TYPECAST REG_TYPECAST_UWORD
22841 #define R_USB_IRQ_MASK_CLR__TYPE (REG_UWORD)
22842 #define R_USB_IRQ_MASK_CLR__GET REG_GET_WO
22843 #define R_USB_IRQ_MASK_CLR__IGET REG_IGET_WO
22844 #define R_USB_IRQ_MASK_CLR__SET REG_SET_WO
22845 #define R_USB_IRQ_MASK_CLR__ISET REG_ISET_WO
22846 #define R_USB_IRQ_MASK_CLR__SET_VAL REG_SET_VAL_WO
22847 #define R_USB_IRQ_MASK_CLR__EQL REG_EQL_WO
22848 #define R_USB_IRQ_MASK_CLR__IEQL REG_IEQL_WO
22849 #define R_USB_IRQ_MASK_CLR__RD REG_RD_WO
22850 #define R_USB_IRQ_MASK_CLR__IRD REG_IRD_WO
22851 #define R_USB_IRQ_MASK_CLR__WR REG_WR_WO
22852 #define R_USB_IRQ_MASK_CLR__IWR REG_IWR_WO
22853
22854 #define R_USB_IRQ_MASK_CLR__WRITE(addr,value) \
22855 (*(addr) = (value))
22856
22857 #define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__MASK 0x00002000U
22858 #define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__MASK 0x00001000U
22859 #define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__MASK 0x00000800U
22860 #define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__MASK 0x00000400U
22861 #define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__MASK 0x00000200U
22862 #define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__MASK 0x00000100U
22863 #define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__MASK 0x00000008U
22864 #define R_USB_IRQ_MASK_CLR__sof__sof__MASK 0x00000004U
22865 #define R_USB_IRQ_MASK_CLR__port_status__port_status__MASK 0x00000002U
22866 #define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__MASK 0x00000001U
22867
22868 #define R_USB_IRQ_MASK_CLR__iso_eof__MAX 0x1
22869 #define R_USB_IRQ_MASK_CLR__intr_eof__MAX 0x1
22870 #define R_USB_IRQ_MASK_CLR__iso_eot__MAX 0x1
22871 #define R_USB_IRQ_MASK_CLR__intr_eot__MAX 0x1
22872 #define R_USB_IRQ_MASK_CLR__ctl_eot__MAX 0x1
22873 #define R_USB_IRQ_MASK_CLR__bulk_eot__MAX 0x1
22874 #define R_USB_IRQ_MASK_CLR__epid_attn__MAX 0x1
22875 #define R_USB_IRQ_MASK_CLR__sof__MAX 0x1
22876 #define R_USB_IRQ_MASK_CLR__port_status__MAX 0x1
22877 #define R_USB_IRQ_MASK_CLR__ctl_status__MAX 0x1
22878
22879 #define R_USB_IRQ_MASK_CLR__iso_eof__MIN 0
22880 #define R_USB_IRQ_MASK_CLR__intr_eof__MIN 0
22881 #define R_USB_IRQ_MASK_CLR__iso_eot__MIN 0
22882 #define R_USB_IRQ_MASK_CLR__intr_eot__MIN 0
22883 #define R_USB_IRQ_MASK_CLR__ctl_eot__MIN 0
22884 #define R_USB_IRQ_MASK_CLR__bulk_eot__MIN 0
22885 #define R_USB_IRQ_MASK_CLR__epid_attn__MIN 0
22886 #define R_USB_IRQ_MASK_CLR__sof__MIN 0
22887 #define R_USB_IRQ_MASK_CLR__port_status__MIN 0
22888 #define R_USB_IRQ_MASK_CLR__ctl_status__MIN 0
22889
22890 #define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
22891 #define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
22892 #define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
22893 #define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
22894 #define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
22895 #define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
22896 #define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
22897 #define R_USB_IRQ_MASK_CLR__sof__BITNR 2
22898 #define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
22899 #define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
22900
22901 #define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__VAL REG_VAL_ENUM
22902 #define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__VAL REG_VAL_ENUM
22903 #define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__VAL REG_VAL_ENUM
22904 #define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__VAL REG_VAL_ENUM
22905 #define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
22906 #define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
22907 #define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__VAL REG_VAL_ENUM
22908 #define R_USB_IRQ_MASK_CLR__sof__sof__VAL REG_VAL_ENUM
22909 #define R_USB_IRQ_MASK_CLR__port_status__port_status__VAL REG_VAL_ENUM
22910 #define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__VAL REG_VAL_ENUM
22911
22912 #define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__clr 1
22913 #define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__nop 0
22914 #define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__clr 1
22915 #define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__nop 0
22916 #define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__clr 1
22917 #define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__nop 0
22918 #define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__clr 1
22919 #define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__nop 0
22920 #define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__clr 1
22921 #define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__nop 0
22922 #define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__clr 1
22923 #define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__nop 0
22924 #define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__clr 1
22925 #define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__nop 0
22926 #define R_USB_IRQ_MASK_CLR__sof__sof__clr 1
22927 #define R_USB_IRQ_MASK_CLR__sof__sof__nop 0
22928 #define R_USB_IRQ_MASK_CLR__port_status__port_status__clr 1
22929 #define R_USB_IRQ_MASK_CLR__port_status__port_status__nop 0
22930 #define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__clr 1
22931 #define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__nop 0
22932
22933 #endif
22934
22935 /*
22936 * R_USB_IRQ_MASK_CLR_DEV
22937 * - type: WO
22938 * - addr: 0xb0000206
22939 * - group: USB interface control registers
22940 */
22941
22942 #if USE_GROUP__USB_interface_control_registers
22943
22944 #define R_USB_IRQ_MASK_CLR_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206)
22945
22946 #ifndef REG_NO_SHADOW
22947 #define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0))
22948 #define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0))
22949 #else /* REG_NO_SHADOW */
22950 #define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
22951 #define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
22952 #endif /* REG_NO_SHADOW */
22953
22954 #define R_USB_IRQ_MASK_CLR_DEV__STYPECAST REG_STYPECAST_UWORD
22955 #define R_USB_IRQ_MASK_CLR_DEV__SVAL REG_SVAL_SHADOW
22956 #define R_USB_IRQ_MASK_CLR_DEV__SVAL_I REG_SVAL_I_SHADOW
22957 #define R_USB_IRQ_MASK_CLR_DEV__TYPECAST REG_TYPECAST_UWORD
22958 #define R_USB_IRQ_MASK_CLR_DEV__TYPE (REG_UWORD)
22959 #define R_USB_IRQ_MASK_CLR_DEV__GET REG_GET_WO
22960 #define R_USB_IRQ_MASK_CLR_DEV__IGET REG_IGET_WO
22961 #define R_USB_IRQ_MASK_CLR_DEV__SET REG_SET_WO
22962 #define R_USB_IRQ_MASK_CLR_DEV__ISET REG_ISET_WO
22963 #define R_USB_IRQ_MASK_CLR_DEV__SET_VAL REG_SET_VAL_WO
22964 #define R_USB_IRQ_MASK_CLR_DEV__EQL REG_EQL_WO
22965 #define R_USB_IRQ_MASK_CLR_DEV__IEQL REG_IEQL_WO
22966 #define R_USB_IRQ_MASK_CLR_DEV__RD REG_RD_WO
22967 #define R_USB_IRQ_MASK_CLR_DEV__IRD REG_IRD_WO
22968 #define R_USB_IRQ_MASK_CLR_DEV__WR REG_WR_WO
22969 #define R_USB_IRQ_MASK_CLR_DEV__IWR REG_IWR_WO
22970
22971 #define R_USB_IRQ_MASK_CLR_DEV__WRITE(addr,value) \
22972 (*(addr) = (value))
22973
22974 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__MASK 0x00001000U
22975 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
22976 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
22977 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
22978 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
22979 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__MASK 0x00000008U
22980 #define R_USB_IRQ_MASK_CLR_DEV__sof__sof__MASK 0x00000004U
22981 #define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__MASK 0x00000002U
22982 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__MASK 0x00000001U
22983
22984 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__MAX 0x1
22985 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MAX 0x1
22986 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MAX 0x1
22987 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MAX 0x1
22988 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MAX 0x1
22989 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MAX 0x1
22990 #define R_USB_IRQ_MASK_CLR_DEV__sof__MAX 0x1
22991 #define R_USB_IRQ_MASK_CLR_DEV__port_status__MAX 0x1
22992 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MAX 0x1
22993
22994 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__MIN 0
22995 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MIN 0
22996 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MIN 0
22997 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MIN 0
22998 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MIN 0
22999 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MIN 0
23000 #define R_USB_IRQ_MASK_CLR_DEV__sof__MIN 0
23001 #define R_USB_IRQ_MASK_CLR_DEV__port_status__MIN 0
23002 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MIN 0
23003
23004 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
23005 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
23006 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
23007 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
23008 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
23009 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
23010 #define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
23011 #define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
23012 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
23013
23014 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
23015 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
23016 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
23017 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
23018 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
23019 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
23020 #define R_USB_IRQ_MASK_CLR_DEV__sof__sof__VAL REG_VAL_ENUM
23021 #define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__VAL REG_VAL_ENUM
23022 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
23023
23024 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__clr 1
23025 #define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__nop 0
23026 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__clr 1
23027 #define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__nop 0
23028 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__clr 1
23029 #define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__nop 0
23030 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__clr 1
23031 #define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__nop 0
23032 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__clr 1
23033 #define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__nop 0
23034 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__clr 1
23035 #define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__nop 0
23036 #define R_USB_IRQ_MASK_CLR_DEV__sof__sof__clr 1
23037 #define R_USB_IRQ_MASK_CLR_DEV__sof__sof__nop 0
23038 #define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__clr 1
23039 #define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__nop 0
23040 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__clr 1
23041 #define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__nop 0
23042
23043 #endif
23044
23045 /*
23046 * R_USB_IRQ_MASK_READ
23047 * - type: RO
23048 * - addr: 0xb0000204
23049 * - group: USB interface control registers
23050 */
23051
23052 #if USE_GROUP__USB_interface_control_registers
23053
23054 #define R_USB_IRQ_MASK_READ__ADDR (REG_TYPECAST_UWORD 0xb0000204)
23055 #define R_USB_IRQ_MASK_READ__SVAL REG_SVAL_SHADOW
23056 #define R_USB_IRQ_MASK_READ__SVAL_I REG_SVAL_I_SHADOW
23057 #define R_USB_IRQ_MASK_READ__TYPECAST REG_TYPECAST_UWORD
23058 #define R_USB_IRQ_MASK_READ__TYPE (REG_UWORD)
23059 #define R_USB_IRQ_MASK_READ__GET REG_GET_RO
23060 #define R_USB_IRQ_MASK_READ__IGET REG_IGET_RO
23061 #define R_USB_IRQ_MASK_READ__SET REG_SET_RO
23062 #define R_USB_IRQ_MASK_READ__ISET REG_ISET_RO
23063 #define R_USB_IRQ_MASK_READ__SET_VAL REG_SET_VAL_RO
23064 #define R_USB_IRQ_MASK_READ__EQL REG_EQL_RO
23065 #define R_USB_IRQ_MASK_READ__IEQL REG_IEQL_RO
23066 #define R_USB_IRQ_MASK_READ__RD REG_RD_RO
23067 #define R_USB_IRQ_MASK_READ__IRD REG_IRD_RO
23068 #define R_USB_IRQ_MASK_READ__WR REG_WR_RO
23069 #define R_USB_IRQ_MASK_READ__IWR REG_IWR_RO
23070
23071 #define R_USB_IRQ_MASK_READ__READ(addr) \
23072 (*(addr))
23073
23074 #define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__MASK 0x00002000U
23075 #define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__MASK 0x00001000U
23076 #define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__MASK 0x00000800U
23077 #define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__MASK 0x00000400U
23078 #define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__MASK 0x00000200U
23079 #define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__MASK 0x00000100U
23080 #define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__MASK 0x00000008U
23081 #define R_USB_IRQ_MASK_READ__sof__sof__MASK 0x00000004U
23082 #define R_USB_IRQ_MASK_READ__port_status__port_status__MASK 0x00000002U
23083 #define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__MASK 0x00000001U
23084
23085 #define R_USB_IRQ_MASK_READ__iso_eof__MAX 0x1
23086 #define R_USB_IRQ_MASK_READ__intr_eof__MAX 0x1
23087 #define R_USB_IRQ_MASK_READ__iso_eot__MAX 0x1
23088 #define R_USB_IRQ_MASK_READ__intr_eot__MAX 0x1
23089 #define R_USB_IRQ_MASK_READ__ctl_eot__MAX 0x1
23090 #define R_USB_IRQ_MASK_READ__bulk_eot__MAX 0x1
23091 #define R_USB_IRQ_MASK_READ__epid_attn__MAX 0x1
23092 #define R_USB_IRQ_MASK_READ__sof__MAX 0x1
23093 #define R_USB_IRQ_MASK_READ__port_status__MAX 0x1
23094 #define R_USB_IRQ_MASK_READ__ctl_status__MAX 0x1
23095
23096 #define R_USB_IRQ_MASK_READ__iso_eof__MIN 0
23097 #define R_USB_IRQ_MASK_READ__intr_eof__MIN 0
23098 #define R_USB_IRQ_MASK_READ__iso_eot__MIN 0
23099 #define R_USB_IRQ_MASK_READ__intr_eot__MIN 0
23100 #define R_USB_IRQ_MASK_READ__ctl_eot__MIN 0
23101 #define R_USB_IRQ_MASK_READ__bulk_eot__MIN 0
23102 #define R_USB_IRQ_MASK_READ__epid_attn__MIN 0
23103 #define R_USB_IRQ_MASK_READ__sof__MIN 0
23104 #define R_USB_IRQ_MASK_READ__port_status__MIN 0
23105 #define R_USB_IRQ_MASK_READ__ctl_status__MIN 0
23106
23107 #define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
23108 #define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
23109 #define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
23110 #define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
23111 #define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
23112 #define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
23113 #define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
23114 #define R_USB_IRQ_MASK_READ__sof__BITNR 2
23115 #define R_USB_IRQ_MASK_READ__port_status__BITNR 1
23116 #define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
23117
23118 #define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM
23119 #define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM
23120 #define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM
23121 #define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM
23122 #define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
23123 #define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
23124 #define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM
23125 #define R_USB_IRQ_MASK_READ__sof__sof__VAL REG_VAL_ENUM
23126 #define R_USB_IRQ_MASK_READ__port_status__port_status__VAL REG_VAL_ENUM
23127 #define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM
23128
23129 #define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__no_pend 0
23130 #define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__pend 1
23131 #define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__no_pend 0
23132 #define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__pend 1
23133 #define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__no_pend 0
23134 #define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__pend 1
23135 #define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__no_pend 0
23136 #define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__pend 1
23137 #define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__no_pend 0
23138 #define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__pend 1
23139 #define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__no_pend 0
23140 #define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__pend 1
23141 #define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__no_pend 0
23142 #define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__pend 1
23143 #define R_USB_IRQ_MASK_READ__sof__sof__no_pend 0
23144 #define R_USB_IRQ_MASK_READ__sof__sof__pend 1
23145 #define R_USB_IRQ_MASK_READ__port_status__port_status__no_pend 0
23146 #define R_USB_IRQ_MASK_READ__port_status__port_status__pend 1
23147 #define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__no_pend 0
23148 #define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__pend 1
23149
23150 #endif
23151
23152 /*
23153 * R_USB_IRQ_MASK_READ_DEV
23154 * - type: RO
23155 * - addr: 0xb0000204
23156 * - group: USB interface control registers
23157 */
23158
23159 #if USE_GROUP__USB_interface_control_registers
23160
23161 #define R_USB_IRQ_MASK_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204)
23162 #define R_USB_IRQ_MASK_READ_DEV__SVAL REG_SVAL_SHADOW
23163 #define R_USB_IRQ_MASK_READ_DEV__SVAL_I REG_SVAL_I_SHADOW
23164 #define R_USB_IRQ_MASK_READ_DEV__TYPECAST REG_TYPECAST_UWORD
23165 #define R_USB_IRQ_MASK_READ_DEV__TYPE (REG_UWORD)
23166 #define R_USB_IRQ_MASK_READ_DEV__GET REG_GET_RO
23167 #define R_USB_IRQ_MASK_READ_DEV__IGET REG_IGET_RO
23168 #define R_USB_IRQ_MASK_READ_DEV__SET REG_SET_RO
23169 #define R_USB_IRQ_MASK_READ_DEV__ISET REG_ISET_RO
23170 #define R_USB_IRQ_MASK_READ_DEV__SET_VAL REG_SET_VAL_RO
23171 #define R_USB_IRQ_MASK_READ_DEV__EQL REG_EQL_RO
23172 #define R_USB_IRQ_MASK_READ_DEV__IEQL REG_IEQL_RO
23173 #define R_USB_IRQ_MASK_READ_DEV__RD REG_RD_RO
23174 #define R_USB_IRQ_MASK_READ_DEV__IRD REG_IRD_RO
23175 #define R_USB_IRQ_MASK_READ_DEV__WR REG_WR_RO
23176 #define R_USB_IRQ_MASK_READ_DEV__IWR REG_IWR_RO
23177
23178 #define R_USB_IRQ_MASK_READ_DEV__READ(addr) \
23179 (*(addr))
23180
23181 #define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__MASK 0x00001000U
23182 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
23183 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
23184 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
23185 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
23186 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U
23187 #define R_USB_IRQ_MASK_READ_DEV__sof__sof__MASK 0x00000004U
23188 #define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__MASK 0x00000002U
23189 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U
23190
23191 #define R_USB_IRQ_MASK_READ_DEV__out_eot__MAX 0x1
23192 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MAX 0x1
23193 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MAX 0x1
23194 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MAX 0x1
23195 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MAX 0x1
23196 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__MAX 0x1
23197 #define R_USB_IRQ_MASK_READ_DEV__sof__MAX 0x1
23198 #define R_USB_IRQ_MASK_READ_DEV__port_status__MAX 0x1
23199 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__MAX 0x1
23200
23201 #define R_USB_IRQ_MASK_READ_DEV__out_eot__MIN 0
23202 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MIN 0
23203 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MIN 0
23204 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MIN 0
23205 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MIN 0
23206 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__MIN 0
23207 #define R_USB_IRQ_MASK_READ_DEV__sof__MIN 0
23208 #define R_USB_IRQ_MASK_READ_DEV__port_status__MIN 0
23209 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__MIN 0
23210
23211 #define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
23212 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
23213 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
23214 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
23215 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
23216 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
23217 #define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
23218 #define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
23219 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
23220
23221 #define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
23222 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
23223 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
23224 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
23225 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
23226 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
23227 #define R_USB_IRQ_MASK_READ_DEV__sof__sof__VAL REG_VAL_ENUM
23228 #define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM
23229 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
23230
23231 #define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__no_pend 0
23232 #define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__pend 1
23233 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0
23234 #define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1
23235 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0
23236 #define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1
23237 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0
23238 #define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1
23239 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0
23240 #define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1
23241 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__no_pend 0
23242 #define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__pend 1
23243 #define R_USB_IRQ_MASK_READ_DEV__sof__sof__no_pend 0
23244 #define R_USB_IRQ_MASK_READ_DEV__sof__sof__pend 1
23245 #define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__no_pend 0
23246 #define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__pend 1
23247 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__no_pend 0
23248 #define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__pend 1
23249
23250 #endif
23251
23252 /*
23253 * R_USB_IRQ_MASK_SET
23254 * - type: WO
23255 * - addr: 0xb0000204
23256 * - group: USB interface control registers
23257 */
23258
23259 #if USE_GROUP__USB_interface_control_registers
23260
23261 #define R_USB_IRQ_MASK_SET__ADDR (REG_TYPECAST_UWORD 0xb0000204)
23262
23263 #ifndef REG_NO_SHADOW
23264 #define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0))
23265 #define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0))
23266 #else /* REG_NO_SHADOW */
23267 #define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
23268 #define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
23269 #endif /* REG_NO_SHADOW */
23270
23271 #define R_USB_IRQ_MASK_SET__STYPECAST REG_STYPECAST_UWORD
23272 #define R_USB_IRQ_MASK_SET__SVAL REG_SVAL_ZERO
23273 #define R_USB_IRQ_MASK_SET__SVAL_I REG_SVAL_I_ZERO
23274 #define R_USB_IRQ_MASK_SET__TYPECAST REG_TYPECAST_UWORD
23275 #define R_USB_IRQ_MASK_SET__TYPE (REG_UWORD)
23276 #define R_USB_IRQ_MASK_SET__GET REG_GET_WO
23277 #define R_USB_IRQ_MASK_SET__IGET REG_IGET_WO
23278 #define R_USB_IRQ_MASK_SET__SET REG_SET_WO
23279 #define R_USB_IRQ_MASK_SET__ISET REG_ISET_WO
23280 #define R_USB_IRQ_MASK_SET__SET_VAL REG_SET_VAL_WO
23281 #define R_USB_IRQ_MASK_SET__EQL REG_EQL_WO
23282 #define R_USB_IRQ_MASK_SET__IEQL REG_IEQL_WO
23283 #define R_USB_IRQ_MASK_SET__RD REG_RD_WO
23284 #define R_USB_IRQ_MASK_SET__IRD REG_IRD_WO
23285 #define R_USB_IRQ_MASK_SET__WR REG_WR_WO
23286 #define R_USB_IRQ_MASK_SET__IWR REG_IWR_WO
23287
23288 #define R_USB_IRQ_MASK_SET__WRITE(addr,value) \
23289 (*(addr) = (value))
23290
23291 #define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__MASK 0x00002000U
23292 #define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__MASK 0x00001000U
23293 #define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__MASK 0x00000800U
23294 #define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__MASK 0x00000400U
23295 #define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__MASK 0x00000200U
23296 #define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__MASK 0x00000100U
23297 #define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__MASK 0x00000008U
23298 #define R_USB_IRQ_MASK_SET__sof__sof__MASK 0x00000004U
23299 #define R_USB_IRQ_MASK_SET__port_status__port_status__MASK 0x00000002U
23300 #define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__MASK 0x00000001U
23301
23302 #define R_USB_IRQ_MASK_SET__iso_eof__MAX 0x1
23303 #define R_USB_IRQ_MASK_SET__intr_eof__MAX 0x1
23304 #define R_USB_IRQ_MASK_SET__iso_eot__MAX 0x1
23305 #define R_USB_IRQ_MASK_SET__intr_eot__MAX 0x1
23306 #define R_USB_IRQ_MASK_SET__ctl_eot__MAX 0x1
23307 #define R_USB_IRQ_MASK_SET__bulk_eot__MAX 0x1
23308 #define R_USB_IRQ_MASK_SET__epid_attn__MAX 0x1
23309 #define R_USB_IRQ_MASK_SET__sof__MAX 0x1
23310 #define R_USB_IRQ_MASK_SET__port_status__MAX 0x1
23311 #define R_USB_IRQ_MASK_SET__ctl_status__MAX 0x1
23312
23313 #define R_USB_IRQ_MASK_SET__iso_eof__MIN 0
23314 #define R_USB_IRQ_MASK_SET__intr_eof__MIN 0
23315 #define R_USB_IRQ_MASK_SET__iso_eot__MIN 0
23316 #define R_USB_IRQ_MASK_SET__intr_eot__MIN 0
23317 #define R_USB_IRQ_MASK_SET__ctl_eot__MIN 0
23318 #define R_USB_IRQ_MASK_SET__bulk_eot__MIN 0
23319 #define R_USB_IRQ_MASK_SET__epid_attn__MIN 0
23320 #define R_USB_IRQ_MASK_SET__sof__MIN 0
23321 #define R_USB_IRQ_MASK_SET__port_status__MIN 0
23322 #define R_USB_IRQ_MASK_SET__ctl_status__MIN 0
23323
23324 #define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
23325 #define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
23326 #define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
23327 #define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
23328 #define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
23329 #define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
23330 #define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
23331 #define R_USB_IRQ_MASK_SET__sof__BITNR 2
23332 #define R_USB_IRQ_MASK_SET__port_status__BITNR 1
23333 #define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
23334
23335 #define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__VAL REG_VAL_ENUM
23336 #define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__VAL REG_VAL_ENUM
23337 #define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__VAL REG_VAL_ENUM
23338 #define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__VAL REG_VAL_ENUM
23339 #define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
23340 #define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
23341 #define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__VAL REG_VAL_ENUM
23342 #define R_USB_IRQ_MASK_SET__sof__sof__VAL REG_VAL_ENUM
23343 #define R_USB_IRQ_MASK_SET__port_status__port_status__VAL REG_VAL_ENUM
23344 #define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__VAL REG_VAL_ENUM
23345
23346 #define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__nop 0
23347 #define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__set 1
23348 #define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__nop 0
23349 #define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__set 1
23350 #define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__nop 0
23351 #define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__set 1
23352 #define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__nop 0
23353 #define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__set 1
23354 #define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__nop 0
23355 #define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__set 1
23356 #define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__nop 0
23357 #define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__set 1
23358 #define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__nop 0
23359 #define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__set 1
23360 #define R_USB_IRQ_MASK_SET__sof__sof__nop 0
23361 #define R_USB_IRQ_MASK_SET__sof__sof__set 1
23362 #define R_USB_IRQ_MASK_SET__port_status__port_status__nop 0
23363 #define R_USB_IRQ_MASK_SET__port_status__port_status__set 1
23364 #define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__nop 0
23365 #define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__set 1
23366
23367 #endif
23368
23369 /*
23370 * R_USB_IRQ_MASK_SET_DEV
23371 * - type: WO
23372 * - addr: 0xb0000204
23373 * - group: USB interface control registers
23374 */
23375
23376 #if USE_GROUP__USB_interface_control_registers
23377
23378 #define R_USB_IRQ_MASK_SET_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204)
23379
23380 #ifndef REG_NO_SHADOW
23381 #define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0))
23382 #define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0))
23383 #else /* REG_NO_SHADOW */
23384 #define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
23385 #define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
23386 #endif /* REG_NO_SHADOW */
23387
23388 #define R_USB_IRQ_MASK_SET_DEV__STYPECAST REG_STYPECAST_UWORD
23389 #define R_USB_IRQ_MASK_SET_DEV__SVAL REG_SVAL_SHADOW
23390 #define R_USB_IRQ_MASK_SET_DEV__SVAL_I REG_SVAL_I_SHADOW
23391 #define R_USB_IRQ_MASK_SET_DEV__TYPECAST REG_TYPECAST_UWORD
23392 #define R_USB_IRQ_MASK_SET_DEV__TYPE (REG_UWORD)
23393 #define R_USB_IRQ_MASK_SET_DEV__GET REG_GET_WO
23394 #define R_USB_IRQ_MASK_SET_DEV__IGET REG_IGET_WO
23395 #define R_USB_IRQ_MASK_SET_DEV__SET REG_SET_WO
23396 #define R_USB_IRQ_MASK_SET_DEV__ISET REG_ISET_WO
23397 #define R_USB_IRQ_MASK_SET_DEV__SET_VAL REG_SET_VAL_WO
23398 #define R_USB_IRQ_MASK_SET_DEV__EQL REG_EQL_WO
23399 #define R_USB_IRQ_MASK_SET_DEV__IEQL REG_IEQL_WO
23400 #define R_USB_IRQ_MASK_SET_DEV__RD REG_RD_WO
23401 #define R_USB_IRQ_MASK_SET_DEV__IRD REG_IRD_WO
23402 #define R_USB_IRQ_MASK_SET_DEV__WR REG_WR_WO
23403 #define R_USB_IRQ_MASK_SET_DEV__IWR REG_IWR_WO
23404
23405 #define R_USB_IRQ_MASK_SET_DEV__WRITE(addr,value) \
23406 (*(addr) = (value))
23407
23408 #define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__MASK 0x00001000U
23409 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
23410 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
23411 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
23412 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
23413 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__MASK 0x00000008U
23414 #define R_USB_IRQ_MASK_SET_DEV__sof__sof__MASK 0x00000004U
23415 #define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__MASK 0x00000002U
23416 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__MASK 0x00000001U
23417
23418 #define R_USB_IRQ_MASK_SET_DEV__out_eot__MAX 0x1
23419 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MAX 0x1
23420 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MAX 0x1
23421 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MAX 0x1
23422 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MAX 0x1
23423 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__MAX 0x1
23424 #define R_USB_IRQ_MASK_SET_DEV__sof__MAX 0x1
23425 #define R_USB_IRQ_MASK_SET_DEV__port_status__MAX 0x1
23426 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__MAX 0x1
23427
23428 #define R_USB_IRQ_MASK_SET_DEV__out_eot__MIN 0
23429 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MIN 0
23430 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MIN 0
23431 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MIN 0
23432 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MIN 0
23433 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__MIN 0
23434 #define R_USB_IRQ_MASK_SET_DEV__sof__MIN 0
23435 #define R_USB_IRQ_MASK_SET_DEV__port_status__MIN 0
23436 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__MIN 0
23437
23438 #define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
23439 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
23440 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
23441 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
23442 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
23443 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
23444 #define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
23445 #define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
23446 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
23447
23448 #define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
23449 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
23450 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
23451 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
23452 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
23453 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
23454 #define R_USB_IRQ_MASK_SET_DEV__sof__sof__VAL REG_VAL_ENUM
23455 #define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__VAL REG_VAL_ENUM
23456 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
23457
23458 #define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__nop 0
23459 #define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__set 1
23460 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__nop 0
23461 #define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__set 1
23462 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__nop 0
23463 #define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__set 1
23464 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__nop 0
23465 #define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__set 1
23466 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__nop 0
23467 #define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__set 1
23468 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__nop 0
23469 #define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__set 1
23470 #define R_USB_IRQ_MASK_SET_DEV__sof__sof__nop 0
23471 #define R_USB_IRQ_MASK_SET_DEV__sof__sof__set 1
23472 #define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__nop 0
23473 #define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__set 1
23474 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__nop 0
23475 #define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__set 1
23476
23477 #endif
23478
23479 /*
23480 * R_USB_IRQ_READ
23481 * - type: RO
23482 * - addr: 0xb0000206
23483 * - group: USB interface control registers
23484 */
23485
23486 #if USE_GROUP__USB_interface_control_registers
23487
23488 #define R_USB_IRQ_READ__ADDR (REG_TYPECAST_UWORD 0xb0000206)
23489 #define R_USB_IRQ_READ__SVAL REG_SVAL_SHADOW
23490 #define R_USB_IRQ_READ__SVAL_I REG_SVAL_I_SHADOW
23491 #define R_USB_IRQ_READ__TYPECAST REG_TYPECAST_UWORD
23492 #define R_USB_IRQ_READ__TYPE (REG_UWORD)
23493 #define R_USB_IRQ_READ__GET REG_GET_RO
23494 #define R_USB_IRQ_READ__IGET REG_IGET_RO
23495 #define R_USB_IRQ_READ__SET REG_SET_RO
23496 #define R_USB_IRQ_READ__ISET REG_ISET_RO
23497 #define R_USB_IRQ_READ__SET_VAL REG_SET_VAL_RO
23498 #define R_USB_IRQ_READ__EQL REG_EQL_RO
23499 #define R_USB_IRQ_READ__IEQL REG_IEQL_RO
23500 #define R_USB_IRQ_READ__RD REG_RD_RO
23501 #define R_USB_IRQ_READ__IRD REG_IRD_RO
23502 #define R_USB_IRQ_READ__WR REG_WR_RO
23503 #define R_USB_IRQ_READ__IWR REG_IWR_RO
23504
23505 #define R_USB_IRQ_READ__READ(addr) \
23506 (*(addr))
23507
23508 #define R_USB_IRQ_READ__iso_eof__iso_eof__MASK 0x00002000U
23509 #define R_USB_IRQ_READ__intr_eof__intr_eof__MASK 0x00001000U
23510 #define R_USB_IRQ_READ__iso_eot__iso_eot__MASK 0x00000800U
23511 #define R_USB_IRQ_READ__intr_eot__intr_eot__MASK 0x00000400U
23512 #define R_USB_IRQ_READ__ctl_eot__ctl_eot__MASK 0x00000200U
23513 #define R_USB_IRQ_READ__bulk_eot__bulk_eot__MASK 0x00000100U
23514 #define R_USB_IRQ_READ__epid_attn__epid_attn__MASK 0x00000008U
23515 #define R_USB_IRQ_READ__sof__sof__MASK 0x00000004U
23516 #define R_USB_IRQ_READ__port_status__port_status__MASK 0x00000002U
23517 #define R_USB_IRQ_READ__ctl_status__ctl_status__MASK 0x00000001U
23518
23519 #define R_USB_IRQ_READ__iso_eof__MAX 0x1
23520 #define R_USB_IRQ_READ__intr_eof__MAX 0x1
23521 #define R_USB_IRQ_READ__iso_eot__MAX 0x1
23522 #define R_USB_IRQ_READ__intr_eot__MAX 0x1
23523 #define R_USB_IRQ_READ__ctl_eot__MAX 0x1
23524 #define R_USB_IRQ_READ__bulk_eot__MAX 0x1
23525 #define R_USB_IRQ_READ__epid_attn__MAX 0x1
23526 #define R_USB_IRQ_READ__sof__MAX 0x1
23527 #define R_USB_IRQ_READ__port_status__MAX 0x1
23528 #define R_USB_IRQ_READ__ctl_status__MAX 0x1
23529
23530 #define R_USB_IRQ_READ__iso_eof__MIN 0
23531 #define R_USB_IRQ_READ__intr_eof__MIN 0
23532 #define R_USB_IRQ_READ__iso_eot__MIN 0
23533 #define R_USB_IRQ_READ__intr_eot__MIN 0
23534 #define R_USB_IRQ_READ__ctl_eot__MIN 0
23535 #define R_USB_IRQ_READ__bulk_eot__MIN 0
23536 #define R_USB_IRQ_READ__epid_attn__MIN 0
23537 #define R_USB_IRQ_READ__sof__MIN 0
23538 #define R_USB_IRQ_READ__port_status__MIN 0
23539 #define R_USB_IRQ_READ__ctl_status__MIN 0
23540
23541 #define R_USB_IRQ_READ__iso_eof__BITNR 13
23542 #define R_USB_IRQ_READ__intr_eof__BITNR 12
23543 #define R_USB_IRQ_READ__iso_eot__BITNR 11
23544 #define R_USB_IRQ_READ__intr_eot__BITNR 10
23545 #define R_USB_IRQ_READ__ctl_eot__BITNR 9
23546 #define R_USB_IRQ_READ__bulk_eot__BITNR 8
23547 #define R_USB_IRQ_READ__epid_attn__BITNR 3
23548 #define R_USB_IRQ_READ__sof__BITNR 2
23549 #define R_USB_IRQ_READ__port_status__BITNR 1
23550 #define R_USB_IRQ_READ__ctl_status__BITNR 0
23551
23552 #define R_USB_IRQ_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM
23553 #define R_USB_IRQ_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM
23554 #define R_USB_IRQ_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM
23555 #define R_USB_IRQ_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM
23556 #define R_USB_IRQ_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
23557 #define R_USB_IRQ_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
23558 #define R_USB_IRQ_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM
23559 #define R_USB_IRQ_READ__sof__sof__VAL REG_VAL_ENUM
23560 #define R_USB_IRQ_READ__port_status__port_status__VAL REG_VAL_ENUM
23561 #define R_USB_IRQ_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM
23562
23563 #define R_USB_IRQ_READ__iso_eof__iso_eof__no_pend 0
23564 #define R_USB_IRQ_READ__iso_eof__iso_eof__pend 1
23565 #define R_USB_IRQ_READ__intr_eof__intr_eof__no_pend 0
23566 #define R_USB_IRQ_READ__intr_eof__intr_eof__pend 1
23567 #define R_USB_IRQ_READ__iso_eot__iso_eot__no_pend 0
23568 #define R_USB_IRQ_READ__iso_eot__iso_eot__pend 1
23569 #define R_USB_IRQ_READ__intr_eot__intr_eot__no_pend 0
23570 #define R_USB_IRQ_READ__intr_eot__intr_eot__pend 1
23571 #define R_USB_IRQ_READ__ctl_eot__ctl_eot__no_pend 0
23572 #define R_USB_IRQ_READ__ctl_eot__ctl_eot__pend 1
23573 #define R_USB_IRQ_READ__bulk_eot__bulk_eot__no_pend 0
23574 #define R_USB_IRQ_READ__bulk_eot__bulk_eot__pend 1
23575 #define R_USB_IRQ_READ__epid_attn__epid_attn__no_pend 0
23576 #define R_USB_IRQ_READ__epid_attn__epid_attn__pend 1
23577 #define R_USB_IRQ_READ__sof__sof__no_pend 0
23578 #define R_USB_IRQ_READ__sof__sof__pend 1
23579 #define R_USB_IRQ_READ__port_status__port_status__no_pend 0
23580 #define R_USB_IRQ_READ__port_status__port_status__pend 1
23581 #define R_USB_IRQ_READ__ctl_status__ctl_status__no_pend 0
23582 #define R_USB_IRQ_READ__ctl_status__ctl_status__pend 1
23583
23584 #endif
23585
23586 /*
23587 * R_USB_IRQ_READ_DEV
23588 * - type: RO
23589 * - addr: 0xb0000206
23590 * - group: USB interface control registers
23591 */
23592
23593 #if USE_GROUP__USB_interface_control_registers
23594
23595 #define R_USB_IRQ_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206)
23596 #define R_USB_IRQ_READ_DEV__SVAL REG_SVAL_SHADOW
23597 #define R_USB_IRQ_READ_DEV__SVAL_I REG_SVAL_I_SHADOW
23598 #define R_USB_IRQ_READ_DEV__TYPECAST REG_TYPECAST_UWORD
23599 #define R_USB_IRQ_READ_DEV__TYPE (REG_UWORD)
23600 #define R_USB_IRQ_READ_DEV__GET REG_GET_RO
23601 #define R_USB_IRQ_READ_DEV__IGET REG_IGET_RO
23602 #define R_USB_IRQ_READ_DEV__SET REG_SET_RO
23603 #define R_USB_IRQ_READ_DEV__ISET REG_ISET_RO
23604 #define R_USB_IRQ_READ_DEV__SET_VAL REG_SET_VAL_RO
23605 #define R_USB_IRQ_READ_DEV__EQL REG_EQL_RO
23606 #define R_USB_IRQ_READ_DEV__IEQL REG_IEQL_RO
23607 #define R_USB_IRQ_READ_DEV__RD REG_RD_RO
23608 #define R_USB_IRQ_READ_DEV__IRD REG_IRD_RO
23609 #define R_USB_IRQ_READ_DEV__WR REG_WR_RO
23610 #define R_USB_IRQ_READ_DEV__IWR REG_IWR_RO
23611
23612 #define R_USB_IRQ_READ_DEV__READ(addr) \
23613 (*(addr))
23614
23615 #define R_USB_IRQ_READ_DEV__out_eot__out_eot__MASK 0x00001000U
23616 #define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
23617 #define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
23618 #define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
23619 #define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
23620 #define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U
23621 #define R_USB_IRQ_READ_DEV__sof__sof__MASK 0x00000004U
23622 #define R_USB_IRQ_READ_DEV__port_status__port_status__MASK 0x00000002U
23623 #define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U
23624
23625 #define R_USB_IRQ_READ_DEV__out_eot__MAX 0x1
23626 #define R_USB_IRQ_READ_DEV__ep3_in_eot__MAX 0x1
23627 #define R_USB_IRQ_READ_DEV__ep2_in_eot__MAX 0x1
23628 #define R_USB_IRQ_READ_DEV__ep1_in_eot__MAX 0x1
23629 #define R_USB_IRQ_READ_DEV__ep0_in_eot__MAX 0x1
23630 #define R_USB_IRQ_READ_DEV__epid_attn__MAX 0x1
23631 #define R_USB_IRQ_READ_DEV__sof__MAX 0x1
23632 #define R_USB_IRQ_READ_DEV__port_status__MAX 0x1
23633 #define R_USB_IRQ_READ_DEV__ctl_status__MAX 0x1
23634
23635 #define R_USB_IRQ_READ_DEV__out_eot__MIN 0
23636 #define R_USB_IRQ_READ_DEV__ep3_in_eot__MIN 0
23637 #define R_USB_IRQ_READ_DEV__ep2_in_eot__MIN 0
23638 #define R_USB_IRQ_READ_DEV__ep1_in_eot__MIN 0
23639 #define R_USB_IRQ_READ_DEV__ep0_in_eot__MIN 0
23640 #define R_USB_IRQ_READ_DEV__epid_attn__MIN 0
23641 #define R_USB_IRQ_READ_DEV__sof__MIN 0
23642 #define R_USB_IRQ_READ_DEV__port_status__MIN 0
23643 #define R_USB_IRQ_READ_DEV__ctl_status__MIN 0
23644
23645 #define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
23646 #define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
23647 #define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
23648 #define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
23649 #define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
23650 #define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
23651 #define R_USB_IRQ_READ_DEV__sof__BITNR 2
23652 #define R_USB_IRQ_READ_DEV__port_status__BITNR 1
23653 #define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
23654
23655 #define R_USB_IRQ_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
23656 #define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
23657 #define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
23658 #define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
23659 #define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
23660 #define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
23661 #define R_USB_IRQ_READ_DEV__sof__sof__VAL REG_VAL_ENUM
23662 #define R_USB_IRQ_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM
23663 #define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
23664
23665 #define R_USB_IRQ_READ_DEV__out_eot__out_eot__no_pend 0
23666 #define R_USB_IRQ_READ_DEV__out_eot__out_eot__pend 1
23667 #define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0
23668 #define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1
23669 #define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0
23670 #define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1
23671 #define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0
23672 #define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1
23673 #define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0
23674 #define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1
23675 #define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__no_pend 0
23676 #define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__pend 1
23677 #define R_USB_IRQ_READ_DEV__sof__sof__no_pend 0
23678 #define R_USB_IRQ_READ_DEV__sof__sof__pend 1
23679 #define R_USB_IRQ_READ_DEV__port_status__port_status__no_pend 0
23680 #define R_USB_IRQ_READ_DEV__port_status__port_status__pend 1
23681 #define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__no_pend 0
23682 #define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__pend 1
23683
23684 #endif
23685
23686 /*
23687 * R_USB_PORT1_DISABLE
23688 * - type: WO
23689 * - addr: 0xb000006a
23690 * - group: USB interface control registers
23691 */
23692
23693 #if USE_GROUP__USB_interface_control_registers
23694
23695 #define R_USB_PORT1_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb000006a)
23696
23697 #ifndef REG_NO_SHADOW
23698 #define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2))
23699 #define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2))
23700 #else /* REG_NO_SHADOW */
23701 #define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
23702 #define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
23703 #endif /* REG_NO_SHADOW */
23704
23705 #define R_USB_PORT1_DISABLE__STYPECAST REG_STYPECAST_BYTE
23706 #define R_USB_PORT1_DISABLE__SVAL REG_SVAL_SHADOW
23707 #define R_USB_PORT1_DISABLE__SVAL_I REG_SVAL_I_SHADOW
23708 #define R_USB_PORT1_DISABLE__TYPECAST REG_TYPECAST_BYTE
23709 #define R_USB_PORT1_DISABLE__TYPE (REG_BYTE)
23710 #define R_USB_PORT1_DISABLE__GET REG_GET_WO
23711 #define R_USB_PORT1_DISABLE__IGET REG_IGET_WO
23712 #define R_USB_PORT1_DISABLE__SET REG_SET_WO
23713 #define R_USB_PORT1_DISABLE__ISET REG_ISET_WO
23714 #define R_USB_PORT1_DISABLE__SET_VAL REG_SET_VAL_WO
23715 #define R_USB_PORT1_DISABLE__EQL REG_EQL_WO
23716 #define R_USB_PORT1_DISABLE__IEQL REG_IEQL_WO
23717 #define R_USB_PORT1_DISABLE__RD REG_RD_WO
23718 #define R_USB_PORT1_DISABLE__IRD REG_IRD_WO
23719 #define R_USB_PORT1_DISABLE__WR REG_WR_WO
23720 #define R_USB_PORT1_DISABLE__IWR REG_IWR_WO
23721
23722 #define R_USB_PORT1_DISABLE__WRITE(addr,value) \
23723 (*(addr) = (value))
23724
23725 #define R_USB_PORT1_DISABLE__disable__disable__MASK 0x00000001U
23726
23727 #define R_USB_PORT1_DISABLE__disable__MAX 0x1
23728
23729 #define R_USB_PORT1_DISABLE__disable__MIN 0
23730
23731 #define R_USB_PORT1_DISABLE__disable__BITNR 0
23732
23733 #define R_USB_PORT1_DISABLE__disable__disable__VAL REG_VAL_ENUM
23734
23735 #define R_USB_PORT1_DISABLE__disable__disable__no 1
23736 #define R_USB_PORT1_DISABLE__disable__disable__yes 0
23737
23738 #endif
23739
23740 /*
23741 * R_USB_PORT2_DISABLE
23742 * - type: WO
23743 * - addr: 0xb0000052
23744 * - group: USB interface control registers
23745 */
23746
23747 #if USE_GROUP__USB_interface_control_registers
23748
23749 #define R_USB_PORT2_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb0000052)
23750
23751 #ifndef REG_NO_SHADOW
23752 #define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
23753 #define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
23754 #else /* REG_NO_SHADOW */
23755 #define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
23756 #define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
23757 #endif /* REG_NO_SHADOW */
23758
23759 #define R_USB_PORT2_DISABLE__STYPECAST REG_STYPECAST_BYTE
23760 #define R_USB_PORT2_DISABLE__SVAL REG_SVAL_SHADOW
23761 #define R_USB_PORT2_DISABLE__SVAL_I REG_SVAL_I_SHADOW
23762 #define R_USB_PORT2_DISABLE__TYPECAST REG_TYPECAST_BYTE
23763 #define R_USB_PORT2_DISABLE__TYPE (REG_BYTE)
23764 #define R_USB_PORT2_DISABLE__GET REG_GET_WO
23765 #define R_USB_PORT2_DISABLE__IGET REG_IGET_WO
23766 #define R_USB_PORT2_DISABLE__SET REG_SET_WO
23767 #define R_USB_PORT2_DISABLE__ISET REG_ISET_WO
23768 #define R_USB_PORT2_DISABLE__SET_VAL REG_SET_VAL_WO
23769 #define R_USB_PORT2_DISABLE__EQL REG_EQL_WO
23770 #define R_USB_PORT2_DISABLE__IEQL REG_IEQL_WO
23771 #define R_USB_PORT2_DISABLE__RD REG_RD_WO
23772 #define R_USB_PORT2_DISABLE__IRD REG_IRD_WO
23773 #define R_USB_PORT2_DISABLE__WR REG_WR_WO
23774 #define R_USB_PORT2_DISABLE__IWR REG_IWR_WO
23775
23776 #define R_USB_PORT2_DISABLE__WRITE(addr,value) \
23777 (*(addr) = (value))
23778
23779 #define R_USB_PORT2_DISABLE__disable__disable__MASK 0x00000001U
23780
23781 #define R_USB_PORT2_DISABLE__disable__MAX 0x1
23782
23783 #define R_USB_PORT2_DISABLE__disable__MIN 0
23784
23785 #define R_USB_PORT2_DISABLE__disable__BITNR 0
23786
23787 #define R_USB_PORT2_DISABLE__disable__disable__VAL REG_VAL_ENUM
23788
23789 #define R_USB_PORT2_DISABLE__disable__disable__no 1
23790 #define R_USB_PORT2_DISABLE__disable__disable__yes 0
23791
23792 #endif
23793
23794 /*
23795 * R_USB_REVISION
23796 * - type: RO
23797 * - addr: 0xb0000200
23798 * - group: USB interface control registers
23799 */
23800
23801 #if USE_GROUP__USB_interface_control_registers
23802
23803 #define R_USB_REVISION__ADDR (REG_TYPECAST_BYTE 0xb0000200)
23804 #define R_USB_REVISION__SVAL REG_SVAL_SHADOW
23805 #define R_USB_REVISION__SVAL_I REG_SVAL_I_SHADOW
23806 #define R_USB_REVISION__TYPECAST REG_TYPECAST_BYTE
23807 #define R_USB_REVISION__TYPE (REG_BYTE)
23808 #define R_USB_REVISION__GET REG_GET_RO
23809 #define R_USB_REVISION__IGET REG_IGET_RO
23810 #define R_USB_REVISION__SET REG_SET_RO
23811 #define R_USB_REVISION__ISET REG_ISET_RO
23812 #define R_USB_REVISION__SET_VAL REG_SET_VAL_RO
23813 #define R_USB_REVISION__EQL REG_EQL_RO
23814 #define R_USB_REVISION__IEQL REG_IEQL_RO
23815 #define R_USB_REVISION__RD REG_RD_RO
23816 #define R_USB_REVISION__IRD REG_IRD_RO
23817 #define R_USB_REVISION__WR REG_WR_RO
23818 #define R_USB_REVISION__IWR REG_IWR_RO
23819
23820 #define R_USB_REVISION__READ(addr) \
23821 (*(addr))
23822
23823 #define R_USB_REVISION__major__major__MASK 0x000000f0U
23824 #define R_USB_REVISION__minor__minor__MASK 0x0000000fU
23825
23826 #define R_USB_REVISION__major__MAX 0xf
23827 #define R_USB_REVISION__minor__MAX 0xf
23828
23829 #define R_USB_REVISION__major__MIN 0
23830 #define R_USB_REVISION__minor__MIN 0
23831
23832 #define R_USB_REVISION__major__BITNR 4
23833 #define R_USB_REVISION__minor__BITNR 0
23834
23835 #define R_USB_REVISION__major__major__VAL REG_VAL_VAL
23836 #define R_USB_REVISION__minor__minor__VAL REG_VAL_ENUM
23837
23838 #define R_USB_REVISION__minor__minor__v1_v2 1
23839 #define R_USB_REVISION__minor__minor__v3 0
23840
23841 #endif
23842
23843 /*
23844 * R_USB_RH_PORT_STATUS_1
23845 * - type: RO
23846 * - addr: 0xb0000218
23847 * - group: USB interface control registers
23848 */
23849
23850 #if USE_GROUP__USB_interface_control_registers
23851
23852 #define R_USB_RH_PORT_STATUS_1__ADDR (REG_TYPECAST_UWORD 0xb0000218)
23853 #define R_USB_RH_PORT_STATUS_1__SVAL REG_SVAL_SHADOW
23854 #define R_USB_RH_PORT_STATUS_1__SVAL_I REG_SVAL_I_SHADOW
23855 #define R_USB_RH_PORT_STATUS_1__TYPECAST REG_TYPECAST_UWORD
23856 #define R_USB_RH_PORT_STATUS_1__TYPE (REG_UWORD)
23857 #define R_USB_RH_PORT_STATUS_1__GET REG_GET_RO
23858 #define R_USB_RH_PORT_STATUS_1__IGET REG_IGET_RO
23859 #define R_USB_RH_PORT_STATUS_1__SET REG_SET_RO
23860 #define R_USB_RH_PORT_STATUS_1__ISET REG_ISET_RO
23861 #define R_USB_RH_PORT_STATUS_1__SET_VAL REG_SET_VAL_RO
23862 #define R_USB_RH_PORT_STATUS_1__EQL REG_EQL_RO
23863 #define R_USB_RH_PORT_STATUS_1__IEQL REG_IEQL_RO
23864 #define R_USB_RH_PORT_STATUS_1__RD REG_RD_RO
23865 #define R_USB_RH_PORT_STATUS_1__IRD REG_IRD_RO
23866 #define R_USB_RH_PORT_STATUS_1__WR REG_WR_RO
23867 #define R_USB_RH_PORT_STATUS_1__IWR REG_IWR_RO
23868
23869 #define R_USB_RH_PORT_STATUS_1__READ(addr) \
23870 (*(addr))
23871
23872 #define R_USB_RH_PORT_STATUS_1__speed__speed__MASK 0x00000200U
23873 #define R_USB_RH_PORT_STATUS_1__power__power__MASK 0x00000100U
23874 #define R_USB_RH_PORT_STATUS_1__reset__reset__MASK 0x00000010U
23875 #define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__MASK 0x00000008U
23876 #define R_USB_RH_PORT_STATUS_1__suspended__suspended__MASK 0x00000004U
23877 #define R_USB_RH_PORT_STATUS_1__enabled__enabled__MASK 0x00000002U
23878 #define R_USB_RH_PORT_STATUS_1__connected__connected__MASK 0x00000001U
23879
23880 #define R_USB_RH_PORT_STATUS_1__speed__MAX 0x1
23881 #define R_USB_RH_PORT_STATUS_1__power__MAX 0x1
23882 #define R_USB_RH_PORT_STATUS_1__reset__MAX 0x1
23883 #define R_USB_RH_PORT_STATUS_1__overcurrent__MAX 0x1
23884 #define R_USB_RH_PORT_STATUS_1__suspended__MAX 0x1
23885 #define R_USB_RH_PORT_STATUS_1__enabled__MAX 0x1
23886 #define R_USB_RH_PORT_STATUS_1__connected__MAX 0x1
23887
23888 #define R_USB_RH_PORT_STATUS_1__speed__MIN 0
23889 #define R_USB_RH_PORT_STATUS_1__power__MIN 0
23890 #define R_USB_RH_PORT_STATUS_1__reset__MIN 0
23891 #define R_USB_RH_PORT_STATUS_1__overcurrent__MIN 0
23892 #define R_USB_RH_PORT_STATUS_1__suspended__MIN 0
23893 #define R_USB_RH_PORT_STATUS_1__enabled__MIN 0
23894 #define R_USB_RH_PORT_STATUS_1__connected__MIN 0
23895
23896 #define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
23897 #define R_USB_RH_PORT_STATUS_1__power__BITNR 8
23898 #define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
23899 #define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
23900 #define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
23901 #define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
23902 #define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
23903
23904 #define R_USB_RH_PORT_STATUS_1__speed__speed__VAL REG_VAL_ENUM
23905 #define R_USB_RH_PORT_STATUS_1__power__power__VAL REG_VAL_VAL
23906 #define R_USB_RH_PORT_STATUS_1__reset__reset__VAL REG_VAL_ENUM
23907 #define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__VAL REG_VAL_ENUM
23908 #define R_USB_RH_PORT_STATUS_1__suspended__suspended__VAL REG_VAL_ENUM
23909 #define R_USB_RH_PORT_STATUS_1__enabled__enabled__VAL REG_VAL_ENUM
23910 #define R_USB_RH_PORT_STATUS_1__connected__connected__VAL REG_VAL_ENUM
23911
23912 #define R_USB_RH_PORT_STATUS_1__speed__speed__full 0
23913 #define R_USB_RH_PORT_STATUS_1__speed__speed__low 1
23914 #define R_USB_RH_PORT_STATUS_1__reset__reset__no 0
23915 #define R_USB_RH_PORT_STATUS_1__reset__reset__yes 1
23916 #define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__no 0
23917 #define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__yes 1
23918 #define R_USB_RH_PORT_STATUS_1__suspended__suspended__no 0
23919 #define R_USB_RH_PORT_STATUS_1__suspended__suspended__yes 1
23920 #define R_USB_RH_PORT_STATUS_1__enabled__enabled__no 0
23921 #define R_USB_RH_PORT_STATUS_1__enabled__enabled__yes 1
23922 #define R_USB_RH_PORT_STATUS_1__connected__connected__no 0
23923 #define R_USB_RH_PORT_STATUS_1__connected__connected__yes 1
23924
23925 #endif
23926
23927 /*
23928 * R_USB_RH_PORT_STATUS_2
23929 * - type: RO
23930 * - addr: 0xb000021a
23931 * - group: USB interface control registers
23932 */
23933
23934 #if USE_GROUP__USB_interface_control_registers
23935
23936 #define R_USB_RH_PORT_STATUS_2__ADDR (REG_TYPECAST_UWORD 0xb000021a)
23937 #define R_USB_RH_PORT_STATUS_2__SVAL REG_SVAL_SHADOW
23938 #define R_USB_RH_PORT_STATUS_2__SVAL_I REG_SVAL_I_SHADOW
23939 #define R_USB_RH_PORT_STATUS_2__TYPECAST REG_TYPECAST_UWORD
23940 #define R_USB_RH_PORT_STATUS_2__TYPE (REG_UWORD)
23941 #define R_USB_RH_PORT_STATUS_2__GET REG_GET_RO
23942 #define R_USB_RH_PORT_STATUS_2__IGET REG_IGET_RO
23943 #define R_USB_RH_PORT_STATUS_2__SET REG_SET_RO
23944 #define R_USB_RH_PORT_STATUS_2__ISET REG_ISET_RO
23945 #define R_USB_RH_PORT_STATUS_2__SET_VAL REG_SET_VAL_RO
23946 #define R_USB_RH_PORT_STATUS_2__EQL REG_EQL_RO
23947 #define R_USB_RH_PORT_STATUS_2__IEQL REG_IEQL_RO
23948 #define R_USB_RH_PORT_STATUS_2__RD REG_RD_RO
23949 #define R_USB_RH_PORT_STATUS_2__IRD REG_IRD_RO
23950 #define R_USB_RH_PORT_STATUS_2__WR REG_WR_RO
23951 #define R_USB_RH_PORT_STATUS_2__IWR REG_IWR_RO
23952
23953 #define R_USB_RH_PORT_STATUS_2__READ(addr) \
23954 (*(addr))
23955
23956 #define R_USB_RH_PORT_STATUS_2__speed__speed__MASK 0x00000200U
23957 #define R_USB_RH_PORT_STATUS_2__power__power__MASK 0x00000100U
23958 #define R_USB_RH_PORT_STATUS_2__reset__reset__MASK 0x00000010U
23959 #define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__MASK 0x00000008U
23960 #define R_USB_RH_PORT_STATUS_2__suspended__suspended__MASK 0x00000004U
23961 #define R_USB_RH_PORT_STATUS_2__enabled__enabled__MASK 0x00000002U
23962 #define R_USB_RH_PORT_STATUS_2__connected__connected__MASK 0x00000001U
23963
23964 #define R_USB_RH_PORT_STATUS_2__speed__MAX 0x1
23965 #define R_USB_RH_PORT_STATUS_2__power__MAX 0x1
23966 #define R_USB_RH_PORT_STATUS_2__reset__MAX 0x1
23967 #define R_USB_RH_PORT_STATUS_2__overcurrent__MAX 0x1
23968 #define R_USB_RH_PORT_STATUS_2__suspended__MAX 0x1
23969 #define R_USB_RH_PORT_STATUS_2__enabled__MAX 0x1
23970 #define R_USB_RH_PORT_STATUS_2__connected__MAX 0x1
23971
23972 #define R_USB_RH_PORT_STATUS_2__speed__MIN 0
23973 #define R_USB_RH_PORT_STATUS_2__power__MIN 0
23974 #define R_USB_RH_PORT_STATUS_2__reset__MIN 0
23975 #define R_USB_RH_PORT_STATUS_2__overcurrent__MIN 0
23976 #define R_USB_RH_PORT_STATUS_2__suspended__MIN 0
23977 #define R_USB_RH_PORT_STATUS_2__enabled__MIN 0
23978 #define R_USB_RH_PORT_STATUS_2__connected__MIN 0
23979
23980 #define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
23981 #define R_USB_RH_PORT_STATUS_2__power__BITNR 8
23982 #define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
23983 #define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
23984 #define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
23985 #define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
23986 #define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
23987
23988 #define R_USB_RH_PORT_STATUS_2__speed__speed__VAL REG_VAL_ENUM
23989 #define R_USB_RH_PORT_STATUS_2__power__power__VAL REG_VAL_VAL
23990 #define R_USB_RH_PORT_STATUS_2__reset__reset__VAL REG_VAL_ENUM
23991 #define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__VAL REG_VAL_ENUM
23992 #define R_USB_RH_PORT_STATUS_2__suspended__suspended__VAL REG_VAL_ENUM
23993 #define R_USB_RH_PORT_STATUS_2__enabled__enabled__VAL REG_VAL_ENUM
23994 #define R_USB_RH_PORT_STATUS_2__connected__connected__VAL REG_VAL_ENUM
23995
23996 #define R_USB_RH_PORT_STATUS_2__speed__speed__full 0
23997 #define R_USB_RH_PORT_STATUS_2__speed__speed__low 1
23998 #define R_USB_RH_PORT_STATUS_2__reset__reset__no 0
23999 #define R_USB_RH_PORT_STATUS_2__reset__reset__yes 1
24000 #define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__no 0
24001 #define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__yes 1
24002 #define R_USB_RH_PORT_STATUS_2__suspended__suspended__no 0
24003 #define R_USB_RH_PORT_STATUS_2__suspended__suspended__yes 1
24004 #define R_USB_RH_PORT_STATUS_2__enabled__enabled__no 0
24005 #define R_USB_RH_PORT_STATUS_2__enabled__enabled__yes 1
24006 #define R_USB_RH_PORT_STATUS_2__connected__connected__no 0
24007 #define R_USB_RH_PORT_STATUS_2__connected__connected__yes 1
24008
24009 #endif
24010
24011 /*
24012 * R_USB_RH_STATUS
24013 * - type: RO
24014 * - addr: 0xb0000203
24015 * - group: USB interface control registers
24016 */
24017
24018 #if USE_GROUP__USB_interface_control_registers
24019
24020 #define R_USB_RH_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000203)
24021 #define R_USB_RH_STATUS__SVAL REG_SVAL_SHADOW
24022 #define R_USB_RH_STATUS__SVAL_I REG_SVAL_I_SHADOW
24023 #define R_USB_RH_STATUS__TYPECAST REG_TYPECAST_BYTE
24024 #define R_USB_RH_STATUS__TYPE (REG_BYTE)
24025 #define R_USB_RH_STATUS__GET REG_GET_RO
24026 #define R_USB_RH_STATUS__IGET REG_IGET_RO
24027 #define R_USB_RH_STATUS__SET REG_SET_RO
24028 #define R_USB_RH_STATUS__ISET REG_ISET_RO
24029 #define R_USB_RH_STATUS__SET_VAL REG_SET_VAL_RO
24030 #define R_USB_RH_STATUS__EQL REG_EQL_RO
24031 #define R_USB_RH_STATUS__IEQL REG_IEQL_RO
24032 #define R_USB_RH_STATUS__RD REG_RD_RO
24033 #define R_USB_RH_STATUS__IRD REG_IRD_RO
24034 #define R_USB_RH_STATUS__WR REG_WR_RO
24035 #define R_USB_RH_STATUS__IWR REG_IWR_RO
24036
24037 #define R_USB_RH_STATUS__READ(addr) \
24038 (*(addr))
24039
24040 #define R_USB_RH_STATUS__babble2__babble2__MASK 0x00000080U
24041 #define R_USB_RH_STATUS__babble1__babble1__MASK 0x00000040U
24042 #define R_USB_RH_STATUS__bus1__bus1__MASK 0x00000030U
24043 #define R_USB_RH_STATUS__bus2__bus2__MASK 0x0000000cU
24044 #define R_USB_RH_STATUS__nports__nports__MASK 0x00000003U
24045
24046 #define R_USB_RH_STATUS__babble2__MAX 0x1
24047 #define R_USB_RH_STATUS__babble1__MAX 0x1
24048 #define R_USB_RH_STATUS__bus1__MAX 0x3
24049 #define R_USB_RH_STATUS__bus2__MAX 0x3
24050 #define R_USB_RH_STATUS__nports__MAX 3
24051
24052 #define R_USB_RH_STATUS__babble2__MIN 0
24053 #define R_USB_RH_STATUS__babble1__MIN 0
24054 #define R_USB_RH_STATUS__bus1__MIN 0
24055 #define R_USB_RH_STATUS__bus2__MIN 0
24056 #define R_USB_RH_STATUS__nports__MIN 0
24057
24058 #define R_USB_RH_STATUS__babble2__BITNR 7
24059 #define R_USB_RH_STATUS__babble1__BITNR 6
24060 #define R_USB_RH_STATUS__bus1__BITNR 4
24061 #define R_USB_RH_STATUS__bus2__BITNR 2
24062 #define R_USB_RH_STATUS__nports__BITNR 0
24063
24064 #define R_USB_RH_STATUS__babble2__babble2__VAL REG_VAL_ENUM
24065 #define R_USB_RH_STATUS__babble1__babble1__VAL REG_VAL_ENUM
24066 #define R_USB_RH_STATUS__bus1__bus1__VAL REG_VAL_ENUM
24067 #define R_USB_RH_STATUS__bus2__bus2__VAL REG_VAL_ENUM
24068 #define R_USB_RH_STATUS__nports__nports__VAL REG_VAL_VAL
24069
24070 #define R_USB_RH_STATUS__babble2__babble2__no 0
24071 #define R_USB_RH_STATUS__babble2__babble2__yes 1
24072 #define R_USB_RH_STATUS__babble1__babble1__no 0
24073 #define R_USB_RH_STATUS__babble1__babble1__yes 1
24074 #define R_USB_RH_STATUS__bus1__bus1__Diff0 1
24075 #define R_USB_RH_STATUS__bus1__bus1__Diff1 2
24076 #define R_USB_RH_STATUS__bus1__bus1__SE0 0
24077 #define R_USB_RH_STATUS__bus1__bus1__SE1 3
24078 #define R_USB_RH_STATUS__bus2__bus2__Diff0 1
24079 #define R_USB_RH_STATUS__bus2__bus2__Diff1 2
24080 #define R_USB_RH_STATUS__bus2__bus2__SE0 0
24081 #define R_USB_RH_STATUS__bus2__bus2__SE1 3
24082
24083 #endif
24084
24085 /*
24086 * R_USB_SNMP_TERROR
24087 * - type: RW
24088 * - addr: 0xb0000220
24089 * - group: USB interface control registers
24090 */
24091
24092 #if USE_GROUP__USB_interface_control_registers
24093
24094 #define R_USB_SNMP_TERROR__ADDR (REG_TYPECAST_UDWORD 0xb0000220)
24095 #define R_USB_SNMP_TERROR__SVAL REG_SVAL_SHADOW
24096 #define R_USB_SNMP_TERROR__SVAL_I REG_SVAL_I_SHADOW
24097 #define R_USB_SNMP_TERROR__TYPECAST REG_TYPECAST_UDWORD
24098 #define R_USB_SNMP_TERROR__TYPE (REG_UDWORD)
24099 #define R_USB_SNMP_TERROR__GET REG_GET_RW
24100 #define R_USB_SNMP_TERROR__IGET REG_IGET_RW
24101 #define R_USB_SNMP_TERROR__SET REG_SET_RW
24102 #define R_USB_SNMP_TERROR__ISET REG_ISET_RW
24103 #define R_USB_SNMP_TERROR__SET_VAL REG_SET_VAL_RW
24104 #define R_USB_SNMP_TERROR__EQL REG_EQL_RW
24105 #define R_USB_SNMP_TERROR__IEQL REG_IEQL_RW
24106 #define R_USB_SNMP_TERROR__RD REG_RD_RW
24107 #define R_USB_SNMP_TERROR__IRD REG_IRD_RW
24108 #define R_USB_SNMP_TERROR__WR REG_WR_RW
24109 #define R_USB_SNMP_TERROR__IWR REG_IWR_RW
24110
24111 #define R_USB_SNMP_TERROR__WRITE(addr,value) \
24112 (*(addr) = (value))
24113 #define R_USB_SNMP_TERROR__READ(addr) \
24114 (*(addr))
24115
24116 #define R_USB_SNMP_TERROR__value__value__MASK 0xffffffffU
24117
24118 #define R_USB_SNMP_TERROR__value__MAX 0xffffffff
24119
24120 #define R_USB_SNMP_TERROR__value__MIN 0
24121
24122 #define R_USB_SNMP_TERROR__value__BITNR 0
24123
24124 #define R_USB_SNMP_TERROR__value__value__VAL REG_VAL_VAL
24125
24126
24127 #endif
24128
24129 /*
24130 * R_USB_STATUS
24131 * - type: RO
24132 * - addr: 0xb0000202
24133 * - group: USB interface control registers
24134 */
24135
24136 #if USE_GROUP__USB_interface_control_registers
24137
24138 #define R_USB_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000202)
24139 #define R_USB_STATUS__SVAL REG_SVAL_SHADOW
24140 #define R_USB_STATUS__SVAL_I REG_SVAL_I_SHADOW
24141 #define R_USB_STATUS__TYPECAST REG_TYPECAST_BYTE
24142 #define R_USB_STATUS__TYPE (REG_BYTE)
24143 #define R_USB_STATUS__GET REG_GET_RO
24144 #define R_USB_STATUS__IGET REG_IGET_RO
24145 #define R_USB_STATUS__SET REG_SET_RO
24146 #define R_USB_STATUS__ISET REG_ISET_RO
24147 #define R_USB_STATUS__SET_VAL REG_SET_VAL_RO
24148 #define R_USB_STATUS__EQL REG_EQL_RO
24149 #define R_USB_STATUS__IEQL REG_IEQL_RO
24150 #define R_USB_STATUS__RD REG_RD_RO
24151 #define R_USB_STATUS__IRD REG_IRD_RO
24152 #define R_USB_STATUS__WR REG_WR_RO
24153 #define R_USB_STATUS__IWR REG_IWR_RO
24154
24155 #define R_USB_STATUS__READ(addr) \
24156 (*(addr))
24157
24158 #define R_USB_STATUS__ourun__ourun__MASK 0x00000020U
24159 #define R_USB_STATUS__perror__perror__MASK 0x00000010U
24160 #define R_USB_STATUS__device_mode__device_mode__MASK 0x00000008U
24161 #define R_USB_STATUS__host_mode__host_mode__MASK 0x00000004U
24162 #define R_USB_STATUS__started__started__MASK 0x00000002U
24163 #define R_USB_STATUS__running__running__MASK 0x00000001U
24164
24165 #define R_USB_STATUS__ourun__MAX 0x1
24166 #define R_USB_STATUS__perror__MAX 0x1
24167 #define R_USB_STATUS__device_mode__MAX 0x1
24168 #define R_USB_STATUS__host_mode__MAX 0x1
24169 #define R_USB_STATUS__started__MAX 0x1
24170 #define R_USB_STATUS__running__MAX 0x1
24171
24172 #define R_USB_STATUS__ourun__MIN 0
24173 #define R_USB_STATUS__perror__MIN 0
24174 #define R_USB_STATUS__device_mode__MIN 0
24175 #define R_USB_STATUS__host_mode__MIN 0
24176 #define R_USB_STATUS__started__MIN 0
24177 #define R_USB_STATUS__running__MIN 0
24178
24179 #define R_USB_STATUS__ourun__BITNR 5
24180 #define R_USB_STATUS__perror__BITNR 4
24181 #define R_USB_STATUS__device_mode__BITNR 3
24182 #define R_USB_STATUS__host_mode__BITNR 2
24183 #define R_USB_STATUS__started__BITNR 1
24184 #define R_USB_STATUS__running__BITNR 0
24185
24186 #define R_USB_STATUS__ourun__ourun__VAL REG_VAL_ENUM
24187 #define R_USB_STATUS__perror__perror__VAL REG_VAL_ENUM
24188 #define R_USB_STATUS__device_mode__device_mode__VAL REG_VAL_ENUM
24189 #define R_USB_STATUS__host_mode__host_mode__VAL REG_VAL_ENUM
24190 #define R_USB_STATUS__started__started__VAL REG_VAL_ENUM
24191 #define R_USB_STATUS__running__running__VAL REG_VAL_ENUM
24192
24193 #define R_USB_STATUS__ourun__ourun__no 0
24194 #define R_USB_STATUS__ourun__ourun__yes 1
24195 #define R_USB_STATUS__perror__perror__no 0
24196 #define R_USB_STATUS__perror__perror__yes 1
24197 #define R_USB_STATUS__device_mode__device_mode__no 0
24198 #define R_USB_STATUS__device_mode__device_mode__yes 1
24199 #define R_USB_STATUS__host_mode__host_mode__no 0
24200 #define R_USB_STATUS__host_mode__host_mode__yes 1
24201 #define R_USB_STATUS__started__started__no 0
24202 #define R_USB_STATUS__started__started__yes 1
24203 #define R_USB_STATUS__running__running__no 0
24204 #define R_USB_STATUS__running__running__yes 1
24205
24206 #endif
24207
24208 /*
24209 * R_VECT_MASK_CLR
24210 * - type: WO
24211 * - addr: 0xb00000d8
24212 * - group: Interrupt mask and status registers
24213 */
24214
24215 #if USE_GROUP__Interrupt_mask_and_status_registers
24216
24217 #define R_VECT_MASK_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d8)
24218
24219 #ifndef REG_NO_SHADOW
24220 #define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_CLR + 0))
24221 #define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_CLR + 0))
24222 #else /* REG_NO_SHADOW */
24223 #define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
24224 #define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
24225 #endif /* REG_NO_SHADOW */
24226
24227 #define R_VECT_MASK_CLR__STYPECAST REG_STYPECAST_UDWORD
24228 #define R_VECT_MASK_CLR__SVAL REG_SVAL_ZERO
24229 #define R_VECT_MASK_CLR__SVAL_I REG_SVAL_I_ZERO
24230 #define R_VECT_MASK_CLR__TYPECAST REG_TYPECAST_UDWORD
24231 #define R_VECT_MASK_CLR__TYPE (REG_UDWORD)
24232 #define R_VECT_MASK_CLR__GET REG_GET_WO
24233 #define R_VECT_MASK_CLR__IGET REG_IGET_WO
24234 #define R_VECT_MASK_CLR__SET REG_SET_WO
24235 #define R_VECT_MASK_CLR__ISET REG_ISET_WO
24236 #define R_VECT_MASK_CLR__SET_VAL REG_SET_VAL_WO
24237 #define R_VECT_MASK_CLR__EQL REG_EQL_WO
24238 #define R_VECT_MASK_CLR__IEQL REG_IEQL_WO
24239 #define R_VECT_MASK_CLR__RD REG_RD_WO
24240 #define R_VECT_MASK_CLR__IRD REG_IRD_WO
24241 #define R_VECT_MASK_CLR__WR REG_WR_WO
24242 #define R_VECT_MASK_CLR__IWR REG_IWR_WO
24243
24244 #define R_VECT_MASK_CLR__WRITE(addr,value) \
24245 (*(addr) = (value))
24246
24247 #define R_VECT_MASK_CLR__usb__usb__MASK 0x80000000U
24248 #define R_VECT_MASK_CLR__dma9__dma9__MASK 0x02000000U
24249 #define R_VECT_MASK_CLR__dma8__dma8__MASK 0x01000000U
24250 #define R_VECT_MASK_CLR__dma7__dma7__MASK 0x00800000U
24251 #define R_VECT_MASK_CLR__dma6__dma6__MASK 0x00400000U
24252 #define R_VECT_MASK_CLR__dma5__dma5__MASK 0x00200000U
24253 #define R_VECT_MASK_CLR__dma4__dma4__MASK 0x00100000U
24254 #define R_VECT_MASK_CLR__dma3__dma3__MASK 0x00080000U
24255 #define R_VECT_MASK_CLR__dma2__dma2__MASK 0x00040000U
24256 #define R_VECT_MASK_CLR__dma1__dma1__MASK 0x00020000U
24257 #define R_VECT_MASK_CLR__dma0__dma0__MASK 0x00010000U
24258 #define R_VECT_MASK_CLR__ext_dma1__ext_dma1__MASK 0x00002000U
24259 #define R_VECT_MASK_CLR__ext_dma0__ext_dma0__MASK 0x00001000U
24260 #define R_VECT_MASK_CLR__pa__pa__MASK 0x00000800U
24261 #define R_VECT_MASK_CLR__irq_intnr__irq_intnr__MASK 0x00000400U
24262 #define R_VECT_MASK_CLR__sw__sw__MASK 0x00000200U
24263 #define R_VECT_MASK_CLR__serial__serial__MASK 0x00000100U
24264 #define R_VECT_MASK_CLR__snmp__snmp__MASK 0x00000080U
24265 #define R_VECT_MASK_CLR__network__network__MASK 0x00000040U
24266 #define R_VECT_MASK_CLR__scsi1__scsi1__MASK 0x00000020U
24267 #define R_VECT_MASK_CLR__par1__par1__MASK 0x00000020U
24268 #define R_VECT_MASK_CLR__scsi1__par1__MASK 0x00000020U
24269 #define R_VECT_MASK_CLR__scsi0__scsi0__MASK 0x00000010U
24270 #define R_VECT_MASK_CLR__par0__par0__MASK 0x00000010U
24271 #define R_VECT_MASK_CLR__scsi0__par0__MASK 0x00000010U
24272 #define R_VECT_MASK_CLR__ata__ata__MASK 0x00000010U
24273 #define R_VECT_MASK_CLR__scsi0__ata__MASK 0x00000010U
24274 #define R_VECT_MASK_CLR__mio__mio__MASK 0x00000010U
24275 #define R_VECT_MASK_CLR__scsi0__mio__MASK 0x00000010U
24276 #define R_VECT_MASK_CLR__timer1__timer1__MASK 0x00000008U
24277 #define R_VECT_MASK_CLR__timer0__timer0__MASK 0x00000004U
24278 #define R_VECT_MASK_CLR__nmi__nmi__MASK 0x00000002U
24279 #define R_VECT_MASK_CLR__some__some__MASK 0x00000001U
24280
24281 #define R_VECT_MASK_CLR__usb__MAX 0x1
24282 #define R_VECT_MASK_CLR__dma9__MAX 0x1
24283 #define R_VECT_MASK_CLR__dma8__MAX 0x1
24284 #define R_VECT_MASK_CLR__dma7__MAX 0x1
24285 #define R_VECT_MASK_CLR__dma6__MAX 0x1
24286 #define R_VECT_MASK_CLR__dma5__MAX 0x1
24287 #define R_VECT_MASK_CLR__dma4__MAX 0x1
24288 #define R_VECT_MASK_CLR__dma3__MAX 0x1
24289 #define R_VECT_MASK_CLR__dma2__MAX 0x1
24290 #define R_VECT_MASK_CLR__dma1__MAX 0x1
24291 #define R_VECT_MASK_CLR__dma0__MAX 0x1
24292 #define R_VECT_MASK_CLR__ext_dma1__MAX 0x1
24293 #define R_VECT_MASK_CLR__ext_dma0__MAX 0x1
24294 #define R_VECT_MASK_CLR__pa__MAX 0x1
24295 #define R_VECT_MASK_CLR__irq_intnr__MAX 0x1
24296 #define R_VECT_MASK_CLR__sw__MAX 0x1
24297 #define R_VECT_MASK_CLR__serial__MAX 0x1
24298 #define R_VECT_MASK_CLR__snmp__MAX 0x1
24299 #define R_VECT_MASK_CLR__network__MAX 0x1
24300 #define R_VECT_MASK_CLR__scsi1__MAX 0x1
24301 #define R_VECT_MASK_CLR__par1__MAX 0x1
24302 #define R_VECT_MASK_CLR__scsi0__MAX 0x1
24303 #define R_VECT_MASK_CLR__par0__MAX 0x1
24304 #define R_VECT_MASK_CLR__ata__MAX 0x1
24305 #define R_VECT_MASK_CLR__mio__MAX 0x1
24306 #define R_VECT_MASK_CLR__timer1__MAX 0x1
24307 #define R_VECT_MASK_CLR__timer0__MAX 0x1
24308 #define R_VECT_MASK_CLR__nmi__MAX 0x1
24309 #define R_VECT_MASK_CLR__some__MAX 0x1
24310
24311 #define R_VECT_MASK_CLR__usb__MIN 0
24312 #define R_VECT_MASK_CLR__dma9__MIN 0
24313 #define R_VECT_MASK_CLR__dma8__MIN 0
24314 #define R_VECT_MASK_CLR__dma7__MIN 0
24315 #define R_VECT_MASK_CLR__dma6__MIN 0
24316 #define R_VECT_MASK_CLR__dma5__MIN 0
24317 #define R_VECT_MASK_CLR__dma4__MIN 0
24318 #define R_VECT_MASK_CLR__dma3__MIN 0
24319 #define R_VECT_MASK_CLR__dma2__MIN 0
24320 #define R_VECT_MASK_CLR__dma1__MIN 0
24321 #define R_VECT_MASK_CLR__dma0__MIN 0
24322 #define R_VECT_MASK_CLR__ext_dma1__MIN 0
24323 #define R_VECT_MASK_CLR__ext_dma0__MIN 0
24324 #define R_VECT_MASK_CLR__pa__MIN 0
24325 #define R_VECT_MASK_CLR__irq_intnr__MIN 0
24326 #define R_VECT_MASK_CLR__sw__MIN 0
24327 #define R_VECT_MASK_CLR__serial__MIN 0
24328 #define R_VECT_MASK_CLR__snmp__MIN 0
24329 #define R_VECT_MASK_CLR__network__MIN 0
24330 #define R_VECT_MASK_CLR__scsi1__MIN 0
24331 #define R_VECT_MASK_CLR__par1__MIN 0
24332 #define R_VECT_MASK_CLR__scsi0__MIN 0
24333 #define R_VECT_MASK_CLR__par0__MIN 0
24334 #define R_VECT_MASK_CLR__ata__MIN 0
24335 #define R_VECT_MASK_CLR__mio__MIN 0
24336 #define R_VECT_MASK_CLR__timer1__MIN 0
24337 #define R_VECT_MASK_CLR__timer0__MIN 0
24338 #define R_VECT_MASK_CLR__nmi__MIN 0
24339 #define R_VECT_MASK_CLR__some__MIN 0
24340
24341 #define R_VECT_MASK_CLR__usb__BITNR 31
24342 #define R_VECT_MASK_CLR__dma9__BITNR 25
24343 #define R_VECT_MASK_CLR__dma8__BITNR 24
24344 #define R_VECT_MASK_CLR__dma7__BITNR 23
24345 #define R_VECT_MASK_CLR__dma6__BITNR 22
24346 #define R_VECT_MASK_CLR__dma5__BITNR 21
24347 #define R_VECT_MASK_CLR__dma4__BITNR 20
24348 #define R_VECT_MASK_CLR__dma3__BITNR 19
24349 #define R_VECT_MASK_CLR__dma2__BITNR 18
24350 #define R_VECT_MASK_CLR__dma1__BITNR 17
24351 #define R_VECT_MASK_CLR__dma0__BITNR 16
24352 #define R_VECT_MASK_CLR__ext_dma1__BITNR 13
24353 #define R_VECT_MASK_CLR__ext_dma0__BITNR 12
24354 #define R_VECT_MASK_CLR__pa__BITNR 11
24355 #define R_VECT_MASK_CLR__irq_intnr__BITNR 10
24356 #define R_VECT_MASK_CLR__sw__BITNR 9
24357 #define R_VECT_MASK_CLR__serial__BITNR 8
24358 #define R_VECT_MASK_CLR__snmp__BITNR 7
24359 #define R_VECT_MASK_CLR__network__BITNR 6
24360 #define R_VECT_MASK_CLR__scsi1__BITNR 5
24361 #define R_VECT_MASK_CLR__par1__BITNR 5
24362 #define R_VECT_MASK_CLR__scsi0__BITNR 4
24363 #define R_VECT_MASK_CLR__par0__BITNR 4
24364 #define R_VECT_MASK_CLR__ata__BITNR 4
24365 #define R_VECT_MASK_CLR__mio__BITNR 4
24366 #define R_VECT_MASK_CLR__timer1__BITNR 3
24367 #define R_VECT_MASK_CLR__timer0__BITNR 2
24368 #define R_VECT_MASK_CLR__nmi__BITNR 1
24369 #define R_VECT_MASK_CLR__some__BITNR 0
24370
24371 #define R_VECT_MASK_CLR__usb__usb__VAL REG_VAL_ENUM
24372 #define R_VECT_MASK_CLR__dma9__dma9__VAL REG_VAL_ENUM
24373 #define R_VECT_MASK_CLR__dma8__dma8__VAL REG_VAL_ENUM
24374 #define R_VECT_MASK_CLR__dma7__dma7__VAL REG_VAL_ENUM
24375 #define R_VECT_MASK_CLR__dma6__dma6__VAL REG_VAL_ENUM
24376 #define R_VECT_MASK_CLR__dma5__dma5__VAL REG_VAL_ENUM
24377 #define R_VECT_MASK_CLR__dma4__dma4__VAL REG_VAL_ENUM
24378 #define R_VECT_MASK_CLR__dma3__dma3__VAL REG_VAL_ENUM
24379 #define R_VECT_MASK_CLR__dma2__dma2__VAL REG_VAL_ENUM
24380 #define R_VECT_MASK_CLR__dma1__dma1__VAL REG_VAL_ENUM
24381 #define R_VECT_MASK_CLR__dma0__dma0__VAL REG_VAL_ENUM
24382 #define R_VECT_MASK_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
24383 #define R_VECT_MASK_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
24384 #define R_VECT_MASK_CLR__pa__pa__VAL REG_VAL_ENUM
24385 #define R_VECT_MASK_CLR__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
24386 #define R_VECT_MASK_CLR__sw__sw__VAL REG_VAL_ENUM
24387 #define R_VECT_MASK_CLR__serial__serial__VAL REG_VAL_ENUM
24388 #define R_VECT_MASK_CLR__snmp__snmp__VAL REG_VAL_ENUM
24389 #define R_VECT_MASK_CLR__network__network__VAL REG_VAL_ENUM
24390 #define R_VECT_MASK_CLR__scsi1__scsi1__VAL REG_VAL_ENUM
24391 #define R_VECT_MASK_CLR__par1__par1__VAL REG_VAL_ENUM
24392 #define R_VECT_MASK_CLR__scsi1__par1__VAL REG_VAL_ENUM
24393 #define R_VECT_MASK_CLR__scsi0__scsi0__VAL REG_VAL_ENUM
24394 #define R_VECT_MASK_CLR__par0__par0__VAL REG_VAL_ENUM
24395 #define R_VECT_MASK_CLR__scsi0__par0__VAL REG_VAL_ENUM
24396 #define R_VECT_MASK_CLR__ata__ata__VAL REG_VAL_ENUM
24397 #define R_VECT_MASK_CLR__scsi0__ata__VAL REG_VAL_ENUM
24398 #define R_VECT_MASK_CLR__mio__mio__VAL REG_VAL_ENUM
24399 #define R_VECT_MASK_CLR__scsi0__mio__VAL REG_VAL_ENUM
24400 #define R_VECT_MASK_CLR__timer1__timer1__VAL REG_VAL_ENUM
24401 #define R_VECT_MASK_CLR__timer0__timer0__VAL REG_VAL_ENUM
24402 #define R_VECT_MASK_CLR__nmi__nmi__VAL REG_VAL_ENUM
24403 #define R_VECT_MASK_CLR__some__some__VAL REG_VAL_ENUM
24404
24405 #define R_VECT_MASK_CLR__usb__usb__clr 1
24406 #define R_VECT_MASK_CLR__usb__usb__nop 0
24407 #define R_VECT_MASK_CLR__dma9__dma9__clr 1
24408 #define R_VECT_MASK_CLR__dma9__dma9__nop 0
24409 #define R_VECT_MASK_CLR__dma8__dma8__clr 1
24410 #define R_VECT_MASK_CLR__dma8__dma8__nop 0
24411 #define R_VECT_MASK_CLR__dma7__dma7__clr 1
24412 #define R_VECT_MASK_CLR__dma7__dma7__nop 0
24413 #define R_VECT_MASK_CLR__dma6__dma6__clr 1
24414 #define R_VECT_MASK_CLR__dma6__dma6__nop 0
24415 #define R_VECT_MASK_CLR__dma5__dma5__clr 1
24416 #define R_VECT_MASK_CLR__dma5__dma5__nop 0
24417 #define R_VECT_MASK_CLR__dma4__dma4__clr 1
24418 #define R_VECT_MASK_CLR__dma4__dma4__nop 0
24419 #define R_VECT_MASK_CLR__dma3__dma3__clr 1
24420 #define R_VECT_MASK_CLR__dma3__dma3__nop 0
24421 #define R_VECT_MASK_CLR__dma2__dma2__clr 1
24422 #define R_VECT_MASK_CLR__dma2__dma2__nop 0
24423 #define R_VECT_MASK_CLR__dma1__dma1__clr 1
24424 #define R_VECT_MASK_CLR__dma1__dma1__nop 0
24425 #define R_VECT_MASK_CLR__dma0__dma0__clr 1
24426 #define R_VECT_MASK_CLR__dma0__dma0__nop 0
24427 #define R_VECT_MASK_CLR__ext_dma1__ext_dma1__clr 1
24428 #define R_VECT_MASK_CLR__ext_dma1__ext_dma1__nop 0
24429 #define R_VECT_MASK_CLR__ext_dma0__ext_dma0__clr 1
24430 #define R_VECT_MASK_CLR__ext_dma0__ext_dma0__nop 0
24431 #define R_VECT_MASK_CLR__pa__pa__clr 1
24432 #define R_VECT_MASK_CLR__pa__pa__nop 0
24433 #define R_VECT_MASK_CLR__irq_intnr__irq_intnr__clr 1
24434 #define R_VECT_MASK_CLR__irq_intnr__irq_intnr__nop 0
24435 #define R_VECT_MASK_CLR__sw__sw__clr 1
24436 #define R_VECT_MASK_CLR__sw__sw__nop 0
24437 #define R_VECT_MASK_CLR__serial__serial__clr 1
24438 #define R_VECT_MASK_CLR__serial__serial__nop 0
24439 #define R_VECT_MASK_CLR__snmp__snmp__clr 1
24440 #define R_VECT_MASK_CLR__snmp__snmp__nop 0
24441 #define R_VECT_MASK_CLR__network__network__clr 1
24442 #define R_VECT_MASK_CLR__network__network__nop 0
24443 #define R_VECT_MASK_CLR__scsi1__scsi1__clr 1
24444 #define R_VECT_MASK_CLR__scsi1__scsi1__nop 0
24445 #define R_VECT_MASK_CLR__par1__par1__clr 1
24446 #define R_VECT_MASK_CLR__par1__par1__nop 0
24447 #define R_VECT_MASK_CLR__scsi0__scsi0__clr 1
24448 #define R_VECT_MASK_CLR__scsi0__scsi0__nop 0
24449 #define R_VECT_MASK_CLR__par0__par0__clr 1
24450 #define R_VECT_MASK_CLR__par0__par0__nop 0
24451 #define R_VECT_MASK_CLR__ata__ata__clr 1
24452 #define R_VECT_MASK_CLR__ata__ata__nop 0
24453 #define R_VECT_MASK_CLR__mio__mio__clr 1
24454 #define R_VECT_MASK_CLR__mio__mio__nop 0
24455 #define R_VECT_MASK_CLR__timer1__timer1__clr 1
24456 #define R_VECT_MASK_CLR__timer1__timer1__nop 0
24457 #define R_VECT_MASK_CLR__timer0__timer0__clr 1
24458 #define R_VECT_MASK_CLR__timer0__timer0__nop 0
24459 #define R_VECT_MASK_CLR__nmi__nmi__clr 1
24460 #define R_VECT_MASK_CLR__nmi__nmi__nop 0
24461 #define R_VECT_MASK_CLR__some__some__clr 1
24462 #define R_VECT_MASK_CLR__some__some__nop 0
24463
24464 #endif
24465
24466 /*
24467 * R_VECT_MASK_RD
24468 * - type: RO
24469 * - addr: 0xb00000d8
24470 * - group: Interrupt mask and status registers
24471 */
24472
24473 #if USE_GROUP__Interrupt_mask_and_status_registers
24474
24475 #define R_VECT_MASK_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d8)
24476 #define R_VECT_MASK_RD__SVAL REG_SVAL_SHADOW
24477 #define R_VECT_MASK_RD__SVAL_I REG_SVAL_I_SHADOW
24478 #define R_VECT_MASK_RD__TYPECAST REG_TYPECAST_UDWORD
24479 #define R_VECT_MASK_RD__TYPE (REG_UDWORD)
24480 #define R_VECT_MASK_RD__GET REG_GET_RO
24481 #define R_VECT_MASK_RD__IGET REG_IGET_RO
24482 #define R_VECT_MASK_RD__SET REG_SET_RO
24483 #define R_VECT_MASK_RD__ISET REG_ISET_RO
24484 #define R_VECT_MASK_RD__SET_VAL REG_SET_VAL_RO
24485 #define R_VECT_MASK_RD__EQL REG_EQL_RO
24486 #define R_VECT_MASK_RD__IEQL REG_IEQL_RO
24487 #define R_VECT_MASK_RD__RD REG_RD_RO
24488 #define R_VECT_MASK_RD__IRD REG_IRD_RO
24489 #define R_VECT_MASK_RD__WR REG_WR_RO
24490 #define R_VECT_MASK_RD__IWR REG_IWR_RO
24491
24492 #define R_VECT_MASK_RD__READ(addr) \
24493 (*(addr))
24494
24495 #define R_VECT_MASK_RD__usb__usb__MASK 0x80000000U
24496 #define R_VECT_MASK_RD__dma9__dma9__MASK 0x02000000U
24497 #define R_VECT_MASK_RD__dma8__dma8__MASK 0x01000000U
24498 #define R_VECT_MASK_RD__dma7__dma7__MASK 0x00800000U
24499 #define R_VECT_MASK_RD__dma6__dma6__MASK 0x00400000U
24500 #define R_VECT_MASK_RD__dma5__dma5__MASK 0x00200000U
24501 #define R_VECT_MASK_RD__dma4__dma4__MASK 0x00100000U
24502 #define R_VECT_MASK_RD__dma3__dma3__MASK 0x00080000U
24503 #define R_VECT_MASK_RD__dma2__dma2__MASK 0x00040000U
24504 #define R_VECT_MASK_RD__dma1__dma1__MASK 0x00020000U
24505 #define R_VECT_MASK_RD__dma0__dma0__MASK 0x00010000U
24506 #define R_VECT_MASK_RD__ext_dma1__ext_dma1__MASK 0x00002000U
24507 #define R_VECT_MASK_RD__ext_dma0__ext_dma0__MASK 0x00001000U
24508 #define R_VECT_MASK_RD__pa__pa__MASK 0x00000800U
24509 #define R_VECT_MASK_RD__irq_intnr__irq_intnr__MASK 0x00000400U
24510 #define R_VECT_MASK_RD__sw__sw__MASK 0x00000200U
24511 #define R_VECT_MASK_RD__serial__serial__MASK 0x00000100U
24512 #define R_VECT_MASK_RD__snmp__snmp__MASK 0x00000080U
24513 #define R_VECT_MASK_RD__network__network__MASK 0x00000040U
24514 #define R_VECT_MASK_RD__scsi1__scsi1__MASK 0x00000020U
24515 #define R_VECT_MASK_RD__par1__par1__MASK 0x00000020U
24516 #define R_VECT_MASK_RD__scsi1__par1__MASK 0x00000020U
24517 #define R_VECT_MASK_RD__scsi0__scsi0__MASK 0x00000010U
24518 #define R_VECT_MASK_RD__par0__par0__MASK 0x00000010U
24519 #define R_VECT_MASK_RD__scsi0__par0__MASK 0x00000010U
24520 #define R_VECT_MASK_RD__ata__ata__MASK 0x00000010U
24521 #define R_VECT_MASK_RD__scsi0__ata__MASK 0x00000010U
24522 #define R_VECT_MASK_RD__mio__mio__MASK 0x00000010U
24523 #define R_VECT_MASK_RD__scsi0__mio__MASK 0x00000010U
24524 #define R_VECT_MASK_RD__timer1__timer1__MASK 0x00000008U
24525 #define R_VECT_MASK_RD__timer0__timer0__MASK 0x00000004U
24526 #define R_VECT_MASK_RD__nmi__nmi__MASK 0x00000002U
24527 #define R_VECT_MASK_RD__some__some__MASK 0x00000001U
24528
24529 #define R_VECT_MASK_RD__usb__MAX 0x1
24530 #define R_VECT_MASK_RD__dma9__MAX 0x1
24531 #define R_VECT_MASK_RD__dma8__MAX 0x1
24532 #define R_VECT_MASK_RD__dma7__MAX 0x1
24533 #define R_VECT_MASK_RD__dma6__MAX 0x1
24534 #define R_VECT_MASK_RD__dma5__MAX 0x1
24535 #define R_VECT_MASK_RD__dma4__MAX 0x1
24536 #define R_VECT_MASK_RD__dma3__MAX 0x1
24537 #define R_VECT_MASK_RD__dma2__MAX 0x1
24538 #define R_VECT_MASK_RD__dma1__MAX 0x1
24539 #define R_VECT_MASK_RD__dma0__MAX 0x1
24540 #define R_VECT_MASK_RD__ext_dma1__MAX 0x1
24541 #define R_VECT_MASK_RD__ext_dma0__MAX 0x1
24542 #define R_VECT_MASK_RD__pa__MAX 0x1
24543 #define R_VECT_MASK_RD__irq_intnr__MAX 0x1
24544 #define R_VECT_MASK_RD__sw__MAX 0x1
24545 #define R_VECT_MASK_RD__serial__MAX 0x1
24546 #define R_VECT_MASK_RD__snmp__MAX 0x1
24547 #define R_VECT_MASK_RD__network__MAX 0x1
24548 #define R_VECT_MASK_RD__scsi1__MAX 0x1
24549 #define R_VECT_MASK_RD__par1__MAX 0x1
24550 #define R_VECT_MASK_RD__scsi0__MAX 0x1
24551 #define R_VECT_MASK_RD__par0__MAX 0x1
24552 #define R_VECT_MASK_RD__ata__MAX 0x1
24553 #define R_VECT_MASK_RD__mio__MAX 0x1
24554 #define R_VECT_MASK_RD__timer1__MAX 0x1
24555 #define R_VECT_MASK_RD__timer0__MAX 0x1
24556 #define R_VECT_MASK_RD__nmi__MAX 0x1
24557 #define R_VECT_MASK_RD__some__MAX 0x1
24558
24559 #define R_VECT_MASK_RD__usb__MIN 0
24560 #define R_VECT_MASK_RD__dma9__MIN 0
24561 #define R_VECT_MASK_RD__dma8__MIN 0
24562 #define R_VECT_MASK_RD__dma7__MIN 0
24563 #define R_VECT_MASK_RD__dma6__MIN 0
24564 #define R_VECT_MASK_RD__dma5__MIN 0
24565 #define R_VECT_MASK_RD__dma4__MIN 0
24566 #define R_VECT_MASK_RD__dma3__MIN 0
24567 #define R_VECT_MASK_RD__dma2__MIN 0
24568 #define R_VECT_MASK_RD__dma1__MIN 0
24569 #define R_VECT_MASK_RD__dma0__MIN 0
24570 #define R_VECT_MASK_RD__ext_dma1__MIN 0
24571 #define R_VECT_MASK_RD__ext_dma0__MIN 0
24572 #define R_VECT_MASK_RD__pa__MIN 0
24573 #define R_VECT_MASK_RD__irq_intnr__MIN 0
24574 #define R_VECT_MASK_RD__sw__MIN 0
24575 #define R_VECT_MASK_RD__serial__MIN 0
24576 #define R_VECT_MASK_RD__snmp__MIN 0
24577 #define R_VECT_MASK_RD__network__MIN 0
24578 #define R_VECT_MASK_RD__scsi1__MIN 0
24579 #define R_VECT_MASK_RD__par1__MIN 0
24580 #define R_VECT_MASK_RD__scsi0__MIN 0
24581 #define R_VECT_MASK_RD__par0__MIN 0
24582 #define R_VECT_MASK_RD__ata__MIN 0
24583 #define R_VECT_MASK_RD__mio__MIN 0
24584 #define R_VECT_MASK_RD__timer1__MIN 0
24585 #define R_VECT_MASK_RD__timer0__MIN 0
24586 #define R_VECT_MASK_RD__nmi__MIN 0
24587 #define R_VECT_MASK_RD__some__MIN 0
24588
24589 #define R_VECT_MASK_RD__usb__BITNR 31
24590 #define R_VECT_MASK_RD__dma9__BITNR 25
24591 #define R_VECT_MASK_RD__dma8__BITNR 24
24592 #define R_VECT_MASK_RD__dma7__BITNR 23
24593 #define R_VECT_MASK_RD__dma6__BITNR 22
24594 #define R_VECT_MASK_RD__dma5__BITNR 21
24595 #define R_VECT_MASK_RD__dma4__BITNR 20
24596 #define R_VECT_MASK_RD__dma3__BITNR 19
24597 #define R_VECT_MASK_RD__dma2__BITNR 18
24598 #define R_VECT_MASK_RD__dma1__BITNR 17
24599 #define R_VECT_MASK_RD__dma0__BITNR 16
24600 #define R_VECT_MASK_RD__ext_dma1__BITNR 13
24601 #define R_VECT_MASK_RD__ext_dma0__BITNR 12
24602 #define R_VECT_MASK_RD__pa__BITNR 11
24603 #define R_VECT_MASK_RD__irq_intnr__BITNR 10
24604 #define R_VECT_MASK_RD__sw__BITNR 9
24605 #define R_VECT_MASK_RD__serial__BITNR 8
24606 #define R_VECT_MASK_RD__snmp__BITNR 7
24607 #define R_VECT_MASK_RD__network__BITNR 6
24608 #define R_VECT_MASK_RD__scsi1__BITNR 5
24609 #define R_VECT_MASK_RD__par1__BITNR 5
24610 #define R_VECT_MASK_RD__scsi0__BITNR 4
24611 #define R_VECT_MASK_RD__par0__BITNR 4
24612 #define R_VECT_MASK_RD__ata__BITNR 4
24613 #define R_VECT_MASK_RD__mio__BITNR 4
24614 #define R_VECT_MASK_RD__timer1__BITNR 3
24615 #define R_VECT_MASK_RD__timer0__BITNR 2
24616 #define R_VECT_MASK_RD__nmi__BITNR 1
24617 #define R_VECT_MASK_RD__some__BITNR 0
24618
24619 #define R_VECT_MASK_RD__usb__usb__VAL REG_VAL_ENUM
24620 #define R_VECT_MASK_RD__dma9__dma9__VAL REG_VAL_ENUM
24621 #define R_VECT_MASK_RD__dma8__dma8__VAL REG_VAL_ENUM
24622 #define R_VECT_MASK_RD__dma7__dma7__VAL REG_VAL_ENUM
24623 #define R_VECT_MASK_RD__dma6__dma6__VAL REG_VAL_ENUM
24624 #define R_VECT_MASK_RD__dma5__dma5__VAL REG_VAL_ENUM
24625 #define R_VECT_MASK_RD__dma4__dma4__VAL REG_VAL_ENUM
24626 #define R_VECT_MASK_RD__dma3__dma3__VAL REG_VAL_ENUM
24627 #define R_VECT_MASK_RD__dma2__dma2__VAL REG_VAL_ENUM
24628 #define R_VECT_MASK_RD__dma1__dma1__VAL REG_VAL_ENUM
24629 #define R_VECT_MASK_RD__dma0__dma0__VAL REG_VAL_ENUM
24630 #define R_VECT_MASK_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
24631 #define R_VECT_MASK_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
24632 #define R_VECT_MASK_RD__pa__pa__VAL REG_VAL_ENUM
24633 #define R_VECT_MASK_RD__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
24634 #define R_VECT_MASK_RD__sw__sw__VAL REG_VAL_ENUM
24635 #define R_VECT_MASK_RD__serial__serial__VAL REG_VAL_ENUM
24636 #define R_VECT_MASK_RD__snmp__snmp__VAL REG_VAL_ENUM
24637 #define R_VECT_MASK_RD__network__network__VAL REG_VAL_ENUM
24638 #define R_VECT_MASK_RD__scsi1__scsi1__VAL REG_VAL_ENUM
24639 #define R_VECT_MASK_RD__par1__par1__VAL REG_VAL_ENUM
24640 #define R_VECT_MASK_RD__scsi1__par1__VAL REG_VAL_ENUM
24641 #define R_VECT_MASK_RD__scsi0__scsi0__VAL REG_VAL_ENUM
24642 #define R_VECT_MASK_RD__par0__par0__VAL REG_VAL_ENUM
24643 #define R_VECT_MASK_RD__scsi0__par0__VAL REG_VAL_ENUM
24644 #define R_VECT_MASK_RD__ata__ata__VAL REG_VAL_ENUM
24645 #define R_VECT_MASK_RD__scsi0__ata__VAL REG_VAL_ENUM
24646 #define R_VECT_MASK_RD__mio__mio__VAL REG_VAL_ENUM
24647 #define R_VECT_MASK_RD__scsi0__mio__VAL REG_VAL_ENUM
24648 #define R_VECT_MASK_RD__timer1__timer1__VAL REG_VAL_ENUM
24649 #define R_VECT_MASK_RD__timer0__timer0__VAL REG_VAL_ENUM
24650 #define R_VECT_MASK_RD__nmi__nmi__VAL REG_VAL_ENUM
24651 #define R_VECT_MASK_RD__some__some__VAL REG_VAL_ENUM
24652
24653 #define R_VECT_MASK_RD__usb__usb__active 1
24654 #define R_VECT_MASK_RD__usb__usb__inactive 0
24655 #define R_VECT_MASK_RD__dma9__dma9__active 1
24656 #define R_VECT_MASK_RD__dma9__dma9__inactive 0
24657 #define R_VECT_MASK_RD__dma8__dma8__active 1
24658 #define R_VECT_MASK_RD__dma8__dma8__inactive 0
24659 #define R_VECT_MASK_RD__dma7__dma7__active 1
24660 #define R_VECT_MASK_RD__dma7__dma7__inactive 0
24661 #define R_VECT_MASK_RD__dma6__dma6__active 1
24662 #define R_VECT_MASK_RD__dma6__dma6__inactive 0
24663 #define R_VECT_MASK_RD__dma5__dma5__active 1
24664 #define R_VECT_MASK_RD__dma5__dma5__inactive 0
24665 #define R_VECT_MASK_RD__dma4__dma4__active 1
24666 #define R_VECT_MASK_RD__dma4__dma4__inactive 0
24667 #define R_VECT_MASK_RD__dma3__dma3__active 1
24668 #define R_VECT_MASK_RD__dma3__dma3__inactive 0
24669 #define R_VECT_MASK_RD__dma2__dma2__active 1
24670 #define R_VECT_MASK_RD__dma2__dma2__inactive 0
24671 #define R_VECT_MASK_RD__dma1__dma1__active 1
24672 #define R_VECT_MASK_RD__dma1__dma1__inactive 0
24673 #define R_VECT_MASK_RD__dma0__dma0__active 1
24674 #define R_VECT_MASK_RD__dma0__dma0__inactive 0
24675 #define R_VECT_MASK_RD__ext_dma1__ext_dma1__active 1
24676 #define R_VECT_MASK_RD__ext_dma1__ext_dma1__inactive 0
24677 #define R_VECT_MASK_RD__ext_dma0__ext_dma0__active 1
24678 #define R_VECT_MASK_RD__ext_dma0__ext_dma0__inactive 0
24679 #define R_VECT_MASK_RD__pa__pa__active 1
24680 #define R_VECT_MASK_RD__pa__pa__inactive 0
24681 #define R_VECT_MASK_RD__irq_intnr__irq_intnr__active 1
24682 #define R_VECT_MASK_RD__irq_intnr__irq_intnr__inactive 0
24683 #define R_VECT_MASK_RD__sw__sw__active 1
24684 #define R_VECT_MASK_RD__sw__sw__inactive 0
24685 #define R_VECT_MASK_RD__serial__serial__active 1
24686 #define R_VECT_MASK_RD__serial__serial__inactive 0
24687 #define R_VECT_MASK_RD__snmp__snmp__active 1
24688 #define R_VECT_MASK_RD__snmp__snmp__inactive 0
24689 #define R_VECT_MASK_RD__network__network__active 1
24690 #define R_VECT_MASK_RD__network__network__inactive 0
24691 #define R_VECT_MASK_RD__scsi1__scsi1__active 1
24692 #define R_VECT_MASK_RD__scsi1__scsi1__inactive 0
24693 #define R_VECT_MASK_RD__par1__par1__active 1
24694 #define R_VECT_MASK_RD__par1__par1__inactive 0
24695 #define R_VECT_MASK_RD__scsi0__scsi0__active 1
24696 #define R_VECT_MASK_RD__scsi0__scsi0__inactive 0
24697 #define R_VECT_MASK_RD__par0__par0__active 1
24698 #define R_VECT_MASK_RD__par0__par0__inactive 0
24699 #define R_VECT_MASK_RD__ata__ata__active 1
24700 #define R_VECT_MASK_RD__ata__ata__inactive 0
24701 #define R_VECT_MASK_RD__mio__mio__active 1
24702 #define R_VECT_MASK_RD__mio__mio__inactive 0
24703 #define R_VECT_MASK_RD__timer1__timer1__active 1
24704 #define R_VECT_MASK_RD__timer1__timer1__inactive 0
24705 #define R_VECT_MASK_RD__timer0__timer0__active 1
24706 #define R_VECT_MASK_RD__timer0__timer0__inactive 0
24707 #define R_VECT_MASK_RD__nmi__nmi__active 1
24708 #define R_VECT_MASK_RD__nmi__nmi__inactive 0
24709 #define R_VECT_MASK_RD__some__some__active 1
24710 #define R_VECT_MASK_RD__some__some__inactive 0
24711
24712 #endif
24713
24714 /*
24715 * R_VECT_MASK_SET
24716 * - type: WO
24717 * - addr: 0xb00000dc
24718 * - group: Interrupt mask and status registers
24719 */
24720
24721 #if USE_GROUP__Interrupt_mask_and_status_registers
24722
24723 #define R_VECT_MASK_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000dc)
24724
24725 #ifndef REG_NO_SHADOW
24726 #define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_SET + 0))
24727 #define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_SET + 0))
24728 #else /* REG_NO_SHADOW */
24729 #define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
24730 #define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
24731 #endif /* REG_NO_SHADOW */
24732
24733 #define R_VECT_MASK_SET__STYPECAST REG_STYPECAST_UDWORD
24734 #define R_VECT_MASK_SET__SVAL REG_SVAL_ZERO
24735 #define R_VECT_MASK_SET__SVAL_I REG_SVAL_I_ZERO
24736 #define R_VECT_MASK_SET__TYPECAST REG_TYPECAST_UDWORD
24737 #define R_VECT_MASK_SET__TYPE (REG_UDWORD)
24738 #define R_VECT_MASK_SET__GET REG_GET_WO
24739 #define R_VECT_MASK_SET__IGET REG_IGET_WO
24740 #define R_VECT_MASK_SET__SET REG_SET_WO
24741 #define R_VECT_MASK_SET__ISET REG_ISET_WO
24742 #define R_VECT_MASK_SET__SET_VAL REG_SET_VAL_WO
24743 #define R_VECT_MASK_SET__EQL REG_EQL_WO
24744 #define R_VECT_MASK_SET__IEQL REG_IEQL_WO
24745 #define R_VECT_MASK_SET__RD REG_RD_WO
24746 #define R_VECT_MASK_SET__IRD REG_IRD_WO
24747 #define R_VECT_MASK_SET__WR REG_WR_WO
24748 #define R_VECT_MASK_SET__IWR REG_IWR_WO
24749
24750 #define R_VECT_MASK_SET__WRITE(addr,value) \
24751 (*(addr) = (value))
24752
24753 #define R_VECT_MASK_SET__usb__usb__MASK 0x80000000U
24754 #define R_VECT_MASK_SET__dma9__dma9__MASK 0x02000000U
24755 #define R_VECT_MASK_SET__dma8__dma8__MASK 0x01000000U
24756 #define R_VECT_MASK_SET__dma7__dma7__MASK 0x00800000U
24757 #define R_VECT_MASK_SET__dma6__dma6__MASK 0x00400000U
24758 #define R_VECT_MASK_SET__dma5__dma5__MASK 0x00200000U
24759 #define R_VECT_MASK_SET__dma4__dma4__MASK 0x00100000U
24760 #define R_VECT_MASK_SET__dma3__dma3__MASK 0x00080000U
24761 #define R_VECT_MASK_SET__dma2__dma2__MASK 0x00040000U
24762 #define R_VECT_MASK_SET__dma1__dma1__MASK 0x00020000U
24763 #define R_VECT_MASK_SET__dma0__dma0__MASK 0x00010000U
24764 #define R_VECT_MASK_SET__ext_dma1__ext_dma1__MASK 0x00002000U
24765 #define R_VECT_MASK_SET__ext_dma0__ext_dma0__MASK 0x00001000U
24766 #define R_VECT_MASK_SET__pa__pa__MASK 0x00000800U
24767 #define R_VECT_MASK_SET__irq_intnr__irq_intnr__MASK 0x00000400U
24768 #define R_VECT_MASK_SET__sw__sw__MASK 0x00000200U
24769 #define R_VECT_MASK_SET__serial__serial__MASK 0x00000100U
24770 #define R_VECT_MASK_SET__snmp__snmp__MASK 0x00000080U
24771 #define R_VECT_MASK_SET__network__network__MASK 0x00000040U
24772 #define R_VECT_MASK_SET__scsi1__scsi1__MASK 0x00000020U
24773 #define R_VECT_MASK_SET__par1__par1__MASK 0x00000020U
24774 #define R_VECT_MASK_SET__scsi1__par1__MASK 0x00000020U
24775 #define R_VECT_MASK_SET__scsi0__scsi0__MASK 0x00000010U
24776 #define R_VECT_MASK_SET__par0__par0__MASK 0x00000010U
24777 #define R_VECT_MASK_SET__scsi0__par0__MASK 0x00000010U
24778 #define R_VECT_MASK_SET__ata__ata__MASK 0x00000010U
24779 #define R_VECT_MASK_SET__scsi0__ata__MASK 0x00000010U
24780 #define R_VECT_MASK_SET__mio__mio__MASK 0x00000010U
24781 #define R_VECT_MASK_SET__scsi0__mio__MASK 0x00000010U
24782 #define R_VECT_MASK_SET__timer1__timer1__MASK 0x00000008U
24783 #define R_VECT_MASK_SET__timer0__timer0__MASK 0x00000004U
24784 #define R_VECT_MASK_SET__nmi__nmi__MASK 0x00000002U
24785 #define R_VECT_MASK_SET__some__some__MASK 0x00000001U
24786
24787 #define R_VECT_MASK_SET__usb__MAX 0x1
24788 #define R_VECT_MASK_SET__dma9__MAX 0x1
24789 #define R_VECT_MASK_SET__dma8__MAX 0x1
24790 #define R_VECT_MASK_SET__dma7__MAX 0x1
24791 #define R_VECT_MASK_SET__dma6__MAX 0x1
24792 #define R_VECT_MASK_SET__dma5__MAX 0x1
24793 #define R_VECT_MASK_SET__dma4__MAX 0x1
24794 #define R_VECT_MASK_SET__dma3__MAX 0x1
24795 #define R_VECT_MASK_SET__dma2__MAX 0x1
24796 #define R_VECT_MASK_SET__dma1__MAX 0x1
24797 #define R_VECT_MASK_SET__dma0__MAX 0x1
24798 #define R_VECT_MASK_SET__ext_dma1__MAX 0x1
24799 #define R_VECT_MASK_SET__ext_dma0__MAX 0x1
24800 #define R_VECT_MASK_SET__pa__MAX 0x1
24801 #define R_VECT_MASK_SET__irq_intnr__MAX 0x1
24802 #define R_VECT_MASK_SET__sw__MAX 0x1
24803 #define R_VECT_MASK_SET__serial__MAX 0x1
24804 #define R_VECT_MASK_SET__snmp__MAX 0x1
24805 #define R_VECT_MASK_SET__network__MAX 0x1
24806 #define R_VECT_MASK_SET__scsi1__MAX 0x1
24807 #define R_VECT_MASK_SET__par1__MAX 0x1
24808 #define R_VECT_MASK_SET__scsi0__MAX 0x1
24809 #define R_VECT_MASK_SET__par0__MAX 0x1
24810 #define R_VECT_MASK_SET__ata__MAX 0x1
24811 #define R_VECT_MASK_SET__mio__MAX 0x1
24812 #define R_VECT_MASK_SET__timer1__MAX 0x1
24813 #define R_VECT_MASK_SET__timer0__MAX 0x1
24814 #define R_VECT_MASK_SET__nmi__MAX 0x1
24815 #define R_VECT_MASK_SET__some__MAX 0x1
24816
24817 #define R_VECT_MASK_SET__usb__MIN 0
24818 #define R_VECT_MASK_SET__dma9__MIN 0
24819 #define R_VECT_MASK_SET__dma8__MIN 0
24820 #define R_VECT_MASK_SET__dma7__MIN 0
24821 #define R_VECT_MASK_SET__dma6__MIN 0
24822 #define R_VECT_MASK_SET__dma5__MIN 0
24823 #define R_VECT_MASK_SET__dma4__MIN 0
24824 #define R_VECT_MASK_SET__dma3__MIN 0
24825 #define R_VECT_MASK_SET__dma2__MIN 0
24826 #define R_VECT_MASK_SET__dma1__MIN 0
24827 #define R_VECT_MASK_SET__dma0__MIN 0
24828 #define R_VECT_MASK_SET__ext_dma1__MIN 0
24829 #define R_VECT_MASK_SET__ext_dma0__MIN 0
24830 #define R_VECT_MASK_SET__pa__MIN 0
24831 #define R_VECT_MASK_SET__irq_intnr__MIN 0
24832 #define R_VECT_MASK_SET__sw__MIN 0
24833 #define R_VECT_MASK_SET__serial__MIN 0
24834 #define R_VECT_MASK_SET__snmp__MIN 0
24835 #define R_VECT_MASK_SET__network__MIN 0
24836 #define R_VECT_MASK_SET__scsi1__MIN 0
24837 #define R_VECT_MASK_SET__par1__MIN 0
24838 #define R_VECT_MASK_SET__scsi0__MIN 0
24839 #define R_VECT_MASK_SET__par0__MIN 0
24840 #define R_VECT_MASK_SET__ata__MIN 0
24841 #define R_VECT_MASK_SET__mio__MIN 0
24842 #define R_VECT_MASK_SET__timer1__MIN 0
24843 #define R_VECT_MASK_SET__timer0__MIN 0
24844 #define R_VECT_MASK_SET__nmi__MIN 0
24845 #define R_VECT_MASK_SET__some__MIN 0
24846
24847 #define R_VECT_MASK_SET__usb__BITNR 31
24848 #define R_VECT_MASK_SET__dma9__BITNR 25
24849 #define R_VECT_MASK_SET__dma8__BITNR 24
24850 #define R_VECT_MASK_SET__dma7__BITNR 23
24851 #define R_VECT_MASK_SET__dma6__BITNR 22
24852 #define R_VECT_MASK_SET__dma5__BITNR 21
24853 #define R_VECT_MASK_SET__dma4__BITNR 20
24854 #define R_VECT_MASK_SET__dma3__BITNR 19
24855 #define R_VECT_MASK_SET__dma2__BITNR 18
24856 #define R_VECT_MASK_SET__dma1__BITNR 17
24857 #define R_VECT_MASK_SET__dma0__BITNR 16
24858 #define R_VECT_MASK_SET__ext_dma1__BITNR 13
24859 #define R_VECT_MASK_SET__ext_dma0__BITNR 12
24860 #define R_VECT_MASK_SET__pa__BITNR 11
24861 #define R_VECT_MASK_SET__irq_intnr__BITNR 10
24862 #define R_VECT_MASK_SET__sw__BITNR 9
24863 #define R_VECT_MASK_SET__serial__BITNR 8
24864 #define R_VECT_MASK_SET__snmp__BITNR 7
24865 #define R_VECT_MASK_SET__network__BITNR 6
24866 #define R_VECT_MASK_SET__scsi1__BITNR 5
24867 #define R_VECT_MASK_SET__par1__BITNR 5
24868 #define R_VECT_MASK_SET__scsi0__BITNR 4
24869 #define R_VECT_MASK_SET__par0__BITNR 4
24870 #define R_VECT_MASK_SET__ata__BITNR 4
24871 #define R_VECT_MASK_SET__mio__BITNR 4
24872 #define R_VECT_MASK_SET__timer1__BITNR 3
24873 #define R_VECT_MASK_SET__timer0__BITNR 2
24874 #define R_VECT_MASK_SET__nmi__BITNR 1
24875 #define R_VECT_MASK_SET__some__BITNR 0
24876
24877 #define R_VECT_MASK_SET__usb__usb__VAL REG_VAL_ENUM
24878 #define R_VECT_MASK_SET__dma9__dma9__VAL REG_VAL_ENUM
24879 #define R_VECT_MASK_SET__dma8__dma8__VAL REG_VAL_ENUM
24880 #define R_VECT_MASK_SET__dma7__dma7__VAL REG_VAL_ENUM
24881 #define R_VECT_MASK_SET__dma6__dma6__VAL REG_VAL_ENUM
24882 #define R_VECT_MASK_SET__dma5__dma5__VAL REG_VAL_ENUM
24883 #define R_VECT_MASK_SET__dma4__dma4__VAL REG_VAL_ENUM
24884 #define R_VECT_MASK_SET__dma3__dma3__VAL REG_VAL_ENUM
24885 #define R_VECT_MASK_SET__dma2__dma2__VAL REG_VAL_ENUM
24886 #define R_VECT_MASK_SET__dma1__dma1__VAL REG_VAL_ENUM
24887 #define R_VECT_MASK_SET__dma0__dma0__VAL REG_VAL_ENUM
24888 #define R_VECT_MASK_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
24889 #define R_VECT_MASK_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
24890 #define R_VECT_MASK_SET__pa__pa__VAL REG_VAL_ENUM
24891 #define R_VECT_MASK_SET__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
24892 #define R_VECT_MASK_SET__sw__sw__VAL REG_VAL_ENUM
24893 #define R_VECT_MASK_SET__serial__serial__VAL REG_VAL_ENUM
24894 #define R_VECT_MASK_SET__snmp__snmp__VAL REG_VAL_ENUM
24895 #define R_VECT_MASK_SET__network__network__VAL REG_VAL_ENUM
24896 #define R_VECT_MASK_SET__scsi1__scsi1__VAL REG_VAL_ENUM
24897 #define R_VECT_MASK_SET__par1__par1__VAL REG_VAL_ENUM
24898 #define R_VECT_MASK_SET__scsi1__par1__VAL REG_VAL_ENUM
24899 #define R_VECT_MASK_SET__scsi0__scsi0__VAL REG_VAL_ENUM
24900 #define R_VECT_MASK_SET__par0__par0__VAL REG_VAL_ENUM
24901 #define R_VECT_MASK_SET__scsi0__par0__VAL REG_VAL_ENUM
24902 #define R_VECT_MASK_SET__ata__ata__VAL REG_VAL_ENUM
24903 #define R_VECT_MASK_SET__scsi0__ata__VAL REG_VAL_ENUM
24904 #define R_VECT_MASK_SET__mio__mio__VAL REG_VAL_ENUM
24905 #define R_VECT_MASK_SET__scsi0__mio__VAL REG_VAL_ENUM
24906 #define R_VECT_MASK_SET__timer1__timer1__VAL REG_VAL_ENUM
24907 #define R_VECT_MASK_SET__timer0__timer0__VAL REG_VAL_ENUM
24908 #define R_VECT_MASK_SET__nmi__nmi__VAL REG_VAL_ENUM
24909 #define R_VECT_MASK_SET__some__some__VAL REG_VAL_ENUM
24910
24911 #define R_VECT_MASK_SET__usb__usb__nop 0
24912 #define R_VECT_MASK_SET__usb__usb__set 1
24913 #define R_VECT_MASK_SET__dma9__dma9__nop 0
24914 #define R_VECT_MASK_SET__dma9__dma9__set 1
24915 #define R_VECT_MASK_SET__dma8__dma8__nop 0
24916 #define R_VECT_MASK_SET__dma8__dma8__set 1
24917 #define R_VECT_MASK_SET__dma7__dma7__nop 0
24918 #define R_VECT_MASK_SET__dma7__dma7__set 1
24919 #define R_VECT_MASK_SET__dma6__dma6__nop 0
24920 #define R_VECT_MASK_SET__dma6__dma6__set 1
24921 #define R_VECT_MASK_SET__dma5__dma5__nop 0
24922 #define R_VECT_MASK_SET__dma5__dma5__set 1
24923 #define R_VECT_MASK_SET__dma4__dma4__nop 0
24924 #define R_VECT_MASK_SET__dma4__dma4__set 1
24925 #define R_VECT_MASK_SET__dma3__dma3__nop 0
24926 #define R_VECT_MASK_SET__dma3__dma3__set 1
24927 #define R_VECT_MASK_SET__dma2__dma2__nop 0
24928 #define R_VECT_MASK_SET__dma2__dma2__set 1
24929 #define R_VECT_MASK_SET__dma1__dma1__nop 0
24930 #define R_VECT_MASK_SET__dma1__dma1__set 1
24931 #define R_VECT_MASK_SET__dma0__dma0__nop 0
24932 #define R_VECT_MASK_SET__dma0__dma0__set 1
24933 #define R_VECT_MASK_SET__ext_dma1__ext_dma1__nop 0
24934 #define R_VECT_MASK_SET__ext_dma1__ext_dma1__set 1
24935 #define R_VECT_MASK_SET__ext_dma0__ext_dma0__nop 0
24936 #define R_VECT_MASK_SET__ext_dma0__ext_dma0__set 1
24937 #define R_VECT_MASK_SET__pa__pa__nop 0
24938 #define R_VECT_MASK_SET__pa__pa__set 1
24939 #define R_VECT_MASK_SET__irq_intnr__irq_intnr__nop 0
24940 #define R_VECT_MASK_SET__irq_intnr__irq_intnr__set 1
24941 #define R_VECT_MASK_SET__sw__sw__nop 0
24942 #define R_VECT_MASK_SET__sw__sw__set 1
24943 #define R_VECT_MASK_SET__serial__serial__nop 0
24944 #define R_VECT_MASK_SET__serial__serial__set 1
24945 #define R_VECT_MASK_SET__snmp__snmp__nop 0
24946 #define R_VECT_MASK_SET__snmp__snmp__set 1
24947 #define R_VECT_MASK_SET__network__network__nop 0
24948 #define R_VECT_MASK_SET__network__network__set 1
24949 #define R_VECT_MASK_SET__scsi1__scsi1__nop 0
24950 #define R_VECT_MASK_SET__scsi1__scsi1__set 1
24951 #define R_VECT_MASK_SET__par1__par1__nop 0
24952 #define R_VECT_MASK_SET__par1__par1__set 1
24953 #define R_VECT_MASK_SET__scsi0__scsi0__nop 0
24954 #define R_VECT_MASK_SET__scsi0__scsi0__set 1
24955 #define R_VECT_MASK_SET__par0__par0__nop 0
24956 #define R_VECT_MASK_SET__par0__par0__set 1
24957 #define R_VECT_MASK_SET__ata__ata__nop 0
24958 #define R_VECT_MASK_SET__ata__ata__set 1
24959 #define R_VECT_MASK_SET__mio__mio__nop 0
24960 #define R_VECT_MASK_SET__mio__mio__set 1
24961 #define R_VECT_MASK_SET__timer1__timer1__nop 0
24962 #define R_VECT_MASK_SET__timer1__timer1__set 1
24963 #define R_VECT_MASK_SET__timer0__timer0__nop 0
24964 #define R_VECT_MASK_SET__timer0__timer0__set 1
24965 #define R_VECT_MASK_SET__nmi__nmi__nop 0
24966 #define R_VECT_MASK_SET__nmi__nmi__set 1
24967 #define R_VECT_MASK_SET__some__some__nop 0
24968 #define R_VECT_MASK_SET__some__some__set 1
24969
24970 #endif
24971
24972 /*
24973 * R_VECT_READ
24974 * - type: RO
24975 * - addr: 0xb00000dc
24976 * - group: Interrupt mask and status registers
24977 */
24978
24979 #if USE_GROUP__Interrupt_mask_and_status_registers
24980
24981 #define R_VECT_READ__ADDR (REG_TYPECAST_UDWORD 0xb00000dc)
24982 #define R_VECT_READ__SVAL REG_SVAL_SHADOW
24983 #define R_VECT_READ__SVAL_I REG_SVAL_I_SHADOW
24984 #define R_VECT_READ__TYPECAST REG_TYPECAST_UDWORD
24985 #define R_VECT_READ__TYPE (REG_UDWORD)
24986 #define R_VECT_READ__GET REG_GET_RO
24987 #define R_VECT_READ__IGET REG_IGET_RO
24988 #define R_VECT_READ__SET REG_SET_RO
24989 #define R_VECT_READ__ISET REG_ISET_RO
24990 #define R_VECT_READ__SET_VAL REG_SET_VAL_RO
24991 #define R_VECT_READ__EQL REG_EQL_RO
24992 #define R_VECT_READ__IEQL REG_IEQL_RO
24993 #define R_VECT_READ__RD REG_RD_RO
24994 #define R_VECT_READ__IRD REG_IRD_RO
24995 #define R_VECT_READ__WR REG_WR_RO
24996 #define R_VECT_READ__IWR REG_IWR_RO
24997
24998 #define R_VECT_READ__READ(addr) \
24999 (*(addr))
25000
25001 #define R_VECT_READ__usb__usb__MASK 0x80000000U
25002 #define R_VECT_READ__dma9__dma9__MASK 0x02000000U
25003 #define R_VECT_READ__dma8__dma8__MASK 0x01000000U
25004 #define R_VECT_READ__dma7__dma7__MASK 0x00800000U
25005 #define R_VECT_READ__dma6__dma6__MASK 0x00400000U
25006 #define R_VECT_READ__dma5__dma5__MASK 0x00200000U
25007 #define R_VECT_READ__dma4__dma4__MASK 0x00100000U
25008 #define R_VECT_READ__dma3__dma3__MASK 0x00080000U
25009 #define R_VECT_READ__dma2__dma2__MASK 0x00040000U
25010 #define R_VECT_READ__dma1__dma1__MASK 0x00020000U
25011 #define R_VECT_READ__dma0__dma0__MASK 0x00010000U
25012 #define R_VECT_READ__ext_dma1__ext_dma1__MASK 0x00002000U
25013 #define R_VECT_READ__ext_dma0__ext_dma0__MASK 0x00001000U
25014 #define R_VECT_READ__pa__pa__MASK 0x00000800U
25015 #define R_VECT_READ__irq_intnr__irq_intnr__MASK 0x00000400U
25016 #define R_VECT_READ__sw__sw__MASK 0x00000200U
25017 #define R_VECT_READ__serial__serial__MASK 0x00000100U
25018 #define R_VECT_READ__snmp__snmp__MASK 0x00000080U
25019 #define R_VECT_READ__network__network__MASK 0x00000040U
25020 #define R_VECT_READ__scsi1__scsi1__MASK 0x00000020U
25021 #define R_VECT_READ__par1__par1__MASK 0x00000020U
25022 #define R_VECT_READ__scsi1__par1__MASK 0x00000020U
25023 #define R_VECT_READ__scsi0__scsi0__MASK 0x00000010U
25024 #define R_VECT_READ__par0__par0__MASK 0x00000010U
25025 #define R_VECT_READ__scsi0__par0__MASK 0x00000010U
25026 #define R_VECT_READ__ata__ata__MASK 0x00000010U
25027 #define R_VECT_READ__scsi0__ata__MASK 0x00000010U
25028 #define R_VECT_READ__mio__mio__MASK 0x00000010U
25029 #define R_VECT_READ__scsi0__mio__MASK 0x00000010U
25030 #define R_VECT_READ__timer1__timer1__MASK 0x00000008U
25031 #define R_VECT_READ__timer0__timer0__MASK 0x00000004U
25032 #define R_VECT_READ__nmi__nmi__MASK 0x00000002U
25033 #define R_VECT_READ__some__some__MASK 0x00000001U
25034
25035 #define R_VECT_READ__usb__MAX 0x1
25036 #define R_VECT_READ__dma9__MAX 0x1
25037 #define R_VECT_READ__dma8__MAX 0x1
25038 #define R_VECT_READ__dma7__MAX 0x1
25039 #define R_VECT_READ__dma6__MAX 0x1
25040 #define R_VECT_READ__dma5__MAX 0x1
25041 #define R_VECT_READ__dma4__MAX 0x1
25042 #define R_VECT_READ__dma3__MAX 0x1
25043 #define R_VECT_READ__dma2__MAX 0x1
25044 #define R_VECT_READ__dma1__MAX 0x1
25045 #define R_VECT_READ__dma0__MAX 0x1
25046 #define R_VECT_READ__ext_dma1__MAX 0x1
25047 #define R_VECT_READ__ext_dma0__MAX 0x1
25048 #define R_VECT_READ__pa__MAX 0x1
25049 #define R_VECT_READ__irq_intnr__MAX 0x1
25050 #define R_VECT_READ__sw__MAX 0x1
25051 #define R_VECT_READ__serial__MAX 0x1
25052 #define R_VECT_READ__snmp__MAX 0x1
25053 #define R_VECT_READ__network__MAX 0x1
25054 #define R_VECT_READ__scsi1__MAX 0x1
25055 #define R_VECT_READ__par1__MAX 0x1
25056 #define R_VECT_READ__scsi0__MAX 0x1
25057 #define R_VECT_READ__par0__MAX 0x1
25058 #define R_VECT_READ__ata__MAX 0x1
25059 #define R_VECT_READ__mio__MAX 0x1
25060 #define R_VECT_READ__timer1__MAX 0x1
25061 #define R_VECT_READ__timer0__MAX 0x1
25062 #define R_VECT_READ__nmi__MAX 0x1
25063 #define R_VECT_READ__some__MAX 0x1
25064
25065 #define R_VECT_READ__usb__MIN 0
25066 #define R_VECT_READ__dma9__MIN 0
25067 #define R_VECT_READ__dma8__MIN 0
25068 #define R_VECT_READ__dma7__MIN 0
25069 #define R_VECT_READ__dma6__MIN 0
25070 #define R_VECT_READ__dma5__MIN 0
25071 #define R_VECT_READ__dma4__MIN 0
25072 #define R_VECT_READ__dma3__MIN 0
25073 #define R_VECT_READ__dma2__MIN 0
25074 #define R_VECT_READ__dma1__MIN 0
25075 #define R_VECT_READ__dma0__MIN 0
25076 #define R_VECT_READ__ext_dma1__MIN 0
25077 #define R_VECT_READ__ext_dma0__MIN 0
25078 #define R_VECT_READ__pa__MIN 0
25079 #define R_VECT_READ__irq_intnr__MIN 0
25080 #define R_VECT_READ__sw__MIN 0
25081 #define R_VECT_READ__serial__MIN 0
25082 #define R_VECT_READ__snmp__MIN 0
25083 #define R_VECT_READ__network__MIN 0
25084 #define R_VECT_READ__scsi1__MIN 0
25085 #define R_VECT_READ__par1__MIN 0
25086 #define R_VECT_READ__scsi0__MIN 0
25087 #define R_VECT_READ__par0__MIN 0
25088 #define R_VECT_READ__ata__MIN 0
25089 #define R_VECT_READ__mio__MIN 0
25090 #define R_VECT_READ__timer1__MIN 0
25091 #define R_VECT_READ__timer0__MIN 0
25092 #define R_VECT_READ__nmi__MIN 0
25093 #define R_VECT_READ__some__MIN 0
25094
25095 #define R_VECT_READ__usb__BITNR 31
25096 #define R_VECT_READ__dma9__BITNR 25
25097 #define R_VECT_READ__dma8__BITNR 24
25098 #define R_VECT_READ__dma7__BITNR 23
25099 #define R_VECT_READ__dma6__BITNR 22
25100 #define R_VECT_READ__dma5__BITNR 21
25101 #define R_VECT_READ__dma4__BITNR 20
25102 #define R_VECT_READ__dma3__BITNR 19
25103 #define R_VECT_READ__dma2__BITNR 18
25104 #define R_VECT_READ__dma1__BITNR 17
25105 #define R_VECT_READ__dma0__BITNR 16
25106 #define R_VECT_READ__ext_dma1__BITNR 13
25107 #define R_VECT_READ__ext_dma0__BITNR 12
25108 #define R_VECT_READ__pa__BITNR 11
25109 #define R_VECT_READ__irq_intnr__BITNR 10
25110 #define R_VECT_READ__sw__BITNR 9
25111 #define R_VECT_READ__serial__BITNR 8
25112 #define R_VECT_READ__snmp__BITNR 7
25113 #define R_VECT_READ__network__BITNR 6
25114 #define R_VECT_READ__scsi1__BITNR 5
25115 #define R_VECT_READ__par1__BITNR 5
25116 #define R_VECT_READ__scsi0__BITNR 4
25117 #define R_VECT_READ__par0__BITNR 4
25118 #define R_VECT_READ__ata__BITNR 4
25119 #define R_VECT_READ__mio__BITNR 4
25120 #define R_VECT_READ__timer1__BITNR 3
25121 #define R_VECT_READ__timer0__BITNR 2
25122 #define R_VECT_READ__nmi__BITNR 1
25123 #define R_VECT_READ__some__BITNR 0
25124
25125 #define R_VECT_READ__usb__usb__VAL REG_VAL_ENUM
25126 #define R_VECT_READ__dma9__dma9__VAL REG_VAL_ENUM
25127 #define R_VECT_READ__dma8__dma8__VAL REG_VAL_ENUM
25128 #define R_VECT_READ__dma7__dma7__VAL REG_VAL_ENUM
25129 #define R_VECT_READ__dma6__dma6__VAL REG_VAL_ENUM
25130 #define R_VECT_READ__dma5__dma5__VAL REG_VAL_ENUM
25131 #define R_VECT_READ__dma4__dma4__VAL REG_VAL_ENUM
25132 #define R_VECT_READ__dma3__dma3__VAL REG_VAL_ENUM
25133 #define R_VECT_READ__dma2__dma2__VAL REG_VAL_ENUM
25134 #define R_VECT_READ__dma1__dma1__VAL REG_VAL_ENUM
25135 #define R_VECT_READ__dma0__dma0__VAL REG_VAL_ENUM
25136 #define R_VECT_READ__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
25137 #define R_VECT_READ__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
25138 #define R_VECT_READ__pa__pa__VAL REG_VAL_ENUM
25139 #define R_VECT_READ__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
25140 #define R_VECT_READ__sw__sw__VAL REG_VAL_ENUM
25141 #define R_VECT_READ__serial__serial__VAL REG_VAL_ENUM
25142 #define R_VECT_READ__snmp__snmp__VAL REG_VAL_ENUM
25143 #define R_VECT_READ__network__network__VAL REG_VAL_ENUM
25144 #define R_VECT_READ__scsi1__scsi1__VAL REG_VAL_ENUM
25145 #define R_VECT_READ__par1__par1__VAL REG_VAL_ENUM
25146 #define R_VECT_READ__scsi1__par1__VAL REG_VAL_ENUM
25147 #define R_VECT_READ__scsi0__scsi0__VAL REG_VAL_ENUM
25148 #define R_VECT_READ__par0__par0__VAL REG_VAL_ENUM
25149 #define R_VECT_READ__scsi0__par0__VAL REG_VAL_ENUM
25150 #define R_VECT_READ__ata__ata__VAL REG_VAL_ENUM
25151 #define R_VECT_READ__scsi0__ata__VAL REG_VAL_ENUM
25152 #define R_VECT_READ__mio__mio__VAL REG_VAL_ENUM
25153 #define R_VECT_READ__scsi0__mio__VAL REG_VAL_ENUM
25154 #define R_VECT_READ__timer1__timer1__VAL REG_VAL_ENUM
25155 #define R_VECT_READ__timer0__timer0__VAL REG_VAL_ENUM
25156 #define R_VECT_READ__nmi__nmi__VAL REG_VAL_ENUM
25157 #define R_VECT_READ__some__some__VAL REG_VAL_ENUM
25158
25159 #define R_VECT_READ__usb__usb__active 1
25160 #define R_VECT_READ__usb__usb__inactive 0
25161 #define R_VECT_READ__dma9__dma9__active 1
25162 #define R_VECT_READ__dma9__dma9__inactive 0
25163 #define R_VECT_READ__dma8__dma8__active 1
25164 #define R_VECT_READ__dma8__dma8__inactive 0
25165 #define R_VECT_READ__dma7__dma7__active 1
25166 #define R_VECT_READ__dma7__dma7__inactive 0
25167 #define R_VECT_READ__dma6__dma6__active 1
25168 #define R_VECT_READ__dma6__dma6__inactive 0
25169 #define R_VECT_READ__dma5__dma5__active 1
25170 #define R_VECT_READ__dma5__dma5__inactive 0
25171 #define R_VECT_READ__dma4__dma4__active 1
25172 #define R_VECT_READ__dma4__dma4__inactive 0
25173 #define R_VECT_READ__dma3__dma3__active 1
25174 #define R_VECT_READ__dma3__dma3__inactive 0
25175 #define R_VECT_READ__dma2__dma2__active 1
25176 #define R_VECT_READ__dma2__dma2__inactive 0
25177 #define R_VECT_READ__dma1__dma1__active 1
25178 #define R_VECT_READ__dma1__dma1__inactive 0
25179 #define R_VECT_READ__dma0__dma0__active 1
25180 #define R_VECT_READ__dma0__dma0__inactive 0
25181 #define R_VECT_READ__ext_dma1__ext_dma1__active 1
25182 #define R_VECT_READ__ext_dma1__ext_dma1__inactive 0
25183 #define R_VECT_READ__ext_dma0__ext_dma0__active 1
25184 #define R_VECT_READ__ext_dma0__ext_dma0__inactive 0
25185 #define R_VECT_READ__pa__pa__active 1
25186 #define R_VECT_READ__pa__pa__inactive 0
25187 #define R_VECT_READ__irq_intnr__irq_intnr__active 1
25188 #define R_VECT_READ__irq_intnr__irq_intnr__inactive 0
25189 #define R_VECT_READ__sw__sw__active 1
25190 #define R_VECT_READ__sw__sw__inactive 0
25191 #define R_VECT_READ__serial__serial__active 1
25192 #define R_VECT_READ__serial__serial__inactive 0
25193 #define R_VECT_READ__snmp__snmp__active 1
25194 #define R_VECT_READ__snmp__snmp__inactive 0
25195 #define R_VECT_READ__network__network__active 1
25196 #define R_VECT_READ__network__network__inactive 0
25197 #define R_VECT_READ__scsi1__scsi1__active 1
25198 #define R_VECT_READ__scsi1__scsi1__inactive 0
25199 #define R_VECT_READ__par1__par1__active 1
25200 #define R_VECT_READ__par1__par1__inactive 0
25201 #define R_VECT_READ__scsi0__scsi0__active 1
25202 #define R_VECT_READ__scsi0__scsi0__inactive 0
25203 #define R_VECT_READ__par0__par0__active 1
25204 #define R_VECT_READ__par0__par0__inactive 0
25205 #define R_VECT_READ__ata__ata__active 1
25206 #define R_VECT_READ__ata__ata__inactive 0
25207 #define R_VECT_READ__mio__mio__active 1
25208 #define R_VECT_READ__mio__mio__inactive 0
25209 #define R_VECT_READ__timer1__timer1__active 1
25210 #define R_VECT_READ__timer1__timer1__inactive 0
25211 #define R_VECT_READ__timer0__timer0__active 1
25212 #define R_VECT_READ__timer0__timer0__inactive 0
25213 #define R_VECT_READ__nmi__nmi__active 1
25214 #define R_VECT_READ__nmi__nmi__inactive 0
25215 #define R_VECT_READ__some__some__active 1
25216 #define R_VECT_READ__some__some__inactive 0
25217
25218 #endif
25219
25220 /*
25221 * R_WAITSTATES
25222 * - type: WO
25223 * - addr: 0xb0000000
25224 * - group: Bus interface configuration registers
25225 */
25226
25227 #if USE_GROUP__Bus_interface_configuration_registers
25228
25229 #define R_WAITSTATES__ADDR (REG_TYPECAST_UDWORD 0xb0000000)
25230
25231 #ifndef REG_NO_SHADOW
25232 #define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WAITSTATES + 0))
25233 #define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WAITSTATES + 0))
25234 #else /* REG_NO_SHADOW */
25235 #define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
25236 #define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
25237 #endif /* REG_NO_SHADOW */
25238
25239 #define R_WAITSTATES__STYPECAST REG_STYPECAST_UDWORD
25240 #define R_WAITSTATES__SVAL REG_SVAL_SHADOW
25241 #define R_WAITSTATES__SVAL_I REG_SVAL_I_SHADOW
25242 #define R_WAITSTATES__TYPECAST REG_TYPECAST_UDWORD
25243 #define R_WAITSTATES__TYPE (REG_UDWORD)
25244 #define R_WAITSTATES__GET REG_GET_WO
25245 #define R_WAITSTATES__IGET REG_IGET_WO
25246 #define R_WAITSTATES__SET REG_SET_WO
25247 #define R_WAITSTATES__ISET REG_ISET_WO
25248 #define R_WAITSTATES__SET_VAL REG_SET_VAL_WO
25249 #define R_WAITSTATES__EQL REG_EQL_WO
25250 #define R_WAITSTATES__IEQL REG_IEQL_WO
25251 #define R_WAITSTATES__RD REG_RD_WO
25252 #define R_WAITSTATES__IRD REG_IRD_WO
25253 #define R_WAITSTATES__WR REG_WR_WO
25254 #define R_WAITSTATES__IWR REG_IWR_WO
25255
25256 #define R_WAITSTATES__WRITE(addr,value) \
25257 (*(addr) = (value))
25258
25259 #define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__MASK 0xc0000000U
25260 #define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__MASK 0x30000000U
25261 #define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__MASK 0x0f000000U
25262 #define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__MASK 0x00c00000U
25263 #define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__MASK 0x00300000U
25264 #define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__MASK 0x000f0000U
25265 #define R_WAITSTATES__sram_zw__sram_zw__MASK 0x0000c000U
25266 #define R_WAITSTATES__sram_ew__sram_ew__MASK 0x00003000U
25267 #define R_WAITSTATES__sram_lw__sram_lw__MASK 0x00000f00U
25268 #define R_WAITSTATES__flash_zw__flash_zw__MASK 0x000000c0U
25269 #define R_WAITSTATES__flash_ew__flash_ew__MASK 0x00000030U
25270 #define R_WAITSTATES__flash_lw__flash_lw__MASK 0x0000000fU
25271
25272 #define R_WAITSTATES__pcs4_7_zw__MAX 3
25273 #define R_WAITSTATES__pcs4_7_ew__MAX 3
25274 #define R_WAITSTATES__pcs4_7_lw__MAX 15
25275 #define R_WAITSTATES__pcs0_3_zw__MAX 3
25276 #define R_WAITSTATES__pcs0_3_ew__MAX 3
25277 #define R_WAITSTATES__pcs0_3_lw__MAX 15
25278 #define R_WAITSTATES__sram_zw__MAX 3
25279 #define R_WAITSTATES__sram_ew__MAX 3
25280 #define R_WAITSTATES__sram_lw__MAX 15
25281 #define R_WAITSTATES__flash_zw__MAX 3
25282 #define R_WAITSTATES__flash_ew__MAX 3
25283 #define R_WAITSTATES__flash_lw__MAX 15
25284
25285 #define R_WAITSTATES__pcs4_7_zw__MIN 0
25286 #define R_WAITSTATES__pcs4_7_ew__MIN 0
25287 #define R_WAITSTATES__pcs4_7_lw__MIN 0
25288 #define R_WAITSTATES__pcs0_3_zw__MIN 0
25289 #define R_WAITSTATES__pcs0_3_ew__MIN 0
25290 #define R_WAITSTATES__pcs0_3_lw__MIN 0
25291 #define R_WAITSTATES__sram_zw__MIN 0
25292 #define R_WAITSTATES__sram_ew__MIN 0
25293 #define R_WAITSTATES__sram_lw__MIN 0
25294 #define R_WAITSTATES__flash_zw__MIN 0
25295 #define R_WAITSTATES__flash_ew__MIN 0
25296 #define R_WAITSTATES__flash_lw__MIN 0
25297
25298 #define R_WAITSTATES__pcs4_7_zw__BITNR 30
25299 #define R_WAITSTATES__pcs4_7_ew__BITNR 28
25300 #define R_WAITSTATES__pcs4_7_lw__BITNR 24
25301 #define R_WAITSTATES__pcs0_3_zw__BITNR 22
25302 #define R_WAITSTATES__pcs0_3_ew__BITNR 20
25303 #define R_WAITSTATES__pcs0_3_lw__BITNR 16
25304 #define R_WAITSTATES__sram_zw__BITNR 14
25305 #define R_WAITSTATES__sram_ew__BITNR 12
25306 #define R_WAITSTATES__sram_lw__BITNR 8
25307 #define R_WAITSTATES__flash_zw__BITNR 6
25308 #define R_WAITSTATES__flash_ew__BITNR 4
25309 #define R_WAITSTATES__flash_lw__BITNR 0
25310
25311 #define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__VAL REG_VAL_VAL
25312 #define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__VAL REG_VAL_VAL
25313 #define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__VAL REG_VAL_VAL
25314 #define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__VAL REG_VAL_VAL
25315 #define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__VAL REG_VAL_VAL
25316 #define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__VAL REG_VAL_VAL
25317 #define R_WAITSTATES__sram_zw__sram_zw__VAL REG_VAL_VAL
25318 #define R_WAITSTATES__sram_ew__sram_ew__VAL REG_VAL_VAL
25319 #define R_WAITSTATES__sram_lw__sram_lw__VAL REG_VAL_VAL
25320 #define R_WAITSTATES__flash_zw__flash_zw__VAL REG_VAL_VAL
25321 #define R_WAITSTATES__flash_ew__flash_ew__VAL REG_VAL_VAL
25322 #define R_WAITSTATES__flash_lw__flash_lw__VAL REG_VAL_VAL
25323
25324
25325 #endif
25326
25327 /*
25328 * R_WATCHDOG
25329 * - type: WO
25330 * - addr: 0xb0000024
25331 * - group: Timer registers
25332 */
25333
25334 #if USE_GROUP__Timer_registers
25335
25336 #define R_WATCHDOG__ADDR (REG_TYPECAST_UDWORD 0xb0000024)
25337
25338 #ifndef REG_NO_SHADOW
25339 #define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WATCHDOG + 0))
25340 #define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WATCHDOG + 0))
25341 #else /* REG_NO_SHADOW */
25342 #define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
25343 #define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
25344 #endif /* REG_NO_SHADOW */
25345
25346 #define R_WATCHDOG__STYPECAST REG_STYPECAST_UDWORD
25347 #define R_WATCHDOG__SVAL REG_SVAL_SHADOW
25348 #define R_WATCHDOG__SVAL_I REG_SVAL_I_SHADOW
25349 #define R_WATCHDOG__TYPECAST REG_TYPECAST_UDWORD
25350 #define R_WATCHDOG__TYPE (REG_UDWORD)
25351 #define R_WATCHDOG__GET REG_GET_WO
25352 #define R_WATCHDOG__IGET REG_IGET_WO
25353 #define R_WATCHDOG__SET REG_SET_WO
25354 #define R_WATCHDOG__ISET REG_ISET_WO
25355 #define R_WATCHDOG__SET_VAL REG_SET_VAL_WO
25356 #define R_WATCHDOG__EQL REG_EQL_WO
25357 #define R_WATCHDOG__IEQL REG_IEQL_WO
25358 #define R_WATCHDOG__RD REG_RD_WO
25359 #define R_WATCHDOG__IRD REG_IRD_WO
25360 #define R_WATCHDOG__WR REG_WR_WO
25361 #define R_WATCHDOG__IWR REG_IWR_WO
25362
25363 #define R_WATCHDOG__WRITE(addr,value) \
25364 (*(addr) = (value))
25365
25366 #define R_WATCHDOG__key__key__MASK 0x0000000eU
25367 #define R_WATCHDOG__enable__enable__MASK 0x00000001U
25368
25369 #define R_WATCHDOG__key__MAX 7
25370 #define R_WATCHDOG__enable__MAX 0x1
25371
25372 #define R_WATCHDOG__key__MIN 0
25373 #define R_WATCHDOG__enable__MIN 0
25374
25375 #define R_WATCHDOG__key__BITNR 1
25376 #define R_WATCHDOG__enable__BITNR 0
25377
25378 #define R_WATCHDOG__key__key__VAL REG_VAL_VAL
25379 #define R_WATCHDOG__enable__enable__VAL REG_VAL_ENUM
25380
25381 #define R_WATCHDOG__enable__enable__start 1
25382 #define R_WATCHDOG__enable__enable__stop 0
25383
25384 #endif
25385
25386 #endif
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