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kernel: ar8xxx: get_arl_table now shows all ports of an entry
[openwrt/staging/dedeckeh.git] / target / linux / generic / files / drivers / net / phy / ar8327.c
1 /*
2 * ar8327.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
29
30 #include "ar8216.h"
31 #include "ar8327.h"
32
33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
35
36 static u32
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
38 {
39 u32 t;
40
41 if (!cfg)
42 return 0;
43
44 t = 0;
45 switch (cfg->mode) {
46 case AR8327_PAD_NC:
47 break;
48
49 case AR8327_PAD_MAC2MAC_MII:
50 t = AR8327_PAD_MAC_MII_EN;
51 if (cfg->rxclk_sel)
52 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
53 if (cfg->txclk_sel)
54 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
55 break;
56
57 case AR8327_PAD_MAC2MAC_GMII:
58 t = AR8327_PAD_MAC_GMII_EN;
59 if (cfg->rxclk_sel)
60 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
61 if (cfg->txclk_sel)
62 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
63 break;
64
65 case AR8327_PAD_MAC_SGMII:
66 t = AR8327_PAD_SGMII_EN;
67
68 /*
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
73 */
74 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
75 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
76 if (cfg->rxclk_delay_en)
77 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
78 if (cfg->txclk_delay_en)
79 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
80
81 if (cfg->sgmii_delay_en)
82 t |= AR8327_PAD_SGMII_DELAY_EN;
83
84 break;
85
86 case AR8327_PAD_MAC2PHY_MII:
87 t = AR8327_PAD_PHY_MII_EN;
88 if (cfg->rxclk_sel)
89 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
90 if (cfg->txclk_sel)
91 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
92 break;
93
94 case AR8327_PAD_MAC2PHY_GMII:
95 t = AR8327_PAD_PHY_GMII_EN;
96 if (cfg->pipe_rxclk_sel)
97 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
98 if (cfg->rxclk_sel)
99 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
100 if (cfg->txclk_sel)
101 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
102 break;
103
104 case AR8327_PAD_MAC_RGMII:
105 t = AR8327_PAD_RGMII_EN;
106 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
107 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
108 if (cfg->rxclk_delay_en)
109 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
110 if (cfg->txclk_delay_en)
111 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
112 break;
113
114 case AR8327_PAD_PHY_GMII:
115 t = AR8327_PAD_PHYX_GMII_EN;
116 break;
117
118 case AR8327_PAD_PHY_RGMII:
119 t = AR8327_PAD_PHYX_RGMII_EN;
120 break;
121
122 case AR8327_PAD_PHY_MII:
123 t = AR8327_PAD_PHYX_MII_EN;
124 break;
125 }
126
127 return t;
128 }
129
130 static void
131 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
132 {
133 switch (priv->chip_rev) {
134 case 1:
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
139 break;
140
141 case 2:
142 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);
143 /* fallthrough */
144 case 4:
145 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
149 break;
150 }
151 }
152
153 static u32
154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
155 {
156 u32 t;
157
158 if (!cfg->force_link)
159 return AR8216_PORT_STATUS_LINK_AUTO;
160
161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
165
166 switch (cfg->speed) {
167 case AR8327_PORT_SPEED_10:
168 t |= AR8216_PORT_SPEED_10M;
169 break;
170 case AR8327_PORT_SPEED_100:
171 t |= AR8216_PORT_SPEED_100M;
172 break;
173 case AR8327_PORT_SPEED_1000:
174 t |= AR8216_PORT_SPEED_1000M;
175 break;
176 }
177
178 return t;
179 }
180
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
183
184 static const struct ar8327_led_entry
185 ar8327_led_map[AR8327_NUM_LEDS] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
189
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
193
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
197
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
201
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
205 };
206
207 static void
208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
209 enum ar8327_led_pattern pattern)
210 {
211 const struct ar8327_led_entry *entry;
212
213 entry = &ar8327_led_map[led_num];
214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
215 (3 << entry->shift), pattern << entry->shift);
216 }
217
218 static void
219 ar8327_led_work_func(struct work_struct *work)
220 {
221 struct ar8327_led *aled;
222 u8 pattern;
223
224 aled = container_of(work, struct ar8327_led, led_work);
225
226 pattern = aled->pattern;
227
228 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
229 pattern);
230 }
231
232 static void
233 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
234 {
235 if (aled->pattern == pattern)
236 return;
237
238 aled->pattern = pattern;
239 schedule_work(&aled->led_work);
240 }
241
242 static inline struct ar8327_led *
243 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
244 {
245 return container_of(led_cdev, struct ar8327_led, cdev);
246 }
247
248 static int
249 ar8327_led_blink_set(struct led_classdev *led_cdev,
250 unsigned long *delay_on,
251 unsigned long *delay_off)
252 {
253 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
254
255 if (*delay_on == 0 && *delay_off == 0) {
256 *delay_on = 125;
257 *delay_off = 125;
258 }
259
260 if (*delay_on != 125 || *delay_off != 125) {
261 /*
262 * The hardware only supports blinking at 4Hz. Fall back
263 * to software implementation in other cases.
264 */
265 return -EINVAL;
266 }
267
268 spin_lock(&aled->lock);
269
270 aled->enable_hw_mode = false;
271 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
272
273 spin_unlock(&aled->lock);
274
275 return 0;
276 }
277
278 static void
279 ar8327_led_set_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281 {
282 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
283 u8 pattern;
284 bool active;
285
286 active = (brightness != LED_OFF);
287 active ^= aled->active_low;
288
289 pattern = (active) ? AR8327_LED_PATTERN_ON :
290 AR8327_LED_PATTERN_OFF;
291
292 spin_lock(&aled->lock);
293
294 aled->enable_hw_mode = false;
295 ar8327_led_schedule_change(aled, pattern);
296
297 spin_unlock(&aled->lock);
298 }
299
300 static ssize_t
301 ar8327_led_enable_hw_mode_show(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304 {
305 struct led_classdev *led_cdev = dev_get_drvdata(dev);
306 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
307 ssize_t ret = 0;
308
309 ret += scnprintf(buf, PAGE_SIZE, "%d\n", aled->enable_hw_mode);
310
311 return ret;
312 }
313
314 static ssize_t
315 ar8327_led_enable_hw_mode_store(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf,
318 size_t size)
319 {
320 struct led_classdev *led_cdev = dev_get_drvdata(dev);
321 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
322 u8 pattern;
323 u8 value;
324 int ret;
325
326 ret = kstrtou8(buf, 10, &value);
327 if (ret < 0)
328 return -EINVAL;
329
330 spin_lock(&aled->lock);
331
332 aled->enable_hw_mode = !!value;
333 if (aled->enable_hw_mode)
334 pattern = AR8327_LED_PATTERN_RULE;
335 else
336 pattern = AR8327_LED_PATTERN_OFF;
337
338 ar8327_led_schedule_change(aled, pattern);
339
340 spin_unlock(&aled->lock);
341
342 return size;
343 }
344
345 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
346 ar8327_led_enable_hw_mode_show,
347 ar8327_led_enable_hw_mode_store);
348
349 static int
350 ar8327_led_register(struct ar8327_led *aled)
351 {
352 int ret;
353
354 ret = led_classdev_register(NULL, &aled->cdev);
355 if (ret < 0)
356 return ret;
357
358 if (aled->mode == AR8327_LED_MODE_HW) {
359 ret = device_create_file(aled->cdev.dev,
360 &dev_attr_enable_hw_mode);
361 if (ret)
362 goto err_unregister;
363 }
364
365 return 0;
366
367 err_unregister:
368 led_classdev_unregister(&aled->cdev);
369 return ret;
370 }
371
372 static void
373 ar8327_led_unregister(struct ar8327_led *aled)
374 {
375 if (aled->mode == AR8327_LED_MODE_HW)
376 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
377
378 led_classdev_unregister(&aled->cdev);
379 cancel_work_sync(&aled->led_work);
380 }
381
382 static int
383 ar8327_led_create(struct ar8xxx_priv *priv,
384 const struct ar8327_led_info *led_info)
385 {
386 struct ar8327_data *data = priv->chip_data;
387 struct ar8327_led *aled;
388 int ret;
389
390 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
391 return 0;
392
393 if (!led_info->name)
394 return -EINVAL;
395
396 if (led_info->led_num >= AR8327_NUM_LEDS)
397 return -EINVAL;
398
399 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
400 GFP_KERNEL);
401 if (!aled)
402 return -ENOMEM;
403
404 aled->sw_priv = priv;
405 aled->led_num = led_info->led_num;
406 aled->active_low = led_info->active_low;
407 aled->mode = led_info->mode;
408
409 if (aled->mode == AR8327_LED_MODE_HW)
410 aled->enable_hw_mode = true;
411
412 aled->name = (char *)(aled + 1);
413 strcpy(aled->name, led_info->name);
414
415 aled->cdev.name = aled->name;
416 aled->cdev.brightness_set = ar8327_led_set_brightness;
417 aled->cdev.blink_set = ar8327_led_blink_set;
418 aled->cdev.default_trigger = led_info->default_trigger;
419
420 spin_lock_init(&aled->lock);
421 mutex_init(&aled->mutex);
422 INIT_WORK(&aled->led_work, ar8327_led_work_func);
423
424 ret = ar8327_led_register(aled);
425 if (ret)
426 goto err_free;
427
428 data->leds[data->num_leds++] = aled;
429
430 return 0;
431
432 err_free:
433 kfree(aled);
434 return ret;
435 }
436
437 static void
438 ar8327_led_destroy(struct ar8327_led *aled)
439 {
440 ar8327_led_unregister(aled);
441 kfree(aled);
442 }
443
444 static void
445 ar8327_leds_init(struct ar8xxx_priv *priv)
446 {
447 struct ar8327_data *data = priv->chip_data;
448 unsigned i;
449
450 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
451 return;
452
453 for (i = 0; i < data->num_leds; i++) {
454 struct ar8327_led *aled;
455
456 aled = data->leds[i];
457
458 if (aled->enable_hw_mode)
459 aled->pattern = AR8327_LED_PATTERN_RULE;
460 else
461 aled->pattern = AR8327_LED_PATTERN_OFF;
462
463 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
464 }
465 }
466
467 static void
468 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
469 {
470 struct ar8327_data *data = priv->chip_data;
471 unsigned i;
472
473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
474 return;
475
476 for (i = 0; i < data->num_leds; i++) {
477 struct ar8327_led *aled;
478
479 aled = data->leds[i];
480 ar8327_led_destroy(aled);
481 }
482
483 kfree(data->leds);
484 }
485
486 static int
487 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
488 struct ar8327_platform_data *pdata)
489 {
490 struct ar8327_led_cfg *led_cfg;
491 struct ar8327_data *data = priv->chip_data;
492 u32 pos, new_pos;
493 u32 t;
494
495 if (!pdata)
496 return -EINVAL;
497
498 priv->get_port_link = pdata->get_port_link;
499
500 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
501 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
502
503 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
504 if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
505 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
506 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
507
508 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
509 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
510 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
511 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
512
513 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
514 new_pos = pos;
515
516 led_cfg = pdata->led_cfg;
517 if (led_cfg) {
518 if (led_cfg->open_drain)
519 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
520 else
521 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
522
523 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
524 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
525 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
526 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
527
528 if (new_pos != pos)
529 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
530 }
531
532 if (pdata->sgmii_cfg) {
533 t = pdata->sgmii_cfg->sgmii_ctrl;
534 if (priv->chip_rev == 1)
535 t |= AR8327_SGMII_CTRL_EN_PLL |
536 AR8327_SGMII_CTRL_EN_RX |
537 AR8327_SGMII_CTRL_EN_TX;
538 else
539 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
540 AR8327_SGMII_CTRL_EN_RX |
541 AR8327_SGMII_CTRL_EN_TX);
542
543 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
544
545 if (pdata->sgmii_cfg->serdes_aen)
546 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
547 else
548 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
549 }
550
551 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
552
553 if (pdata->leds && pdata->num_leds) {
554 int i;
555
556 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
557 GFP_KERNEL);
558 if (!data->leds)
559 return -ENOMEM;
560
561 for (i = 0; i < pdata->num_leds; i++)
562 ar8327_led_create(priv, &pdata->leds[i]);
563 }
564
565 return 0;
566 }
567
568 #ifdef CONFIG_OF
569 static int
570 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
571 {
572 struct ar8327_data *data = priv->chip_data;
573 const __be32 *paddr;
574 int len;
575 int i;
576
577 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
578 if (!paddr || len < (2 * sizeof(*paddr)))
579 return -EINVAL;
580
581 len /= sizeof(*paddr);
582
583 for (i = 0; i < len - 1; i += 2) {
584 u32 reg;
585 u32 val;
586
587 reg = be32_to_cpup(paddr + i);
588 val = be32_to_cpup(paddr + i + 1);
589
590 switch (reg) {
591 case AR8327_REG_PORT_STATUS(0):
592 data->port0_status = val;
593 break;
594 case AR8327_REG_PORT_STATUS(6):
595 data->port6_status = val;
596 break;
597 default:
598 ar8xxx_write(priv, reg, val);
599 break;
600 }
601 }
602
603 return 0;
604 }
605 #else
606 static inline int
607 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
608 {
609 return -EINVAL;
610 }
611 #endif
612
613 static int
614 ar8327_hw_init(struct ar8xxx_priv *priv)
615 {
616 int ret;
617
618 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
619 if (!priv->chip_data)
620 return -ENOMEM;
621
622 if (priv->phy->mdio.dev.of_node)
623 ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node);
624 else
625 ret = ar8327_hw_config_pdata(priv,
626 priv->phy->mdio.dev.platform_data);
627
628 if (ret)
629 return ret;
630
631 ar8327_leds_init(priv);
632
633 ar8xxx_phy_init(priv);
634
635 return 0;
636 }
637
638 static void
639 ar8327_cleanup(struct ar8xxx_priv *priv)
640 {
641 ar8327_leds_cleanup(priv);
642 }
643
644 static void
645 ar8327_init_globals(struct ar8xxx_priv *priv)
646 {
647 struct ar8327_data *data = priv->chip_data;
648 u32 t;
649 int i;
650
651 /* enable CPU port and disable mirror port */
652 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
653 AR8327_FWD_CTRL0_MIRROR_PORT;
654 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
655
656 /* forward multicast and broadcast frames to CPU */
657 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
658 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
659 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
660 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
661
662 /* enable jumbo frames */
663 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
664 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
665
666 /* Enable MIB counters */
667 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
668 AR8327_MODULE_EN_MIB);
669
670 /* Disable EEE on all phy's due to stability issues */
671 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
672 data->eee[i] = false;
673 }
674
675 static void
676 ar8327_init_port(struct ar8xxx_priv *priv, int port)
677 {
678 struct ar8327_data *data = priv->chip_data;
679 u32 t;
680
681 if (port == AR8216_PORT_CPU)
682 t = data->port0_status;
683 else if (port == 6)
684 t = data->port6_status;
685 else
686 t = AR8216_PORT_STATUS_LINK_AUTO;
687
688 if (port != AR8216_PORT_CPU && port != 6) {
689 /*hw limitation:if configure mac when there is traffic,
690 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
691 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0);
692 msleep(100);
693 t |= AR8216_PORT_STATUS_FLOW_CONTROL;
694 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
695 } else {
696 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
697 }
698
699 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
700
701 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0);
702
703 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
704 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
705
706 t = AR8327_PORT_LOOKUP_LEARN;
707 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
708 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
709 }
710
711 static u32
712 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
713 {
714 u32 t;
715
716 t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
717 /* map the flow control autoneg result bits to the flow control bits
718 * used in forced mode to allow ar8216_read_port_link detect
719 * flow control properly if autoneg is used
720 */
721 if (t & AR8216_PORT_STATUS_LINK_UP &&
722 t & AR8216_PORT_STATUS_LINK_AUTO) {
723 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
724 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
725 t |= AR8216_PORT_STATUS_TXFLOW;
726 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
727 t |= AR8216_PORT_STATUS_RXFLOW;
728 }
729
730 return t;
731 }
732
733 static u32
734 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
735 {
736 int phy;
737 u16 t;
738
739 if (port >= priv->dev.ports)
740 return 0;
741
742 if (port == 0 || port == 6)
743 return 0;
744
745 phy = port - 1;
746
747 /* EEE Ability Auto-negotiation Result */
748 t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);
749
750 return mmd_eee_adv_to_ethtool_adv_t(t);
751 }
752
753 static int
754 ar8327_atu_flush(struct ar8xxx_priv *priv)
755 {
756 int ret;
757
758 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
759 AR8327_ATU_FUNC_BUSY, 0);
760 if (!ret)
761 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
762 AR8327_ATU_FUNC_OP_FLUSH |
763 AR8327_ATU_FUNC_BUSY);
764
765 return ret;
766 }
767
768 static int
769 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
770 {
771 u32 t;
772 int ret;
773
774 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
775 AR8327_ATU_FUNC_BUSY, 0);
776 if (!ret) {
777 t = (port << AR8327_ATU_PORT_NUM_S);
778 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
779 t |= AR8327_ATU_FUNC_BUSY;
780 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
781 }
782
783 return ret;
784 }
785
786 static int
787 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
788 {
789 u32 fwd_ctrl, frame_ack;
790
791 fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
792 frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
793 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
794 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
795 AR8327_FRAME_ACK_CTRL_S(port));
796
797 return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
798 fwd_ctrl) == fwd_ctrl &&
799 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
800 frame_ack) == frame_ack;
801 }
802
803 static void
804 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
805 {
806 int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
807 u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
808 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
809 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
810 AR8327_FRAME_ACK_CTRL_S(port);
811
812 if (enable) {
813 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
814 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
815 BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
816 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
817 } else {
818 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
819 BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
820 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
821 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
822 }
823 }
824
825 static void
826 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
827 {
828 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
829 AR8327_VTU_FUNC1_BUSY, 0))
830 return;
831
832 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
833 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
834
835 op |= AR8327_VTU_FUNC1_BUSY;
836 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
837 }
838
839 static void
840 ar8327_vtu_flush(struct ar8xxx_priv *priv)
841 {
842 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
843 }
844
845 static void
846 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
847 {
848 u32 op;
849 u32 val;
850 int i;
851
852 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
853 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
854 for (i = 0; i < AR8327_NUM_PORTS; i++) {
855 u32 mode;
856
857 if ((port_mask & BIT(i)) == 0)
858 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
859 else if (priv->vlan == 0)
860 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
861 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
862 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
863 else
864 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
865
866 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
867 }
868 ar8327_vtu_op(priv, op, val);
869 }
870
871 static void
872 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
873 {
874 u32 t;
875 u32 egress, ingress;
876 u32 pvid = priv->vlan_id[priv->pvid[port]];
877
878 if (priv->vlan) {
879 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
880 ingress = AR8216_IN_SECURE;
881 } else {
882 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
883 ingress = AR8216_IN_PORT_ONLY;
884 }
885
886 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
887 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
888 if (priv->vlan && priv->port_vlan_prio[port]) {
889 u32 prio = priv->port_vlan_prio[port];
890
891 t |= prio << AR8327_PORT_VLAN0_DEF_SPRI_S;
892 t |= prio << AR8327_PORT_VLAN0_DEF_CPRI_S;
893 }
894 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
895
896 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
897 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
898 if (priv->vlan && priv->port_vlan_prio[port])
899 t |= AR8327_PORT_VLAN1_VLAN_PRI_PROP;
900
901 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
902
903 t = members;
904 t |= AR8327_PORT_LOOKUP_LEARN;
905 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
906 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
907 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
908 }
909
910 static int
911 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
912 {
913 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
914 u8 ports = priv->vlan_table[val->port_vlan];
915 int i;
916
917 val->len = 0;
918 for (i = 0; i < dev->ports; i++) {
919 struct switch_port *p;
920
921 if (!(ports & (1 << i)))
922 continue;
923
924 p = &val->value.ports[val->len++];
925 p->id = i;
926 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
927 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
928 else
929 p->flags = 0;
930 }
931 return 0;
932 }
933
934 static int
935 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
936 {
937 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
938 u8 *vt = &priv->vlan_table[val->port_vlan];
939 int i;
940
941 *vt = 0;
942 for (i = 0; i < val->len; i++) {
943 struct switch_port *p = &val->value.ports[i];
944
945 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
946 if (val->port_vlan == priv->pvid[p->id]) {
947 priv->vlan_tagged |= (1 << p->id);
948 }
949 } else {
950 priv->vlan_tagged &= ~(1 << p->id);
951 priv->pvid[p->id] = val->port_vlan;
952 }
953
954 *vt |= 1 << p->id;
955 }
956 return 0;
957 }
958
959 static void
960 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
961 {
962 int port;
963
964 /* reset all mirror registers */
965 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
966 AR8327_FWD_CTRL0_MIRROR_PORT,
967 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
968 for (port = 0; port < AR8327_NUM_PORTS; port++) {
969 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
970 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
971
972 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
973 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
974 }
975
976 /* now enable mirroring if necessary */
977 if (priv->source_port >= AR8327_NUM_PORTS ||
978 priv->monitor_port >= AR8327_NUM_PORTS ||
979 priv->source_port == priv->monitor_port) {
980 return;
981 }
982
983 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
984 AR8327_FWD_CTRL0_MIRROR_PORT,
985 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
986
987 if (priv->mirror_rx)
988 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
989 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
990
991 if (priv->mirror_tx)
992 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
993 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
994 }
995
996 static int
997 ar8327_sw_set_eee(struct switch_dev *dev,
998 const struct switch_attr *attr,
999 struct switch_val *val)
1000 {
1001 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1002 struct ar8327_data *data = priv->chip_data;
1003 int port = val->port_vlan;
1004 int phy;
1005
1006 if (port >= dev->ports)
1007 return -EINVAL;
1008 if (port == 0 || port == 6)
1009 return -EOPNOTSUPP;
1010
1011 phy = port - 1;
1012
1013 data->eee[phy] = !!(val->value.i);
1014
1015 return 0;
1016 }
1017
1018 static int
1019 ar8327_sw_get_eee(struct switch_dev *dev,
1020 const struct switch_attr *attr,
1021 struct switch_val *val)
1022 {
1023 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1024 const struct ar8327_data *data = priv->chip_data;
1025 int port = val->port_vlan;
1026 int phy;
1027
1028 if (port >= dev->ports)
1029 return -EINVAL;
1030 if (port == 0 || port == 6)
1031 return -EOPNOTSUPP;
1032
1033 phy = port - 1;
1034
1035 val->value.i = data->eee[phy];
1036
1037 return 0;
1038 }
1039
1040 static void
1041 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1042 {
1043 int timeout = 20;
1044
1045 while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) {
1046 udelay(10);
1047 cond_resched();
1048 }
1049
1050 if (!timeout)
1051 pr_err("ar8327: timeout waiting for atu to become ready\n");
1052 }
1053
1054 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1055 struct arl_entry *a, u32 *status, enum arl_op op)
1056 {
1057 struct mii_bus *bus = priv->mii_bus;
1058 u16 r2, page;
1059 u16 r1_data0, r1_data1, r1_data2, r1_func;
1060 u32 val0, val1, val2;
1061
1062 split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1063 r2 |= 0x10;
1064
1065 r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1066 r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1067 r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1068
1069 switch (op) {
1070 case AR8XXX_ARL_INITIALIZE:
1071 /* all ATU registers are on the same page
1072 * therefore set page only once
1073 */
1074 bus->write(bus, 0x18, 0, page);
1075 wait_for_page_switch();
1076
1077 ar8327_wait_atu_ready(priv, r2, r1_func);
1078
1079 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1080 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1081 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1082 break;
1083 case AR8XXX_ARL_GET_NEXT:
1084 ar8xxx_mii_write32(priv, r2, r1_func,
1085 AR8327_ATU_FUNC_OP_GET_NEXT |
1086 AR8327_ATU_FUNC_BUSY);
1087 ar8327_wait_atu_ready(priv, r2, r1_func);
1088
1089 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1090 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1091 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1092
1093 *status = val2 & AR8327_ATU_STATUS;
1094 if (!*status)
1095 break;
1096
1097 a->portmap = (val1 & AR8327_ATU_PORTS) >> AR8327_ATU_PORTS_S;
1098 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1099 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1100 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1101 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1102 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1103 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1104 break;
1105 }
1106 }
1107
1108 static int
1109 ar8327_sw_hw_apply(struct switch_dev *dev)
1110 {
1111 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1112 const struct ar8327_data *data = priv->chip_data;
1113 int ret, i;
1114
1115 ret = ar8xxx_sw_hw_apply(dev);
1116 if (ret)
1117 return ret;
1118
1119 for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1120 if (data->eee[i])
1121 ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1122 AR8327_EEE_CTRL_DISABLE_PHY(i));
1123 else
1124 ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1125 AR8327_EEE_CTRL_DISABLE_PHY(i));
1126 }
1127
1128 return 0;
1129 }
1130
1131 int
1132 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1133 const struct switch_attr *attr,
1134 struct switch_val *val)
1135 {
1136 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1137 int port = val->port_vlan;
1138
1139 if (port >= dev->ports)
1140 return -EINVAL;
1141
1142 mutex_lock(&priv->reg_mutex);
1143 val->value.i = ar8327_get_port_igmp(priv, port);
1144 mutex_unlock(&priv->reg_mutex);
1145
1146 return 0;
1147 }
1148
1149 int
1150 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1151 const struct switch_attr *attr,
1152 struct switch_val *val)
1153 {
1154 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1155 int port = val->port_vlan;
1156
1157 if (port >= dev->ports)
1158 return -EINVAL;
1159
1160 mutex_lock(&priv->reg_mutex);
1161 ar8327_set_port_igmp(priv, port, val->value.i);
1162 mutex_unlock(&priv->reg_mutex);
1163
1164 return 0;
1165 }
1166
1167 int
1168 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1169 const struct switch_attr *attr,
1170 struct switch_val *val)
1171 {
1172 int port;
1173
1174 for (port = 0; port < dev->ports; port++) {
1175 val->port_vlan = port;
1176 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1177 !val->value.i)
1178 break;
1179 }
1180
1181 return 0;
1182 }
1183
1184 int
1185 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1186 const struct switch_attr *attr,
1187 struct switch_val *val)
1188 {
1189 int port;
1190
1191 for (port = 0; port < dev->ports; port++) {
1192 val->port_vlan = port;
1193 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1194 break;
1195 }
1196
1197 return 0;
1198 }
1199
1200 int
1201 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1202 const struct switch_attr *attr,
1203 struct switch_val *val)
1204 {
1205 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1206 u32 val_reg;
1207
1208 mutex_lock(&priv->reg_mutex);
1209 val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1210 val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1211 mutex_unlock(&priv->reg_mutex);
1212
1213 return 0;
1214 }
1215
1216 int
1217 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1218 const struct switch_attr *attr,
1219 struct switch_val *val)
1220 {
1221 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1222
1223 mutex_lock(&priv->reg_mutex);
1224 if (val->value.i)
1225 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1226 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1227 else
1228 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1229 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1230 mutex_unlock(&priv->reg_mutex);
1231
1232 return 0;
1233 }
1234
1235 static int
1236 ar8327_sw_set_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,
1237 struct switch_val *val)
1238 {
1239 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1240 int port = val->port_vlan;
1241
1242 if (port >= dev->ports)
1243 return -EINVAL;
1244 if (port == 0 || port == 6)
1245 return -EOPNOTSUPP;
1246 if (val->value.i < 0 || val->value.i > 7)
1247 return -EINVAL;
1248
1249 priv->port_vlan_prio[port] = val->value.i;
1250
1251 return 0;
1252 }
1253
1254 static int
1255 ar8327_sw_get_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,
1256 struct switch_val *val)
1257 {
1258 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1259 int port = val->port_vlan;
1260
1261 val->value.i = priv->port_vlan_prio[port];
1262
1263 return 0;
1264 }
1265
1266 static const struct switch_attr ar8327_sw_attr_globals[] = {
1267 {
1268 .type = SWITCH_TYPE_INT,
1269 .name = "enable_vlan",
1270 .description = "Enable VLAN mode",
1271 .set = ar8xxx_sw_set_vlan,
1272 .get = ar8xxx_sw_get_vlan,
1273 .max = 1
1274 },
1275 {
1276 .type = SWITCH_TYPE_NOVAL,
1277 .name = "reset_mibs",
1278 .description = "Reset all MIB counters",
1279 .set = ar8xxx_sw_set_reset_mibs,
1280 },
1281 {
1282 .type = SWITCH_TYPE_INT,
1283 .name = "enable_mirror_rx",
1284 .description = "Enable mirroring of RX packets",
1285 .set = ar8xxx_sw_set_mirror_rx_enable,
1286 .get = ar8xxx_sw_get_mirror_rx_enable,
1287 .max = 1
1288 },
1289 {
1290 .type = SWITCH_TYPE_INT,
1291 .name = "enable_mirror_tx",
1292 .description = "Enable mirroring of TX packets",
1293 .set = ar8xxx_sw_set_mirror_tx_enable,
1294 .get = ar8xxx_sw_get_mirror_tx_enable,
1295 .max = 1
1296 },
1297 {
1298 .type = SWITCH_TYPE_INT,
1299 .name = "mirror_monitor_port",
1300 .description = "Mirror monitor port",
1301 .set = ar8xxx_sw_set_mirror_monitor_port,
1302 .get = ar8xxx_sw_get_mirror_monitor_port,
1303 .max = AR8327_NUM_PORTS - 1
1304 },
1305 {
1306 .type = SWITCH_TYPE_INT,
1307 .name = "mirror_source_port",
1308 .description = "Mirror source port",
1309 .set = ar8xxx_sw_set_mirror_source_port,
1310 .get = ar8xxx_sw_get_mirror_source_port,
1311 .max = AR8327_NUM_PORTS - 1
1312 },
1313 {
1314 .type = SWITCH_TYPE_INT,
1315 .name = "arl_age_time",
1316 .description = "ARL age time (secs)",
1317 .set = ar8xxx_sw_set_arl_age_time,
1318 .get = ar8xxx_sw_get_arl_age_time,
1319 },
1320 {
1321 .type = SWITCH_TYPE_STRING,
1322 .name = "arl_table",
1323 .description = "Get ARL table",
1324 .set = NULL,
1325 .get = ar8xxx_sw_get_arl_table,
1326 },
1327 {
1328 .type = SWITCH_TYPE_NOVAL,
1329 .name = "flush_arl_table",
1330 .description = "Flush ARL table",
1331 .set = ar8xxx_sw_set_flush_arl_table,
1332 },
1333 {
1334 .type = SWITCH_TYPE_INT,
1335 .name = "igmp_snooping",
1336 .description = "Enable IGMP Snooping",
1337 .set = ar8327_sw_set_igmp_snooping,
1338 .get = ar8327_sw_get_igmp_snooping,
1339 .max = 1
1340 },
1341 {
1342 .type = SWITCH_TYPE_INT,
1343 .name = "igmp_v3",
1344 .description = "Enable IGMPv3 support",
1345 .set = ar8327_sw_set_igmp_v3,
1346 .get = ar8327_sw_get_igmp_v3,
1347 .max = 1
1348 },
1349 };
1350
1351 static const struct switch_attr ar8327_sw_attr_port[] = {
1352 {
1353 .type = SWITCH_TYPE_NOVAL,
1354 .name = "reset_mib",
1355 .description = "Reset single port MIB counters",
1356 .set = ar8xxx_sw_set_port_reset_mib,
1357 },
1358 {
1359 .type = SWITCH_TYPE_STRING,
1360 .name = "mib",
1361 .description = "Get port's MIB counters",
1362 .set = NULL,
1363 .get = ar8xxx_sw_get_port_mib,
1364 },
1365 {
1366 .type = SWITCH_TYPE_INT,
1367 .name = "enable_eee",
1368 .description = "Enable EEE PHY sleep mode",
1369 .set = ar8327_sw_set_eee,
1370 .get = ar8327_sw_get_eee,
1371 .max = 1,
1372 },
1373 {
1374 .type = SWITCH_TYPE_NOVAL,
1375 .name = "flush_arl_table",
1376 .description = "Flush port's ARL table entries",
1377 .set = ar8xxx_sw_set_flush_port_arl_table,
1378 },
1379 {
1380 .type = SWITCH_TYPE_INT,
1381 .name = "igmp_snooping",
1382 .description = "Enable port's IGMP Snooping",
1383 .set = ar8327_sw_set_port_igmp_snooping,
1384 .get = ar8327_sw_get_port_igmp_snooping,
1385 .max = 1
1386 },
1387 {
1388 .type = SWITCH_TYPE_INT,
1389 .name = "vlan_prio",
1390 .description = "Port VLAN default priority (VLAN PCP) (0-7)",
1391 .set = ar8327_sw_set_port_vlan_prio,
1392 .get = ar8327_sw_get_port_vlan_prio,
1393 .max = 7,
1394 },
1395 };
1396
1397 static const struct switch_dev_ops ar8327_sw_ops = {
1398 .attr_global = {
1399 .attr = ar8327_sw_attr_globals,
1400 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1401 },
1402 .attr_port = {
1403 .attr = ar8327_sw_attr_port,
1404 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1405 },
1406 .attr_vlan = {
1407 .attr = ar8xxx_sw_attr_vlan,
1408 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1409 },
1410 .get_port_pvid = ar8xxx_sw_get_pvid,
1411 .set_port_pvid = ar8xxx_sw_set_pvid,
1412 .get_vlan_ports = ar8327_sw_get_ports,
1413 .set_vlan_ports = ar8327_sw_set_ports,
1414 .apply_config = ar8327_sw_hw_apply,
1415 .reset_switch = ar8xxx_sw_reset_switch,
1416 .get_port_link = ar8xxx_sw_get_port_link,
1417 /* The following op is disabled as it hogs the CPU and degrades performance.
1418 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1419 on ar8xxx switches.
1420
1421 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1422 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1423 the request to update the MIB counter is cleared. */
1424 #if 0
1425 .get_port_stats = ar8xxx_sw_get_port_stats,
1426 #endif
1427 };
1428
1429 const struct ar8xxx_chip ar8327_chip = {
1430 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1431 .config_at_probe = true,
1432 .mii_lo_first = true,
1433
1434 .name = "Atheros AR8327",
1435 .ports = AR8327_NUM_PORTS,
1436 .vlans = AR8X16_MAX_VLANS,
1437 .swops = &ar8327_sw_ops,
1438
1439 .reg_port_stats_start = 0x1000,
1440 .reg_port_stats_length = 0x100,
1441 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1442
1443 .hw_init = ar8327_hw_init,
1444 .cleanup = ar8327_cleanup,
1445 .init_globals = ar8327_init_globals,
1446 .init_port = ar8327_init_port,
1447 .setup_port = ar8327_setup_port,
1448 .read_port_status = ar8327_read_port_status,
1449 .read_port_eee_status = ar8327_read_port_eee_status,
1450 .atu_flush = ar8327_atu_flush,
1451 .atu_flush_port = ar8327_atu_flush_port,
1452 .vtu_flush = ar8327_vtu_flush,
1453 .vtu_load_vlan = ar8327_vtu_load_vlan,
1454 .phy_fixup = ar8327_phy_fixup,
1455 .set_mirror_regs = ar8327_set_mirror_regs,
1456 .get_arl_entry = ar8327_get_arl_entry,
1457 .sw_hw_apply = ar8327_sw_hw_apply,
1458
1459 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1460 .mib_decs = ar8236_mibs,
1461 .mib_func = AR8327_REG_MIB_FUNC
1462 };
1463
1464 const struct ar8xxx_chip ar8337_chip = {
1465 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1466 .config_at_probe = true,
1467 .mii_lo_first = true,
1468
1469 .name = "Atheros AR8337",
1470 .ports = AR8327_NUM_PORTS,
1471 .vlans = AR8X16_MAX_VLANS,
1472 .swops = &ar8327_sw_ops,
1473
1474 .reg_port_stats_start = 0x1000,
1475 .reg_port_stats_length = 0x100,
1476 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1477
1478 .hw_init = ar8327_hw_init,
1479 .cleanup = ar8327_cleanup,
1480 .init_globals = ar8327_init_globals,
1481 .init_port = ar8327_init_port,
1482 .setup_port = ar8327_setup_port,
1483 .read_port_status = ar8327_read_port_status,
1484 .read_port_eee_status = ar8327_read_port_eee_status,
1485 .atu_flush = ar8327_atu_flush,
1486 .atu_flush_port = ar8327_atu_flush_port,
1487 .vtu_flush = ar8327_vtu_flush,
1488 .vtu_load_vlan = ar8327_vtu_load_vlan,
1489 .phy_fixup = ar8327_phy_fixup,
1490 .set_mirror_regs = ar8327_set_mirror_regs,
1491 .get_arl_entry = ar8327_get_arl_entry,
1492 .sw_hw_apply = ar8327_sw_hw_apply,
1493
1494 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1495 .mib_decs = ar8236_mibs,
1496 .mib_func = AR8327_REG_MIB_FUNC
1497 };
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