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imagebuilder: x86 fails to build inside the imagebuilder
[openwrt/staging/dedeckeh.git] / target / linux / generic / patches-3.12 / 770-bgmac-backport.patch
1 --- a/drivers/net/ethernet/broadcom/Kconfig
2 +++ b/drivers/net/ethernet/broadcom/Kconfig
3 @@ -23,6 +23,7 @@ config B44
4 depends on SSB_POSSIBLE && HAS_DMA
5 select SSB
6 select MII
7 + select PHYLIB
8 ---help---
9 If you have a network (Ethernet) controller of this type, say Y
10 or M and read the Ethernet-HOWTO, available from
11 --- a/drivers/net/ethernet/broadcom/bgmac.c
12 +++ b/drivers/net/ethernet/broadcom/bgmac.c
13 @@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct b
14 u32 ctl;
15
16 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
17 + if (bgmac->core->id.rev >= 4) {
18 + ctl &= ~BGMAC_DMA_TX_BL_MASK;
19 + ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
20 +
21 + ctl &= ~BGMAC_DMA_TX_MR_MASK;
22 + ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
23 +
24 + ctl &= ~BGMAC_DMA_TX_PC_MASK;
25 + ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
26 +
27 + ctl &= ~BGMAC_DMA_TX_PT_MASK;
28 + ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
29 + }
30 ctl |= BGMAC_DMA_TX_ENABLE;
31 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
32 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
33 @@ -149,6 +162,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
34 dma_desc->ctl0 = cpu_to_le32(ctl0);
35 dma_desc->ctl1 = cpu_to_le32(ctl1);
36
37 + netdev_sent_queue(net_dev, skb->len);
38 +
39 wmb();
40
41 /* Increase ring->end to point empty slot. We tell hardware the first
42 @@ -178,6 +193,7 @@ static void bgmac_dma_tx_free(struct bgm
43 struct device *dma_dev = bgmac->core->dma_dev;
44 int empty_slot;
45 bool freed = false;
46 + unsigned bytes_compl = 0, pkts_compl = 0;
47
48 /* The last slot that hardware didn't consume yet */
49 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
50 @@ -195,6 +211,9 @@ static void bgmac_dma_tx_free(struct bgm
51 slot->skb->len, DMA_TO_DEVICE);
52 slot->dma_addr = 0;
53
54 + bytes_compl += slot->skb->len;
55 + pkts_compl++;
56 +
57 /* Free memory! :) */
58 dev_kfree_skb(slot->skb);
59 slot->skb = NULL;
60 @@ -208,6 +227,8 @@ static void bgmac_dma_tx_free(struct bgm
61 freed = true;
62 }
63
64 + netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
65 +
66 if (freed && netif_queue_stopped(bgmac->net_dev))
67 netif_wake_queue(bgmac->net_dev);
68 }
69 @@ -232,6 +253,16 @@ static void bgmac_dma_rx_enable(struct b
70 u32 ctl;
71
72 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
73 + if (bgmac->core->id.rev >= 4) {
74 + ctl &= ~BGMAC_DMA_RX_BL_MASK;
75 + ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
76 +
77 + ctl &= ~BGMAC_DMA_RX_PC_MASK;
78 + ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
79 +
80 + ctl &= ~BGMAC_DMA_RX_PT_MASK;
81 + ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
82 + }
83 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
84 ctl |= BGMAC_DMA_RX_ENABLE;
85 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
86 @@ -244,31 +275,59 @@ static int bgmac_dma_rx_skb_for_slot(str
87 struct bgmac_slot_info *slot)
88 {
89 struct device *dma_dev = bgmac->core->dma_dev;
90 + struct sk_buff *skb;
91 + dma_addr_t dma_addr;
92 struct bgmac_rx_header *rx;
93
94 /* Alloc skb */
95 - slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
96 - if (!slot->skb)
97 + skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
98 + if (!skb)
99 return -ENOMEM;
100
101 /* Poison - if everything goes fine, hardware will overwrite it */
102 - rx = (struct bgmac_rx_header *)slot->skb->data;
103 + rx = (struct bgmac_rx_header *)skb->data;
104 rx->len = cpu_to_le16(0xdead);
105 rx->flags = cpu_to_le16(0xbeef);
106
107 /* Map skb for the DMA */
108 - slot->dma_addr = dma_map_single(dma_dev, slot->skb->data,
109 - BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
110 - if (dma_mapping_error(dma_dev, slot->dma_addr)) {
111 + dma_addr = dma_map_single(dma_dev, skb->data,
112 + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
113 + if (dma_mapping_error(dma_dev, dma_addr)) {
114 bgmac_err(bgmac, "DMA mapping error\n");
115 + dev_kfree_skb(skb);
116 return -ENOMEM;
117 }
118 +
119 + /* Update the slot */
120 + slot->skb = skb;
121 + slot->dma_addr = dma_addr;
122 +
123 if (slot->dma_addr & 0xC0000000)
124 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
125
126 return 0;
127 }
128
129 +static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
130 + struct bgmac_dma_ring *ring, int desc_idx)
131 +{
132 + struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
133 + u32 ctl0 = 0, ctl1 = 0;
134 +
135 + if (desc_idx == ring->num_slots - 1)
136 + ctl0 |= BGMAC_DESC_CTL0_EOT;
137 + ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
138 + /* Is there any BGMAC device that requires extension? */
139 + /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
140 + * B43_DMA64_DCTL1_ADDREXT_MASK;
141 + */
142 +
143 + dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
144 + dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
145 + dma_desc->ctl0 = cpu_to_le32(ctl0);
146 + dma_desc->ctl1 = cpu_to_le32(ctl1);
147 +}
148 +
149 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
150 int weight)
151 {
152 @@ -287,7 +346,6 @@ static int bgmac_dma_rx_read(struct bgma
153 struct device *dma_dev = bgmac->core->dma_dev;
154 struct bgmac_slot_info *slot = &ring->slots[ring->start];
155 struct sk_buff *skb = slot->skb;
156 - struct sk_buff *new_skb;
157 struct bgmac_rx_header *rx;
158 u16 len, flags;
159
160 @@ -300,38 +358,51 @@ static int bgmac_dma_rx_read(struct bgma
161 len = le16_to_cpu(rx->len);
162 flags = le16_to_cpu(rx->flags);
163
164 - /* Check for poison and drop or pass the packet */
165 - if (len == 0xdead && flags == 0xbeef) {
166 - bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
167 - ring->start);
168 - } else {
169 + do {
170 + dma_addr_t old_dma_addr = slot->dma_addr;
171 + int err;
172 +
173 + /* Check for poison and drop or pass the packet */
174 + if (len == 0xdead && flags == 0xbeef) {
175 + bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
176 + ring->start);
177 + dma_sync_single_for_device(dma_dev,
178 + slot->dma_addr,
179 + BGMAC_RX_BUF_SIZE,
180 + DMA_FROM_DEVICE);
181 + break;
182 + }
183 +
184 /* Omit CRC. */
185 len -= ETH_FCS_LEN;
186
187 - new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
188 - if (new_skb) {
189 - skb_put(new_skb, len);
190 - skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
191 - new_skb->data,
192 - len);
193 - skb_checksum_none_assert(skb);
194 - new_skb->protocol =
195 - eth_type_trans(new_skb, bgmac->net_dev);
196 - netif_receive_skb(new_skb);
197 - handled++;
198 - } else {
199 - bgmac->net_dev->stats.rx_dropped++;
200 - bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
201 + /* Prepare new skb as replacement */
202 + err = bgmac_dma_rx_skb_for_slot(bgmac, slot);
203 + if (err) {
204 + /* Poison the old skb */
205 + rx->len = cpu_to_le16(0xdead);
206 + rx->flags = cpu_to_le16(0xbeef);
207 +
208 + dma_sync_single_for_device(dma_dev,
209 + slot->dma_addr,
210 + BGMAC_RX_BUF_SIZE,
211 + DMA_FROM_DEVICE);
212 + break;
213 }
214 + bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
215
216 - /* Poison the old skb */
217 - rx->len = cpu_to_le16(0xdead);
218 - rx->flags = cpu_to_le16(0xbeef);
219 - }
220 -
221 - /* Make it back accessible to the hardware */
222 - dma_sync_single_for_device(dma_dev, slot->dma_addr,
223 - BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
224 + /* Unmap old skb, we'll pass it to the netfif */
225 + dma_unmap_single(dma_dev, old_dma_addr,
226 + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
227 +
228 + skb_put(skb, BGMAC_RX_FRAME_OFFSET + len);
229 + skb_pull(skb, BGMAC_RX_FRAME_OFFSET);
230 +
231 + skb_checksum_none_assert(skb);
232 + skb->protocol = eth_type_trans(skb, bgmac->net_dev);
233 + netif_receive_skb(skb);
234 + handled++;
235 + } while (0);
236
237 if (++ring->start >= BGMAC_RX_RING_SLOTS)
238 ring->start = 0;
239 @@ -495,8 +566,6 @@ err_dma_free:
240 static void bgmac_dma_init(struct bgmac *bgmac)
241 {
242 struct bgmac_dma_ring *ring;
243 - struct bgmac_dma_desc *dma_desc;
244 - u32 ctl0, ctl1;
245 int i;
246
247 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
248 @@ -529,23 +598,8 @@ static void bgmac_dma_init(struct bgmac
249 if (ring->unaligned)
250 bgmac_dma_rx_enable(bgmac, ring);
251
252 - for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
253 - j++, dma_desc++) {
254 - ctl0 = ctl1 = 0;
255 -
256 - if (j == ring->num_slots - 1)
257 - ctl0 |= BGMAC_DESC_CTL0_EOT;
258 - ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
259 - /* Is there any BGMAC device that requires extension? */
260 - /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
261 - * B43_DMA64_DCTL1_ADDREXT_MASK;
262 - */
263 -
264 - dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[j].dma_addr));
265 - dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[j].dma_addr));
266 - dma_desc->ctl0 = cpu_to_le32(ctl0);
267 - dma_desc->ctl1 = cpu_to_le32(ctl1);
268 - }
269 + for (j = 0; j < ring->num_slots; j++)
270 + bgmac_dma_rx_setup_desc(bgmac, ring, j);
271
272 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
273 ring->index_base +
274 @@ -651,70 +705,6 @@ static int bgmac_phy_write(struct bgmac
275 return 0;
276 }
277
278 -/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
279 -static void bgmac_phy_force(struct bgmac *bgmac)
280 -{
281 - u16 ctl;
282 - u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
283 - BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
284 -
285 - if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
286 - return;
287 -
288 - if (bgmac->autoneg)
289 - return;
290 -
291 - ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
292 - ctl &= mask;
293 - if (bgmac->full_duplex)
294 - ctl |= BGMAC_PHY_CTL_DUPLEX;
295 - if (bgmac->speed == BGMAC_SPEED_100)
296 - ctl |= BGMAC_PHY_CTL_SPEED_100;
297 - else if (bgmac->speed == BGMAC_SPEED_1000)
298 - ctl |= BGMAC_PHY_CTL_SPEED_1000;
299 - bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
300 -}
301 -
302 -/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
303 -static void bgmac_phy_advertise(struct bgmac *bgmac)
304 -{
305 - u16 adv;
306 -
307 - if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
308 - return;
309 -
310 - if (!bgmac->autoneg)
311 - return;
312 -
313 - /* Adv selected 10/100 speeds */
314 - adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
315 - adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
316 - BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
317 - if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
318 - adv |= BGMAC_PHY_ADV_10HALF;
319 - if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
320 - adv |= BGMAC_PHY_ADV_100HALF;
321 - if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
322 - adv |= BGMAC_PHY_ADV_10FULL;
323 - if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
324 - adv |= BGMAC_PHY_ADV_100FULL;
325 - bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
326 -
327 - /* Adv selected 1000 speeds */
328 - adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
329 - adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
330 - if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
331 - adv |= BGMAC_PHY_ADV2_1000HALF;
332 - if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
333 - adv |= BGMAC_PHY_ADV2_1000FULL;
334 - bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
335 -
336 - /* Restart */
337 - bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
338 - bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
339 - BGMAC_PHY_CTL_RESTART);
340 -}
341 -
342 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
343 static void bgmac_phy_init(struct bgmac *bgmac)
344 {
345 @@ -758,11 +748,9 @@ static void bgmac_phy_reset(struct bgmac
346 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
347 return;
348
349 - bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
350 - BGMAC_PHY_CTL_RESET);
351 + bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
352 udelay(100);
353 - if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
354 - BGMAC_PHY_CTL_RESET)
355 + if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
356 bgmac_err(bgmac, "PHY reset failed\n");
357 bgmac_phy_init(bgmac);
358 }
359 @@ -780,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct
360 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
361 u32 new_val = (cmdcfg & mask) | set;
362
363 - bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
364 + bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
365 udelay(2);
366
367 if (new_val != cmdcfg || force)
368 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
369
370 - bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
371 + bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
372 udelay(2);
373 }
374
375 @@ -845,31 +833,56 @@ static void bgmac_clear_mib(struct bgmac
376 }
377
378 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
379 -static void bgmac_speed(struct bgmac *bgmac, int speed)
380 +static void bgmac_mac_speed(struct bgmac *bgmac)
381 {
382 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
383 u32 set = 0;
384
385 - if (speed & BGMAC_SPEED_10)
386 + switch (bgmac->mac_speed) {
387 + case SPEED_10:
388 set |= BGMAC_CMDCFG_ES_10;
389 - if (speed & BGMAC_SPEED_100)
390 + break;
391 + case SPEED_100:
392 set |= BGMAC_CMDCFG_ES_100;
393 - if (speed & BGMAC_SPEED_1000)
394 + break;
395 + case SPEED_1000:
396 set |= BGMAC_CMDCFG_ES_1000;
397 - if (!bgmac->full_duplex)
398 + break;
399 + case SPEED_2500:
400 + set |= BGMAC_CMDCFG_ES_2500;
401 + break;
402 + default:
403 + bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
404 + }
405 +
406 + if (bgmac->mac_duplex == DUPLEX_HALF)
407 set |= BGMAC_CMDCFG_HD;
408 +
409 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
410 }
411
412 static void bgmac_miiconfig(struct bgmac *bgmac)
413 {
414 - u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
415 - BGMAC_DS_MM_SHIFT;
416 - if (imode == 0 || imode == 1) {
417 - if (bgmac->autoneg)
418 - bgmac_speed(bgmac, BGMAC_SPEED_100);
419 - else
420 - bgmac_speed(bgmac, bgmac->speed);
421 + struct bcma_device *core = bgmac->core;
422 + struct bcma_chipinfo *ci = &core->bus->chipinfo;
423 + u8 imode;
424 +
425 + if (ci->id == BCMA_CHIP_ID_BCM4707 ||
426 + ci->id == BCMA_CHIP_ID_BCM53018) {
427 + bcma_awrite32(core, BCMA_IOCTL,
428 + bcma_aread32(core, BCMA_IOCTL) | 0x40 |
429 + BGMAC_BCMA_IOCTL_SW_CLKEN);
430 + bgmac->mac_speed = SPEED_2500;
431 + bgmac->mac_duplex = DUPLEX_FULL;
432 + bgmac_mac_speed(bgmac);
433 + } else {
434 + imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
435 + BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
436 + if (imode == 0 || imode == 1) {
437 + bgmac->mac_speed = SPEED_100;
438 + bgmac->mac_duplex = DUPLEX_FULL;
439 + bgmac_mac_speed(bgmac);
440 + }
441 }
442 }
443
444 @@ -879,7 +892,7 @@ static void bgmac_chip_reset(struct bgma
445 struct bcma_device *core = bgmac->core;
446 struct bcma_bus *bus = core->bus;
447 struct bcma_chipinfo *ci = &bus->chipinfo;
448 - u32 flags = 0;
449 + u32 flags;
450 u32 iost;
451 int i;
452
453 @@ -902,26 +915,36 @@ static void bgmac_chip_reset(struct bgma
454 }
455
456 iost = bcma_aread32(core, BCMA_IOST);
457 - if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
458 + if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
459 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
460 - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
461 + (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
462 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
463
464 - if (iost & BGMAC_BCMA_IOST_ATTACHED) {
465 - flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
466 - if (!bgmac->has_robosw)
467 - flags |= BGMAC_BCMA_IOCTL_SW_RESET;
468 + /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
469 + if (ci->id != BCMA_CHIP_ID_BCM4707) {
470 + flags = 0;
471 + if (iost & BGMAC_BCMA_IOST_ATTACHED) {
472 + flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
473 + if (!bgmac->has_robosw)
474 + flags |= BGMAC_BCMA_IOCTL_SW_RESET;
475 + }
476 + bcma_core_enable(core, flags);
477 }
478
479 - bcma_core_enable(core, flags);
480 -
481 - if (core->id.rev > 2) {
482 - bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
483 - bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
484 + /* Request Misc PLL for corerev > 2 */
485 + if (core->id.rev > 2 &&
486 + ci->id != BCMA_CHIP_ID_BCM4707 &&
487 + ci->id != BCMA_CHIP_ID_BCM53018) {
488 + bgmac_set(bgmac, BCMA_CLKCTLST,
489 + BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
490 + bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
491 + BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
492 + BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
493 1000);
494 }
495
496 - if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
497 + if (ci->id == BCMA_CHIP_ID_BCM5357 ||
498 + ci->id == BCMA_CHIP_ID_BCM4749 ||
499 ci->id == BCMA_CHIP_ID_BCM53572) {
500 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
501 u8 et_swtype = 0;
502 @@ -936,10 +959,11 @@ static void bgmac_chip_reset(struct bgma
503 et_swtype &= 0x0f;
504 et_swtype <<= 4;
505 sw_type = et_swtype;
506 - } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
507 + } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
508 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
509 - } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
510 - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
511 + } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
512 + (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
513 + (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
514 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
515 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
516 }
517 @@ -976,8 +1000,10 @@ static void bgmac_chip_reset(struct bgma
518 BGMAC_CMDCFG_PROM |
519 BGMAC_CMDCFG_NLC |
520 BGMAC_CMDCFG_CFE |
521 - BGMAC_CMDCFG_SR,
522 + BGMAC_CMDCFG_SR(core->id.rev),
523 false);
524 + bgmac->mac_speed = SPEED_UNKNOWN;
525 + bgmac->mac_duplex = DUPLEX_UNKNOWN;
526
527 bgmac_clear_mib(bgmac);
528 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
529 @@ -988,6 +1014,8 @@ static void bgmac_chip_reset(struct bgma
530 bgmac_miiconfig(bgmac);
531 bgmac_phy_init(bgmac);
532
533 + netdev_reset_queue(bgmac->net_dev);
534 +
535 bgmac->int_status = 0;
536 }
537
538 @@ -1015,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
539
540 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
541 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
542 - BGMAC_CMDCFG_SR, true);
543 + BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
544 udelay(2);
545 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
546 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
547 @@ -1044,12 +1072,16 @@ static void bgmac_enable(struct bgmac *b
548 break;
549 }
550
551 - rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
552 - rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
553 - bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
554 - mdp = (bp_clk * 128 / 1000) - 3;
555 - rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
556 - bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
557 + if (ci->id != BCMA_CHIP_ID_BCM4707 &&
558 + ci->id != BCMA_CHIP_ID_BCM53018) {
559 + rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
560 + rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
561 + bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
562 + 1000000;
563 + mdp = (bp_clk * 128 / 1000) - 3;
564 + rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
565 + bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
566 + }
567 }
568
569 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
570 @@ -1075,13 +1107,6 @@ static void bgmac_chip_init(struct bgmac
571
572 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
573
574 - if (!bgmac->autoneg) {
575 - bgmac_speed(bgmac, bgmac->speed);
576 - bgmac_phy_force(bgmac);
577 - } else if (bgmac->speed) { /* if there is anything to adv */
578 - bgmac_phy_advertise(bgmac);
579 - }
580 -
581 if (full_init) {
582 bgmac_dma_init(bgmac);
583 if (1) /* FIXME: is there any case we don't want IRQs? */
584 @@ -1171,6 +1196,8 @@ static int bgmac_open(struct net_device
585 }
586 napi_enable(&bgmac->napi);
587
588 + phy_start(bgmac->phy_dev);
589 +
590 netif_carrier_on(net_dev);
591
592 err_out:
593 @@ -1183,6 +1210,8 @@ static int bgmac_stop(struct net_device
594
595 netif_carrier_off(net_dev);
596
597 + phy_stop(bgmac->phy_dev);
598 +
599 napi_disable(&bgmac->napi);
600 bgmac_chip_intrs_off(bgmac);
601 free_irq(bgmac->core->irq, net_dev);
602 @@ -1219,27 +1248,11 @@ static int bgmac_set_mac_address(struct
603 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
604 {
605 struct bgmac *bgmac = netdev_priv(net_dev);
606 - struct mii_ioctl_data *data = if_mii(ifr);
607
608 - switch (cmd) {
609 - case SIOCGMIIPHY:
610 - data->phy_id = bgmac->phyaddr;
611 - /* fallthru */
612 - case SIOCGMIIREG:
613 - if (!netif_running(net_dev))
614 - return -EAGAIN;
615 - data->val_out = bgmac_phy_read(bgmac, data->phy_id,
616 - data->reg_num & 0x1f);
617 - return 0;
618 - case SIOCSMIIREG:
619 - if (!netif_running(net_dev))
620 - return -EAGAIN;
621 - bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
622 - data->val_in);
623 - return 0;
624 - default:
625 - return -EOPNOTSUPP;
626 - }
627 + if (!netif_running(net_dev))
628 + return -EINVAL;
629 +
630 + return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
631 }
632
633 static const struct net_device_ops bgmac_netdev_ops = {
634 @@ -1261,61 +1274,16 @@ static int bgmac_get_settings(struct net
635 {
636 struct bgmac *bgmac = netdev_priv(net_dev);
637
638 - cmd->supported = SUPPORTED_10baseT_Half |
639 - SUPPORTED_10baseT_Full |
640 - SUPPORTED_100baseT_Half |
641 - SUPPORTED_100baseT_Full |
642 - SUPPORTED_1000baseT_Half |
643 - SUPPORTED_1000baseT_Full |
644 - SUPPORTED_Autoneg;
645 -
646 - if (bgmac->autoneg) {
647 - WARN_ON(cmd->advertising);
648 - if (bgmac->full_duplex) {
649 - if (bgmac->speed & BGMAC_SPEED_10)
650 - cmd->advertising |= ADVERTISED_10baseT_Full;
651 - if (bgmac->speed & BGMAC_SPEED_100)
652 - cmd->advertising |= ADVERTISED_100baseT_Full;
653 - if (bgmac->speed & BGMAC_SPEED_1000)
654 - cmd->advertising |= ADVERTISED_1000baseT_Full;
655 - } else {
656 - if (bgmac->speed & BGMAC_SPEED_10)
657 - cmd->advertising |= ADVERTISED_10baseT_Half;
658 - if (bgmac->speed & BGMAC_SPEED_100)
659 - cmd->advertising |= ADVERTISED_100baseT_Half;
660 - if (bgmac->speed & BGMAC_SPEED_1000)
661 - cmd->advertising |= ADVERTISED_1000baseT_Half;
662 - }
663 - } else {
664 - switch (bgmac->speed) {
665 - case BGMAC_SPEED_10:
666 - ethtool_cmd_speed_set(cmd, SPEED_10);
667 - break;
668 - case BGMAC_SPEED_100:
669 - ethtool_cmd_speed_set(cmd, SPEED_100);
670 - break;
671 - case BGMAC_SPEED_1000:
672 - ethtool_cmd_speed_set(cmd, SPEED_1000);
673 - break;
674 - }
675 - }
676 -
677 - cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
678 -
679 - cmd->autoneg = bgmac->autoneg;
680 -
681 - return 0;
682 + return phy_ethtool_gset(bgmac->phy_dev, cmd);
683 }
684
685 -#if 0
686 static int bgmac_set_settings(struct net_device *net_dev,
687 struct ethtool_cmd *cmd)
688 {
689 struct bgmac *bgmac = netdev_priv(net_dev);
690
691 - return -1;
692 + return phy_ethtool_sset(bgmac->phy_dev, cmd);
693 }
694 -#endif
695
696 static void bgmac_get_drvinfo(struct net_device *net_dev,
697 struct ethtool_drvinfo *info)
698 @@ -1326,6 +1294,7 @@ static void bgmac_get_drvinfo(struct net
699
700 static const struct ethtool_ops bgmac_ethtool_ops = {
701 .get_settings = bgmac_get_settings,
702 + .set_settings = bgmac_set_settings,
703 .get_drvinfo = bgmac_get_drvinfo,
704 };
705
706 @@ -1344,9 +1313,35 @@ static int bgmac_mii_write(struct mii_bu
707 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
708 }
709
710 +static void bgmac_adjust_link(struct net_device *net_dev)
711 +{
712 + struct bgmac *bgmac = netdev_priv(net_dev);
713 + struct phy_device *phy_dev = bgmac->phy_dev;
714 + bool update = false;
715 +
716 + if (phy_dev->link) {
717 + if (phy_dev->speed != bgmac->mac_speed) {
718 + bgmac->mac_speed = phy_dev->speed;
719 + update = true;
720 + }
721 +
722 + if (phy_dev->duplex != bgmac->mac_duplex) {
723 + bgmac->mac_duplex = phy_dev->duplex;
724 + update = true;
725 + }
726 + }
727 +
728 + if (update) {
729 + bgmac_mac_speed(bgmac);
730 + phy_print_status(phy_dev);
731 + }
732 +}
733 +
734 static int bgmac_mii_register(struct bgmac *bgmac)
735 {
736 struct mii_bus *mii_bus;
737 + struct phy_device *phy_dev;
738 + char bus_id[MII_BUS_ID_SIZE + 3];
739 int i, err = 0;
740
741 mii_bus = mdiobus_alloc();
742 @@ -1378,8 +1373,22 @@ static int bgmac_mii_register(struct bgm
743
744 bgmac->mii_bus = mii_bus;
745
746 + /* Connect to the PHY */
747 + snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
748 + bgmac->phyaddr);
749 + phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
750 + PHY_INTERFACE_MODE_MII);
751 + if (IS_ERR(phy_dev)) {
752 + bgmac_err(bgmac, "PHY connecton failed\n");
753 + err = PTR_ERR(phy_dev);
754 + goto err_unregister_bus;
755 + }
756 + bgmac->phy_dev = phy_dev;
757 +
758 return err;
759
760 +err_unregister_bus:
761 + mdiobus_unregister(mii_bus);
762 err_free_irq:
763 kfree(mii_bus->irq);
764 err_free_bus:
765 @@ -1434,9 +1443,6 @@ static int bgmac_probe(struct bcma_devic
766 bcma_set_drvdata(core, bgmac);
767
768 /* Defaults */
769 - bgmac->autoneg = true;
770 - bgmac->full_duplex = true;
771 - bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
772 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
773
774 /* On BCM4706 we need common core to access PHY */
775 @@ -1467,6 +1473,27 @@ static int bgmac_probe(struct bcma_devic
776
777 bgmac_chip_reset(bgmac);
778
779 + /* For Northstar, we have to take all GMAC core out of reset */
780 + if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
781 + core->id.id == BCMA_CHIP_ID_BCM53018) {
782 + struct bcma_device *ns_core;
783 + int ns_gmac;
784 +
785 + /* Northstar has 4 GMAC cores */
786 + for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
787 + /* As Northstar requirement, we have to reset all GMACs
788 + * before accessing one. bgmac_chip_reset() call
789 + * bcma_core_enable() for this core. Then the other
790 + * three GMACs didn't reset. We do it here.
791 + */
792 + ns_core = bcma_find_core_unit(core->bus,
793 + BCMA_CORE_MAC_GBIT,
794 + ns_gmac);
795 + if (ns_core && !bcma_core_is_enabled(ns_core))
796 + bcma_core_enable(ns_core, 0);
797 + }
798 + }
799 +
800 err = bgmac_dma_alloc(bgmac);
801 if (err) {
802 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
803 @@ -1491,14 +1518,12 @@ static int bgmac_probe(struct bcma_devic
804 err = bgmac_mii_register(bgmac);
805 if (err) {
806 bgmac_err(bgmac, "Cannot register MDIO\n");
807 - err = -ENOTSUPP;
808 goto err_dma_free;
809 }
810
811 err = register_netdev(bgmac->net_dev);
812 if (err) {
813 bgmac_err(bgmac, "Cannot register net device\n");
814 - err = -ENOTSUPP;
815 goto err_mii_unregister;
816 }
817
818 --- a/drivers/net/ethernet/broadcom/bgmac.h
819 +++ b/drivers/net/ethernet/broadcom/bgmac.h
820 @@ -95,7 +95,11 @@
821 #define BGMAC_RXQ_CTL_MDP_SHIFT 24
822 #define BGMAC_GPIO_SELECT 0x194
823 #define BGMAC_GPIO_OUTPUT_EN 0x198
824 -/* For 0x1e0 see BCMA_CLKCTLST */
825 +
826 +/* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
827 +#define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100
828 +#define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000
829 +
830 #define BGMAC_HW_WAR 0x1e4
831 #define BGMAC_PWR_CTL 0x1e8
832 #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
833 @@ -185,6 +189,7 @@
834 #define BGMAC_CMDCFG_ES_10 0x00000000
835 #define BGMAC_CMDCFG_ES_100 0x00000004
836 #define BGMAC_CMDCFG_ES_1000 0x00000008
837 +#define BGMAC_CMDCFG_ES_2500 0x0000000C
838 #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
839 #define BGMAC_CMDCFG_PAD_EN 0x00000020
840 #define BGMAC_CMDCFG_CF 0x00000040
841 @@ -193,7 +198,9 @@
842 #define BGMAC_CMDCFG_TAI 0x00000200
843 #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
844 #define BGMAC_CMDCFG_HD_SHIFT 10
845 -#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
846 +#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
847 +#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
848 +#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
849 #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
850 #define BGMAC_CMDCFG_AE 0x00400000
851 #define BGMAC_CMDCFG_CFE 0x00800000
852 @@ -216,27 +223,6 @@
853 #define BGMAC_RX_STATUS 0xb38
854 #define BGMAC_TX_STATUS 0xb3c
855
856 -#define BGMAC_PHY_CTL 0x00
857 -#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
858 -#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
859 -#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
860 -#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
861 -#define BGMAC_PHY_CTL_SPEED 0x2000
862 -#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
863 -#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
864 -/* Helpers */
865 -#define BGMAC_PHY_CTL_SPEED_10 0
866 -#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
867 -#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
868 -#define BGMAC_PHY_ADV 0x04
869 -#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
870 -#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
871 -#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
872 -#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
873 -#define BGMAC_PHY_ADV2 0x09
874 -#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
875 -#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
876 -
877 /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
878 #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
879 #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
880 @@ -254,9 +240,34 @@
881 #define BGMAC_DMA_TX_SUSPEND 0x00000002
882 #define BGMAC_DMA_TX_LOOPBACK 0x00000004
883 #define BGMAC_DMA_TX_FLUSH 0x00000010
884 +#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
885 +#define BGMAC_DMA_TX_MR_SHIFT 6
886 +#define BGMAC_DMA_TX_MR_1 0
887 +#define BGMAC_DMA_TX_MR_2 1
888 #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
889 #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
890 #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
891 +#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
892 +#define BGMAC_DMA_TX_BL_SHIFT 18
893 +#define BGMAC_DMA_TX_BL_16 0
894 +#define BGMAC_DMA_TX_BL_32 1
895 +#define BGMAC_DMA_TX_BL_64 2
896 +#define BGMAC_DMA_TX_BL_128 3
897 +#define BGMAC_DMA_TX_BL_256 4
898 +#define BGMAC_DMA_TX_BL_512 5
899 +#define BGMAC_DMA_TX_BL_1024 6
900 +#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
901 +#define BGMAC_DMA_TX_PC_SHIFT 21
902 +#define BGMAC_DMA_TX_PC_0 0
903 +#define BGMAC_DMA_TX_PC_4 1
904 +#define BGMAC_DMA_TX_PC_8 2
905 +#define BGMAC_DMA_TX_PC_16 3
906 +#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
907 +#define BGMAC_DMA_TX_PT_SHIFT 24
908 +#define BGMAC_DMA_TX_PT_1 0
909 +#define BGMAC_DMA_TX_PT_2 1
910 +#define BGMAC_DMA_TX_PT_4 2
911 +#define BGMAC_DMA_TX_PT_8 3
912 #define BGMAC_DMA_TX_INDEX 0x04
913 #define BGMAC_DMA_TX_RINGLO 0x08
914 #define BGMAC_DMA_TX_RINGHI 0x0C
915 @@ -284,8 +295,33 @@
916 #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
917 #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
918 #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
919 +#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
920 +#define BGMAC_DMA_RX_MR_SHIFT 6
921 +#define BGMAC_DMA_TX_MR_1 0
922 +#define BGMAC_DMA_TX_MR_2 1
923 #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
924 #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
925 +#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
926 +#define BGMAC_DMA_RX_BL_SHIFT 18
927 +#define BGMAC_DMA_RX_BL_16 0
928 +#define BGMAC_DMA_RX_BL_32 1
929 +#define BGMAC_DMA_RX_BL_64 2
930 +#define BGMAC_DMA_RX_BL_128 3
931 +#define BGMAC_DMA_RX_BL_256 4
932 +#define BGMAC_DMA_RX_BL_512 5
933 +#define BGMAC_DMA_RX_BL_1024 6
934 +#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
935 +#define BGMAC_DMA_RX_PC_SHIFT 21
936 +#define BGMAC_DMA_RX_PC_0 0
937 +#define BGMAC_DMA_RX_PC_4 1
938 +#define BGMAC_DMA_RX_PC_8 2
939 +#define BGMAC_DMA_RX_PC_16 3
940 +#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
941 +#define BGMAC_DMA_RX_PT_SHIFT 24
942 +#define BGMAC_DMA_RX_PT_1 0
943 +#define BGMAC_DMA_RX_PT_2 1
944 +#define BGMAC_DMA_RX_PT_4 2
945 +#define BGMAC_DMA_RX_PT_8 3
946 #define BGMAC_DMA_RX_INDEX 0x24
947 #define BGMAC_DMA_RX_RINGLO 0x28
948 #define BGMAC_DMA_RX_RINGHI 0x2C
949 @@ -342,10 +378,6 @@
950 #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
951 #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
952
953 -#define BGMAC_SPEED_10 0x0001
954 -#define BGMAC_SPEED_100 0x0002
955 -#define BGMAC_SPEED_1000 0x0004
956 -
957 #define BGMAC_WEIGHT 64
958
959 #define ETHER_MAX_LEN 1518
960 @@ -402,6 +434,7 @@ struct bgmac {
961 struct net_device *net_dev;
962 struct napi_struct napi;
963 struct mii_bus *mii_bus;
964 + struct phy_device *phy_dev;
965
966 /* DMA */
967 struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
968 @@ -416,10 +449,9 @@ struct bgmac {
969 u32 int_mask;
970 u32 int_status;
971
972 - /* Speed-related */
973 - int speed;
974 - bool autoneg;
975 - bool full_duplex;
976 + /* Current MAC state */
977 + int mac_speed;
978 + int mac_duplex;
979
980 u8 phyaddr;
981 bool has_robosw;
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