target/linux/ipq40xx/patches-5.15/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch

   1 From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Wed, 9 Sep 2020 18:38:31 +0200
   4 Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
   5
   6 Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
  10 Cc: Luka Perkov <luka.perkov@sartura.hr>
  11 Reviewed-by: Vinod Koul <vkoul@kernel.org>
  12 Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
  13 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  14 ---
  15  arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
  16  1 file changed, 74 insertions(+)
  17
  18 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  19 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  20 @@ -605,5 +605,79 @@
  21                                 reg = <4>;
  22                         };
  23                 };
  24 +
  25 +               usb3_ss_phy: ssphy@9a000 {
  26 +                       compatible = "qcom,usb-ss-ipq4019-phy";
  27 +                       #phy-cells = <0>;
  28 +                       reg = <0x9a000 0x800>;
  29 +                       reg-names = "phy_base";
  30 +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
  31 +                       reset-names = "por_rst";
  32 +                       status = "disabled";
  33 +               };
  34 +
  35 +               usb3_hs_phy: hsphy@a6000 {
  36 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  37 +                       #phy-cells = <0>;
  38 +                       reg = <0xa6000 0x40>;
  39 +                       reg-names = "phy_base";
  40 +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
  41 +                       reset-names = "por_rst", "srif_rst";
  42 +                       status = "disabled";
  43 +               };
  44 +
  45 +               usb3: usb3@8af8800 {
  46 +                       compatible = "qcom,dwc3";
  47 +                       reg = <0x8af8800 0x100>;
  48 +                       #address-cells = <1>;
  49 +                       #size-cells = <1>;
  50 +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
  51 +                                <&gcc GCC_USB3_SLEEP_CLK>,
  52 +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  53 +                       clock-names = "master", "sleep", "mock_utmi";
  54 +                       ranges;
  55 +                       status = "disabled";
  56 +
  57 +                       dwc3@8a00000 {
  58 +                               compatible = "snps,dwc3";
  59 +                               reg = <0x8a00000 0xf8000>;
  60 +                               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  61 +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
  62 +                               phy-names = "usb2-phy", "usb3-phy";
  63 +                               dr_mode = "host";
  64 +                       };
  65 +               };
  66 +
  67 +               usb2_hs_phy: hsphy@a8000 {
  68 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  69 +                       #phy-cells = <0>;
  70 +                       reg = <0xa8000 0x40>;
  71 +                       reg-names = "phy_base";
  72 +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
  73 +                       reset-names = "por_rst", "srif_rst";
  74 +                       status = "disabled";
  75 +               };
  76 +
  77 +               usb2: usb2@60f8800 {
  78 +                       compatible = "qcom,dwc3";
  79 +                       reg = <0x60f8800 0x100>;
  80 +                       #address-cells = <1>;
  81 +                       #size-cells = <1>;
  82 +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
  83 +                                <&gcc GCC_USB2_SLEEP_CLK>,
  84 +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
  85 +                       clock-names = "master", "sleep", "mock_utmi";
  86 +                       ranges;
  87 +                       status = "disabled";
  88 +
  89 +                       dwc3@6000000 {
  90 +                               compatible = "snps,dwc3";
  91 +                               reg = <0x6000000 0xf8000>;
  92 +                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  93 +                               phys = <&usb2_hs_phy>;
  94 +                               phy-names = "usb2-phy";
  95 +                               dr_mode = "host";
  96 +                       };
  97 +               };
  98         };
  99  };