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ipq806x: copy kernel 5.4 patches to 5.10
[openwrt/staging/dedeckeh.git] / target / linux / ipq806x / patches-5.10 / 083-ipq8064-dtsi-additions.patch
1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
3 @@ -8,6 +8,8 @@
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
9
10 / {
11 #address-cells = <1>;
12 @@ -28,6 +30,16 @@
13 next-level-cache = <&L2>;
14 qcom,acc = <&acc0>;
15 qcom,saw = <&saw0>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
26 };
27
28 cpu1: cpu@1 {
29 @@ -38,11 +50,458 @@
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc1>;
32 qcom,saw = <&saw1>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
43 };
44
45 L2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 + qcom,saw = <&saw_l2>;
49 + };
50 +
51 + qcom,l2 {
52 + qcom,l2-rates = <384000000 1000000000 1200000000>;
53 + qcom,l2-cpufreq = <384000000 600000000 1200000000>;
54 + qcom,l2-volt = <1100000 1100000 1150000>;
55 + qcom,l2-supply = <&smb208_s1a>;
56 + };
57 +
58 + idle-states {
59 + CPU_SPC: spc {
60 + compatible = "qcom,idle-state-spc", "arm,idle-state";
61 + status = "disabled";
62 + entry-latency-us = <400>;
63 + exit-latency-us = <900>;
64 + min-residency-us = <3000>;
65 + };
66 + };
67 + };
68 +
69 + opp_table0: opp_table0 {
70 + compatible = "operating-points-v2-kryo-cpu";
71 + nvmem-cells = <&speedbin_efuse>;
72 +
73 + opp-384000000 {
74 + opp-hz = /bits/ 64 <384000000>;
75 + opp-microvolt-speed0-pvs0-v0 = <1000000>;
76 + opp-microvolt-speed0-pvs1-v0 = <925000>;
77 + opp-microvolt-speed0-pvs2-v0 = <875000>;
78 + opp-microvolt-speed0-pvs3-v0 = <800000>;
79 + opp-supported-hw = <0x1>;
80 + clock-latency-ns = <100000>;
81 + };
82 +
83 + opp-600000000 {
84 + opp-hz = /bits/ 64 <600000000>;
85 + opp-microvolt-speed0-pvs0-v0 = <1050000>;
86 + opp-microvolt-speed0-pvs1-v0 = <975000>;
87 + opp-microvolt-speed0-pvs2-v0 = <925000>;
88 + opp-microvolt-speed0-pvs3-v0 = <850000>;
89 + opp-supported-hw = <0x1>;
90 + clock-latency-ns = <100000>;
91 + };
92 +
93 + opp-800000000 {
94 + opp-hz = /bits/ 64 <800000000>;
95 + opp-microvolt-speed0-pvs0-v0 = <1100000>;
96 + opp-microvolt-speed0-pvs1-v0 = <1025000>;
97 + opp-microvolt-speed0-pvs2-v0 = <995000>;
98 + opp-microvolt-speed0-pvs3-v0 = <900000>;
99 + opp-supported-hw = <0x1>;
100 + clock-latency-ns = <100000>;
101 + };
102 +
103 + opp-1000000000 {
104 + opp-hz = /bits/ 64 <1000000000>;
105 + opp-microvolt-speed0-pvs0-v0 = <1150000>;
106 + opp-microvolt-speed0-pvs1-v0 = <1075000>;
107 + opp-microvolt-speed0-pvs2-v0 = <1025000>;
108 + opp-microvolt-speed0-pvs3-v0 = <950000>;
109 + opp-supported-hw = <0x1>;
110 + clock-latency-ns = <100000>;
111 + };
112 +
113 + opp-1200000000 {
114 + opp-hz = /bits/ 64 <1200000000>;
115 + opp-microvolt-speed0-pvs0-v0 = <1200000>;
116 + opp-microvolt-speed0-pvs1-v0 = <1125000>;
117 + opp-microvolt-speed0-pvs2-v0 = <1075000>;
118 + opp-microvolt-speed0-pvs3-v0 = <1000000>;
119 + opp-supported-hw = <0x1>;
120 + clock-latency-ns = <100000>;
121 + };
122 +
123 + opp-1400000000 {
124 + opp-hz = /bits/ 64 <1400000000>;
125 + opp-microvolt-speed0-pvs0-v0 = <1250000>;
126 + opp-microvolt-speed0-pvs1-v0 = <1175000>;
127 + opp-microvolt-speed0-pvs2-v0 = <1125000>;
128 + opp-microvolt-speed0-pvs3-v0 = <1050000>;
129 + opp-supported-hw = <0x1>;
130 + clock-latency-ns = <100000>;
131 + };
132 + };
133 +
134 + thermal-zones {
135 + tsens_tz_sensor0 {
136 + polling-delay-passive = <0>;
137 + polling-delay = <0>;
138 + thermal-sensors = <&tsens 0>;
139 +
140 + trips {
141 + cpu-critical-hi {
142 + temperature = <125000>;
143 + hysteresis = <2000>;
144 + type = "critical_high";
145 + };
146 +
147 + cpu-config-hi {
148 + temperature = <105000>;
149 + hysteresis = <2000>;
150 + type = "configurable_hi";
151 + };
152 +
153 + cpu-config-lo {
154 + temperature = <95000>;
155 + hysteresis = <2000>;
156 + type = "configurable_lo";
157 + };
158 +
159 + cpu-critical-low {
160 + temperature = <0>;
161 + hysteresis = <2000>;
162 + type = "critical_low";
163 + };
164 + };
165 + };
166 +
167 + tsens_tz_sensor1 {
168 + polling-delay-passive = <0>;
169 + polling-delay = <0>;
170 + thermal-sensors = <&tsens 1>;
171 +
172 + trips {
173 + cpu-critical-hi {
174 + temperature = <125000>;
175 + hysteresis = <2000>;
176 + type = "critical_high";
177 + };
178 +
179 + cpu-config-hi {
180 + temperature = <105000>;
181 + hysteresis = <2000>;
182 + type = "configurable_hi";
183 + };
184 +
185 + cpu-config-lo {
186 + temperature = <95000>;
187 + hysteresis = <2000>;
188 + type = "configurable_lo";
189 + };
190 +
191 + cpu-critical-low {
192 + temperature = <0>;
193 + hysteresis = <2000>;
194 + type = "critical_low";
195 + };
196 + };
197 + };
198 +
199 + tsens_tz_sensor2 {
200 + polling-delay-passive = <0>;
201 + polling-delay = <0>;
202 + thermal-sensors = <&tsens 2>;
203 +
204 + trips {
205 + cpu-critical-hi {
206 + temperature = <125000>;
207 + hysteresis = <2000>;
208 + type = "critical_high";
209 + };
210 +
211 + cpu-config-hi {
212 + temperature = <105000>;
213 + hysteresis = <2000>;
214 + type = "configurable_hi";
215 + };
216 +
217 + cpu-config-lo {
218 + temperature = <95000>;
219 + hysteresis = <2000>;
220 + type = "configurable_lo";
221 + };
222 +
223 + cpu-critical-low {
224 + temperature = <0>;
225 + hysteresis = <2000>;
226 + type = "critical_low";
227 + };
228 + };
229 + };
230 +
231 + tsens_tz_sensor3 {
232 + polling-delay-passive = <0>;
233 + polling-delay = <0>;
234 + thermal-sensors = <&tsens 3>;
235 +
236 + trips {
237 + cpu-critical-hi {
238 + temperature = <125000>;
239 + hysteresis = <2000>;
240 + type = "critical_high";
241 + };
242 +
243 + cpu-config-hi {
244 + temperature = <105000>;
245 + hysteresis = <2000>;
246 + type = "configurable_hi";
247 + };
248 +
249 + cpu-config-lo {
250 + temperature = <95000>;
251 + hysteresis = <2000>;
252 + type = "configurable_lo";
253 + };
254 +
255 + cpu-critical-low {
256 + temperature = <0>;
257 + hysteresis = <2000>;
258 + type = "critical_low";
259 + };
260 + };
261 + };
262 +
263 + tsens_tz_sensor4 {
264 + polling-delay-passive = <0>;
265 + polling-delay = <0>;
266 + thermal-sensors = <&tsens 4>;
267 +
268 + trips {
269 + cpu-critical-hi {
270 + temperature = <125000>;
271 + hysteresis = <2000>;
272 + type = "critical_high";
273 + };
274 +
275 + cpu-config-hi {
276 + temperature = <105000>;
277 + hysteresis = <2000>;
278 + type = "configurable_hi";
279 + };
280 +
281 + cpu-config-lo {
282 + temperature = <95000>;
283 + hysteresis = <2000>;
284 + type = "configurable_lo";
285 + };
286 +
287 + cpu-critical-low {
288 + temperature = <0>;
289 + hysteresis = <2000>;
290 + type = "critical_low";
291 + };
292 + };
293 + };
294 +
295 + tsens_tz_sensor5 {
296 + polling-delay-passive = <0>;
297 + polling-delay = <0>;
298 + thermal-sensors = <&tsens 5>;
299 +
300 + trips {
301 + cpu-critical-hi {
302 + temperature = <125000>;
303 + hysteresis = <2000>;
304 + type = "critical_high";
305 + };
306 +
307 + cpu-config-hi {
308 + temperature = <105000>;
309 + hysteresis = <2000>;
310 + type = "configurable_hi";
311 + };
312 +
313 + cpu-config-lo {
314 + temperature = <95000>;
315 + hysteresis = <2000>;
316 + type = "configurable_lo";
317 + };
318 +
319 + cpu-critical-low {
320 + temperature = <0>;
321 + hysteresis = <2000>;
322 + type = "critical_low";
323 + };
324 + };
325 + };
326 +
327 + tsens_tz_sensor6 {
328 + polling-delay-passive = <0>;
329 + polling-delay = <0>;
330 + thermal-sensors = <&tsens 6>;
331 +
332 + trips {
333 + cpu-critical-hi {
334 + temperature = <125000>;
335 + hysteresis = <2000>;
336 + type = "critical_high";
337 + };
338 +
339 + cpu-config-hi {
340 + temperature = <105000>;
341 + hysteresis = <2000>;
342 + type = "configurable_hi";
343 + };
344 +
345 + cpu-config-lo {
346 + temperature = <95000>;
347 + hysteresis = <2000>;
348 + type = "configurable_lo";
349 + };
350 +
351 + cpu-critical-low {
352 + temperature = <0>;
353 + hysteresis = <2000>;
354 + type = "critical_low";
355 + };
356 + };
357 + };
358 +
359 + tsens_tz_sensor7 {
360 + polling-delay-passive = <0>;
361 + polling-delay = <0>;
362 + thermal-sensors = <&tsens 7>;
363 +
364 + trips {
365 + cpu-critical-hi {
366 + temperature = <125000>;
367 + hysteresis = <2000>;
368 + type = "critical_high";
369 + };
370 +
371 + cpu-config-hi {
372 + temperature = <105000>;
373 + hysteresis = <2000>;
374 + type = "configurable_hi";
375 + };
376 +
377 + cpu-config-lo {
378 + temperature = <95000>;
379 + hysteresis = <2000>;
380 + type = "configurable_lo";
381 + };
382 +
383 + cpu-critical-low {
384 + temperature = <0>;
385 + hysteresis = <2000>;
386 + type = "critical_low";
387 + };
388 + };
389 + };
390 +
391 + tsens_tz_sensor8 {
392 + polling-delay-passive = <0>;
393 + polling-delay = <0>;
394 + thermal-sensors = <&tsens 8>;
395 +
396 + trips {
397 + cpu-critical-hi {
398 + temperature = <125000>;
399 + hysteresis = <2000>;
400 + type = "critical_high";
401 + };
402 +
403 + cpu-config-hi {
404 + temperature = <105000>;
405 + hysteresis = <2000>;
406 + type = "configurable_hi";
407 + };
408 +
409 + cpu-config-lo {
410 + temperature = <95000>;
411 + hysteresis = <2000>;
412 + type = "configurable_lo";
413 + };
414 +
415 + cpu-critical-low {
416 + temperature = <0>;
417 + hysteresis = <2000>;
418 + type = "critical_low";
419 + };
420 + };
421 + };
422 +
423 + tsens_tz_sensor9 {
424 + polling-delay-passive = <0>;
425 + polling-delay = <0>;
426 + thermal-sensors = <&tsens 9>;
427 +
428 + trips {
429 + cpu-critical-hi {
430 + temperature = <125000>;
431 + hysteresis = <2000>;
432 + type = "critical_high";
433 + };
434 +
435 + cpu-config-hi {
436 + temperature = <105000>;
437 + hysteresis = <2000>;
438 + type = "configurable_hi";
439 + };
440 +
441 + cpu-config-lo {
442 + temperature = <95000>;
443 + hysteresis = <2000>;
444 + type = "configurable_lo";
445 + };
446 +
447 + cpu-critical-low {
448 + temperature = <0>;
449 + hysteresis = <2000>;
450 + type = "critical_low";
451 + };
452 + };
453 + };
454 +
455 + tsens_tz_sensor10 {
456 + polling-delay-passive = <0>;
457 + polling-delay = <0>;
458 + thermal-sensors = <&tsens 10>;
459 +
460 + trips {
461 + cpu-critical-hi {
462 + temperature = <125000>;
463 + hysteresis = <2000>;
464 + type = "critical_high";
465 + };
466 +
467 + cpu-config-hi {
468 + temperature = <105000>;
469 + hysteresis = <2000>;
470 + type = "configurable_hi";
471 + };
472 +
473 + cpu-config-lo {
474 + temperature = <95000>;
475 + hysteresis = <2000>;
476 + type = "configurable_lo";
477 + };
478 +
479 + cpu-critical-low {
480 + temperature = <0>;
481 + hysteresis = <2000>;
482 + type = "critical_low";
483 + };
484 + };
485 };
486 };
487
488 @@ -93,6 +552,15 @@
489 };
490 };
491
492 + fab-scaling {
493 + compatible = "qcom,fab-scaling";
494 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
495 + clock-names = "apps-fab-clk", "ddr-fab-clk";
496 + fab_freq_high = <533000000>;
497 + fab_freq_nominal = <400000000>;
498 + cpu_freq_threshold = <1000000000>;
499 + };
500 +
501 firmware {
502 scm {
503 compatible = "qcom,scm-ipq806x", "qcom,scm";
504 @@ -120,6 +588,84 @@
505 reg-names = "lpass-lpaif";
506 };
507
508 + qfprom: qfprom@700000 {
509 + compatible = "qcom,qfprom", "syscon";
510 + reg = <0x700000 0x1000>;
511 + #address-cells = <1>;
512 + #size-cells = <1>;
513 + status = "okay";
514 + tsens_calib: calib@400 {
515 + reg = <0x400 0xb>;
516 + };
517 + tsens_backup: backup@410 {
518 + reg = <0x410 0xb>;
519 + };
520 + speedbin_efuse: speedbin@0c0 {
521 + reg = <0x0c0 0x4>;
522 + };
523 + };
524 +
525 + rpm: rpm@108000 {
526 + compatible = "qcom,rpm-ipq8064";
527 + reg = <0x108000 0x1000>;
528 + qcom,ipc = <&l2cc 0x8 2>;
529 +
530 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
531 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
532 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
533 + interrupt-names = "ack", "err", "wakeup";
534 +
535 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
536 + clock-names = "ram";
537 +
538 + #address-cells = <1>;
539 + #size-cells = <0>;
540 +
541 + rpmcc: clock-controller {
542 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
543 + #clock-cells = <1>;
544 + };
545 +
546 + regulators {
547 + compatible = "qcom,rpm-smb208-regulators";
548 +
549 + smb208_s1a: s1a {
550 + regulator-min-microvolt = <1050000>;
551 + regulator-max-microvolt = <1150000>;
552 +
553 + qcom,switch-mode-frequency = <1200000>;
554 + };
555 +
556 + smb208_s1b: s1b {
557 + regulator-min-microvolt = <1050000>;
558 + regulator-max-microvolt = <1150000>;
559 +
560 + qcom,switch-mode-frequency = <1200000>;
561 + };
562 +
563 + smb208_s2a: s2a {
564 + regulator-min-microvolt = < 800000>;
565 + regulator-max-microvolt = <1250000>;
566 +
567 + qcom,switch-mode-frequency = <1200000>;
568 + };
569 +
570 + smb208_s2b: s2b {
571 + regulator-min-microvolt = < 800000>;
572 + regulator-max-microvolt = <1250000>;
573 +
574 + qcom,switch-mode-frequency = <1200000>;
575 + };
576 + };
577 + };
578 +
579 + rng@1a500000 {
580 + compatible = "qcom,prng";
581 + reg = <0x1a500000 0x200>;
582 + clocks = <&gcc PRNG_CLK>;
583 + clock-names = "core";
584 + };
585 +
586 qcom_pinmux: pinmux@800000 {
587 compatible = "qcom,ipq8064-pinctrl";
588 reg = <0x800000 0x4000>;
589 @@ -159,6 +705,15 @@
590 };
591 };
592
593 + i2c4_pins: i2c4_pinmux {
594 + mux {
595 + pins = "gpio12", "gpio13";
596 + function = "gsbi4";
597 + drive-strength = <12>;
598 + bias-disable;
599 + };
600 + };
601 +
602 spi_pins: spi_pins {
603 mux {
604 pins = "gpio18", "gpio19", "gpio21";
605 @@ -168,6 +723,53 @@
606 };
607 };
608
609 + nand_pins: nand_pins {
610 + disable {
611 + pins = "gpio34", "gpio35", "gpio36",
612 + "gpio37", "gpio38";
613 + function = "nand";
614 + drive-strength = <10>;
615 + bias-disable;
616 + };
617 +
618 + pullups {
619 + pins = "gpio39";
620 + function = "nand";
621 + drive-strength = <10>;
622 + bias-pull-up;
623 + };
624 +
625 + hold {
626 + pins = "gpio40", "gpio41", "gpio42",
627 + "gpio43", "gpio44", "gpio45",
628 + "gpio46", "gpio47";
629 + function = "nand";
630 + drive-strength = <10>;
631 + bias-bus-hold;
632 + };
633 + };
634 +
635 + mdio0_pins: mdio0_pins {
636 + mux {
637 + pins = "gpio0", "gpio1";
638 + function = "mdio";
639 + drive-strength = <8>;
640 + bias-disable;
641 + };
642 + };
643 +
644 + rgmii2_pins: rgmii2_pins {
645 + mux {
646 + pins = "gpio27", "gpio28", "gpio29",
647 + "gpio30", "gpio31", "gpio32",
648 + "gpio51", "gpio52", "gpio59",
649 + "gpio60", "gpio61", "gpio62";
650 + function = "rgmii2";
651 + drive-strength = <8>;
652 + bias-disable;
653 + };
654 + };
655 +
656 leds_pins: leds_pins {
657 mux {
658 pins = "gpio7", "gpio8", "gpio9",
659 @@ -229,6 +831,17 @@
660 clock-output-names = "acpu1_aux";
661 };
662
663 + l2cc: clock-controller@2011000 {
664 + compatible = "qcom,kpss-gcc", "syscon";
665 + reg = <0x2011000 0x1000>;
666 + clock-output-names = "acpu_l2_aux";
667 + };
668 +
669 + kraitcc: clock-controller {
670 + compatible = "qcom,krait-cc-v1";
671 + #clock-cells = <1>;
672 + };
673 +
674 saw0: regulator@2089000 {
675 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
676 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
677 @@ -241,6 +854,17 @@
678 regulator;
679 };
680
681 + saw_l2: regulator@02012000 {
682 + compatible = "qcom,saw2", "syscon";
683 + reg = <0x02012000 0x1000>;
684 + regulator;
685 + };
686 +
687 + sic_non_secure: sic-non-secure@12100000 {
688 + compatible = "syscon";
689 + reg = <0x12100000 0x10000>;
690 + };
691 +
692 gsbi2: gsbi@12480000 {
693 compatible = "qcom,gsbi-v1.0.0";
694 cell-index = <2>;
695 @@ -436,6 +1060,15 @@
696 #power-domain-cells = <1>;
697 };
698
699 + tsens: thermal-sensor@900000 {
700 + compatible = "qcom,ipq8064-tsens";
701 + reg = <0x900000 0x3680>;
702 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
703 + nvmem-cell-names = "calib", "calib_backup";
704 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
705 + #thermal-sensor-cells = <1>;
706 + };
707 +
708 tcsr: syscon@1a400000 {
709 compatible = "qcom,tcsr-ipq8064", "syscon";
710 reg = <0x1a400000 0x100>;
711 @@ -448,6 +1081,95 @@
712 #reset-cells = <1>;
713 };
714
715 + sfpb_mutex_block: syscon@1200600 {
716 + compatible = "syscon";
717 + reg = <0x01200600 0x100>;
718 + };
719 +
720 + hs_phy_0: hs_phy_0 {
721 + compatible = "qcom,ipq806x-usb-phy-hs";
722 + reg = <0x110f8800 0x30>;
723 + clocks = <&gcc USB30_0_UTMI_CLK>;
724 + clock-names = "ref";
725 + #phy-cells = <0>;
726 + };
727 +
728 + ss_phy_0: ss_phy_0 {
729 + compatible = "qcom,ipq806x-usb-phy-ss";
730 + reg = <0x110f8830 0x30>;
731 + clocks = <&gcc USB30_0_MASTER_CLK>;
732 + clock-names = "ref";
733 + #phy-cells = <0>;
734 + };
735 +
736 + usb3_0: usb3@110f8800 {
737 + compatible = "qcom,dwc3", "syscon";
738 + #address-cells = <1>;
739 + #size-cells = <1>;
740 + reg = <0x110f8800 0x8000>;
741 + clocks = <&gcc USB30_0_MASTER_CLK>;
742 + clock-names = "core";
743 +
744 + ranges;
745 +
746 + resets = <&gcc USB30_0_MASTER_RESET>;
747 + reset-names = "master";
748 +
749 + status = "disabled";
750 +
751 + dwc3_0: dwc3@11000000 {
752 + compatible = "snps,dwc3";
753 + reg = <0x11000000 0xcd00>;
754 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
755 + phys = <&hs_phy_0>, <&ss_phy_0>;
756 + phy-names = "usb2-phy", "usb3-phy";
757 + dr_mode = "host";
758 + snps,dis_u3_susphy_quirk;
759 + };
760 + };
761 +
762 + hs_phy_1: hs_phy_1 {
763 + compatible = "qcom,ipq806x-usb-phy-hs";
764 + reg = <0x100f8800 0x30>;
765 + clocks = <&gcc USB30_1_UTMI_CLK>;
766 + clock-names = "ref";
767 + #phy-cells = <0>;
768 + };
769 +
770 + ss_phy_1: ss_phy_1 {
771 + compatible = "qcom,ipq806x-usb-phy-ss";
772 + reg = <0x100f8830 0x30>;
773 + clocks = <&gcc USB30_1_MASTER_CLK>;
774 + clock-names = "ref";
775 + #phy-cells = <0>;
776 + };
777 +
778 + usb3_1: usb3@100f8800 {
779 + compatible = "qcom,dwc3", "syscon";
780 + #address-cells = <1>;
781 + #size-cells = <1>;
782 + reg = <0x100f8800 0x8000>;
783 + clocks = <&gcc USB30_1_MASTER_CLK>;
784 + clock-names = "core";
785 +
786 + ranges;
787 +
788 + resets = <&gcc USB30_1_MASTER_RESET>;
789 + reset-names = "master";
790 +
791 + status = "disabled";
792 +
793 + dwc3_1: dwc3@10000000 {
794 + compatible = "snps,dwc3";
795 + reg = <0x10000000 0xcd00>;
796 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
797 + phys = <&hs_phy_1>, <&ss_phy_1>;
798 + phy-names = "usb2-phy", "usb3-phy";
799 + dr_mode = "host";
800 + snps,dis_u3_susphy_quirk;
801 + };
802 + };
803 +
804 pcie0: pci@1b500000 {
805 compatible = "qcom,pcie-ipq8064";
806 reg = <0x1b500000 0x1000
807 @@ -601,6 +1323,167 @@
808 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
809 };
810
811 + adm_dma: dma@18300000 {
812 + compatible = "qcom,adm";
813 + reg = <0x18300000 0x100000>;
814 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
815 + #dma-cells = <1>;
816 +
817 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
818 + clock-names = "core", "iface";
819 +
820 + resets = <&gcc ADM0_RESET>,
821 + <&gcc ADM0_PBUS_RESET>,
822 + <&gcc ADM0_C0_RESET>,
823 + <&gcc ADM0_C1_RESET>,
824 + <&gcc ADM0_C2_RESET>;
825 + reset-names = "clk", "pbus", "c0", "c1", "c2";
826 + qcom,ee = <0>;
827 +
828 + status = "disabled";
829 + };
830 +
831 + nand_controller: nand-controller@1ac00000 {
832 + compatible = "qcom,ipq806x-nand";
833 + reg = <0x1ac00000 0x800>;
834 +
835 + clocks = <&gcc EBI2_CLK>,
836 + <&gcc EBI2_AON_CLK>;
837 + clock-names = "core", "aon";
838 +
839 + dmas = <&adm_dma 3>;
840 + dma-names = "rxtx";
841 + qcom,cmd-crci = <15>;
842 + qcom,data-crci = <3>;
843 +
844 + status = "disabled";
845 +
846 + #address-cells = <1>;
847 + #size-cells = <0>;
848 + };
849 +
850 + nss_common: syscon@03000000 {
851 + compatible = "syscon";
852 + reg = <0x03000000 0x0000FFFF>;
853 + };
854 +
855 + qsgmii_csr: syscon@1bb00000 {
856 + compatible = "syscon";
857 + reg = <0x1bb00000 0x000001FF>;
858 + };
859 +
860 + stmmac_axi_setup: stmmac-axi-config {
861 + snps,wr_osr_lmt = <7>;
862 + snps,rd_osr_lmt = <7>;
863 + snps,blen = <16 0 0 0 0 0 0>;
864 + };
865 +
866 + mdio0: mdio@37000000 {
867 + #address-cells = <1>;
868 + #size-cells = <0>;
869 +
870 + compatible = "qcom,ipq8064-mdio", "syscon";
871 + reg = <0x37000000 0x200000>;
872 + resets = <&gcc GMAC_CORE1_RESET>;
873 + reset-names = "stmmaceth";
874 + clocks = <&gcc GMAC_CORE1_CLK>;
875 + clock-names = "stmmaceth";
876 +
877 + status = "disabled";
878 + };
879 +
880 + gmac0: ethernet@37000000 {
881 + device_type = "network";
882 + compatible = "qcom,ipq806x-gmac";
883 + reg = <0x37000000 0x200000>;
884 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
885 + interrupt-names = "macirq";
886 +
887 + snps,axi-config = <&stmmac_axi_setup>;
888 + snps,pbl = <32>;
889 + snps,aal = <1>;
890 +
891 + qcom,nss-common = <&nss_common>;
892 + qcom,qsgmii-csr = <&qsgmii_csr>;
893 +
894 + clocks = <&gcc GMAC_CORE1_CLK>;
895 + clock-names = "stmmaceth";
896 +
897 + resets = <&gcc GMAC_CORE1_RESET>;
898 + reset-names = "stmmaceth";
899 +
900 + status = "disabled";
901 + };
902 +
903 + gmac1: ethernet@37200000 {
904 + device_type = "network";
905 + compatible = "qcom,ipq806x-gmac";
906 + reg = <0x37200000 0x200000>;
907 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
908 + interrupt-names = "macirq";
909 +
910 + snps,axi-config = <&stmmac_axi_setup>;
911 + snps,pbl = <32>;
912 + snps,aal = <1>;
913 +
914 + qcom,nss-common = <&nss_common>;
915 + qcom,qsgmii-csr = <&qsgmii_csr>;
916 +
917 + clocks = <&gcc GMAC_CORE2_CLK>;
918 + clock-names = "stmmaceth";
919 +
920 + resets = <&gcc GMAC_CORE2_RESET>;
921 + reset-names = "stmmaceth";
922 +
923 + status = "disabled";
924 + };
925 +
926 + gmac2: ethernet@37400000 {
927 + device_type = "network";
928 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
929 + reg = <0x37400000 0x200000>;
930 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
931 + interrupt-names = "macirq";
932 +
933 + snps,axi-config = <&stmmac_axi_setup>;
934 + snps,pbl = <32>;
935 + snps,aal = <1>;
936 +
937 + qcom,nss-common = <&nss_common>;
938 + qcom,qsgmii-csr = <&qsgmii_csr>;
939 +
940 + clocks = <&gcc GMAC_CORE3_CLK>;
941 + clock-names = "stmmaceth";
942 +
943 + resets = <&gcc GMAC_CORE3_RESET>;
944 + reset-names = "stmmaceth";
945 +
946 + status = "disabled";
947 + };
948 +
949 + gmac3: ethernet@37600000 {
950 + device_type = "network";
951 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
952 + reg = <0x37600000 0x200000>;
953 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
954 + interrupt-names = "macirq";
955 +
956 + snps,axi-config = <&stmmac_axi_setup>;
957 + snps,pbl = <32>;
958 + snps,aal = <1>;
959 +
960 + qcom,nss-common = <&nss_common>;
961 + qcom,qsgmii-csr = <&qsgmii_csr>;
962 +
963 + clocks = <&gcc GMAC_CORE4_CLK>;
964 + clock-names = "stmmaceth";
965 +
966 + resets = <&gcc GMAC_CORE4_RESET>;
967 + reset-names = "stmmaceth";
968 +
969 + status = "disabled";
970 + };
971 +
972 vsdcc_fixed: vsdcc-regulator {
973 compatible = "regulator-fixed";
974 regulator-name = "SDCC Power";
975 @@ -676,4 +1559,17 @@
976 };
977 };
978 };
979 +
980 + sfpb_mutex: sfpb-mutex {
981 + compatible = "qcom,sfpb-mutex";
982 + syscon = <&sfpb_mutex_block 4 4>;
983 +
984 + #hwlock-cells = <1>;
985 + };
986 +
987 + smem {
988 + compatible = "qcom,smem";
989 + memory-region = <&smem>;
990 + hwlocks = <&sfpb_mutex 3>;
991 + };
992 };
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