target/linux/ipq806x/patches-5.10/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch

   1 From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
   2 From: Ajay Kishore <akisho@codeaurora.org>
   3 Date: Fri, 27 Mar 2020 23:32:08 +0100
   4 Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
   5
   6 For IPQ806x targets, TZ protects the registers that are used to
   7 configure the routing of interrupts to a target processor.
   8 To resolve this, this patch uses scm call to route GPIO interrupts
   9 to application processor. Also the scm call interface is changed.
  10
  11 Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
  14 Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  16 ---
  17  drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
  18  1 file changed, 37 insertions(+), 6 deletions(-)
  19
  20 (limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
  21
  22 --- a/drivers/pinctrl/qcom/pinctrl-msm.c
  23 +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
  24 @@ -22,6 +22,8 @@
  25  #include <linux/reboot.h>
  26  #include <linux/pm.h>
  27  #include <linux/log2.h>
  28 +#include <linux/qcom_scm.h>
  29 +#include <linux/io.h>
  30
  31  #include "../core.h"
  32  #include "../pinconf.h"
  33 @@ -57,6 +59,8 @@ struct msm_pinctrl {
  34         struct irq_chip irq_chip;
  35         int irq;
  36
  37 +       bool intr_target_use_scm;
  38 +
  39         raw_spinlock_t lock;
  40
  41         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  42 @@ -64,6 +68,7 @@ struct msm_pinctrl {
  43
  44         const struct msm_pinctrl_soc_data *soc;
  45         void __iomem *regs[MAX_NR_TILES];
  46 +       u32 phys_base[MAX_NR_TILES];
  47  };
  48
  49  #define MSM_ACCESSOR(name) \
  50 @@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
  51         else
  52                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
  53
  54 -       /* Route interrupts to application cpu */
  55 -       val = msm_readl_intr_target(pctrl, g);
  56 -       val &= ~(7 << g->intr_target_bit);
  57 -       val |= g->intr_target_kpss_val << g->intr_target_bit;
  58 -       msm_writel_intr_target(val, pctrl, g);
  59 +       /* Route interrupts to application cpu.
  60 +        * With intr_target_use_scm interrupts are routed to
  61 +        * application cpu using scm calls.
  62 +        */
  63 +       if (pctrl->intr_target_use_scm) {
  64 +               u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
  65 +               int ret;
  66 +
  67 +               qcom_scm_io_readl(addr, &val);
  68 +
  69 +               val &= ~(7 << g->intr_target_bit);
  70 +               val |= g->intr_target_kpss_val << g->intr_target_bit;
  71 +
  72 +               ret = qcom_scm_io_writel(addr, val);
  73 +               if (ret)
  74 +                       dev_err(pctrl->dev,
  75 +                               "Failed routing %lu interrupt to Apps proc",
  76 +                               d->hwirq);
  77 +       } else {
  78 +               val = msm_readl_intr_target(pctrl, g);
  79 +               val &= ~(7 << g->intr_target_bit);
  80 +               val |= g->intr_target_kpss_val << g->intr_target_bit;
  81 +               msm_writel_intr_target(val, pctrl, g);
  82 +       }
  83
  84         /* Update configuration for gpio.
  85          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
  86 @@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
  87         pctrl->dev = &pdev->dev;
  88         pctrl->soc = soc_data;
  89         pctrl->chip = msm_gpio_template;
  90 +       pctrl->intr_target_use_scm = of_device_is_compatible(
  91 +                                       pctrl->dev->of_node,
  92 +                                       "qcom,ipq8064-pinctrl");
  93
  94         raw_spin_lock_init(&pctrl->lock);
  95
  96 @@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
  97                 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
  98                 if (IS_ERR(pctrl->regs[0]))
  99                         return PTR_ERR(pctrl->regs[0]);
 100 +
 101 +               pctrl->phys_base[0] = res->start;
 102         }
 103
 104         msm_pinctrl_setup_pm_reset(pctrl);