lantiq: bump to 3.1
[openwrt/staging/dedeckeh.git] / target / linux / lantiq / patches / 0016-MIPS-lantiq-adds-xway-nand-driver.patch
1 From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Aug 2011 20:08:14 +0200
4 Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver
5
6 This patch adds a nand driver for XWAY SoCs. The patch makes use of the
7 plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
8 endianess swap problem on read. To workaround this problem we make the
9 read_byte() callback available via the plat_nand driver causing the nand
10 layer to do byte reads.
11
12 Signed-off-by: John Crispin <blogic@openwrt.org>
13
14 TODO : memory ranges
15 cs lines
16 plat dev
17 ebu2 and not ebu1 ?
18 ---
19 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
20 arch/mips/lantiq/xway/Makefile | 2 +-
21 arch/mips/lantiq/xway/nand.c | 185 ++++++++++++++++++++
22 drivers/mtd/nand/plat_nand.c | 1 +
23 include/linux/mtd/nand.h | 1 +
24 5 files changed, 190 insertions(+), 1 deletions(-)
25 create mode 100644 arch/mips/lantiq/xway/nand.c
26
27 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
28 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
29 @@ -140,6 +140,8 @@
30 /* register access macros for EBU and CGU */
31 #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
32 #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
33 +#define ltq_ebu_w32_mask(x, y, z) \
34 + ltq_w32_mask(x, y, ltq_ebu_membase + (z))
35 #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
36 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
37
38 --- a/arch/mips/lantiq/xway/Makefile
39 +++ b/arch/mips/lantiq/xway/Makefile
40 @@ -1,4 +1,4 @@
41 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
42 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
43
44 obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
45 obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
46 --- /dev/null
47 +++ b/arch/mips/lantiq/xway/nand.c
48 @@ -0,0 +1,185 @@
49 +/*
50 + * This program is free software; you can redistribute it and/or modify it
51 + * under the terms of the GNU General Public License version 2 as published
52 + * by the Free Software Foundation.
53 + *
54 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
55 + */
56 +
57 +#include <linux/mtd/physmap.h>
58 +#include <linux/mtd/nand.h>
59 +#include <linux/platform_device.h>
60 +
61 +#include <lantiq_soc.h>
62 +#include <lantiq_irq.h>
63 +#include <lantiq_platform.h>
64 +
65 +#include "devices.h"
66 +
67 +/* nand registers */
68 +#define LTQ_EBU_NAND_WAIT 0xB4
69 +#define LTQ_EBU_NAND_ECC0 0xB8
70 +#define LTQ_EBU_NAND_ECC_AC 0xBC
71 +#define LTQ_EBU_NAND_CON 0xB0
72 +#define LTQ_EBU_ADDSEL1 0x24
73 +
74 +/* gpio definitions */
75 +#define PIN_ALE 13
76 +#define PIN_CLE 24
77 +#define PIN_CS1 23
78 +#define PIN_RDY 48 /* NFLASH_READY */
79 +#define PIN_RD 49 /* NFLASH_READ_N */
80 +
81 +#define NAND_CMD_ALE (1 << 2)
82 +#define NAND_CMD_CLE (1 << 3)
83 +#define NAND_CMD_CS (1 << 4)
84 +#define NAND_WRITE_CMD_RESET 0xff
85 +#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
86 +#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
87 +#define NAND_WRITE_DATA (NAND_CMD_CS)
88 +#define NAND_READ_DATA (NAND_CMD_CS)
89 +#define NAND_WAIT_WR_C (1 << 3)
90 +#define NAND_WAIT_RD (0x1)
91 +
92 +#define ADDSEL1_MASK(x) (x << 4)
93 +#define ADDSEL1_REGEN 1
94 +#define BUSCON1_SETUP (1 << 22)
95 +#define BUSCON1_BCGEN_RES (0x3 << 12)
96 +#define BUSCON1_WAITWRC2 (2 << 8)
97 +#define BUSCON1_WAITRDC2 (2 << 6)
98 +#define BUSCON1_HOLDC1 (1 << 4)
99 +#define BUSCON1_RECOVC1 (1 << 2)
100 +#define BUSCON1_CMULT4 1
101 +#define NAND_CON_NANDM 1
102 +#define NAND_CON_CSMUX (1 << 1)
103 +#define NAND_CON_CS_P (1 << 4)
104 +#define NAND_CON_SE_P (1 << 5)
105 +#define NAND_CON_WP_P (1 << 6)
106 +#define NAND_CON_PRE_P (1 << 7)
107 +#define NAND_CON_IN_CS0 0
108 +#define NAND_CON_OUT_CS0 0
109 +#define NAND_CON_IN_CS1 (1 << 8)
110 +#define NAND_CON_OUT_CS1 (1 << 10)
111 +#define NAND_CON_CE (1 << 20)
112 +
113 +#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
114 +
115 +static const char *part_probes[] = { "cmdlinepart", NULL };
116 +
117 +static void
118 +xway_select_chip(struct mtd_info *mtd, int chip)
119 +{
120 + switch (chip) {
121 + case -1:
122 + ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
123 + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
124 + break;
125 + case 0:
126 + ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
127 + ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
128 + /* reset the nand chip */
129 + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
130 + ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
131 + break;
132 + default:
133 + BUG();
134 + }
135 +}
136 +
137 +static void
138 +xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
139 +{
140 + struct nand_chip *this = mtd->priv;
141 +
142 + if (ctrl & NAND_CTRL_CHANGE) {
143 + if(ctrl & NAND_CLE)
144 + this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD);
145 + else if(ctrl & NAND_ALE)
146 + this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
147 + }
148 +
149 + if(data != NAND_CMD_NONE) {
150 + *(volatile u8*)((u32)this->IO_ADDR_W) = data;
151 + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
152 + }
153 +}
154 +
155 +static int
156 +xway_dev_ready(struct mtd_info *mtd)
157 +{
158 + return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
159 +}
160 +
161 +void
162 +nand_write(unsigned int addr, unsigned int val)
163 +{
164 + ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr)));
165 + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
166 +}
167 +
168 +unsigned char
169 +ltq_nand_read_byte(struct mtd_info *mtd)
170 +{
171 + return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
172 +}
173 +
174 +int xway_nand_probe(struct platform_device *pdev)
175 +{
176 +// ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
177 + ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
178 + ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
179 + if (ltq_is_ar9() || ltq_is_vr9()) {
180 + ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
181 + ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
182 + }
183 +
184 + ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
185 + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
186 +
187 + ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
188 + | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
189 + | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
190 +
191 + ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
192 + | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
193 + | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
194 +
195 + ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
196 + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
197 +
198 + return 0;
199 +}
200 +
201 +static struct platform_nand_data falcon_flash_nand_data = {
202 + .chip = {
203 + .nr_chips = 1,
204 + .chip_delay = 30,
205 + .part_probe_types = part_probes,
206 + },
207 + .ctrl = {
208 + .probe = xway_nand_probe,
209 + .cmd_ctrl = xway_cmd_ctrl,
210 + .dev_ready = xway_dev_ready,
211 + .select_chip = xway_select_chip,
212 + .read_byte = ltq_nand_read_byte,
213 + }
214 +};
215 +
216 +static struct resource ltq_nand_res =
217 + MEM_RES("nand", 0x14000000, 0x3ffffff);
218 +
219 +static struct platform_device ltq_flash_nand = {
220 + .name = "gen_nand",
221 + .id = -1,
222 + .num_resources = 1,
223 + .resource = &ltq_nand_res,
224 + .dev = {
225 + .platform_data = &falcon_flash_nand_data,
226 + },
227 +};
228 +
229 +void __init
230 +xway_register_nand(void)
231 +{
232 + platform_device_register(&ltq_flash_nand);
233 +}
234 --- a/drivers/mtd/nand/plat_nand.c
235 +++ b/drivers/mtd/nand/plat_nand.c
236 @@ -77,6 +77,7 @@ static int __devinit plat_nand_probe(str
237 data->chip.select_chip = pdata->ctrl.select_chip;
238 data->chip.write_buf = pdata->ctrl.write_buf;
239 data->chip.read_buf = pdata->ctrl.read_buf;
240 + data->chip.read_byte = pdata->ctrl.read_byte;
241 data->chip.chip_delay = pdata->chip.chip_delay;
242 data->chip.options |= pdata->chip.options;
243
244 --- a/include/linux/mtd/nand.h
245 +++ b/include/linux/mtd/nand.h
246 @@ -657,6 +657,7 @@ struct platform_nand_ctrl {
247 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
248 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
249 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
250 + unsigned char (*read_byte)(struct mtd_info *mtd);
251 void *priv;
252 };
253